Broadband coupled input impedance matching LNA architecture

Abstract

Circuits and methods for a radio frequency amplifier, such as an LNA, including a wideband coupled input impedance matching network. One embodiment comprises: a first inductor coupled between a first terminal and a first node, the first terminal being coupleable to a degeneration terminal of an amplifier core; a second inductor coupled between a second terminal and the first node or a second node, the second terminal being coupleable to an input terminal of the amplifier core; a third inductor coupled between the first node and a third terminal, the third terminal being coupleable to a reference potential; and, in a variant embodiment, a fourth inductor coupled between the second node and a fourth terminal, the fourth terminal being coupleable to a reference potential; wherein the first inductor and the second inductor are coupled with each other. Some embodiments allow multiple modes to allow tradeoff of gain with linearity and NF characteristics.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Patent Application No. 17 / 855,443, filed on June 30, 2022, the contents of which are incorporated herein by reference in their entirety. background (1) Technical field

[0004] The present invention relates to electronic circuits and, more particularly, to radio frequency amplifier circuits.

[0005] (2) Background

[0006] Many modern electronic systems include radio frequency (RF) receivers; examples include cellular phones, personal computers, tablet computers, wireless network components, televisions, cable television system "set-top boxes," and radar systems. Many RF receivers are paired with an RF transmitter in the form of a transceiver, which is typically a very sophisticated two-way radio. In some cases, an RF transceiver is capable of transmitting and receiving across multiple frequencies in multiple frequency bands.

[0007] Amplifiers are common components in RF transmitters, receivers, and transceivers, and are often used for power amplification of transmitted RF signals and for low-noise amplification of received RF signals. For many RF systems, particularly those that require low power consumption and / or portability (e.g., cell phones, WiFi-connected computers, cameras, and other devices), it has become common to use complementary metal oxide semiconductor (CMOS) manufacturing technology to create low-cost, low-power integrated circuits (ICs). CMOS devices include bulk-CMOS, silicon-on-insulator (SOI) CMOS, and silicon-on-sapphire (SOS) CMOS (SOS is a type of SOI manufacturing technology).

[0008] Receiving RF signals in many environments requires a high-quality low noise amplifier (LNA) as part of the RF "front end" (RFFE) receiver or transceiver circuit chain. Important desired characteristics of an LNA are high gain and low noise, wide bandwidth, good linearity, and good input and output impedance matching. However, typically, all of these factors cannot be optimized simultaneously, and therefore there is a trade-off between these characteristics when designing an LNA.

[0009] The five important design parameters for LNAs are gain, noise figure (NF), input referred third-order intercept point (IIP3), output reflection coefficient, and input reflection coefficient. NF is a measure of the degradation of the signal-to-noise ratio (SNR) caused by components in the signal chain, where lower values ​​indicate better performance. IIP3 is a figure of merit that represents the linearity of the amplifier, where higher values ​​indicate better performance. Typically, NF has stricter specifications in high gain mode than in low gain mode, while IIP3 has stricter specifications in low gain mode than in high gain mode. The output reflection coefficient is an S22 scattering parameter (or "S parameter") and is an indication of output impedance matching, where lower (more negative when evaluated logarithmically) numbers indicate better impedance matching. The input reflection coefficient is an S11 S parameter and is an indication of input impedance matching, where lower (more negative when evaluated logarithmically) numbers indicate better performance.

[0010] The increase in RF communication band and channel frequencies and the continued increase in the number of used bands and channels pushes current LNA architectures to their limits. For example, for some of the new 5G mobile network bands, especially the 3 GHz to 6 GHz NR band, the upcoming 7 GHz to 24 GHz band, and the millimeter wave range (e.g., 24.25 GHz to 52.6 GHz), it is difficult and sometimes even impossible to achieve the stringent requirements for gain, bandwidth percentage, linearity, and input and output impedance matching with conventional LNA architectures due to insufficient broadband performance.

[0011] There are several design challenges for wideband LNAs. For example, achieving effective wideband impedance matching at the input of the LNA is a key goal in achieving overall performance, especially NF. Known methods of input impedance (IM) matching involve using a series inductor or a series inductor / shunt inductor combination between the LNA input terminal and the amplification core (e.g., a cascode transistor pair), but these solutions have limited bandwidth. Multi-stage IM matching comes with other trade-offs, primarily in terms of lower NF and additional manufacturing cost and integrated circuit (IC) die area.

[0012] Therefore, there is a need for an LNA architecture that overcomes the limitations of conventional LNA architectures. Summary of the invention

[0013] The present invention includes circuits and methods for high frequency LNAs including broadband coupled input impedance matching networks. Some embodiments allow multiple operating modes to allow selection of gain vs. linearity and NF characteristics. The circuits and methods of the present invention may also be applied to other types of amplifiers such as power amplifiers.

[0014] A first embodiment includes a broadband input impedance matching network, comprising: a first inductor, the first inductor coupled between a first terminal and a first node, the first terminal being configured to be coupled to a degeneration terminal of an amplifier core; a second inductor, the second inductor coupled between a second terminal and the first node, the second terminal being configured to be coupled to an input terminal of the amplifier core; and a third inductor, the third inductor coupled between the first node and a third terminal, the third terminal being configured to be coupled to a reference potential; wherein the first inductor and the second inductor are coupled to each other.

[0015] A second embodiment includes a broadband input impedance matching network, which includes: a first inductor, the first inductor is coupled between a first terminal and a first node, the first terminal is configured to be coupled to a degeneration terminal of an amplifier core; a second inductor, the second inductor is coupled between a second terminal and a second node, the second terminal is configured to be coupled to an input terminal of the amplifier core; a third inductor, the third inductor is coupled between the first node and a third terminal, the third terminal is configured to be coupled to a reference potential; and a fourth inductor, the fourth inductor is coupled between the second node and a fourth terminal, the fourth terminal is configured to be coupled to the reference potential; wherein the first inductor and the second inductor are coupled to each other.

[0016] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a simplified schematic diagram of a first embodiment of an LNA circuit with a broadband coupled input impedance matching network.

[0018] Figure 2 is a simplified schematic diagram of a second embodiment of an LNA circuit with a wideband coupled input impedance matching network.

[0019] Figure 3A Yes Figure 1 A graph of measured S11 versus frequency performance of an embodiment of an LNA compared to a conventional LNA having a series inductor / shunt inductor combination between the RF input terminal and the amplification core.

[0020] Figure 3B Yes Figure 1 A graph of measured gain versus frequency performance of an embodiment of an LNA compared to a conventional LNA having a series inductor / shunt inductor combination between the RF input terminal and the amplification core.

[0021] Figure 4A Yes Figure 1 LNA (with L S and L G The implementation method of the common connection) is similar to Figure 2 LNA (for L S and L G A graph of measured gain versus frequency performance comparing an embodiment having a separate ground connection).

[0022] Figure 4B Yes Figure 1 The LNA is implemented as Figure 2 A graph comparing the measured S11 vs. frequency performance of various implementations of the LNA.

[0023] Figure 4C Yes Figure 1 The LNA is implemented as Figure 2 A graph comparing the measured NF vs. frequency performance of various implementations of the LNA.

[0024] Figure 5A yes Figure 1 Schematic diagram of an LNA in FIG. 1 shows two possible dividing lines between fabricating WCIIM network circuit components on-die or off-die (eg, within a circuit module to which the LNA die is attached).

[0025] Figure 5B yes Figure 2 Schematic diagram of an LNA in FIG. 1 shows two possible dividing lines between fabricating WCIIM network circuit components on-die or off-die.

[0026] Fig. 6A yes Figure 1 Schematic diagram of a portion of an LNA showing a second method of achieving a high coupling factor k, which is to S The inductance and L G This is particularly useful when the inductance is very small (e.g., about 0.3 nH) compared to the inductance of the capacitor (e.g., about 4 nH).

[0027] Figure 6B is a top view of an example IC transformer coil, where the inductor L G The transformer coil consists of nearly four turns, and the inductor L S1 , L S2 , L S3 Each comprises approximately half a turn of the transformer coil.

[0028] Figure 7 yes Figure 1 Schematic diagram of a portion of an LNA, showing the switchable configuration of the WCIIM network.

[0029] Figure 8 yes Figure 1 Schematic diagram of a portion of the LNA, showing the WCIIM network through a series inductor L SER Coupled to the INT terminal.

[0030] Fig. 9A YesL SER Implementation and non-L SER Graph of simulated gain versus frequency performance comparing implementations.

[0031] Fig. 9B YesL SER Implementation and non-L SER Graph of simulated NF vs. frequency performance comparing embodiments.

[0032] Fig. 9C YesL SER Implementation and non-L SER Graph of simulated S11 vs. frequency performance of implementations comparison.

[0033] Fig.9D YesL SER Implementation and non-L SER Graph of simulated S22 vs. frequency performance for implementation comparisons.

[0034] Fig.9E YesL SER Implementation and non-L SER Smith chart of simulated S11 and optimal noise reflection coefficient Gmin vs. frequency performance of embodiments compared.

[0035] Fig.9F YesL SER Implementation and non-L SER Smith chart of simulated S22 vs. frequency performance of embodiments compared.

[0036] Fig. 10A is a schematic diagram of a first output impedance matching (OIM) network that may be used in conjunction with the LNA circuit of the present disclosure.

[0037] Fig. 10B is a schematic diagram of a second OIM network that may be used in conjunction with the LNA circuit of the present disclosure.

[0038] Fig.11 is a schematic diagram of one embodiment of an input matching feedback circuit.

[0039] Fig.12 is a simplified schematic diagram of one implementation of an output matching feedback circuit.

[0040] Fig.13 is a top view of a substrate which may be, for example, a printed circuit board or a die module substrate (eg, a thin film ceramic board).

[0041] FIG. 14 illustrates an exemplary prior art wireless communication environment that includes different wireless communication systems and that may include one or more mobile wireless devices.

[0042] Fig.15 is a block diagram of a transceiver that may be used in a wireless device such as a cellular telephone and that may beneficially incorporate embodiments of the present invention for improved performance.

[0043] Fig.16 is a process flow diagram illustrating a first method for providing broadband input impedance matching for an amplifier core.

[0044] Fig.17 is a process flow diagram illustrating a second method for providing broadband input impedance matching for an amplifier core.

[0045] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0046] The present invention includes circuits and methods for high frequency LNAs including a broadband coupled input impedance matching network. Some embodiments allow multiple modes of operation to allow selection of gain vs. linearity and NF characteristics. The circuits and methods of the present invention may also be applied to other types of amplifiers, such as power amplifiers.

[0047] Bandwidth Terminology

[0048] For the purposes of this disclosure, “narrowband,” “wideband,” and “ultra-wideband” are characterized by a percentage fractional bandwidth equal to (the cutoff frequency f STOP Subtract the starting frequency f START ) divided by the center frequency f of the band CENTER , or (f STOP -f STARP ) / f CENTER (Expressed as a percentage, where f CENTER =(f STOP +f START ) / 2. Table 1 below shows typical guidelines (not a strict definition) characterizing typical percentage bandwidths.

[0049]

[0050]

[0051] Table 1

[0052] Table 2 below provides examples of common cellular telephone frequency bands and their characterization as wideband or ultra-wideband using the guidelines in Table 1.

[0053]

[0054] Table 2

[0055] First embodiment

[0056] Figure 1 is a simplified schematic diagram of a first embodiment of an LNA circuit 100 having a broadband coupled input impedance matching network 102a.

[0057] In the example shown, the LNA circuit 100 includes an amplifier core 104 including two series-connected FETs (field effect transistors) M1 and M2 in a cascode arrangement. CS 、M CG stack. Apply to the RF input terminal RF IN The RF input signal passes through the DC blocking capacitor C BLK Coupled to common source FET M CS The control gate of the amplification core 104 can be regarded as the input terminal INT of the amplification core 104.

[0058] Common-gate FET M CG The source of the FET M is connected to the common source CS The drain of the common gate FET M CG The drain of provides an amplified RF output signal at an amplified signal terminal AST which can be considered as the amplifying core 104 .

[0059] The output impedance matching (OIM) network 106 has an IN terminal configured to be coupled to the amplified signal terminal AST of the amplification core 104, and an OUT terminal configured to be coupled to the RF output terminal RF OUT The amplified output of the amplified core 104 is coupled to the RF output terminal RF via the OIM network 106. OUT , RF output terminal RF OUT is shown coupled to a resistor represented as R L For many modern RF circuits, R L The value is usually 50 ohms.

[0060] The bias circuit 108 is configured to bias the common-gate FET M in a known manner. CG Provide a suitable bias voltage CG_V BIAS , and to the common source FET M CS Provide a suitable bias voltage CS_V BIAS Other well-known circuit elements that may be included in some applications, such as bypass capacitors, are omitted for clarity.

[0061] The wideband coupled input impedance matching (WCIIM) network 102a includes: an RP terminal configured to be coupled to a reference potential (e.g., circuit ground); a DG terminal configured to be coupled to a degeneration terminal DT of the amplification core 104; and an IN terminal configured to be coupled to the amplifier core 104 via a capacitor C BLK is coupled to the input terminal INT of the amplifying core 104. In the illustrated embodiment, the WCIIM network 102a includes a pair of mutually coupled inductors L S and L G . Source inductor L S is coupled between the DG terminal (and thus may be coupled to the degeneration terminal DT of the amplification core 104) and the node X and functions at least in part as a degeneration inductor. G is coupled between the IN terminal (and thus may be coupled to the input terminal INT of the amplification core 104) and the node X. S and L G The placement of the "dots" on opposite sides of the symbol of L indicates that the coupling is negative. However, in alternative embodiments, the coupling can be positive - that is, the dot will be located at the side representing L S and L G on the same side of the symbol.

[0062] The two main inductors L G and L S are arranged so that they exhibit a mutual inductance with a coupling factor k1 and can be implemented, for example, as coupled segments of a multi-port integrated circuit inductor coil. G With L S The mutual inductance between generates a feedback current to the input terminal INT of the amplifying core 104 , which achieves a wideband input matching with minimal impact on NF.

[0063] The WCIIM network 102a shown also includes a node coupled at node X (and therefore coupled to L G and L S ) and the RP terminal (and thus may be coupled to a reference potential such as circuit ground) R1 Symbol. The third inductor L R1 represents the inherent inductance of the conductive routing trace from the IC implementation of LNA 100 to the ground plane of the module to which the IC is attached. R1 The layout of the conductive routing traces exists during the design phase of the control, so L can be set R1 The inductor value can be further adjusted for specific applications. G and L S of mutual induction.

[0064] Second embodiment

[0065] Figure 2 is a simplified schematic diagram of a second embodiment of an LNA circuit 200 having a broadband coupled input impedance matching network 102b. The LNA circuit 200 is similar in most respects to Figure 1 1 , but includes a variant WCIIM network 102b.

[0066] The WCIIM network 102b includes: separate RP1 and RP2 terminals configured to be coupled to a reference potential (eg, circuit ground); a DG terminal configured to be coupled to a degeneration terminal DT of the amplification core 104; and an IN terminal configured to be coupled to the amplifier core 104 via a capacitor C BLK is coupled to the input terminal INT of the amplifying core 104. In the illustrated embodiment, the WCIIM network 102b includes a pair of mutually coupled inductors L S and L G . Source inductor L S is coupled between the DG terminal (and thus may be coupled to the degeneration terminal DT of the amplification core 104) and the node X and functions at least in part as a degeneration inductor. G is coupled between the IN terminal (and thus may be coupled to the input terminal INT of the amplifying core 104) and the node Y. The two main inductors L G and L S are arranged so that they exhibit a mutual inductance with a coupling factor k2 and can be implemented, for example, as coupled segments of a multi-port integrated circuit inductor. G With L S The mutual inductance between generates a feedback current at the input terminal INT of the amplifying core 104 , which achieves a broadband input matching with minimal impact on NF.

[0067] The WCIIM network 102 shown also includes a node coupled at node X (and therefore coupled to L S ) and the RP1 terminal (and thus may be coupled to a reference potential, such as circuit ground) R1 and coupled at node Y (and hence to L G ) and the RP2 terminal (and thus may be coupled to the reference potential) R2 The third inductor L R1 and the fourth inductor L R2 represents the inductance inherent in each conductive routing trace from the IC implementation of LNA 100 to the ground plane of the module to which the IC is attached. It is worth noting that in the illustrated embodiment, L R1 and L R2 Usually not coupled to each other. R1 and the fourth inductor LR2 The layout of the conductive routing traces exists during the design phase for control, so their individual inductance values ​​can be set to further tune L for a specific application. G and L S of mutual induction.

[0068] One challenge in implementing on-die mutually coupled inductors (also called transformers) is achieving high coupling factors k ( where M is the mutual inductance) and high turns ratio However, by separating L S and L G The common connection and L R1 and L R2 L S and L G A separate connection to the reference potential allows more design freedom for the transformer layout to achieve a high k2.

[0069] Performance Examples

[0070] Figure 3A Yes Figure 1 Graph 300 of measured S11 versus frequency performance of an embodiment of LNA 100 of the present invention is compared with a conventional LNA having a series inductor / shunt inductor combination between the RF input terminal and the amplification core 104. Curve 302 corresponds to LNA 100, while curve 304 corresponds to the conventional LNA. Both embodiments are designed to have optimal performance between about 6 GHz and about 9 GHz (this range is indicated by dashed lines 306 and 308); as shown by inspection of graph 300, the LNA 100 architecture exhibits better average S11 performance in this frequency interval.

[0071] Figure 3B Yes Figure 1 Graph 310 of measured gain versus frequency performance of an embodiment of the LNA 100 of the embodiment of the embodiment of the LNA 100 is compared to a conventional LNA having a series inductor / shunt inductor combination between the RF input terminal and the amplification core 104. Curve 312 corresponds to the LNA 100, while curve 314 corresponds to the conventional LNA. In the 6 GHz to 9 GHz frequency interval, the LNA 100 architecture exhibits flatter gain performance and better minimum gain in the example frequency interval.

[0072] NF performance (not shown) is comparable between LNA 100 and conventional LNAs, with LNA 100 generally exhibiting slightly flatter performance and better average performance over the example frequency interval.

[0073] Figure 4A Yes Figure 1 The LNA100 (with L Sand L G The implementation method of the common connection) is similar to Figure 2 The LNA 200 (with L S and L G 4 is a graph 400 of measured gain versus frequency performance comparing an embodiment of the present invention with a separate ground connection (without a separate ground connection). Curve 402 corresponds to the LNA 100 embodiment, while curve 404 corresponds to the LNA 200 embodiment, which exhibits higher gain over the example frequency interval (corresponding to the 5G N77 band).

[0074] Figure 4B Yes Figure 1 The LNA 100 is implemented as follows Figure 2 Graph 410 of measured S11 versus frequency performance of an embodiment of LNA 200 is shown. Curve 412 corresponds to the LNA 100 embodiment, while curve 414 corresponds to the LNA 200 embodiment, which exhibits slightly higher S11 over the example frequency interval.

[0075] Figure 4C Yes Figure 1 The LNA 100 is implemented as Figure 2 Graph 420 of measured NF versus frequency performance of an embodiment of LNA200 is shown. Lower NF values ​​indicate better performance. Curve 422 corresponds to the LNA100 embodiment, while curve 424 corresponds to the LNA200 embodiment, which exhibits a slightly higher average NF in the example frequency interval.

[0076] In this example, LNA100 requires more coupling on the IC to cancel the opposing coupling on the module; the separate ground connection of LNA200 overcomes this problem and achieves higher gain, but there is some trade-off in S11 and NF performance. It should be understood that either architecture can be used for any particular application and may require performance trade-offs between gain, S11, and NF to meet applicable specifications.

[0077] Compared to input impedance matching circuits having only a series inductor or a series inductor / shunt inductor combination between the LNA input terminal and the amplification core, the new impedance matching input architecture described in the present disclosure has the following advantages: IC area savings, manufacturing cost savings, wider impedance matching bandwidth, and flatter gain response.

[0078] IC-to-module connections and mutual coupling options

[0079] Integrated circuit implementations of LNA circuits 100, 200 may utilize a variety of different possible circuit layouts to trade off inductor coupling and IC area. For example, Figure 5A yes Figure 1 1, showing two possible dividing lines between fabricating the WCIIM network 102a circuit components on-die or off-die (e.g., within a circuit module to which the LNA die is attached) relative to the amplifier core 104. In a first configuration 502, the mutually coupled inductors L G , L S and the common inductor L R1 The inductors L are located off-die relative to the amplifier core 104, thereby saving IC area. G , L S is fabricated on-die (ie, co-fabricated with the amplifier core 104), and the common inductor L R1 (which is essentially always present due to routing requirements) is off-die relative to the amplifier core 104. In the second illustrated configuration, the coupling is negative on the IC and positive off-die (e.g., in a module). Coupling on-die generally provides more control over design characteristics.

[0080] As another example, Figure 5B yes Figure 2 , showing two possible dividing lines between fabricating the WCIIM network 102b circuit components on-die or off-die. In the first configuration 512, the mutually coupled inductors L G , L S and a separate inductor L R1 , L R2 is manufactured outside the die, thereby saving IC area. In the second configuration 514, the mutually coupled inductors L G , L S is manufactured on the die, while the separate inductor L R1 , L R2 is fabricated off-die. In the second illustrated configuration, the coupling is negative on the IC and negligible off-die (e.g., in a module). Coupling on-die generally provides more control over design characteristics.

[0081] Alternative Implementations

[0082] The present invention includes multiple alternative embodiments. For example, Fig. 6A yes Figure 1 A schematic diagram of a portion 600 of an LNA 100 is shown, illustrating a second method of achieving a high coupling factor k, in which the L S The inductance and L G This is particularly useful when the inductance of the capacitor is very small (e.g., about 0.3nH) compared to the inductance of the capacitor (e.g., about 4nH). Fig. 6A As shown, Figure 1A single inductor L S By multiple parallel inductors L S1 , L S2 , ...L Sn , where n ≥ 2. Multiple parallel inductors can be implemented using mutually coupled parallel single-turn inductors instead of using conventional multi-turn single inductors. For example, Figure 6B is a top view of an example IC transformer coil 610, where the inductor L G The transformer coil 610 includes approximately four turns, and the inductor L S1 , L S2 , L S3 Each transformer coil 610 includes approximately half a turn. Note that in the area enclosed by the dashed ellipse 612, the inductor L S1 , L S2 , L S3 The conductive trace covers the inductor L G The final layout of the coupled inductor within the WCIIM network 102a is advantageously compact for IC manufacturing. S1 , L S2 , ...L Sn The configuration can also be Figure 2 Used in conjunction with the LNA200. Fig. 6A and Figure 6B The concepts shown in can also be applied to Figure 2 The LNA200 and comparable LNAs.

[0083] Figure 7 yes Figure 1 Schematic diagram of a portion 700 of the LNA 100, showing a switchable configuration of the WCIIM network 102a. In the illustrated embodiment, Figure 1 The source inductor L S is "split" to include two transformer coils L Sa and L Sb , the two transformer coils L Sa and L Sb can be switchably coupled to the inductor L G . A set of switches is also included, which implements different configurations of the WCIIM network 102a - more specifically, a first switch Sw1 is coupled between the degeneration terminal DT and the circuit ground (as an example of a reference voltage), a second switch Sw2 is coupled between the node X and the circuit ground, and a third switch Sw3 is coupled between the inductor L Sb and the circuit ground, and the fourth switch Sw4 is coupled between the inductor L GOmitted to avoid clutter is the inductance inherent in the conductive routing traces from the IC implementation of the LNA 100 to the ground plane of the module to which the IC is attached. Figure 7 The concepts shown in can also be applied to Figure 2 The LNA200 and comparable LNAs.

[0084] The illustrated architecture can be configured for different modes that trade off between gain and linearity. For example, Table 3 below provides only a few examples of switch positions and final modes that can be achieved using the switchable configuration of the WCIIM network 102a. In the table, "O" means that the switch is set to the open (non-conducting) state, "X" means that the switch is set to the closed (conducting) state, and "-" means that the switch can be set to open or closed as required by the specific application. It should be understood that other combinations of switch configurations are possible.

[0085]

[0086]

[0087] Table 3

[0088] According to different application scenarios, the switch Sw3 can be omitted (so that L Sb connected to circuit ground) to make different trade-offs. For example, in the first topology, if a low-loss switch is available and L Sa Q is important, then switch Sw3 can be connected with L Sb are included in series, such as Figure 7 When Sw2 is closed and Sw3 is open, this helps to increase L Sa Q, because Sw3 prevents the signal from flowing through L Sb (Note that actual FET implementations of Sw2 will not behave as an ideal short circuit with zero resistance, so closing Sw2 will not completely bypass L Sb ). In the second topology, if a low-loss switch is not available, Sw3 can be omitted. This helps to increase L when Sw2 is disconnected. Sa +L Sb The Q value of the series combination of the split, switchable L S The inductor configuration can also be Figure 2 Used in conjunction with the LNA200.

[0089] Figure 8 yes Figure 1 A schematic diagram of a portion 800 of an LNA 100 is shown, showing the WCIIM network 102a connected via a series inductor L SER and DC blocking capacitor C BLK is coupled to the INT terminal. More specifically, the inductor L SERThrough the DC blocking capacitor C BLK is coupled to the input terminal INT (C BLK and L SER The positions of the inductors L are interchangeable), and are coupled to the WCIIM network 102a. G , so that the feedback from the WCIIM network 102a flows through L SER This architecture facilitates input impedance matching with an additional degree of freedom and improves both gain and NF. The series inductor L SER Can also be used with Figure 2 The LNA200 is used in conjunction with a comparable LNA.

[0090] For example, 9A to 9E is used where the LNA includes a series inductor L SER and DC blocking capacitor C BLK The WCIIM network 102a coupled to the INT terminal is Figure 1 The LNA100 (with L S and L G Implementation method of the common connection) ("L SER Implementation method") and for the lack of L SER Similar LNA implementations (“non-L SER The LNA implementation in this example is designed for the 5 GHz to 7 GHz 5G New Wireless Unlicensed (NR-U) cellular radio spectrum. The graph shows the LNA parameter values ​​of various LNA implementations ("Implementation") as a function of frequency. The LNA implementation in this example is designed for the 5 GHz to 7 GHz 5G New Wireless Unlicensed (NR-U) cellular radio spectrum. SER In the case of inductance, the gains S11, S22 and NF can be improved at the same time.

[0091] Fig. 9A YesL SER Implementation (curve 902) and non-L SER Graph 900 of simulated gain versus frequency performance comparing an embodiment (curve 904). The increase in series inductance at the input increases the Q of the input matching network and thus increases the overall LNA gain. SER Embodiments exhibit higher gains over example frequency intervals.

[0092] Fig. 9B YesL SER Implementation (curve 912) and non-L SER Graph 910 of simulated NF vs. frequency performance comparing an embodiment (curve 914). Lower NF values ​​indicate better performance. SER Embodiments exhibit lower NF over the example frequency intervals.

[0093] Fig. 9CYesL SER Implementation (curve 922) and non-L SER Graph 920 of simulated S11 versus frequency performance for an embodiment (curve 924). Lower S11 values ​​indicate better performance. SER Embodiments exhibit lower S11 over the example frequency intervals.

[0094] Fig.9D YesL SER Implementation (curve 932) and non-L SER Graph 930 of simulated S22 versus frequency performance comparing an embodiment (curve 934). Lower S22 values ​​indicate better performance. SER Embodiments exhibit lower S22 over the example frequency intervals.

[0095] Fig.9E YesL SER Implementation method (curve 942 S11 and 942 Gmin ) and non-L SER Implementation method (curve 944 S11 and 944 Gmin ) is a Smith chart 940 comparing the simulated S11 and the optimal noise reflection coefficient Gmin with the frequency performance. As shown in the Smith chart 940, adding L SER Inductance makes L SER S11 (curve 942) of the embodiment S11 ) is closer to the center of the graph 946 (indicating that the SER At the same time, adding L SER Inductance makes L SER Gmin (curve 942) of the embodiment Gmin ) is closer to the center of the graph 946 (indicating that the SER better noise matching compared to the implementation scheme).

[0096] Fig.9F YesL SER Implementation (curve 952) and non-L SER A Smith chart 950 comparing the simulated S22 and frequency performance of the embodiment (curve 954). As shown in the Smith chart 950, adding L SER Inductance makes L SER The embodiment S22 (curve 952) is closer to the center 956 of the graph (indicating the difference with non-L SER implementation compared to better S22 performance).

[0097] Optional circuit components

[0098] A. Output Impedance Matching Circuit The OIM network 106 of the LNA circuit described above may be implemented in a variety of ways that facilitate wideband operation.

[0099] For example, Fig. 10A 1 is a schematic diagram of a first output impedance matching (OIM) network 106a that may be used in conjunction with the LNA circuits 100, 200 of the present disclosure. The OIM network 106a includes a first inductor L1 coupled in series with a second inductor L2 at a node Z, wherein a pair of inductors L1, L2 are coupled to an IN terminal of the OIM network 106b and are configured to be coupled to a power supply V DD . DC blocking capacitor C BLK1 is coupled between node Z and the OUT terminal of the OIM network 106a, which in turn is coupled to the RF OUT Terminals. Inductors L1, L2 and capacitors C BLK1 Any of may be adjustable components as shown, or have fixed values.

[0100] As another example, Fig. 10B is a schematic diagram of a second OIM network 106b that can be used in conjunction with the LNA circuits 100, 200 of the present disclosure. The OIM network 106b includes an inductor L2 coupled to the IN terminal of the OIM network 106b and configured to be coupled to a power supply VDD. A DC blocking capacitor C BLK2 The amplified signal terminal AST of the amplifying core 104 is coupled to the second stage FET M1 which provides the second stage amplification as a source follower circuit. SF In the example shown, the second stage FET M SF has a conductive channel (drain to source) coupled between VDD and inductor L3, which in turn is coupled to a reference potential such as circuit ground. SF The source of the BLK3 The OUT terminal of the OIM network 106b is coupled to the RF OUT Some embodiments may include a capacitor C coupled in parallel with the inductor L3. F0。 Inductors L2, L3 and capacitor C BLK2 , C BLK3 , C F0 Any of may be adjustable components as shown, or have fixed values.

[0101] B. Stacking of FETs. In some embodiments, to overcome the relatively low breakdown voltage of each CMOS FET, such as Figure 1 and Figure 2As shown, at the bottom common gate FET M CG A plurality of common-gate FETs may be coupled in series in the FET stack 120 between the drain of the amplifier core 104 and the amplified signal terminal AST - that is, the amplifier core 104 may have a plurality of common-gate FETs coupled in series in a cascade configuration. The amplified signal terminal AST would then be located at the drain of the uppermost common-gate FET in the amplifier core 104.

[0102] C. Input Match Feedback Circuit. Some embodiments may include an input match (IM) feedback circuit 122. The IM feedback circuit 122 is Figure 1 and Figure 2 104 is shown as coupled between the input terminal INT and the amplified signal terminal AST. More generally, the IM feedback circuit 122 can be coupled to a feedback node in the output signal path of the amplifying core 104, which can be the drain of any one of the FETs in the amplifying core 104 (including within the FET stack 120). The selection of the feedback node for connection to the IM feedback circuit 122 can be made, for example, based on different desired feedback strengths and different desired input impedances.

[0103] Fig.11 FIG. 1 is a schematic diagram of one embodiment of the input matching feedback circuit 122. The IM feedback circuit 122 in the illustrated example includes a switch S F1 The DC blocking capacitor C coupled in series F1 , switch S F1 Then connected in series to the resistor R F1 In some embodiments, C F1 and / or R F1 may be adjustable as shown, or have a fixed value. In an alternative embodiment, the IM feedback circuit 122 may include one or more parallel switches S F11 ……S F1n (usually S F1x ), which in turn is coupled in series to a corresponding parallel resistor R F11 ……R F1n (Usually R F1x ). In the case of n parallel switch / resistor branches, the resistor R F1x The adjustability is equal to 2 n (Total number of switch combinations). Note that resistor R F1x The values ​​of do not need to be the same. This can be achieved by disconnecting all feedback switches S F1x to disable the IM feedback circuit 122.

[0104] In an alternative embodiment, capacitor C F1 , a group of one or more switches S F1x and a set of one or more resistors RF1x The switches S can be connected in any series order. F1x , thereby a group of one or more resistors R F1x Permanently coupled between the input terminal INT and a feedback node in the output signal path of the amplification core 104 .

[0105] In various gain modes, one or more resistors R F1x There are circuits within the LNA that allow the Q factor of the input impedance match to be reduced, which increases the bandwidth of the LNA circuit at the expense of gain and NF.

[0106] An advantage of using a variable or multi-state IM feedback circuit 122 is that multiple resistor values ​​enable multiple gain modes. For example, an LNA in a mobile RF receiver device may require multiple gain modes depending on the input signal strength range at the receiver. In addition, by using a variable or multi-state feedback resistor R F1x Implementing multiple gain modes may eliminate the need for output attenuators (common in conventional receiver LNAs).

[0107] More information about the IM feedback circuit 122 can be found in U.S. patent application No. 17 / 337,227, filed on June 2, 2021, entitled “Wideband Multi Gain LNA Architecture,” which is assigned to the assignee of the present invention, and the contents of which are hereby incorporated by reference.

[0108] D. Output Matching Feedback Circuit. Some embodiments may include an output matching (OM) deQing circuit 124. The OM deQing circuit 124 Figure 1 and Figure 2 is shown as coupling the amplified signal terminal AST with the common gate FET M CG and is used to reduce the transformed Q of the OIM network 106. More generally, the OM de-Q circuit 124 can be coupled to a feedback node in the output signal path of the amplifying core 104, which can be the drain of any of the FETs in the amplifying core 104 (including within the FET stack 120). Reducing the transformed Q extends the output impedance matching bandwidth of the LNA circuit. Compared with other known circuits, this architecture shows better gain and bandwidth trade-offs in various applications.

[0109] Fig.12 FIG. 1 is a simplified schematic diagram of one embodiment of the output matching de-Q circuit 124. The OM de-Q circuit 124 in the illustrated example includes a switch S F2 The DC blocking capacitor C coupled in seriesF2 , switch S F2 Then connected in series to the resistor R F2 In some embodiments, C F2 and / or R F2 may be adjustable as shown, or have a fixed value. In an alternative embodiment, the OM de-Q circuit 124 may include one or more parallel switches S F21 ……S F2n (usually S F2x ), which in turn is coupled in series to a corresponding parallel resistor R F21 ……R F2n (Usually R F2x ). In the case of n parallel switch / resistor branches, the resistor R F2x The adjustability is equal to 2 n (Total number of switch combinations). Note that resistor R F2x The values ​​of do not need to be the same. This can be achieved by disconnecting all feedback switches S F2x to disable the OM de-Q circuit 124.

[0110] In an alternative embodiment, capacitor C F2 , a group of one or more switches S F2x and a set of one or more resistors R F2x The switches S can be connected in any series order. In other embodiments, the switch S can be omitted. F2x , thereby a group of one or more resistors R F2x Permanently coupled between the amplified signal terminal AST and the common gate FET M CG between the control gates.

[0111] In various gain modes, one or more resistors R F2x The presence of circuits within the circuit allows the Q factor of the output impedance matching to be reduced, which increases the bandwidth of the LNA circuit at the expense of gain and NF. For example, switching a single resistor R inside or outside the circuit F2 Two operating modes are provided, the first mode having a wider output impedance matching bandwidth, and the second mode having a narrower output impedance matching bandwidth but having a higher gain than the first mode (assuming no other LNA circuit elements are adjusted simultaneously). F2 Changing or enabling more than one resistor value can allow for more operating modes.

[0112] More specifically, when the switch S F2 When closed, R F2 The amplified signal terminal AST is coupled to the common gate FET M CG The control gate effectively places R F2The equivalent resistance R of the amplifier core 104 circuit D Parallel. R F2 The circuit reduces the impedance Z of the amplifier core 104. DRAIN , as seen at the AST terminals, and reduces the transformed Q of the OIM network 106, where Q is approximately equal to Z DRAIN The real part of the load resistance R L , that is, Re(Z DRAIN ) / R L Therefore, the transformation Q value is reduced, thereby extending the output impedance matching bandwidth of the LNA circuit. Compared with other known circuits, this architecture shows a better gain and bandwidth trade-off in various applications. On the contrary, when the switch S F2 When disconnected, R F2 Relative to R in the equivalent circuit D Out of circuit, and the transformed Q value of the OIM network 106 is not reduced.

[0113] An advantage of using a variable or multi-state OM de-Q circuit 124 is that multiple resistor values ​​enable multiple gain modes. For example, an LNA in a mobile RF receiver device may require multiple gain modes depending on the range of input signal strengths at the receiver. In addition, by using a variable or multi-state feedback resistor R2 Fx Implementing multiple gain modes may eliminate the need for output attenuators (common in conventional receiver LNAs).

[0114] More information about the OM de-Q circuit 124 can be found in U.S. patent application Ser. No. _____________, entitled “Extended Impedance Matching Wideband LNA Architectures,” Attorney Docket No. PER-427-PAP, filed concurrently with the present invention, which is assigned to the assignee of the present invention, the contents of which are hereby incorporated by reference.

[0115] Circuit Implementation

[0116] The circuits and devices according to the present invention can be used alone or in combination with other components, circuits and devices. For example, Figure 1 , Figure 2 , Fig. 6A , Figure 7 and Figure 8 The LNA circuit can be separately Fig. 10A and Fig. 10B Any of the output impedance matching networks 106a, 106b can be used with Fig.11 The IM feedback circuit 122 and / or Fig.12The output matching feedback circuit 124 may be used with or without it.

[0117] Embodiments of the present invention may be manufactured as integrated circuits (ICs), which may be packaged in IC packages and / or in modules for ease of processing, manufacturing and / or improved performance. In particular, IC embodiments of the present invention are typically used in modules in which one or more of such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possible additional ICs) into a package. The ICs and / or modules are then typically combined with other components (typically on a printed circuit board) to form part of a final product such as a cellular phone, a notebook computer, or an electronic tablet, or to form an advanced module that can be used in a variety of products (e.g., vehicles, test equipment, medical devices, etc.). Through various configurations of modules and components, such ICs typically implement a communication mode, typically wireless communication.

[0118] As an example of further integration of embodiments of the present invention with other components, Fig.13 1 is a top view of a substrate 1300, which may be, for example, a printed circuit board or a die module substrate (e.g., a tile). In the example shown, the substrate 1300 includes a plurality of ICs 1302a to 1302d having terminal pads 1304 that are interconnected by conductive vias and / or traces on and / or within the substrate 1300 or on an opposing (rear) surface of the substrate 1300 (to avoid clutter, surface conductive traces are not shown and not all terminal pads are labeled). The ICs 1302a to 1302d may include, for example, signal switches, active filters, amplifiers (including one or more LNAs), and other circuitry. For example, the IC 1302b may be combined with a plurality of ICs 1302a to 1302d such as the IC 1302b shown in FIG. Figure 1 and Figure 2 One or more examples of LNAs of the LNA circuits 100 , 200 shown in FIG.

[0119] The substrate 1300 may also include one or more passive devices 1306 embedded in, formed on, and / or attached to the substrate 1300. Although shown as a general rectangle, the passive device 1306 may be, for example, a filter, a capacitor, an inductor, a transmission line, a resistor, a planar antenna element, a transducer (including, for example, a MEMS-based transducer such as an accelerometer, a gyroscope, a microphone, a pressure sensor, etc.), a battery, etc., interconnected with other passive devices 1306 and / or individual ICs 1302a to 1302d via conductive traces on or in the substrate 1300.

[0120] The front or back surface of substrate 1300 may be used as a location for forming other structures. For example, one or more antennas may be formed on or attached to the front or back surface of substrate 1300; one example of a front surface antenna 1308 is shown coupled to IC die 1302b, which may include RF front end circuitry. Thus, by including one or more antennas on substrate 1300, a complete radio may be created.

[0121] System

[0122] Embodiments of the present invention may be used in a variety of larger radio frequency (RF) circuits and systems for performing a range of functions, including (but not limited to) impedance matching circuits, RF power amplifiers, RF low noise amplifiers (LNAs), phase shifters, attenuators, antenna beam control systems, charge pump devices, RF switches, etc. These functions may be used in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.

[0123] Radio system uses include wireless RF systems (including base stations, relay stations, and handheld transceivers) using various technologies and protocols, including various types of Orthogonal Frequency Division Multiplexing ("OFDM"), Quadrature Amplitude Modulation ("QAM"), Code Division Multiple Access ("CDMA"), Time Division Multiple Access ("TDMA"), Wideband Code Division Multiple Access ("W-CDMA"), Global System for Mobile Communications ("GSM"), Long Term Evolution ("LTE"), 5G, 6G and WiFi (e.g., 802.11a, b, g, ac, ax, be) protocols, and other radio communication standards and protocols.

[0124] As an example of the use of wireless RF systems, FIG14 shows an exemplary prior art wireless communication environment 1400, which includes different wireless communication systems 1402 and 1404, and which may include one or more mobile wireless devices 1406. Wireless device 1406 may be a cellular phone, a wireless-enabled computer or tablet, or some other wireless communication unit or device. Wireless device 1406 may also be referred to as a mobile station, user equipment, access terminal, or some other terminology known in the telecommunications industry.

[0125] The wireless device 1406 may be capable of communicating with multiple wireless communication systems 1402, 1404 using one or more of the telecommunication protocols such as those described above. The wireless device 1406 may also be capable of communicating with one or more satellites 1408, such as navigation satellites (e.g., GPS) and / or communication satellites. The wireless device 1406 may be equipped with multiple antennas externally and / or internally for operating at different frequencies and / or to provide diversity against harmful path effects such as fading and multipath interference.

[0126] The wireless communication system 1402 may be, for example, a CDMA-based system including one or more base transceiver stations (BSTs) 1410 and at least one switching center (SC) 1412. Each BST 1410 provides over-the-air RF communications for wireless devices 1406 within its coverage area. The SC 1412 is coupled to one or more BSTs in the wireless system 1402 and provides coordination and control for these BSTs 1410.

[0127] The wireless communication system 1404 may be, for example, a TDMA-based system including one or more transceiver nodes 1414 and a network center (NC) 1416. Each transceiver node 1414 provides over-the-air RF communications for wireless devices 1406 within its coverage area. The NC 1416 is coupled to one or more transceiver nodes 1414 in the wireless system 1404 and provides coordination and control for these transceiver nodes 1414.

[0128] Typically, each BST 1410 and transceiver node 1414 is a fixed station that provides communication coverage for wireless devices 1406, and may also be referred to as a base station or some other terminology known in the telecommunications industry. SC 1412 and NC 1416 are network entities that provide coordination and control for the base stations, and may also be referred to by other terms known in the telecommunications industry.

[0129] An important aspect of any wireless system, including the system shown in FIG. 14, lies in the details of how the constituent elements of the system perform. Fig.151 is a block diagram of a transceiver 1500 that can be used in a wireless device such as a cellular telephone, and the transceiver 1500 can be beneficially combined with embodiments of the present invention for improved performance. As shown, the transceiver 1500 includes a mix of RF analog circuitry for transmitting and / or transforming signals directly on an RF signal path, non-RF analog circuitry for operating requirements outside the RF signal path (e.g., for bias voltages and switching signals), and digital circuitry for control and user interface requirements. In this example, the receiver path Rx includes an RF front end portion, an intermediate frequency (IF) block portion, a back end portion, and a baseband portion (note that in some implementations, the distinction between the portions may be different). The various illustrated portions and circuit elements can be embodied in one die or multiple IC dies. For example, the RF front end in the illustrated example may include an RFFE module and a hybrid block, which may be embodied in (or as part of) different IC dies or modules. The different dies and / or modules can be connected to each other via transmission lines T IN and T OUT (e.g., microstrip, coplanar waveguide, or equivalent structure or circuit) coupling, one or both of which may have an impedance of, for example, 50Ω.

[0130] The receiver path Rx receives the air RF signal via at least one antenna 1502 and a switching unit 1504, which may be implemented using active switching devices (e.g., field effect transistors or FETs) and / or using passive devices that implement frequency domain multiplexing, such as diplexers or duplexers. The RF filter 1506 passes the desired received RF signal to at least one low noise amplifier (LNA) 1508a, the output of which is coupled from the RFFE module to at least one LNA 1508b in the hybrid block (in this example via a transmission line T IN ). LNA1508b can provide buffering, input matching and reverse isolation. LNA1508a, 1508b can be Figure 1 , Figure 2 , Fig. 6A , Figure 7 and Figure 8 An example of any one of the LNAs disclosed in.

[0131] The output of LNA 1508b is combined with the output of first local oscillator 1512 in corresponding mixer 1510 to produce IF signal. The IF signal may be applied to demodulator 1518 after being amplified by IF amplifier 1514 and passing through IF filter 1516, which may be coupled to second local oscillator 1520. The demodulated output of demodulator 1518 is converted into digital signal by analog-to-digital converter (ADC) 1522 and provided to one or more system components 1524 (e.g., video graphics circuit, sound circuit, memory device, etc.). The converted digital signal may represent, for example, video or still image, sound, or symbol (e.g., text or other characters).

[0132] In the example shown, the transmitter path Tx includes a baseband section, a backend section, an IF block section, and an RF front end section (again, in some implementations, the distinction between the sections may be different). Digital data from one or more system components 1524 is converted into an analog signal by a digital-to-analog converter 1526, and the output of the digital-to-analog converter 1526 is applied to a modulator 1528, which may also be coupled to a second local oscillator 1520. The modulated output of the modulator 1528 may be amplified by an IF amplifier 1532 after passing through an IF filter 1530. The output of the IF amplifier 1532 is then combined with the output of the first local oscillator 1512 in a mixer 1534 to produce an RF signal. The RF signal may be amplified by a driver 1536, and the output of the driver 1536 is coupled to a power amplifier (PA) 1538 (in this example via a transmission line T OUT ). The amplified RF signal may be coupled to the RF filter 1540 , and the output of the RF filter 1540 may be coupled to at least one antenna 1502 via the switch unit 1504 .

[0133] The operation of the transceiver 1500 is controlled in a known manner by a microprocessor 1542, which interacts with system control components 1544 (e.g., user interface, memory / storage, applications, operating system software, power control, etc.). In addition, the transceiver 1500 will typically include other circuitry, such as bias circuitry 1546 (which may be distributed throughout the transceiver 1500 near the transistor devices), electrostatic discharge (ESD) protection circuitry, test circuitry (not shown), a factory programming interface (not shown), etc.

[0134] In modern transceivers, there are typically more than one receiver path Rx and transmitter path Tx, for example, to accommodate multiple frequencies and / or signaling modalities. In addition, it should be apparent to one of ordinary skill in the art that some components of the transceiver 1500 may be positioned in a different order (e.g., filters) or omitted. Other components may (and often are) added, such as (by way of example only) additional filters, impedance matching networks, variable phase shifters / attenuators, power dividers, etc.

[0135] As discussed above, the present invention provides improved IC area savings, manufacturing cost savings, wider impedance matching bandwidth, and flatter gain response of amplifier circuit modules or blocks. Those skilled in the art will appreciate that system architectures are beneficially impacted by the present invention in key aspects, including better dynamic range, better sensitivity, lower cost, and wider bandwidth. In order to comply with system standards or customer requirements, the present invention is therefore Fig.15 The overall solution shown is of crucial importance. Therefore, the present invention specifically defines the system-level embodiments that are creatively enabled by including it in the system.

[0136] method

[0137] Another aspect of the present invention includes a method for broadband input impedance matching of an amplifier core having an amplifier input terminal, an amplified signal terminal, and a degeneration terminal, the amplifier input terminal being configured to receive a radio frequency (RF) signal. For example, Fig.16 1600 is a process flow diagram illustrating a first method for providing broadband input impedance matching for an amplifier core. The method includes: coupling a first inductor between a first terminal and a first node, the first terminal being configured to be coupled to a degeneration terminal of the amplifier core (block 1602); coupling a second inductor between a second terminal and the first node, the second terminal being configured to be coupled to an amplifier input terminal of the amplifier core (block 1604); and coupling a third inductor between the first node and a third terminal, the third terminal being configured to be coupled to a reference potential (block 1606); coupling the first inductor and the second inductor to each other (block 1608).

[0138] As another example, Fig.171700 is a process flow diagram illustrating a second method of providing broadband input impedance matching for an amplifier core. The method includes: coupling a first inductor between a first terminal and a first node, the first terminal being configured to be coupled to a degeneration terminal of the amplifier core (block 1702); coupling a second inductor between a second terminal and a second node, the second terminal being configured to be coupled to an amplifier input terminal of the amplifier core (block 1704); coupling a third inductor between the first node and a third terminal, the third terminal being configured to be coupled to a reference potential (block 1706); coupling a fourth inductor between the second node and a fourth terminal, the fourth terminal being configured to be coupled to a reference potential (block 1708); and coupling the first inductor and the second inductor to each other (block 1710).

[0139] Other aspects of the above method may include one or more of the following: wherein the mutual coupling of the first inductor and the second inductor is negative; wherein the mutual coupling of the first inductor and the second inductor is positive; wherein the amplifier core, the first inductor and the second inductor are jointly manufactured on an integrated circuit die; wherein the amplifier core is manufactured on the integrated circuit die and the first inductor and the second inductor are located outside the integrated circuit die; wherein the first inductor includes a plurality of parallel inductors; wherein the first inductor and the second inductor include mutually coupled sections of an integrated circuit transformer coil; wherein the first inductor includes a first optional inductor coupled in series with a second optional inductor; further comprising a series inductor coupled between an input terminal of the amplifier core and a radio frequency input terminal of the amplifier core, wherein a second terminal of the broadband input impedance matching network is configured to be coupled to an output terminal of the amplifier core through the series inductor; and / or wherein the second inductor and the first optional inductor are mutually coupled in a first optional state, and the second inductor and the series sum of the first optional inductor and the second optional inductor are mutually coupled in a second optional state.

[0140] Manufacturing technology and selection

[0141] Although the example embodiment is an LNA, the circuits and methods of the present invention may also be applied to other types of amplifiers such as power amplifiers.

[0142] For clarity, other well-known circuit elements that may be included in some applications, such as DC blocking capacitors, additional impedance matching circuitry, and additional filters, are omitted. Note also that a circuit component characterized as "adjustable" may have its value selected from a number of possible component value settings and may be fixed during manufacturing, when assembled in a circuit module, during factory testing, or in the field (e.g., by burning or "blowing" a fusible link), or may have its value dynamically changed, adjusted, or programmatically set, for example, in response to other circuitry (e.g., temperature compensation and / or power idle circuitry) or in response to a generated or received command signal.

[0143] The operating mode of the LNA circuit of the present invention can be set by a control circuit (not shown) in a known manner. The control circuit can also be connected to the adjustable components to, for example, select different component values ​​(e.g., capacitors, resistors, inductors) for different gain states to help input and / or output impedance matching or to change the relationship between gain and linearity and / or NF in some operating modes.

[0144] As used in the present disclosure, the term "MOSFET" includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and includes insulated gates having metal or metalloid, insulator and / or semiconductor structures. The terms "metal" or "metalloid" include at least one conductive material (e.g., aluminum, copper or other metal or highly doped polysilicon, graphene or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material); and "semiconductor" includes at least one semiconductor material.

[0145] As used in this disclosure, the term "radio frequency" (RF) refers to oscillation rates in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequency of electromagnetic waves or the frequency of alternating voltage or current in an electrical circuit.

[0146] With respect to the drawings cited in this disclosure, the sizes of the various elements are not to scale; some dimensions may be greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., "top," "bottom," "above," "below," "lateral," "vertical," "horizontal," etc.) are relative to the example drawings and are not necessarily absolute orientations or directions.

[0147] Various embodiments of the present invention can be implemented to meet a variety of specifications. Unless otherwise specified above, the selection of suitable component values ​​is a matter of design choice. Various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structure) or hybrid or discrete circuit form. Any suitable substrate and process (including but not limited to standard bulk silicon, high resistivity bulk CMOS, silicon on insulator (SOI) and silicon on sapphire (SOS)) can be used to manufacture integrated circuit embodiments. Unless otherwise specified above, embodiments of the present invention can be implemented in other transistor technologies, such as bipolar transistors, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAspHEMT and MESFET technology. However, embodiments of the present invention are particularly useful when using SOI or SOS-based process manufacturing or when using processes with similar characteristics. The manufacture of SOI or SOS processes in CMOS enables circuits to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., up to and exceeding 300GHz radio frequency). Monolithic IC implementations are particularly useful because, through careful design, parasitic capacitances can generally be kept low (or at least consistent across all units, allowing them to be compensated for).

[0148] Voltage levels may be adjusted, and / or voltage and / or logic signal polarity may be reversed, depending on the particular specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adjusted as needed, such as by adjusting device size, "stacking" components (particularly FETs) in series to withstand higher voltages, and / or using multiple components in parallel to handle higher currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly changing the functionality of the disclosed circuits.

[0149] in conclusion

[0150] A number of embodiments of the present invention have been described. It should be appreciated that various modifications may be made without departing from the spirit and scope of the present invention. For example, some of the steps described above may be order-independent and therefore may be performed in an order different from that described. In addition, some of the steps described above may be optional. The various activities described with respect to the methods identified above may be performed in a repetitive, serial, and / or parallel manner.

[0151] It should be understood that the above description is intended to illustrate, but not to limit, the scope of the invention, which is defined by the scope of the appended claims, and other embodiments also fall within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or components of matter set forth in the appended claims. (Note that parenthetical markings of claim elements are for convenience of reference to such elements and do not, by themselves, indicate a particular required order or enumeration of the elements; furthermore, such markings may be repeated in dependent claims as references to additional elements without being considered as starting a conflicting marking sequence).

Claims

1. A broadband coupled input impedance matching network, comprising: (a) a first inductor coupled between a first terminal and a first node, the first terminal being configured to be coupled to a degeneration terminal of an amplifier core; (b) a second inductor coupled between a second terminal and the first node, the second terminal being configured to be coupled to an input terminal of the amplifier core; as well as (c) a third inductor coupled between the first node and a third terminal, the third terminal being configured to be coupled to a reference potential; The first inductor and the second inductor are coupled to each other.

2. The invention according to claim 1, wherein: The mutual coupling of the first inductor and the second inductor is negative.

3. The invention according to claim 1, wherein: The mutual coupling between the first inductor and the second inductor is positive.

4. The invention according to claim 1, wherein: The amplifier core, the first inductor, and the second inductor are fabricated together on an integrated circuit die.

5. The invention according to claim 1, wherein: The amplifier core is fabricated on an integrated circuit die, and the first inductor and the second inductor are located external to the integrated circuit die.

6. The invention according to claim 1, wherein: The first inductor includes a plurality of parallel inductors.

7. The invention according to claim 1, wherein: The first inductor and the second inductor comprise mutually coupled sections of an integrated circuit transformer coil.

8. The invention according to claim 1, wherein: The first inductor includes a first selectable inductance coupled in series with a second selectable inductance.

9. The invention according to claim 8, wherein: In a first selectable state, the second inductor and the first selectable inductor are coupled to each other, and in a second selectable state, the second inductor and a series sum of the first selectable inductor and the second selectable inductor are coupled to each other.

10. The invention of claim 1 further comprising a series inductor coupled between the input terminal of the amplifier core and a radio frequency input terminal of the amplifier core, wherein: The second terminal of the broadband input impedance matching network is configured to be coupled to the input terminal of the amplifier core through the series inductor.

11. A broadband coupled input impedance matching network, comprising: (a) a first inductor coupled between a first terminal and a first node, the first terminal being configured to be coupled to a degeneration terminal of an amplifier core; (b) a second inductor coupled between a second terminal and a second node, the second terminal being configured to be coupled to an input terminal of the amplifier core; (c) a third inductor coupled between the first node and a third terminal, the third terminal being configured to be coupled to a reference potential; as well as (d) a fourth inductor coupled between the second node and a fourth terminal, the fourth terminal being configured to be coupled to the reference potential; The first inductor and the second inductor are coupled to each other.

12. The invention according to claim 10, wherein: The mutual coupling of the first inductor and the second inductor is negative.

13. The invention according to claim 10, wherein: The mutual coupling between the first inductor and the second inductor is positive.

14. The invention according to claim 10, wherein: The amplifier core, the first inductor, and the second inductor are fabricated together on an integrated circuit die.

15. The invention according to claim 10, wherein: The amplifier core is fabricated on an integrated circuit die, and the first inductor and the second inductor are located external to the integrated circuit die.

16. The invention according to claim 10, wherein: The first inductor includes a plurality of parallel inductors.

17. The invention according to claim 10, wherein: The first inductor and the second inductor comprise mutually coupled sections of an integrated circuit transformer coil.

18. The invention according to claim 10, wherein: The first inductor includes a first selectable inductance coupled in series with a second selectable inductance.

19. The invention according to claim 18, wherein: In a first selectable state, the second inductor and the first selectable inductor are coupled to each other, and in a second selectable state, the second inductor and a series sum of the first selectable inductor and the second selectable inductor are coupled to each other.

20. The invention of claim 10, further comprising a series inductor coupled between the input terminal of the amplifier core and a radio frequency input terminal of the amplifier core, wherein: The second terminal of the broadband input impedance matching network is configured to be coupled to the input terminal of the amplifier core through the series inductor.

21. An amplifier, comprising: (a) an amplifier core, the amplifier core comprising: (1) an amplifier input terminal configured to receive a radio frequency (RF) signal; (2) amplifying the signal terminal; and (3) Degraded terminals; and (b) a broadband input impedance matching network, the broadband input impedance matching network comprising: (1) a first inductor, the first inductor being coupled between a first terminal and a first node, the first terminal being configured to be coupled to the degeneration terminal; (2) a second inductor coupled between a second terminal and the first node, the second terminal being configured to be coupled to the amplifier input terminal; and (3) a third inductor coupled between the first node and a third terminal, wherein the third terminal is configured to be coupled to a reference potential; The first inductor and the second inductor are coupled to each other.

22. The invention according to claim 21, wherein: The mutual coupling of the first inductor and the second inductor is negative.

23. The invention according to claim 21, wherein: The mutual coupling between the first inductor and the second inductor is positive.

24. The invention according to claim 21, wherein: The amplifier core, the first inductor, and the second inductor are fabricated together on an integrated circuit die.

25. The invention according to claim 21, wherein: The amplifier core is fabricated on an integrated circuit die, and the first inductor and the second inductor are located external to the integrated circuit die.

26. The invention according to claim 21, wherein: The first inductor includes a plurality of parallel inductors.

27. The invention according to claim 21, wherein: The first inductor and the second inductor comprise mutually coupled sections of an integrated circuit transformer coil.

28. The invention according to claim 21, wherein: The first inductor includes a first selectable inductance coupled in series with a second selectable inductance.

29. The invention according to claim 28, wherein: In a first selectable state, the second inductor and the first selectable inductor are coupled to each other, and in a second selectable state, the second inductor and a series sum of the first selectable inductor and the second selectable inductor are coupled to each other.

30. The invention of claim 21 further comprising a series inductor coupled between an input terminal of the amplifier core and a radio frequency input terminal of the amplifier core, wherein: The second terminal of the broadband input impedance matching network is configured to be coupled to the input terminal of the amplifier core through the series inductor.

31. The invention according to claim 21, wherein: The amplifier is a low noise amplifier.

32. The invention according to claim 21, wherein: The amplifier is implemented as an integrated circuit fabricated in silicon-on-insulator technology and includes MOS devices.

33. The invention according to claim 21, wherein: The amplifier is implemented as an integrated circuit assembled in a circuit module.

34. The invention according to claim 21, wherein: The amplifier is implemented as an integrated circuit comprising a part of a communication device.

35. The invention of claim 21, wherein: The amplifier core also includes an output impedance matching network coupled to the amplified signal terminal.

36. The invention of claim 21, wherein: The amplifier core also includes a feedback node in an output signal path of the amplifier core, and also includes an input feedback circuit coupled between the amplifier input terminal and the feedback node.

37. The invention according to claim 36, wherein: The input feedback circuit is selectively switchable between an enabled state and a disabled state.

38. The invention of claim 21, wherein: The amplifier core also includes a feedback node in an output signal path of the amplifier core, and further includes an output feedback circuit coupled between the feedback node and a gate of a common-gate-on FET within the amplifier core.

39. The invention according to claim 38, wherein: The output feedback circuit is selectively switchable between an enabled state and a disabled state.

40. The invention of claim 21, wherein: The amplifier core also includes: (a) a common-source FET having a gate, a source and a drain, the gate being coupled to the amplifier input terminal; (b) a stack comprising at least one common-gate FET, each common-gate FET having a gate, a source, and a drain, the drain outputting an amplified version of the received RF signal, wherein the source of one of the at least one common-gate FET is coupled to the drain of the common-source FET, and wherein the drain of one of the at least one common-gate FET is coupled to the amplified signal terminal of the stack.

41. An amplifier, comprising: (a) an amplifier core, the amplifier core comprising: (1) an amplifier input terminal configured to receive a radio frequency (RF) signal; (2) amplifying the signal terminal; and (3) Degraded terminals; and (b) a broadband input impedance matching network, the broadband input impedance matching network comprising: (1) a first inductor, the first inductor being coupled between a first terminal and a first node, the first terminal being configured to be coupled to the degeneration terminal; (2) a second inductor coupled between a second terminal and a second node, the second terminal being configured to be coupled to the amplifier input terminal; (3) a third inductor coupled between the first node and a third terminal, the third terminal being configured to be coupled to a reference potential; and (4) a fourth inductor coupled between the second node and a fourth terminal, wherein the fourth terminal is configured to be coupled to the reference potential; The first inductor and the second inductor are coupled to each other.

42. The invention according to claim 41, wherein: The mutual coupling of the first inductor and the second inductor is negative.

43. The invention according to claim 41, wherein: The mutual coupling between the first inductor and the second inductor is positive.

44. The invention according to claim 41, wherein: The amplifier core, the first inductor, and the second inductor are fabricated together on an integrated circuit die.

45. The invention of claim 41, wherein: The amplifier core is fabricated on an integrated circuit die, and the first inductor and the second inductor are located external to the integrated circuit die.

46. ​​The invention of claim 41, wherein: The first inductor includes a plurality of parallel inductors.

47. The invention of claim 41, wherein: The first inductor and the second inductor comprise mutually coupled sections of an integrated circuit transformer coil.

48. The invention of claim 41, wherein: The first inductor includes a first selectable inductance coupled in series with a second selectable inductance.

49. The invention of claim 48, wherein: In a first selectable state, the second inductor and the first selectable inductor are coupled to each other, and in a second selectable state, the second inductor and a series sum of the first selectable inductor and the second selectable inductor are coupled to each other.

50. The invention of claim 41 further comprising a series inductor coupled between an input terminal of the amplifier core and a radio frequency input terminal of the amplifier core, wherein: A second terminal of the broadband input impedance matching network is configured to be coupled to the input terminal of the amplifier core through the series inductor.

51. The invention of claim 41, wherein: The amplifier is a low noise amplifier.

52. The invention of claim 41, wherein: The amplifier is implemented as an integrated circuit fabricated in silicon-on-insulator technology and includes MOS devices.

53. The invention of claim 41, wherein: The amplifier is implemented as an integrated circuit assembled in a circuit module.

54. The invention of claim 41, wherein: The amplifier is implemented as an integrated circuit comprising a part of a communication device.

55. The invention of claim 41, wherein: The amplifier core also includes an output impedance matching network coupled to the amplified signal terminal.

56. The invention of claim 41, wherein: The amplifier core also includes a feedback node in an output signal path of the amplifier core, and also includes an input feedback circuit coupled between the amplifier input terminal and the feedback node.

57. The invention of claim 56, wherein: The input feedback circuit is selectively switchable between an enabled state and a disabled state.

58. The invention of claim 41, wherein: The amplifier core also includes a feedback node in an output signal path of the amplifier core, and further includes an output feedback circuit coupled between the feedback node and a gate of a common-gate-on FET within the amplifier core.

59. The invention of claim 58, wherein: The output feedback circuit is selectively switchable between an enabled state and a disabled state.

60. The invention of claim 41, wherein: The amplifier core also includes: (a) a common-source FET having a gate, a source and a drain, the gate being coupled to the amplifier input terminal; (b) a stack comprising at least one common-gate FET, each common-gate FET having a gate, a source, and a drain, the drain outputting an amplified version of the received RF signal, wherein the source of one of the at least one common-gate FET is coupled to the drain of the common-source FET, and wherein the drain of one of the at least one common-gate FET is coupled to the amplified signal terminal of the stack.

61. A method of providing broadband input impedance matching for an amplifier core, the amplifier core having an amplifier input terminal, an amplified signal terminal, and a degeneration terminal, the amplifier input terminal being configured to receive a radio frequency (RF) signal, the method comprising: (a) coupling a first inductor between a first terminal and a first node, the first terminal being configured to be coupled to the degeneration terminal; (b) coupling a second inductor between a second terminal and the first node, the second terminal being configured to be coupled to the amplifier input terminal; (c) coupling a third inductor between the first node and a third terminal, the third terminal being configured to be coupled to a reference potential; as well as (d) coupling the first inductor and the second inductor to each other.

62. A method of providing broadband input impedance matching for an amplifier core, the amplifier core having an amplifier input terminal, an amplified signal terminal, and a degeneration terminal, the amplifier input terminal being configured to receive a radio frequency (RF) signal, the method comprising: (a) coupling a first inductor between a first terminal and a first node, the first terminal being configured to be coupled to the degeneration terminal; (b) coupling a second inductor between a second terminal and a second node, the second terminal being configured to be coupled to the amplifier input terminal; (c) coupling a third inductor between the first node and a third terminal, the third terminal being configured to be coupled to a reference potential; (d) coupling a fourth inductor between the second node and a fourth terminal, the fourth terminal being configured to be coupled to a reference potential; as well as (e) coupling the first inductor and the second inductor to each other.

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