Conductive element, display device, and method of manufacturing display device

Abstract

The conductive element includes: a first semiconductor layer adjacent to a first end portion of the conductive element; a second semiconductor layer adjacent to a second end portion of the conductive element; an active layer disposed between the first semiconductor layer and the second semiconductor layer; an element insulating film covering the active layer and exposing the first end portion and the second end portion; and a conductive pattern layer disposed on the element insulating film.

Description

Technical Field

[0001] Various embodiments relate to a conductive element, a display device, and methods of manufacturing the conductive element and the display device. Background Art

[0002] Recently, as interest in information display increases, research and development of display devices have been continuously conducted. Summary of the invention

[0003] Technical issues

[0004] Various embodiments are directed to a conductive element that emits light or serves as an electrical connection, a display device including the conductive element, and a method of manufacturing the display device.

[0005] However, the embodiments of the disclosure are not limited to the embodiments set forth herein. The above and other embodiments will become more apparent to those skilled in the art to which the disclosure pertains by referring to the detailed description of the disclosure given below.

[0006] Technical Solution

[0007] One or more embodiments may provide a conductive element, comprising: a first semiconductor layer adjacent to a first end of the conductive element; a second semiconductor layer adjacent to a second end of the conductive element; an active layer disposed between the first semiconductor layer and the second semiconductor layer; an element insulating layer covering the active layer and exposing the first end and the second end; and a conductive pattern layer disposed on the element insulating layer.

[0008] In one or more embodiments, the conductive pattern layer may surround the element insulating layer in a cross-sectional direction of the conductive element. The cross-sectional direction may be different from a direction from the first end toward the second end.

[0009] In one or more embodiments, the conductive pattern layer may include a conductive material, and may be electrically insulated from the first semiconductor layer, the second semiconductor layer, and the active layer by the element insulating layer.

[0010] In one or more embodiments, the conductive pattern layer may expose a first portion of the element insulating layer adjacent to the first end portion and a second portion of the element insulating layer adjacent to the second end portion.

[0011] In one or more embodiments, the conductive pattern layer may have a thickness in the range of about 200 nm to about 350 nm.

[0012] In one or more embodiments, the conductive element may have a first length in a direction from the first end toward the second end. The conductive pattern layer may have a second length in a direction from the first end toward the second end. The ratio of the first length to the second length may be in a range of about 1.3 to about 1.6.

[0013] One or more embodiments may provide a display device, the display device comprising: a pad line, which is arranged on a base layer in a pad area and includes a first alignment pad line and a second alignment pad line; a conductive element, including at least a portion arranged on the first alignment pad line and the second alignment pad line; and a chip on film, including a first portion electrically connected to the conductive element and a second portion electrically connected to the flexible circuit assembly. The conductive element may include: a first semiconductor layer, adjacent to a first end of the conductive element; a second semiconductor layer, adjacent to a second end of the conductive element; an active layer, arranged between the first semiconductor layer and the second semiconductor layer; an element insulating layer, covering the active layer and exposing the first end and the second end; and a conductive pattern layer, arranged on the element insulating layer. The conductive pattern layer can electrically connect the pad line to the chip on film.

[0014] In one or more embodiments, the first alignment pad line and the second alignment pad line may be spaced apart from each other.The conductive element may include a plurality of conductive elements disposed between the first alignment pad line and the second alignment pad line.

[0015] In one or more embodiments, the conductive pattern layer may physically contact at least a portion of the pad line.

[0016] In one or more embodiments, the pad line may include a first connection pad line and a second connection pad line, the first connection pad line is on the first alignment pad line, and the second connection pad line is on the second alignment pad line. The first alignment pad line and the second alignment pad line may be spaced apart from each other. The first portion of the conductive pattern layer may physically contact the first connection pad line, and the second portion of the conductive pattern layer may physically contact the second connection pad line.

[0017] In one or more embodiments, a distance between the first alignment pad line and the second alignment pad line may be smaller than a length of the conductive pattern layer.

[0018] In one or more embodiments, the display device may also include: a non-conductive bonding layer, which bonds the chip on the film to at least some of the components arranged on the base layer; and a conductive connector, which is arranged between the chip on the film and the conductive pattern layer, and electrically connects the chip on the film to the conductive pattern layer.

[0019] In one or more embodiments, the display device may further include: electrodes disposed on the base layer in the display area, each electrode including a first electrode and a second electrode. A portion of the conductive element may be aligned between the first electrode and the second electrode to emit light in the display area.

[0020] In one or more embodiments, the display device may further include: a first insulating layer disposed on the first electrode and the second electrode; and an insulating pattern layer disposed on the first insulating layer and protruding in a thickness direction of the base layer.

[0021] In one or more embodiments, the display device may further include: a first connection electrode electrically connected to the first end of the conductive element in the display area; and a second connection electrode electrically connected to the second end of the conductive element in the display area. The first connection electrode and the second connection electrode may be electrically insulated from the conductive pattern layer.

[0022] In one or more embodiments, the display device may further include: a first connection electrode electrically connected to the first end of the conductive element in the display area; and a second connection electrode electrically connected to the second end of the conductive element in the display area. The first connection electrode and the second connection electrode may be electrically insulated from the conductive pattern layer and formed from the same layer.

[0023] In one or more embodiments, the display device may further include: a first insulating layer disposed on the first electrode and the second electrode. The conductive element in the display area and the first insulating layer may form an empty space in an area where the conductive pattern layer is not disposed.

[0024] In one or more embodiments, the display device may further include: a second insulating layer, a conductive pattern layer completely covering the conductive element in the display area.

[0025] One or more embodiments may provide a display device, the display device comprising: a first electrode and a second electrode, disposed on a substrate layer; a conductive element, disposed on the first electrode and the second electrode; a first connection electrode, electrically connected to a first end of the conductive element; and a second connection electrode, electrically connected to a second end of the conductive element. The conductive element may include: a first semiconductor layer, adjacent to the first end; a second semiconductor layer, adjacent to the second end; an active layer, disposed between the first semiconductor layer and the second semiconductor layer; an element insulating layer, covering the active layer and exposing the first end and the second end; and a conductive pattern layer, disposed on the element insulating layer.

[0026] One or more embodiments may provide a display device, comprising: a pad wire disposed on a base layer; a plurality of conductive elements electrically connected to the pad wire; a chip on film comprising a first portion electrically connected to the plurality of conductive elements and a second portion electrically connected to a flexible circuit component; and a non-conductive bonding layer bonding the chip on film to some of the components disposed on the base layer.

[0027] One or more embodiments may provide a method for manufacturing a display device, the method comprising: providing electrodes on a base layer including a pad region and a display region, the electrodes including an alignment pad line provided in the pad region and an alignment electrode provided in the display region; providing a conductive element on the alignment electrode in the display region; patterning a connection electrode on the base layer; providing a conductive element on the alignment pad line in the pad region; and electrically connecting a chip on film to the conductive element in the pad region. The chip on film may be electrically connected to a flexible circuit assembly.

[0028] In one or more embodiments, the step of setting a conductive element in the display area may include: supplying ink including the conductive element to the base layer; applying an alignment signal to each of the electrodes; and aligning the conductive element on the electrode by an electric field formed by the alignment signal.

[0029] In one or more embodiments, the apparatus for disposing the conductive element in the display region can be substantially the same as the apparatus for disposing the conductive element in the pad region.

[0030] In one or more embodiments, patterning the connection electrodes may include: patterning first and second connection electrodes electrically connected to the conductive elements in the display area; and patterning connection pad lines on the alignment pad lines in the pad area.

[0031] In one or more embodiments, each of the conductive elements may include: a first semiconductor layer adjacent to a first end of each conductive element; a second semiconductor layer adjacent to a second end of each conductive element; an active layer disposed between the first semiconductor layer and the second semiconductor layer; an element insulating layer covering the active layer and exposing the first end and the second end; and a conductive pattern layer disposed on the element insulating layer. The step of disposing the conductive element in the pad region may include disposing a connection pad line in contact with the conductive pattern layer.

[0032] In one or more embodiments, the step of electrically connecting the chip on film to the conductive element in the pad region may include electrically connecting the conductive pattern layer to the chip on film through a conductive connector.

[0033] Beneficial Effects

[0034] Various embodiments may provide a conductive element that emits light or serves as an electrical connector. For example, the conductive element may serve as a light-emitting element in the display region. The conductive element may serve as a pad connector in the pad region. Thus, the corresponding processes in the display region and the pad region may be integrated with each other, thereby enhancing processability. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic perspective view illustrating a conductive element according to one or more embodiments.

[0036] Figure 2 is a schematic cross-sectional view illustrating a conductive element according to one or more embodiments.

[0037] Figure 3 is a schematic perspective view illustrating a display device according to one or more embodiments.

[0038] Figure 4 is a schematic plan view illustrating a display device according to one or more embodiments.

[0039] Figure 5 is a schematic block diagram for describing an electrical connection structure of conductive elements in a display area according to one or more embodiments.

[0040] Figure 6 is a schematic plan view illustrating a sub-pixel according to one or more embodiments.

[0041] Figures 7 to 10 are schematic cross-sectional views each illustrating a sub-pixel according to one or more embodiments.

[0042] Fig.11 is a schematic cross-sectional view illustrating a pixel according to one or more embodiments.

[0043] Fig.12 is a schematic cross-sectional view illustrating a sub-pixel according to one or more embodiments.

[0044] Fig.13 is a schematic block diagram for describing an electrical connection structure of conductive elements in a pad region according to one or more embodiments.

[0045] Fig.14 and Fig.15 is a schematic diagram illustrating a pad area according to one or more embodiments.

[0046] Fig.16 is a schematic flowchart illustrating a method of manufacturing a display device according to one or more embodiments.

[0047] Figures 17 to 24is a schematic diagram illustrating a method of manufacturing a display device according to one or more embodiments through process steps. DETAILED DESCRIPTION

[0048] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various embodiments or implementations of the invention. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the device or method disclosed herein. However, it is clear that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not have to be exclusive, nor do they have to limit disclosure. For example, the specific shape, configuration and characteristics of the embodiment can be used or implemented in another embodiment.

[0049] Unless otherwise specified, the illustrated embodiments will be understood to provide features of the invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the invention.

[0050] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the shown elements, and / or any other characteristics, attributes, properties, etc. of the element. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When embodiments may be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0051] When an element, such as a layer, is referred to as being "on," "connected to," or "bonded to" another element or layer, it may be directly on, directly connected to, or directly bonded to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements. In addition, the DR1 axis, the DR2 axis, and the DR3 axis are not limited to the three axes of a rectangular coordinate system (such as the X-axis, the Y-axis, and the Z-axis), and may be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and the DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. In addition, the X-axis, the Y-axis, and the Z-axis are not limited to the three axes of a rectangular coordinate system (such as the X-axis, the Y-axis, and the Z-axis), and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of A and B" may be interpreted as being understood to represent only A, only B, or any combination of A and B. In addition, "at least one of X, Y, and Z" and "at least one of the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term "and / or" includes any combination and all combinations of one or more of the related listed items.

[0052] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the disclosed teachings, the first element discussed below may be referred to as the second element.

[0053] For descriptive purposes, spatially relative terms such as "below," "beneath," "under," "lower," "above," "upper," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein to describe the relationship of one element to another element(s) as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, the spatially relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, then elements described as "below" or "beneath" other elements or features will subsequently be oriented as "above" the other elements or features. Thus, the term "below" can cover both above and below orientations. In addition, the device can be oriented otherwise (e.g., rotated 90 degrees or in other orientations), so the spatially relative descriptors used herein are interpreted accordingly.

[0054] The terms used herein are for the purpose of describing specific embodiments, and are not intended to be limiting. As used herein, unless the context clearly states otherwise, the singular forms "one", "one (kind / person)" and "the (described)" are also intended to include plural forms. In addition, the terms "include", "comprise" and / or and their variations when used in this specification sheet indicate the presence of stated features, integral bodies, steps, operations, elements, components and / or their groups, but do not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It is also noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than degree terms, so as to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0055] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations as schematic illustrations of embodiments and / or intermediate structures. As such, variations in the illustrated shapes resulting from, for example, manufacturing techniques and / or tolerances are anticipated. Therefore, the embodiments disclosed herein should not necessarily be interpreted as being limited to specific illustrated shapes of regions, but rather include shape deviations resulting from, for example, manufacturing. In this manner, the regions shown in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and as such, no limitation is necessarily intended.

[0056] Various embodiments relate to a conductive element, a display device, and a method of manufacturing a display device. Hereinafter, a conductive element, a display device, and a method of manufacturing a display device according to one or more embodiments will be described with reference to the accompanying drawings.

[0057] Will refer to Figure 1 and Figure 2 The conductive element CE according to one or more embodiments will be described. Figure 1 is a schematic perspective view illustrating a conductive element CE according to one or more embodiments. Figure 2 is a schematic cross-sectional view illustrating a conductive element CE according to one or more embodiments.

[0058] The conductive element CE may be used as a light emitting element and / or an electrical connection. For example, the conductive element CE may be used as a display area DA (see Figure 3 ) in the light emitting element. The conductive element CE can be used as a pad area PDA (refer to Figure 3 ) in the electrical connector.

[0059] According to one or more embodiments, the conductive element CE may be formed to emit light. For example, when an electrical signal is applied to the conductive element CE, the conductive element CE may emit light. When an anode signal is supplied from the first end EP1 and a cathode signal is supplied from the second end EP2, the conductive element CE may emit light.

[0060] According to one or more embodiments, the conductive element CE may form an electrical path in a direction. For example, the exposed outer side surface of the conductive element CE may have a conductive property, and the conductive element CE may electrically connect the first component to the second component spaced apart from the first component. The conductive element CE may form an electrical path in a direction opposite to the direction from the first end EP1 to the second end EP2.

[0061] The conductive element CE may have various shapes. For example, the conductive element CE may extend in one direction. Figure 1 and Figure 2 One or more embodiments are shown in which the conductive element CE has a column shape. For example, the conductive element CE may extend from the first end EP1 to the second end EP2. In one or more embodiments, the first length L1 of the conductive element CE may be greater than the first diameter D1 of the conductive element CE. In one or more embodiments, in the case where the conductive element CE may have a rod shape, the conductive element CE may be referred to as a rod-type conductive element.

[0062] In one or more embodiments, the conductive element CE may have a shape in which a central area thereof protrudes more than a peripheral area thereof. In one or more embodiments, based on the conductive pattern layer CO, at least a portion of the conductive element CE may protrude toward the first end portion EP1, and at least another portion of the conductive element CE may protrude toward the second end portion EP2.

[0063] In one or more embodiments, the conductive pattern layer CO may be selectively disposed on an outer surface (e.g., an outer side surface) of the conductive element CE. For example, the conductive element CE may have a first diameter D1 in a region where the conductive pattern layer CO is not disposed, and may have a second diameter D2 in a region where the conductive pattern layer CO is disposed. For example, the first diameter D1 may be smaller than the second diameter D2.

[0064] The conductive element CE may include a first semiconductor layer SCL1, a second semiconductor layer SCL2 and an active layer AL. The conductive element CE may also include an element insulating layer INF and a conductive pattern layer CO. The conductive pattern layer CO may also be referred to as a conductive coating layer. The conductive pattern layer CO may also be referred to as an outer conductive layer.

[0065] The conductive element CE may include a first end EP1 and a second end EP2. In one or more embodiments, the first semiconductor layer SCL1 may be adjacent to the first end EP1 of the conductive element CE. The second semiconductor layer SCL2 may be adjacent to the second end EP2 of the conductive element CE. The active layer AL may be disposed between the first semiconductor layer SCL1 and the second semiconductor layer SCL2.

[0066] The conductive element CE may be formed by etching a stacked structure formed by continuously stacking semiconductor layers. In addition, the conductive element CE may be formed by patterning an element insulating layer INF on the outer surfaces of the first semiconductor layer SCL1, the second semiconductor layer SCL2, and the active layer AL and patterning a conductive pattern layer CO on the element insulating layer INF. For example, the conductive pattern layer CO may be disposed on the element insulating layer INF by a sputtering process. However, the embodiment is not limited thereto.

[0067] The conductive element CE may have a size in the range of nanometer to micrometer. For example, the first diameter D1 and the second diameter D2 may have a size in the range of nanometer to micrometer. The first length L1 and the second length L2 may correspond to a size in the range of nanometer to micrometer. In one or more embodiments, the second diameter D2 may be greater than the first diameter D1 by the thickness of the conductive pattern layer CO (for example, about twice the thickness of the conductive pattern layer CO greater than the first diameter D1). For example, the thickness of the conductive pattern layer CO may be in the range of about 200nm to about 350nm. In another example, the thickness of the conductive pattern layer CO may be in the range of about 250nm to about 300nm. In one or more embodiments, the second length L2 may be greater than half of the first length L1. For example, the ratio of the first length L1 to the second length L2 may be in the range of about 1.3 to about 1.6. However, the embodiment is not limited thereto.

[0068] The first semiconductor layer SCL1 may be a first conductive semiconductor layer. The first semiconductor layer SCL1 may be disposed on the active layer AL, and may include a semiconductor layer having a type different from that of the second semiconductor layer SCL2. For example, the first semiconductor layer SCL1 may include a P-type semiconductor layer. For example, the first semiconductor layer SCL1 may include a P-type semiconductor layer including at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a first conductive dopant such as Ga, B, or Mg. However, the material used to form the first semiconductor layer SCL1 is not limited thereto, and the first semiconductor layer SCL1 may be formed of various other materials.

[0069] The active layer AL may be disposed between the first semiconductor layer SCL1 and the second semiconductor layer SCL2 and have a single quantum well structure or a multi-quantum well structure. The location of the active layer AL is not limited to a specific example.

[0070] A capping layer doped with a conductive dopant may be formed on and / or under the active layer AL. For example, the capping layer may be formed of an AlGaN layer or an InAlGaN layer. In one or more embodiments, a material such as AlGaN or InAlGaN may be used to form the active layer AL, and various other materials may be used to form the active layer AL.

[0071] The second semiconductor layer SCL2 may be a second conductive semiconductor layer. The second semiconductor layer SCL2 may be disposed on the active layer AL, and may include a semiconductor layer of a type different from that of the first semiconductor layer SCL1. For example, the second semiconductor layer SCL2 may include an N-type semiconductor layer. For example, the second semiconductor layer SCL2 may include any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and may include an N-type semiconductor layer doped with a second conductive dopant such as Si, Ge, or Sn. However, the material for forming the second semiconductor layer SCL2 is not limited thereto, and the second semiconductor layer SCL2 may be formed of various other materials.

[0072] When a voltage equal to or greater than a threshold voltage is applied between opposite ends of the conductive element CE, the conductive element CE can emit light by combining (or combining) electron-hole pairs in the active layer AL. Since the light emission of the conductive element CE is controlled based on the aforementioned principle, the conductive element CE can be used as various light-emitting devices and display devices DD (see Figure 3 ) pixel PXL (refer to Figure 4 ) light source.

[0073] The element insulating layer INF may be disposed on respective surfaces of the first semiconductor layer SCL1, the second semiconductor layer SCL2, and the active layer AL. For example, the element insulating layer INF may cover at least the active layer AL, and may also surround (or surround) a region of each of the first semiconductor layer SCL1 and the second semiconductor layer SCL2. In one or more embodiments, the element insulating layer INF may expose the first end EP1 and the second end EP2 of the conductive element CE.

[0074] The element insulating layer INF may be formed of a single layer structure or a double layer structure, but the embodiment is not limited thereto. The element insulating layer INF may be formed of multiple layers. For example, the element insulating layer INF may include a first element insulating layer including a first material and a second element insulating layer including a second material different from the first material. In one or more embodiments, the element insulating layer INF may include a silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) and titanium oxide (TiO x ) is selected from the group consisting of one or more materials. However, the embodiment is not limited thereto.

[0075] The element insulating layer INF may contact the conductive pattern layer CO. For example, the element insulating layer INF may include a contact region that contacts the conductive pattern layer CO and a non-contact region that does not contact the conductive pattern layer CO. For example, the first semiconductor layer SCL1, the second semiconductor layer SCL2, and the active layer AL may be separated from the conductive pattern layer CO (e.g., physically or electrically) by the element insulating layer INF. The element insulating layer INF may separate the first semiconductor layer SCL1, the second semiconductor layer SCL2, and the active layer AL from the conductive pattern layer CO (e.g., physically or electrically).

[0076] The conductive pattern layer CO may be disposed on the element insulating layer INF. The conductive pattern layer CO may overlap the element insulating layer INF. In one or more embodiments, the conductive pattern layer CO may directly contact the element insulating layer INF. The conductive pattern layer CO may expose at least a portion of the element insulating layer INF.

[0077] In one or more embodiments, the conductive pattern layer CO may be selectively disposed in a partial region of the element insulating layer INF, and may not be disposed in a partial region of the element insulating layer INF. For example, the conductive pattern layer CO may be physically spaced apart from the first end EP1 and the second end EP2 of the conductive element CE. The conductive pattern layer CO may be electrically insulated from a layer adjacent to the first end EP1 (e.g., the first semiconductor layer SCL1). The conductive pattern layer CO may be electrically insulated from a layer adjacent to the second end EP2 (e.g., the second semiconductor layer SCL2). For example, the first end EP1 of the conductive element CE may be electrically connected to an electrode for supplying an anode signal (e.g., Figure 5 The first connection electrode CNE1 in the conductive element CE and the second end EP2 of the conductive element CE are electrically connected to an electrode for supplying a cathode signal (eg, Figure 5 In the case of the second connection electrode CNE2 in FIG. 1 , the electrical signal for emitting light through the conductive element CE may not be applied to the conductive pattern layer CO.

[0078] In one or more embodiments, the conductive pattern layer CO may include a conductive material. For example, the conductive pattern layer CO may include one or more materials selected from the group consisting of nickel (Ni), gold (Au), copper (Cu), and silver (Ag). However, the embodiment is not limited thereto.

[0079] In one or more embodiments, the conductive pattern layer CO may form an electrical path in a cross-sectional direction of the conductive element CE (eg, a direction different from a direction from the first end EP1 to the second end EP2). Figure 1 and Figure 2 A portion of the upper side of the conductive element CE (eg, the upper side of the conductive element CE) may be electrically connected to the first component adjacent to the first side. Figure 1 and Figure 2 A portion of the lower side in the conductive pattern layer (the lower side in the conductive pattern layer) can be electrically connected to the second component adjacent to the second side. Therefore, the first component and the second component can be electrically connected through the conductive pattern layer CO.

[0080] In one or more embodiments, the conductive pattern layer CO may form an electrical path in a direction opposite to the direction from the first end EP1 to the second end EP2. The aforementioned structure of the conductive pattern layer CO may be suitable for electrically connecting two or more components to each other. For example, the conductive pattern layer CO may form a chip on film COF (refer to Figure 3 ) is electrically connected to pad PAD (refer to Figure 4 ). A detailed description thereof will be given below.

[0081] The structure of the conductive element CE is not limited thereto. For example, the conductive element CE may further include an electrode layer adjacent to the first end portion EP1 and / or the second end portion EP2. For example, the electrode layer may be an ohmic contact electrode or a Schottky contact electrode.

[0082] For example, refer to Figure 3 and Figure 4 A display device DD including a conductive element CE according to one or more embodiments will be described. Figure 3 is a schematic perspective view illustrating a display device DD according to one or more embodiments. Figure 4 is a schematic plan view illustrating a display device DD according to one or more embodiments.

[0083] Reference Figure 3 and Figure 4 , the display device DD may display an image by emitting light. The display device DD may include a base layer BSL, a pad PAD, and a pixel PXL. The display device DD may include a scan driver 30, a data driver 40, and a driving circuit component DCB.

[0084] The base layer BSL may form (or constitute) a base surface of the display device DD. The base layer BSL may include a rigid material or a flexible material according to the purpose of the display device DD. The base layer BSL may include a flexible substrate or a rigid substrate or a flexible film or a rigid film. In one or more embodiments, the base layer BSL may be substantially transparent or reflective. However, the material of the base layer BSL that can be applied to the embodiment is not limited thereto.

[0085] The display device DD (e.g., the base layer BSL) may include a display area DA and a non-display area NDA. The display area DA may be an area in which pixels PXL are formed. The non-display area NDA may refer to an area in which pixels PXL are not formed. Light generated from the pixels PXL may be emitted from the display area DA. In the display area DA, light may be emitted in a display direction (e.g., a third direction DR3) of the display device DD. In the non-display area NDA, light may not be emitted. The non-display area NDA may include an area other than the display area DA.

[0086] The pixel PXL may include a conductive element CE. In the display area DA, the conductive element CE may emit light so that the pixel PXL may provide light. The pixel PXL may be disposed on the base layer BSL in the display area DA.

[0087] The pixel PXL may emit light based on a signal provided from the scan driver 30 and / or a signal provided from the data driver 40 .

[0088] The pixel PXL may include a first sub-pixel SPXL1, a second sub-pixel SPXL2, and a third sub-pixel SPXL3. The pixel PXL may include a pixel unit PXU. The pixel unit PXU may be arranged in the display area DA. The pixel unit PXU may include a first sub-pixel SPXL1, a second sub-pixel SPXL2, and / or a third sub-pixel SPXL3. Hereinafter, the term "sub-pixel SPXL" will be used to arbitrarily specify any one of the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3, or to uniformly specify two or more sub-pixels.

[0089] The pixel PXL can be based on stripes or The arrangement structure is regularly arranged. The arrangement structure of the pixels PXL is not limited thereto, and the pixels PXL may be arranged in the display area DA in various structures and / or schemes.

[0090] In one or more embodiments, a first sub-pixel SPXL1 emitting light of a first color, a second sub-pixel SPXL2 emitting light of a second color, and a third sub-pixel SPXL3 emitting light of a third color may be arranged in a display area DA. At least one first sub-pixel SPXL1, at least one second sub-pixel SPXL2, and at least one third sub-pixel SPXL3 disposed adjacent to each other may form a pixel unit PXU emitting light of various colors. For example, each of the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may be a pixel emitting light of a certain color. In one or more embodiments, the first sub-pixel SPXL1 may be a red pixel emitting red light, the second sub-pixel SPXL2 may be a green pixel emitting green light, and the third sub-pixel SPXL3 may be a blue pixel emitting blue light. However, the embodiment is not limited thereto.

[0091] In one or more embodiments, the conductive elements CE respectively disposed in the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may emit light of the same color. Fig.11 ) and / or color filter layer CFL (refer to Fig.11 ) may be disposed on the conductive element CE so that the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may emit light of different colors. In one or more embodiments, the conductive elements CE respectively disposed in the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may emit light of different colors. However, the color, type, and / or number of the pixels PXL forming the pixel unit PXU are not limited to the specific examples.

[0092] The scan driver 30 may output a scan signal. The scan driver 30 may output a scan signal along a scan line. The data driver 40 may output (or provide) a data signal.

[0093] The scan driver 30 and the data driver 40 may be connected (e.g., electrically connected) to the lines of the display device DD. In one or more embodiments, the scan driver 30 and the data driver 40 may be disposed (or mounted) on a flexible circuit assembly FPCB. The electrical signals provided from the scan driver 30 and the data driver 40 may be provided to the pixels PXL through the chip on film COF and the pad PAD. In one or more embodiments, the conductive element CE may be connected to the pad line PAL (refer to Fig.13 ) is electrically connected to the chip-on-film COF.

[0094] Various lines, pads (e.g., PADs), and / or internal circuits connected to the pixels PXL of the display area DA may be disposed in the non-display area NDA. The pad area PDA may be disposed in the non-display area NDA. The non-display area NDA may include the pad area PDA. The pad area PDA may be disposed on one side of the display area DA. Figure 3 and Figure 4 It is shown that the pad area PDA is disposed adjacent to the lower side of the display area DA, but the embodiment is not limited thereto.

[0095] The pad PAD may be disposed in the pad area PDA. The pad PAD may be formed. In one or more embodiments, the pad PAD may include a first pad PAD1 and a second pad PAD2. The first pad PAD1 may be a gate pad, and the second pad PAD2 may be a data pad. The first pad PAD1 may be connected (e.g., electrically connected) to the scan driver 30. The scan signal provided from the scan driver 30 may be transmitted to the scan line for the pixel PXL via the first pad PAD1. The second pad PAD2 may be connected (e.g., electrically connected) to the data driver 40. The data signal provided from the data driver 40 may be transmitted to the data line for the pixel PXL via the second pad PAD2. The positions of the first pad PAD1 and the second pad PAD2 in the pad area PDA are not limited.

[0096] The driving circuit assembly DCB may include a chip on film COF and a flexible circuit assembly FPCB.

[0097] The chip on film COF may apply (or provide) an electrical signal generated based on a signal generated by the flexible circuit assembly FPCB to a component (e.g., pixel PXL) disposed in the display area DA. The chip on film COF may apply (or provide) an electrical signal based on a signal provided from the flexible circuit assembly FPCB to the pad PAD. For example, the chip on film COF may apply (or provide) an electrical signal based on a signal provided from the flexible circuit assembly FPCB to a conductive element CE disposed in the pad area PDA.

[0098] The first end (or first portion) of the chip on film COF can be attached or connected (e.g., electrically connected) to the base layer BSL. The second end (or second portion) of the chip on film COF can be attached or connected (e.g., electrically connected) to the flexible circuit assembly FPCB. At least a portion of the chip on film COF can be bent.

[0099] The chip on film COF can be overlapped with the pad area PDA, for example, in a plan view. For example, the first end (or first portion) of the chip on film COF can be attached or connected (e.g., electrically connected) to the pad area PDA. In one or more embodiments, at least a portion of the chip on film COF can be connected (e.g., electrically connected) to the pad PAD (or pad line PAL) through the conductive element CE in the pad area PDA. The first end (or first portion) of the chip on film COF can be connected (e.g., electrically connected) to the conductive element CE in the pad area PDA. For example, the electrical signal provided from the flexible circuit assembly FPCB can be applied (or provided) to the pad PAD (or pad line PAL) through the chip on film COF. In one or more embodiments, the first area of ​​the chip on film COF can be connected (e.g., electrically connected) to the first pad PAD1, and the second area of ​​the chip on film COF can be connected (e.g., electrically connected) to the second pad PAD2.

[0100] The chip-on-film COF may include an insulating film and wires disposed on the insulating film. The chip-on-film COF may be a general term for a structure including an insulating film formed of a thin film and wires formed on the insulating film, and may also be referred to as a tape carrier package, a flexible printed circuit board, etc. In the chip-on-film COF, semiconductor chips connected to at least some of the wires may be further mounted on the insulating film.

[0101] A circuit element that processes an electrical signal to be applied to the pixel PXL may be disposed on the flexible circuit assembly FPCB. In one or more embodiments, the flexible circuit assembly FPCB may be a flexible circuit substrate.

[0102] The flexible circuit assembly FPCB may be disposed on one surface or a rear surface of the base layer BSL. An end of the flexible circuit assembly FPCB may be connected (e.g., electrically connected) to the chip on film COF having a curved shape and may be disposed on the rear surface of the base layer BSL so that the flexible circuit assembly FPCB may be prevented from being visible to the outside.

[0103] For example, refer to Figures 5 to 12 A pixel PXL (eg, a sub-pixel SPXL) according to one or more embodiments will be described. Figure 5 is a schematic block diagram for describing an electrical connection structure of conductive elements CE in a display area DA according to one or more embodiments. Figures 6 to 12 is a diagram illustrating a pixel PXL (or a sub-pixel SPXL) according to one or more embodiments. For convenience of description, redundant descriptions of the above-described embodiments will be simplified or may not be repeated.

[0104] Reference Figure 5 , an electrical connection structure for allowing (or controlling) the conductive element CE to emit light will be described.

[0105] Reference Figure 5 , in the display area DA, the conductive element CE may be connected (eg, electrically connected) between the first connection electrode CNE1 for supplying an anode signal and the second connection electrode CNE2 for supplying a cathode signal.

[0106] In one or more embodiments, the first connection electrode CNE1 may supply an anode signal through the first end EP1 of the conductive element CE. The second connection electrode CNE2 may supply a cathode signal through the second end EP2 of the conductive element CE. For example, the conductive element CE may be a light-emitting element that emits light. For example, the conductive element CE that is normally electrically connected to other lines (or electrodes) may be used as a light-emitting element in the display area DA.

[0107] Will refer to Figure 6 A planar structure of a sub-pixel SPXL including the conductive element CE serving as a light emitting element will be described. Figure 6 is a schematic plan view illustrating a sub-pixel SPXL according to one or more embodiments. Figure 6 The sub-pixel SPXL shown in FIG. 1 may be the sub-pixel SPXL shown in FIG. Figure 4 One of the first sub-pixel SPXL1, the second sub-pixel SPXL2 and the third sub-pixel SPXL3 described above. Figure 6 In the figure, for the convenience of explanation, the conductive element CE is schematically shown.

[0108] The sub-pixel SPXL may include an emission area EMA and a non-emission area NEA. The sub-pixel SPXL may include a bank BNK, an alignment electrode ELT, a conductive element CE, a first connection electrode CNE1, and a second connection electrode CNE2.

[0109] In a plan view, the emission area EMA may overlap the opening OPN defined by the bank BNK. The conductive element CE may be disposed in the emission area EMA.

[0110] The conductive element CE may not be disposed in the non-emission area NEA. A portion of the non-emission area NEA may overlap the bank BNK in a plan view.

[0111] The bank BNK may form (or provide) an opening OPN. For example, the bank BNK may have a shape protruding in the thickness direction of the base layer BSL (for example, in the third direction DR3), and may have a shape surrounding (or surrounding) a certain area. For example, an opening OPN in which the bank BNK is not provided may be formed.

[0112] The bank BNK may form a space. In a plan view, the bank BNK may have a shape that surrounds (or surrounds) some area. The space may refer to an area in which a fluid is contained. In one or more embodiments, the bank BNK may include a first bank (refer to Figure 7 'BNK1') and the second embankment (ref. Figure 7 'BNK2').

[0113] In one or more embodiments, ink including the conductive element CE may be provided to a space defined by the bank BNK (eg, the first bank BNK1 ) so that the conductive element CE may be disposed in the opening OPN.

[0114] In one or more embodiments, the color conversion layer CCL may be disposed (or patterned) in a space defined by the bank BNK (eg, the second bank BNK2 ).

[0115] The bank BNK may define an emission area EMA and a non-emission area NEA. In a plan view, the bank BNK may surround (or surround) at least a portion of the emission area EMA. For example, an area provided with the bank BNK may correspond to (or overlap) the non-emission area NEA. As an area where the bank BNK is not provided, an area provided with the conductive element CE may correspond to (or overlap) the emission area EMA.

[0116] The alignment electrode ELT may be an electrode for aligning the conductive element CE. In one or more embodiments, the alignment electrode ELT may include a first electrode ELT1 and a second electrode ELT2. The alignment electrode ELT may be referred to as an "electrode".

[0117] The alignment electrode ELT may have a single-layer structure or a multi-layer structure. For example, the alignment electrode ELT may include at least one reflective electrode layer containing a reflective conductive material, and optionally also include at least one transparent electrode layer and / or a conductive cover layer. In one or more embodiments, the alignment electrode ELT may include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti) and one of their alloys. However, the embodiment is not limited thereto, and the alignment electrode ELT may include one of various materials having reflectivity. However, the embodiment is not limited thereto.

[0118] The conductive element CE may be disposed on the alignment electrode ELT. In one or more embodiments, at least some of the conductive elements CE may be disposed between the first electrode ELT1 and the second electrode ELT2. The conductive element CE may be aligned between the first electrode ELT1 and the second electrode ELT2. The conductive element CE may form (or constitute) an emission unit EMU. The emission unit EMU may refer to a unit including conductive elements CE adjacent to each other.

[0119] In one or more embodiments, the conductive elements CE may be aligned in various ways. For example, Figure 6 One or more embodiments in which the conductive element CE is aligned in parallel between the first electrode ELT1 and the second electrode ELT2 are shown. However, the embodiments are not limited thereto. For example, the conductive element CE can be aligned in series or in a series / parallel combination structure, and the number of units connected in series and / or in parallel to each other is not limited to a specific number.

[0120] The first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other. For example, the first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other in the first direction DR1 in the emission area EMA, and may both extend in the second direction DR2.

[0121] In one or more embodiments, the first electrode ELT1 and the second electrode ELT2 may be electrodes for aligning the conductive element CE. The first electrode ELT1 may be a first alignment electrode. The second electrode ELT2 may be a second alignment electrode.

[0122] The first electrode ELT1 and the second electrode ELT2 may be supplied (or provided) with a first alignment signal and a second alignment signal, respectively, in a process of aligning the conductive element CE. Fig.18) can be supplied (or provided) to the opening OPN defined by the embankment BNK (e.g., the first embankment BNK1), the first alignment signal can be supplied to the first electrode ELT1, and the second alignment signal can be supplied to the second electrode ELT2. For example, the first alignment signal and the second alignment signal can have different waveforms, different potentials and / or different phases. For example, the first alignment signal can be an AC signal, and the second alignment signal can be a ground signal. However, the embodiment is not limited thereto. An electric field can be formed between (or on) the first electrode ELT1 and the second electrode ELT2, so that the conductive element CE can be aligned between the first electrode ELT1 and the second electrode ELT2 based on the electric field. For example, the conductive element CE can be moved (or rotated) by a force (e.g., a dielectrophoresis (DEP) force) originating from the electric field, and is thus aligned on the alignment electrode ELT (or disposed on the alignment electrode ELT).

[0123] The first electrode ELT1 may be electrically connected to a circuit element (eg, a transistor TR (refer to Figure 7 )). In one or more embodiments, the first electrode ELT1 may provide an anode signal for the conductive element CE to emit light. The first electrode ELT1 may provide a first alignment signal for aligning the conductive element CE.

[0124] The second electrode ELT2 may be connected (eg, electrically connected) to the power line PL (see Figure 7 In one or more embodiments, the second electrode ELT2 may provide a cathode signal for the conductive element CE to emit light. The second electrode ELT2 may provide a second alignment signal for aligning the conductive element CE.

[0125] The positions of the first contact CNT1 and the second contact CNT2 are not limited to Figure 6 The positions shown in FIG. 1 and may be appropriately changed in various ways.

[0126] The conductive element CE may emit light based on the supplied electrical signal. For example, the conductive element CE may provide light based on a first electrical signal (eg, an anode signal) supplied from the first connection electrode CNE1 and a second electrical signal (eg, a cathode signal) supplied from the second connection electrode CNE2.

[0127] The first end EP1 of the conductive element CE may be disposed adjacent to the first electrode ELT1. The second end EP2 of the conductive element CE may be disposed adjacent to the second electrode ELT2. The first end EP1 may overlap with the first electrode ELT1, or may not overlap with the first electrode ELT1. The second end EP2 may overlap with the second electrode ELT2, or may not overlap with the second electrode ELT2.

[0128] In one or more embodiments, the respective first end EP1 of the conductive element CE may be connected (e.g., electrically connected) to the first electrode ELT1 through the first connection electrode CNE1. In one or more embodiments, the respective first end EP1 of the conductive element CE may be directly connected to the first electrode ELT1. In one or more embodiments, the respective first end EP1 of the conductive element CE may be connected (e.g., electrically connected) only to the first connection electrode CNE1, rather than to the first electrode ELT1.

[0129] For example, the corresponding second end EP2 of the conductive element CE may be electrically connected to the second electrode ELT2 via the second connection electrode CNE2. In one or more embodiments, the corresponding second end EP2 of the conductive element CE may be directly connected to the second electrode ELT2. In one or more embodiments, the corresponding second end EP2 of the conductive element CE may be connected (e.g., electrically connected) only to the second connection electrode CNE2, rather than to the second electrode ELT2.

[0130] The first and second connection electrodes CNE1 and CNE2 may be disposed on the first and second end portions EP1 and EP2 of the conductive element CE, respectively.

[0131] The first connection electrode CNE1 may be disposed on the first end portion EP1 of the conductive element CE so that the first connection electrode CNE1 may be connected (e.g., electrically connected) to the first end portion EP1. In one or more embodiments, the first connection electrode CNE1 may be disposed on the first electrode ELT1 and connected (e.g., electrically connected) to the first electrode ELT1. For example, the first end portion EP1 of the conductive element CE may be electrically connected to the first electrode ELT1 through the first connection electrode CNE1.

[0132] The second connection electrode CNE2 may be disposed on the second end portion EP2 of the conductive element CE, so that the second connection electrode CNE2 may be connected (e.g., electrically connected) to the second end portion EP2. In one or more embodiments, the second connection electrode CNE2 may be disposed on the second electrode ELT2 and connected (e.g., electrically connected) to the second electrode ELT2. For example, the second end portion EP2 of the conductive element CE may be electrically connected to the second electrode ELT2 through the second connection electrode CNE2.

[0133] For example, refer to Figures 7 to 12 The cross-sectional structure of a pixel PXL (or a sub-pixel SPXL) according to one or more embodiments is described. Figures 7 to 10 The pixel circuit layer PCL and the display element layer DPL of the sub-pixel SPXL are described. Fig.11 and Fig.12The optical layer OPL, the color filter layer CFL, and the overcoat layer OFL are described below. For convenience of description, redundant descriptions of the above embodiments will be simplified or may not be repeated.

[0134] Figures 7 to 10 are schematic cross-sectional views each showing a sub-pixel SPXL according to one or more embodiments. For example, Figure 7 , Fig. 9 and Fig.10 It is along Figure 6 A schematic cross-sectional view taken along line II'.

[0135] Figure 7 is a schematic cross-sectional view showing the sub-pixel SPXL according to the first embodiment. Figure 8 yes Figure 7 Schematic enlargement of area EA1. Fig. 9 is a schematic cross-sectional view showing a sub-pixel SPXL according to the second embodiment. Fig.10 : is a schematic cross-sectional view showing a sub-pixel SPXL according to the third embodiment. For convenience of explanation, Figure 7 , Fig. 9 and Fig.10 The conductive element CE is schematically shown and will be referred to as Figure 8 To understand the detailed connection structure of the conductive elements CE in the display element layer DPL. Fig.11 is a schematic cross-sectional view illustrating a pixel PXL according to one or more embodiments. Fig.12 is a schematic cross-sectional view illustrating a sub-pixel SPXL according to one or more embodiments.

[0136] For example, refer to Figure 7 The sub-pixel SPXL according to the first embodiment is described. Figure 7 The sub-pixel SPXL may be disposed on the base layer BSL. The sub-pixel SPXL may include a pixel circuit layer PCL and a display element layer DPL.

[0137] The base layer BSL may form a base for forming the sub-pixel SPXL. The base layer BSL may provide a region formed to be disposed therein with the pixel circuit layer PCL and the display element layer DPL.

[0138] The pixel circuit layer PCL may be disposed on the base layer BSL and may include an auxiliary bottom electrode BML, a buffer layer BFL, a transistor TR, a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, and a passivation layer PSV.

[0139] The auxiliary bottom electrode BML may be disposed on the base layer BSL. The auxiliary bottom electrode BML may be used as a path along which an electrical signal is transmitted. In one or more embodiments, a portion of the auxiliary bottom electrode BML may overlap the transistor TR, for example, in a plan view.

[0140] The buffer layer BFL may be disposed on the base layer BSL. The buffer layer BFL may cover the auxiliary bottom electrode BML. The buffer layer BFL may prevent impurities from diffusing or penetrating from the outside. The buffer layer BFL may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) and titanium oxide (TiO x However, the embodiment is not limited thereto.

[0141] The transistor TR may be a thin film transistor. In one or more embodiments, the transistor TR may be a driving transistor. The transistor TR may be electrically connected to the conductive element CE. The transistor TR may be electrically connected to the first end EP1 of the conductive element CE.

[0142] The transistor TR may include an active layer ACT, a first transistor electrode TE1 , a second transistor electrode TE2 , and a gate electrode GE.

[0143] The active layer ACT may refer to a semiconductor layer. The active layer ACT may be disposed on the buffer layer BFL. The active layer ACT may include one selected from the group consisting of polycrystalline silicon, low temperature polycrystalline silicon (LTPS), amorphous silicon, and an oxide semiconductor.

[0144] The active layer ACT may include a first contact region contacting the first transistor electrode TE1 and a second contact region contacting the second transistor electrode TE2. Each of the first contact region and the second contact region may be a semiconductor pattern layer doped with impurities. The region between the first contact region and the second contact region may be a channel region. The channel region may be an intrinsic semiconductor pattern layer not doped with impurities.

[0145] The gate electrode GE may be disposed on the gate insulating layer GI. The position of the gate electrode GE may correspond to the position of the channel region of the active layer ACT. For example, the gate electrode GE may be disposed on the channel region of the active layer ACT, and the gate insulating layer GI is disposed between the gate electrode GE and the active layer ACT.

[0146] The gate insulating layer GI may be disposed on the buffer layer BFL. The gate insulating layer GI may cover the active layer ACT. The gate insulating layer GI may include silicon oxide (SiO x ), silicon nitride (SiNx ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) and titanium oxide (TiO x However, the embodiment is not limited thereto.

[0147] The first interlayer insulating layer ILD1 may be disposed on the gate insulating layer GI. The first interlayer insulating layer ILD1 may cover the gate electrode GE. The first interlayer insulating layer ILD1 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) and titanium oxide (TiO x However, the embodiment is not limited thereto.

[0148] The first transistor electrode TE1 and the second transistor electrode TE2 may be disposed on the first interlayer insulating layer ILD1. The first transistor electrode TE1 may contact a first contact region of the active layer ACT through the gate insulating layer GI and the first interlayer insulating layer ILD1. The second transistor electrode TE2 may contact a second contact region of the active layer ACT through the gate insulating layer GI and the first interlayer insulating layer ILD1. For example, the first transistor electrode TE1 may be a drain electrode, and the second transistor electrode TE2 may be a source electrode, but the embodiment is not limited thereto.

[0149] The first transistor electrode TE1 may be electrically connected to the first electrode ELT1 through a first contact CNT1 passing through the passivation layer PSV and the second interlayer insulating layer ILD2 .

[0150] The power line PL may be disposed on the first interlayer insulating layer ILD1. In one or more embodiments, the power line PL, the first transistor electrode TE1, and the second transistor electrode TE2 may be disposed on the same layer, or may be formed of the same layer (or the same material). The power line PL may be connected (e.g., electrically connected) to the second electrode ELT2 through the second contact CNT2. The power line PL may supply power or an alignment signal through the second electrode ELT2.

[0151] In one or more embodiments, the layer in which the first transistor electrode TE1, the second transistor electrode TE2, and the power line PL are disposed may be a source / drain layer SDL. The source / drain layer SDL may include a layer disposed in the same layer or formed of the same layer (or the same material). For example, the source / drain layer SDL may include the first transistor electrode TE1, the second transistor electrode TE2, and the power line PL.

[0152] The second interlayer insulating layer ILD2 may be disposed on the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may cover the first transistor electrode TE1, the second transistor electrode TE2, and the power line PL. The second interlayer insulating layer ILD2 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) and titanium oxide (TiO x However, the embodiment is not limited thereto.

[0153] The passivation layer PSV may be disposed on the second interlayer insulating layer ILD2. In an embodiment, the passivation layer PSV may be a via layer. The passivation layer PSV may include an organic material for planarizing the step structure formed thereunder. For example, the passivation layer PSV may include an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, or a benzocyclobutene (BCB). However, the embodiment is not limited thereto. The passivation layer PSV may include various inorganic materials, including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0154] In one or more embodiments, the sub-pixel SPXL may include a first contact CNT1 and a second contact CNT2. The first contact CNT1 and the second contact CNT2 may both pass through the second interlayer insulating layer ILD2 and the passivation layer PSV. The first electrode ELT1 and the first transistor electrode TE1 may be electrically connected to each other through the first contact CNT1. The second electrode ELT2 and the power line PL may be electrically connected to each other through the second contact CNT2.

[0155] The display element layer DPL may be disposed on the pixel circuit layer PCL. The display element layer DPL may include a first insulating layer INS1, an insulating pattern layer INP, an alignment electrode ELT, a bank BNK, a conductive element CE, a second insulating layer INS2, a first connection electrode CNE1, a third insulating layer INS3, a second connection electrode CNE2, and a fourth insulating layer INS4.

[0156] The insulating pattern layer INP may be disposed on the passivation layer PSV. In another example, the insulating pattern layer INP may have various shapes. In one or more embodiments, the insulating pattern layer INP may protrude in the thickness direction of the base layer BSL (e.g., in the third direction DR3). In addition, the insulating pattern layer INP may have an inclined surface that is inclined at an angle relative to the base layer BSL. However, embodiments are not limited thereto. The insulating pattern layer INP may have a sidewall having a curved shape or a step shape. For example, the insulating pattern layer INP may have a cross-sectional shape such as a semicircular shape or a semi-elliptical shape.

[0157] The insulating pattern layer INP may be used to form a step difference so that the conductive element CE may be easily aligned in the emission region. In one or more embodiments, the insulating pattern layer INP may be a partition wall.

[0158] In one or more embodiments, a portion of the alignment electrode ELT may be disposed on the insulating pattern layer INP. For example, the insulating pattern layer INP may include a first insulating pattern layer INP1 and a second insulating pattern layer INP2. The first electrode ELT1 may be disposed on the first insulating pattern layer INP1. The second electrode ELT2 may be disposed on the second insulating pattern layer INP2. For example, a reflective wall may be formed on the insulating pattern layer INP. Therefore, the light emitted from the conductive element CE may be recycled or reused, so that the light output efficiency of the display device DD (or pixel PXL) may be improved.

[0159] The insulating pattern layer INP may include at least one organic material and / or inorganic material. For example, the insulating pattern layer INP may include an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, or a benzocyclobutene (BCB). However, the embodiment is not limited thereto. The insulating pattern layer INP may include various inorganic materials, including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) or titanium oxide (TiO x ).

[0160] The alignment electrode ELT may be disposed on the passivation layer PSV and / or the insulating pattern layer INP. As described above, a portion of the alignment electrode ELT may be disposed on the insulating pattern layer INP so that a reflective wall may be formed. Alignment signals (e.g., AC signals and ground signals) for aligning the conductive element CE may be supplied to the alignment electrode ELT. In one or more embodiments, electrical signals (e.g., anode signals and cathode signals) may be supplied to the alignment electrode ELT to cause the conductive element CE to emit light.

[0161] In one or more embodiments, the alignment electrode ELT may be disposed on the rear surface of the first insulating layer INS1. For example, the alignment electrode ELT may be disposed between the first insulating layer INS1 and the insulating pattern layer INP or the passivation layer PSV. For example, the surface of the alignment electrode ELT may contact the first insulating layer INS1.

[0162] The first electrode ELT1 may be connected (eg, electrically connected) to the conductive element CE. The first electrode ELT1 may be electrically connected to the first connection electrode CNE1 through a contact hole formed in the first insulating layer INS1. The first electrode ELT1 may provide an anode signal for the conductive element CE to emit light.

[0163] The second electrode ELT2 may be connected (eg, electrically connected) to the conductive element CE. The second electrode ELT2 may be connected (eg, electrically connected) to the second connection electrode CNE2 through a contact hole formed in the first insulating layer INS1. The second electrode ELT2 may provide a cathode signal (eg, a ground signal) for the conductive element CE to emit light.

[0164] The first insulating layer INS1 may be disposed on the alignment electrode ELT. For example, the first insulating layer INS1 may cover the first electrode ELT1 and the second electrode ELT2.

[0165] The bank BNK may be disposed on the first insulating layer INS1. In one or more embodiments, the bank BNK may include a first bank BNK1 and a second bank BNK2.

[0166] The first bank BNK1 may be disposed on the first insulating layer INS1. In one or more embodiments, for example, in a plan view, the first bank BNK1 may not overlap with the emission area EMA, and may overlap with the non-emission area NEA. As described above, the first bank BNK1 may protrude in the thickness direction of the base layer BSL (for example, in the third direction DR3), so that the first bank BNK1 may define an opening OPN. A space in which the conductive element CE may be disposed during a process of supplying the conductive element CE may be formed in the opening OPN.

[0167] The first bank BNK1 may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyester resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the embodiment is not limited thereto. The first bank BNK1 may include various inorganic materials including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0168] The second bank BNK2 may be disposed on the first bank BNK1. The second bank BNK2 may protrude in a thickness direction of the base layer BSL (eg, in the third direction DR3) so that the second bank BNK2 may define an opening OPN. A space where the color conversion layer CCL is to be disposed may be formed in the opening OPN.

[0169] The second bank BNK2 may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyester resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the embodiment is not limited thereto. The second bank BNK2 may include various inorganic materials including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0170] The conductive element CE may be disposed on the first insulating layer INS1. In one or more embodiments, the conductive element CE may emit light based on electrical signals (eg, anode and cathode signals) provided from the first and second connection electrodes CNE1 and CNE2.

[0171] The conductive element CE may be disposed in a region surrounded (or surrounded) by the first bank BNK1. The conductive element CE may be disposed between the first insulation pattern layer INP1 and the second insulation pattern layer INP2.

[0172] The second insulating layer INS2 may be disposed on the conductive element CE. The second insulating layer INS2 may cover the active layer AL of the conductive element CE.

[0173] The second insulating layer INS2 may expose at least a portion of the conductive element CE. For example, the second insulating layer INS2 may not cover the first end EP1 and the second end EP2 of the conductive element CE. For example, the first end EP1 and the second end EP2 of the conductive element CE may be exposed and connected (e.g., electrically connected) to the first connection electrode CNE1 and the second connection electrode CNE2, respectively.

[0174] In case that the second insulating layer INS2 is formed on the conductive element CE after the alignment of the conductive element CE is completed, the conductive element CE may be prevented from being removed from the aligned position.

[0175] The second insulating layer INS2 may have a single-layer structure or a multi-layer structure. The second insulating layer INS2 may include various inorganic materials, including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ). However, the embodiment is not limited thereto.

[0176] The first connection electrode CNE1 and the second connection electrode CNE2 may be disposed on the first insulating layer INS1. The first connection electrode CNE1 may be connected (eg, electrically connected) to the first end EP1 of the conductive element CE. The second connection electrode CNE2 may be connected (eg, electrically connected) to the second end EP2 of the conductive element CE.

[0177] The first connection electrode CNE1 may be connected (eg, electrically connected) to the first electrode ELT1 through a contact hole passing through the first insulating layer INS1. The second connection electrode CNE2 may be connected (eg, electrically connected) to the second electrode ELT2 through a contact hole passing through the first insulating layer INS1.

[0178] The first connection electrode CNE1 and the second connection electrode CNE2 may include a conductive material. For example, the first connection electrode CNE1 and the second connection electrode CNE2 may include a transparent conductive material including one of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). For example, light emitted from the conductive element CE may be emitted outside the display device DD after passing through the first connection electrode CNE1 and the second connection electrode CNE2. However, the embodiment is not limited thereto.

[0179] In one or more embodiments, after any one electrode of the first connection electrode CNE1 and the second connection electrode CNE2 is patterned, the other electrode may be patterned. However, the embodiment is not limited thereto.

[0180] The third insulating layer INS3 may be disposed on the first insulating layer INS1 and the first connection electrode CNE1. At least a portion of the third insulating layer INS3 may be disposed between the first and second connection electrodes CNE1 and CNE2 so that a short defect between the first and second connection electrodes CNE1 and CNE2 may be prevented from occurring.

[0181] The fourth insulating layer INS4 may be disposed on the third insulating layer INS3 and the second connection electrode CNE2. The fourth insulating layer INS4 may protect components of the display element layer DPL from external influences.

[0182] The third insulating layer INS3 and the fourth insulating layer INS4 may have a single-layer structure or a multi-layer structure. The third insulating layer INS3 and the fourth insulating layer INS4 may include various inorganic materials, including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0183] For example, a connection structure adjacent to the conductive element CE will be described. For the convenience of description, redundant descriptions of the above embodiments will be simplified or may not be repeated.

[0184] Reference Figure 8, the first end EP1 of the conductive element CE may be connected (e.g., electrically connected) to the first connection electrode CNE1 without physically contacting the second connection electrode CNE2. The second end EP2 of the conductive element CE may be connected (e.g., electrically connected) to the second connection electrode CNE2 without physically contacting the first connection electrode CNE1. The first connection electrode CNE1 may be physically spaced apart from the conductive pattern layer CO. The second connection electrode CNE2 may be physically spaced apart from the conductive pattern layer CO.

[0185] In one or more embodiments, the second insulating layer INS2 may overlap (e.g., completely overlap) the conductive pattern layer CO. For example, the second insulating layer INS2 may cover (e.g., completely cover) the conductive pattern layer CO, for example, in a plan view. A portion of the second insulating layer INS2 may overlap the conductive pattern layer CO, for example, in a plan view. Another portion of the second insulating layer INS2 may not overlap the conductive pattern layer CO, for example, in a plan view. For example, the second insulating layer INS2 may surround or surround (e.g., completely surround or completely surround) the conductive pattern layer CO formed on the outer surface of the element insulating layer INF. For example, the first connection electrode CNE1 or the second connection electrode CNE2 may be prevented from physically contacting the conductive pattern layer CO and being connected (e.g., electrically connected) to the conductive pattern layer CO.

[0186] In one or more embodiments, the conductive element CE disposed on the first insulating layer INS1 may form a cavity (or empty space) CAV in a region where the conductive pattern layer CO is not disposed. For example, a conductive pattern layer CO having a certain thickness may be disposed on an outer surface of the element insulating layer INF on an outer side surface of the conductive element CE. Thus, a step difference may be formed in a region of the conductive element CE where the conductive pattern layer CO is not disposed. In one or more embodiments, a surface of the conductive element CE on which the conductive pattern layer CO is not patterned may be spaced apart from the first insulating layer INS1.

[0187] For example, refer to Fig. 9 The sub-pixel SPXL according to the second embodiment will be described. For convenience of description, redundant descriptions of the above-described embodiments will be simplified or may not be repeated.

[0188] The sub-pixel SPXL according to the second embodiment is different from the sub-pixel SPXL according to the first embodiment in that the alignment electrode ELT is disposed under the insulating pattern layer INP.

[0189] According to the second embodiment, the alignment electrode ELT may be disposed on the passivation layer PSV. The insulating pattern layer INP may be disposed on the first insulating layer INS1 covering the alignment electrode ELT. For example, the alignment electrode ELT may be closer to the base layer BSL than the insulating pattern layer INP is adjacent to the base layer BSL. For example, the distance between the alignment electrode ELT and the base layer BSL in the third direction DR3 may be smaller than the distance between the insulating pattern layer INP and the base layer BSL in the third direction DR3. In one or more embodiments, the alignment electrode ELT may contact (e.g., directly contact) the passivation layer PSV.

[0190] According to the second embodiment, the alignment electrode ELT may be patterned to have an overall planar shape along the top surface (or upper surface) of the passivation layer PSV. For example, the alignment degree of the conductive element CE may be improved.

[0191] For example, refer to Fig.10 The sub-pixel SPXL according to the third embodiment will be described. For convenience of description, redundant descriptions of the above embodiments will be simplified or may not be repeated.

[0192] The sub-pixel SPXL according to the third embodiment is different from the sub-pixel SPXL according to the first embodiment in that the first connection electrode CNE1 and the second connection electrode CNE2 are patterned by the same process.

[0193] According to the third embodiment, the first connection electrode CNE1 and the second connection electrode CNE2 may be disposed in the same layer, or may be formed of the same layer. For example, the first connection electrode CNE1 and the second connection electrode CNE2 may include the same material. For example, the first connection electrode CNE1 and the second connection electrode CNE2 may be connected (e.g., electrically connected) to the first end portion EP1 and the second end portion EP2 of the conductive element CE, respectively. According to the third embodiment, the process steps may be simplified, thereby reducing the process cost.

[0194] For example, refer to Fig.11 and Fig.12 Components of the pixel PXL including the color conversion layer CCL will be described. Fig.11 The color conversion layer CCL, the optical layer OPL, the color filter layer CFL, etc. are shown. Fig.11 In the embodiment, among the above-mentioned components, except for the second bank BNK2, the components of the pixel circuit layer PCL and the components of the display element layer DPL will be omitted. Fig.12 A stacked structure of the pixel PXL regarding the color conversion layer CCL, the optical layer OPL, and the color filter layer CFL is shown.

[0195] Reference Fig.11 and Fig.12The second bank BNK2 may be disposed between the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 or in a boundary region therebetween, and defines a space (or region) overlapped with the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3, respectively. The space defined by the second bank BNK2 may be a region in which the color conversion layer CCL may be disposed.

[0196] The color conversion layer CCL may be disposed on the conductive element CE in a space surrounded (or surrounded) by the second bank BNK2. The color conversion layer CCL may include a first color conversion layer CCL1 disposed in the first subpixel SPXL1, a second color conversion layer CCL2 disposed in the second subpixel SPXL2, and a light scattering layer LSL disposed in the third subpixel SPXL3.

[0197] The color conversion layer CCL may be disposed on the conductive element CE. The color conversion layer CCL may be formed to change (or convert) the wavelength of light. In one or more embodiments, the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may include a conductive element CE that emits light of the same color. For example, the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may include a conductive element CE that emits light of a third color (or blue light). Since the color conversion layer CCL including color conversion particles is disposed in each of the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3, a full-color image may be displayed.

[0198] The first color conversion layer CCL1 may include first color conversion particles for converting the third color light emitted from the conductive element CE into the first color light. For example, the first color conversion layer CCL1 may include first quantum dots QD1 dispersed in a matrix material such as a base resin.

[0199] In one or more embodiments, in the case where the conductive element CE is a blue light emitting element emitting blue light and the first sub-pixel SPXL1 is a red pixel, the first color conversion layer CCL1 may include a first quantum dot QD1 that converts the blue light emitted from the blue light emitting element into red light. The first quantum dot QD1 may absorb the blue light, shift its wavelength according to energy transition, and may emit red light. In the case where the first sub-pixel SPXL1 is one of the pixels of other colors, the first color conversion layer CCL1 may include a first quantum dot QD1 corresponding to the color of the first sub-pixel SPXL1.

[0200] The second color conversion layer CCL2 may include second color conversion particles for converting the third color light emitted from the conductive element CE into the second color light. For example, the second color conversion layer CCL2 may include second quantum dots QD2 dispersed in a matrix material such as a base resin.

[0201] In one or more embodiments, in the case where the conductive element CE is a blue light emitting element emitting blue light and the second sub-pixel SPXL2 is a green pixel, the second color conversion layer CCL2 may include a second quantum dot QD2 that converts the blue light emitted from the blue light emitting element into green light. The second quantum dot QD2 may absorb the blue light, shift its wavelength according to energy transition, and emit green light. In the case where the second sub-pixel SPXL2 is one of the pixels of other colors, the second color conversion layer CCL2 may include a second quantum dot QD2 corresponding to the color of the second sub-pixel SPXL2.

[0202] In one or more embodiments, as blue light having a relatively short wavelength in the visible light region is incident on each of the first quantum dot QD1 and the second quantum dot QD2, the absorption coefficient of the first quantum dot QD1 and the second quantum dot QD2 can be increased. Therefore, the efficiency of light emitted from the first sub-pixel SPXL1 and the second sub-pixel SPXL2 can be enhanced, and satisfactory color reproducibility can be ensured. In addition, since the emission unit EMU for the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 is formed by a conductive element CE (e.g., a blue light emitting element) that emits light of the same color, the efficiency of manufacturing the display device DD can be enhanced.

[0203] The light scattering layer LSL may be formed to effectively use the third color light (or blue light) emitted from the conductive element CE. For example, in the case where the conductive element CE is a blue light emitting element emitting blue light and the third sub-pixel SPXL3 is a blue pixel, the light scattering layer LSL may include at least one type of light scatterer SCT to effectively use the light emitted from the conductive element CE. For example, the light scatterer SCT of the light scattering layer LSL may include barium sulfate (BaSO 4 ), calcium carbonate (CaCO 3 ), titanium oxide (TiO 2 ), silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2) and zinc oxide (ZnO). The light scatterer SCT may be disposed not only in the third sub-pixel SPXL3, but may also be selectively included in the first color conversion layer CCL1 or the second color conversion layer CCL2. In one or more embodiments, the light scatterer SCT may be omitted, and the light scattering layer LSL may be formed of a transparent polymer.

[0204] The first cover layer CPL1 may be disposed on the color conversion layer CCL. The first cover layer CPL1 may be disposed over the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3. The first cover layer CPL1 may cover the color conversion layer CCL. The first cover layer CPL1 may prevent the color conversion layer CCL from being damaged or contaminated by penetration of external impurities such as moisture or air.

[0205] The first cover layer CPL1 may be an inorganic layer and may be made of silicon nitride (SiN x ), aluminum nitride (AlN x ), titanium nitride (TiN x ), silicon oxide (SiO x ), aluminum oxide (AlO x ), titanium oxide (TiO x ), Silicon Oxycarbide (SiO x C y ) or silicon oxynitride (SiO x N y )form.

[0206] The optical layer OPL may be disposed on the first cover layer CPL1. The optical layer OPL may be used to recycle light provided from the color conversion layer CCL by reflection (e.g., total reflection), and may enhance light extraction efficiency. For example, the optical layer OPL may have a relatively low refractive index compared to the refractive index of the color conversion layer CCL. For example, the refractive index of the color conversion layer CCL may be approximately in the range of about 1.6 to about 2.0, and the refractive index of the optical layer OPL may be approximately in the range of about 1.1 to about 1.3.

[0207] The second cover layer CPL2 may be disposed on the optical layer OPL. The second cover layer CPL2 may be disposed over the first subpixel SPXL1, the second subpixel SPXL2, and the third subpixel SPXL3. The second cover layer CPL2 may cover the optical layer OPL. The second cover layer CPL2 may prevent the optical layer OPL from being damaged or contaminated by penetration of external impurities such as moisture or air.

[0208] The second capping layer CPL2 may be an inorganic layer and may be made of silicon nitride (SiN x ), aluminum nitride (AlN x ), titanium nitride (TiNx ), silicon oxide (SiO x ), aluminum oxide (AlO x ), titanium oxide (TiO x ), Silicon Oxycarbide (SiO x C y ) or silicon oxynitride (SiO x N y )form.

[0209] The planarization layer PLL may be disposed on the second cover layer CPL2. The planarization layer PLL may be disposed throughout the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3.

[0210] The planarization layer PLL may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyester resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the embodiment is not limited thereto. The planarization layer PLL may include various inorganic materials including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0211] The color filter layer CFL may be disposed on the planarization layer PLL. The color filter layer CFL may include color filters CF1, CF2, and CF3 corresponding to the colors of the corresponding pixels PXL. Since the color filters CF1, CF2, and CF3 corresponding to the corresponding colors of the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 are disposed, a full-color image may be displayed.

[0212] The color filter layer CFL may include a first color filter CF1, a second color filter CF2, and a third color filter CF3, wherein the first color filter CF1 is disposed in the first sub-pixel SPXL1 and allows light emitted from the first sub-pixel SPXL1 to selectively pass through it, the second color filter CF2 is disposed in the second sub-pixel SPXL2 and allows light emitted from the second sub-pixel SPXL2 to selectively pass through it, and the third color filter CF3 is disposed in the third sub-pixel SPXL3 and allows light emitted from the third sub-pixel SPXL3 to selectively pass through it.

[0213] In one or more embodiments, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be a red color filter, a green color filter, and a blue color filter, respectively, but the embodiment is not limited thereto. Hereinafter, the term "color filter CF" will be used to specify any color filter among the first color filter CF1, the second color filter CF2, and the third color filter CF3, or to uniformly specify two or more color filters.

[0214] The first color filter CF1 may overlap the first color conversion layer CCL1 in the thickness direction (e.g., the third direction DR3) of the substrate SUB. The first color filter CF1 may include a color filter material for selectively passing light of the first color (or red light) therethrough. For example, in the case where the first sub-pixel SPXL1 is a red pixel, the first color filter CF1 may include a red color filter material.

[0215] The second color filter CF2 may overlap the second color conversion layer CCL2 in the thickness direction (e.g., the third direction DR3) of the substrate SUB. The second color filter CF2 may include a color filter material for selectively passing light of the second color (or green light) therethrough. For example, in the case where the second sub-pixel SPXL2 is a green pixel, the second color filter CF2 may include a green color filter material.

[0216] The third color filter CF3 may be overlapped with the light scattering layer LSL in the thickness direction (e.g., third direction DR3) of the base layer BSL. The third color filter CF3 may include a color filter material for selectively passing light of a third color (or blue light) therethrough. For example, in the case where the third sub-pixel SPXL3 is a blue pixel, the third color filter CF3 may include a blue color filter material.

[0217] In one or more embodiments, a light blocking layer BM may be further provided between the first color filter CF1, the second color filter CF2, and the third color filter CF3. When the light blocking layer BM is formed between the first color filter CF1, the second color filter CF2, and the third color filter CF3, a color mixing defect visible from the front surface or the side surface of the display device DD may be prevented from occurring. The material of the light blocking layer BM is not limited thereto, and various light blocking materials may be used to form the light blocking layer BM. For example, the light blocking layer BM may include a black matrix, or may be implemented by stacking the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0218] An overcoat layer OC may be disposed on the color filter layer CFL. The overcoat layer OC may be disposed throughout the first subpixel SPXL1, the second subpixel SPXL2, and the third subpixel SPXL3. The overcoat layer OC may cover a lower component including the color filter layer CFL. The overcoat layer OC may prevent moisture or air from penetrating into the lower component. In addition, the overcoat layer OC may protect the lower component from foreign matter such as dust.

[0219] The outer coating OC may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyester resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the embodiment is not limited thereto. The outer coating OC may include various inorganic materials including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0220] The outer film layer OFL may be disposed on the outer coating layer OC. The outer film layer OFL may be disposed at the periphery of the display device DD, thereby alleviating external influences. The outer film layer OFL may be disposed throughout the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3. In one or more embodiments, the outer film layer OFL may include one of a polyethylene terephthalate (PET) film, a low-reflection film, a polarizing film, and a transmittance controllable film, but the embodiment is not limited thereto. In one or more embodiments, the pixel PXL may include an upper substrate without including the outer film layer OFL.

[0221] For example, refer to Figures 13 to 15 The structure of the pad area PDA according to one or more embodiments is described. For the convenience of description, the redundant description of the above embodiments will be simplified or may not be repeated.

[0222] Fig.13 is a schematic block diagram for describing an electrical connection structure of a conductive element CE in a pad area PDA according to one or more embodiments. Fig.14 and Fig.15 is a schematic diagram showing a pad area PDA according to one or more embodiments. For example, Fig.14 yes Figure 4 Schematic enlargement of area EA2. Fig.15 It is along Fig.14A schematic cross-sectional view taken along line II-II'.

[0223] Reference Fig.13 , the conductive element CE can electrically connect two or more components to each other in the pad area PDA. For example, the conductive element CE can electrically connect the pad line PAL used to form the pad PAD to the chip on film COF. In one or more embodiments, a portion of the conductive pattern layer CO of the conductive element CE can be electrically connected to the pad line PAL. Another portion of the conductive pattern layer CO can be electrically connected to the chip on film COF. For example, the chip on film COF can be electrically connected to the pad line PAL.

[0224] For example, the conductive element CE electrically connecting the components in the pad area PDA may have the same configuration as that of the conductive element CE in the display area DA described above.

[0225] In one or more embodiments, the conductive element CE in the pad area PDA may be used as a component for electrically connecting components to each other, rather than as a light emitting element. The conductive element CE may select a suitable electrical connection structure according to the function to be implemented, so that the degree of freedom of designing the process of the display area DA and the pad area PDA may be enhanced.

[0226] Fig.14 The stacked structure of the chip on film COF and the pad PAD in a plan view is shown. Fig.14 , the pad PAD may overlap with a portion of the chip on film COF, for example, in a plan view. For example, the pad PADs may be formed, and each pad PAD may overlap with a portion of the chip on film COF. Each of the pad PADs may be electrically connected to the chip on film COF and may be supplied with an electrical signal.

[0227] For example, refer to Fig.15 1 and 2 will now describe a cross-sectional structure showing an electrical connection structure of the conductive element CE in the pad area PDA. Fig.15 , the pad line PAL (or the pad line PAL forming the pad PAD) may include a lower pad line PSL, an alignment pad line PELT, and a connection pad line PCNE.

[0228] The pad line PSL may be disposed on the base layer BSL. The pad line PSL may be disposed below the passivation layer PSV. The pad line PSL may be disposed on the first interlayer insulating layer ILD1 and may be covered by the second interlayer insulating layer ILD2. In one or more embodiments, the pad line PSL and the above-mentioned source / drain layer SDL may be disposed on the same layer, or may be formed by the same layer (or the same material). For example, the pad line PSL and the source / drain layer SDL (for example, the first transistor electrode TE1, the second transistor electrode TE2, and the power line PL) may be patterned by the same process. In one or more embodiments, the pad line PSL may include a first pad line PSL1 and a second pad line PSL2 spaced apart from the first pad line PSL1.

[0229] In one or more embodiments, the alignment pad line PELT may be disposed on the second interlayer insulating layer ILD2. In one or more embodiments, the alignment pad line PELT and the alignment electrode ELT may be formed by the same layer (or the same material). For example, the alignment pad line PELT and the alignment electrode ELT may be patterned by the same process. In one or more embodiments, the alignment pad line PELT may include a first alignment pad line PELT1 and a second alignment pad line PELT2.

[0230] In one or more embodiments, the alignment pad line PELT may be connected (e.g., electrically connected) to the lower pad line PSL. For example, the first alignment pad line PELT1 may be connected (e.g., electrically connected) to the first lower pad line PSL1 through a contact hole passing through the second interlayer insulating layer ILD2. The second alignment pad line PELT2 may be connected (e.g., electrically connected) to the second lower pad line PSL2 through a contact hole passing through the second interlayer insulating layer ILD2. The alignment pad line PELT may be connected (e.g., electrically connected) to the connection pad line PCNE. For example, the alignment pad line PELT may electrically connect the lower pad line PSL to the connection pad line PCNE.

[0231] The connection pad wire PCNE may be disposed on the alignment pad wire PELT. For example, a portion of the connection pad wire PCNE may be disposed on the alignment pad wire PELT, and another portion of the connection pad wire PCNE may be disposed on the passivation layer PSV. In one or more embodiments, the connection pad wire PCNE may contact (e.g., directly contact) the alignment pad wire PELT. In one or more embodiments, the connection pad wire PCNE may include a first connection pad wire PCNE1 and a second connection pad wire PCNE2. In one or more embodiments, the connection pad wire PCNE and the first connection electrode CNE1 and / or the second connection electrode CNE2 may be formed of the same layer (or the same material). For example, the first connection pad wire PCNE1 and the first connection electrode CNE1 may be patterned by the same process. The second connection pad wire PCNE2 and the second connection electrode CNE2 may be patterned by the same process. In one or more embodiments (e.g., Fig.10 ), in the case where the first connection electrode CNE1 and the second connection electrode CNE2 are patterned by the same process, the first connection pad wire PCNE1 and the second connection pad wire PCNE2 and the first connection electrode CNE1 and the second connection electrode CNE2 may be patterned by the same process.

[0232] In one or more embodiments, the connection pad wire PCNE may be connected (eg, electrically connected) to the alignment pad wire PELT. For example, the first connection pad wire PCNE1 may be connected (eg, electrically connected) to the first alignment pad wire PELT1. The second connection pad wire PCNE2 may be connected (eg, electrically connected) to the second alignment pad wire PELT2.

[0233] The conductive element CE may be disposed on the pad line PAL in the pad area PDA. For example, the first end EP1 (or the second end EP2) of the conductive element CE may face the first alignment pad line PELT1 and the first connection pad line PCNE1 (or overlap the first alignment pad line PELT1 and the first connection pad line PCNE1). The second end EP2 (or the first end EP1) of the conductive element CE may face the second alignment pad line PELT2 and the second connection pad line PCNE2 (or overlap the second alignment pad line PELT2 and the second connection pad line PCNE2).

[0234] The conductive element CE may be disposed between the chip on film COF and the pad line PAL. For example, the conductive element CE may be disposed between the chip on film COF and the connection pad line PCNE. The conductive element CE may be disposed between the conductive connector CP and the connection pad line PCNE. The conductive element CE may be disposed between adjacent non-conductive bonding layers NCF.

[0235] In one or more embodiments, the conductive element CE may be disposed between the first alignment pad line PELT1 and the second alignment pad line PELT2. The conductive element CE may be formed. Each of the conductive elements CE may be aligned to overlap with the first alignment pad line PELT1 and the second alignment pad line PELT2. In one or more embodiments, the conductive element CE may be disposed, for example, between the first connection pad line PCNE1 and the second connection pad line PCNE2 in the length direction (or extension direction) of the conductive element CE. In one or more embodiments, the conductive element CE may be aligned in a manner similar to the manner of the process of disposing the conductive element CE in the display area DA to overlap with the first alignment pad line PELT1 and the second alignment pad line PELT2 in the pad area PDA. For example, the ink INK including the conductive element CE may be supplied to the first alignment pad line PELT1 and the second alignment pad line PELT2, the first alignment signal may be applied to the first alignment pad line PELT1, and the second alignment signal may be supplied to the second alignment pad line PELT2. The conductive element CE in the pad area PDA may be aligned on the alignment pad line PELT based on the electric field generated from the electric signal supplied to the alignment pad line PELT. In one or more embodiments, the conductive element CE may be supplied to the pad area PDA after the connection pad line PCNE is patterned. Therefore, the conductive element CE may be disposed on the connection pad line PCNE.

[0236] In one or more embodiments, the aligned conductive element CE may be electrically connected to the alignment pad line PELT and the connection pad line PCNE. The conductive pattern layer CO of the conductive element CE may be electrically connected to the alignment pad line PELT and the connection pad line PCNE. For example, the conductive pattern layer CO may contact the connection pad line PCNE so that the pad line PAL may be electrically connected to the conductive pattern layer CO. A portion of the conductive pattern layer CO may contact the first connection pad line PCNE1 in the first region S1. Another portion of the conductive pattern layer CO may contact the second connection pad line PCNE2 in the second region S2. In one or more embodiments, the outer surface of the conductive element CE on which the conductive pattern layer CO is not disposed (or the conductive pattern layer CO is not patterned) may be spaced apart from the pad line PAL.

[0237] In one or more embodiments, the second length L2 of the conductive pattern layer CO may be at least greater than the distance (or gap) between the first connection pad wire PCNE1 and the second connection pad wire PCNE2. For example, the first end of the conductive pattern layer CO may contact the first connection pad wire PCNE1, and the second end of the conductive pattern layer CO may contact the second connection pad wire PCNE2.

[0238] In one or more embodiments, a non-conductive bonding layer NCF may be formed on the pad line PAL. The non-conductive bonding layer NCF may bond the connection pad line PCNE to the chip on film COF and the conductive connector CP. The non-conductive bonding layer NCF may include an adhesive material for bonding two or more components to each other. In one or more embodiments, the non-conductive bonding layer NCF may include a non-conductive film.

[0239] The chip on film COF may be electrically connected to the pad line PAL through the conductive element CE. For example, the chip on film COF may be electrically connected to the conductive element CE through the conductive connector CP, and the conductive element CE is electrically connected to the pad line PAL. For example, a portion of the chip on film COF may be bonded to the conductive connector CP. For example, the conductive connector CP may contact a portion of the conductive pattern layer CO. For example, the conductive connector CP may be disposed between the conductive pattern layer CO and the chip on film COF, and the chip on film COF may be electrically connected to the conductive pattern layer CO. Therefore, the conductive connector CP and the conductive pattern layer CO may apply the electrical signal supplied from the chip on film COF to the pad line PAL. The conductive connector CP may include various conductive materials. For example, the conductive connector CP may include one or more materials selected from the group consisting of tin (Sn) and copper (Cu). However, the embodiment is not limited thereto.

[0240] The chip on film COF may be bonded to one or more components on the base layer BSL via a non-conductive bonding layer NCF. For example, the chip on film COF may be bonded to the connection pad line PCNE via a non-conductive bonding layer NCF. However, the embodiment is not limited thereto. In one or more embodiments, one or more insulating layers may be provided on the connection pad line PCNE, and the chip on film COF may be bonded to the one or more insulating layers via a non-conductive bonding layer NCF.

[0241] In one or more embodiments, the conductive pattern layer CO of the conductive element CE may form an electrical path in the thickness direction of the base layer BSL (e.g., in the third direction DR3). For example, the pad line PAL, the conductive element CE, and the chip on film COF may overlap each other in a plan view, and an electrical signal supplied from the flexible circuit assembly FPCB may be supplied to the pad line PAL through the chip on film COF and the conductive pattern layer CO.

[0242] For example, refer to Figures 16 to 24 A method of manufacturing a display device DD according to one or more embodiments will be described. For convenience of description, redundant descriptions of the above embodiments will be simplified or may not be repeated.

[0243] Fig.16 is a schematic flowchart illustrating a method of manufacturing a display device according to one or more embodiments. Figures 17 to 24 is a schematic diagram illustrating a method of manufacturing a display device according to one or more embodiments through process steps.

[0244] Figures 17 to 20 Based on the above reference Figure 7 The cross-sectional structure depicted illustrates the manufacturing method. Figures 17 to 20 The manufacturing method is shown based on the cross-sectional structure in the display area DA. Figures 17 to 20 In the figure, for the convenience of explanation, the illustration of the pixel circuit layer PCL is simplified.

[0245] Figure 21 to Figure 24 Based on the above reference Fig.15 The cross-sectional structure depicted illustrates the manufacturing method. Figure 21 to Figure 24 The manufacturing method is shown based on the cross-sectional structure in the pad area PDA.

[0246] Reference Fig.16 , the method of manufacturing a display device DD according to one or more embodiments may include a step S120 of setting a line on a base layer, a step S140 of providing a conductive element to a display area, a step S160 of patterning a connecting electrode, a step S180 of providing a conductive element to a pad area, and a step S190 of setting a chip on a film.

[0247] Reference Fig.16 , Fig.17 and Fig.21 In the step S120 of providing lines on the base layer, a pixel circuit layer PCL may be formed on the base layer BSL in the display area DA, and an insulating layer and a lower pad line PSL may be formed on the base layer BSL in the pad area PDA. In addition, an alignment electrode ELT may be formed on the pixel circuit layer PCL in the display area DA, and a lower pad line PSL may be formed in the pad area PDA.

[0248] In one or more embodiments, the electrodes (or wires) and the insulating layer disposed on the base layer BSL may be formed by patterning a conductive layer (or metal layer), an inorganic material, an organic material, etc. through a process using a mask.

[0249] In step S120, the source / drain layer SDL for forming the pixel circuit layer PCL may be patterned in the display area DA. In one or more embodiments, an insulating pattern layer INP may be formed on the pixel circuit layer PCL, and an alignment electrode ELT may be formed (or patterned). A first insulating layer INS1 may be formed on the alignment electrode ELT. In one or more embodiments, the first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other with an area therebetween, so that an area in which the conductive element CE may be aligned may be defined.

[0250] In step S120, in the pad area PDA, the lower pad line PSL may be patterned on the base layer BSL, and the alignment pad line PELT connected (e.g., electrically connected) to the lower pad line PSL may be patterned. For example, after setting the first lower pad line PSL1 and the second lower pad line PSL2, a second interlayer insulating layer ILD2 having contact holes formed therein may be set, and the first alignment pad line PELT1 and the second alignment pad line PELT2 may be set. Thus, the first alignment pad line PELT1 connected (e.g., electrically connected) to the first lower pad line PSL1 and the second alignment pad line PELT2 connected (e.g., electrically connected) to the second lower pad line PSL2 may be formed. In one or more embodiments, the first alignment pad line PELT1 and the second alignment pad line PELT2 may be spaced apart from each other so that an area in which the conductive element CE may be aligned may be defined.

[0251] In step S120 , after the second interlayer insulating layer ILD2 is provided, a passivation layer PSV may be provided, and the passivation layer PSV may expose a portion of the second interlayer insulating layer ILD2 so that the align pad line PELT may be provided.

[0252] Reference Fig.16 and Fig.18 In the step S140 of providing the conductive element to the display area, the conductive element CE may be aligned in the display area DA.

[0253] In step S140, a first bank BNK1 may be disposed (or formed) on the first insulating layer INS1. For example, the first bank BNK1 may define a space in which a fluid is accommodated.

[0254] In step S140, the ink INK including the conductive element CE may be supplied to a space defined by the first bank BNK1 and containing a fluid therein. For example, the ink INK including the conductive element CE and the solvent SLV may be supplied on the base layer BSL by a printing device that sprays the fluid. In one or more embodiments, the solvent SLV may include an organic solvent. For example, the solvent SLV may be one of propylene glycol methyl ether acetate (PGMEA), dipropylene glycol n-propyl ether (DGPE), and triethylene glycol n-butyl ether (TGBE). However, the embodiment is not limited thereto.

[0255] In step S140, the ink INK may be contained in the space defined by the first bank BNK1, and an alignment signal may be supplied to the alignment electrode ELT so that the conductive element CE may be aligned based on the electric field generated (or produced) from the alignment signal. As described above, the first alignment signal may be supplied to the first electrode ELT1, and the second alignment signal may be supplied to the second electrode ELT2 so that the conductive element CE may be aligned between the first electrode ELT1 and the second electrode ELT2. Subsequently, the solvent SLV may be removed (the solvent SLV may be dried).

[0256] In one or more embodiments, the conductive element CE may be aligned in a certain area in the display area DA, and in the case where an anode signal and a cathode signal are supplied to the conductive element CE by performing subsequent processes, the conductive element CE may emit light.

[0257] Reference Fig.19 , the solvent SLV may be removed, and a second insulating layer INS2 may be disposed (or patterned) on the conductive element CE.

[0258] In step S140, the second insulating layer INS2 may cover (e.g., completely cover) the conductive pattern layer CO of the conductive element CE. For example, the second insulating layer INS2 may be patterned so as to overlap (e.g., completely overlap) the conductive pattern layer CO, for example in a plan view. Therefore, the risk of the conductive pattern layer CO being electrically connected to the connection electrodes CNE1 and CNE2 in subsequent processes may be prevented.

[0259] Reference Fig.16 , Fig. 20 and Fig. 22 In the step S160 of patterning the connection electrodes, the connection electrodes CNE1 and CNE2 may be patterned in the display area DA, and the connection pad line PCNE may be patterned in the pad area PDA.

[0260] In step S160, the first connection electrode CNE1 and the second connection electrode CNE2 may be patterned in the display area DA. For example, the first connection electrode CNE1 may be provided to be connected (e.g., electrically connected) to the first end EP1 of the conductive element CE. The third insulating layer INS3 may be provided to cover the first connection electrode CNE1. For example, the second connection electrode CNE2 may be provided to be connected (e.g., electrically connected) to the second end EP2 of the conductive element CE. Therefore, the opposite ends EP1 and EP2 of the conductive element CE may be connected (e.g., electrically connected) to the first connection electrode CNE1 and the second connection electrode CNE2, so that the conductive element CE provided in the display area DA may emit light.

[0261] In one or more embodiments, the first connection electrode CNE1 and the second connection electrode CNE2 may be patterned by the same process. For example, the first connection electrode CNE1 and the second connection electrode CNE2 may be formed by deposition at the same time and may include the same material.

[0262] In step S160, the first connection pad wire PCNE1 and the second connection pad wire PCNE2 may be patterned in the pad area PDA. For example, the first connection pad wire PCNE1 may be disposed on the first alignment pad wire PELT1 and connected (e.g., electrically connected) to the first alignment pad wire PELT1. The second connection pad wire PCNE2 may be disposed on the second alignment pad wire PELT2 and connected (e.g., electrically connected) to the second alignment pad wire PELT2.

[0263] Reference Fig.16 and Fig.23 , in the step S180 of providing the conductive element to the pad area, the conductive element CE may be aligned in the pad area PDA.

[0264] In one or more embodiments, the conductive element CE aligned in the pad area PDA and the conductive element CE aligned in the display area DA may refer to the same object. For example, a process device (e.g., a printing device, etc.) used to supply the conductive element CE to the display area DA may also be used to supply the conductive element CE to the pad area PDA.

[0265] In step S180, the conductive element CE may be aligned between the first alignment pad line PELT1 and the second alignment pad line PELT2 in a manner similar to step S140 in which the conductive element CE is provided to the display area DA. For example, a first alignment signal (e.g., an AC signal) may be supplied to the first alignment pad line PELT1 and the first connection pad line PCNE1, and a second alignment signal (e.g., a ground signal) may be supplied to the second alignment pad line PELT2 and the second connection pad line PCNE2. For example, in the pad area PDA, the conductive element CE may be aligned based on an electric field generated (or produced) from the first alignment signal and the second alignment signal. In one or more embodiments, the orientation of the first end EP1 or the second end EP2 of the conductive element CE on the pad line PAL is not limited thereto.

[0266] In step S180, the conductive element CE may be electrically connected to the pad line PAL. For example, the conductive pattern layer CO of the conductive element CE may be connected (eg, electrically connected) to the connection pad line PCNE.

[0267] Reference Fig.16 and Fig.24, in the step S190 of providing the chip on film COF, the chip on film COF may be electrically connected to the conductive element CE and the pad line PAL.

[0268] In step S190, a non-conductive bonding layer NCF may be provided, and a chip on film COF bonded to a conductive connector CP may be provided on the conductive element CE. For example, the conductive pattern layer CO of the conductive element CE may be connected (e.g., electrically connected) to the conductive connector CP, so that the chip on film COF may be electrically connected to the pad line PAL through the conductive connector CP and the conductive pattern layer CO.

[0269] For example, the conductive element CE according to one or more embodiments can be used as a light emitting element in the display area DA and can also be used as an electrical connection member in the thickness direction of the base layer BSL in the pad area PDA. Therefore, the process equipment can be simplified, thereby reducing the process cost.

[0270] Subsequently, the color conversion layer CCL and the color filter layer CFL may be formed, thereby completing the manufacture of the display device DD according to one or more embodiments.

[0271] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments without departing substantially from the principles and spirit and scope of the disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A conductive element, comprising: a first semiconductor layer adjacent to the first end of the conductive element; a second semiconductor layer adjacent to the second end of the conductive element; an active layer, disposed between the first semiconductor layer and the second semiconductor layer; an element insulating layer covering the active layer and exposing the first end portion and the second end portion; as well as The conductive pattern layer is arranged on the element insulating layer.

2. The conductive element according to claim 1, wherein: The conductive pattern layer surrounds the element insulating layer in the cross-sectional direction of the conductive element, and The cross-sectional direction is different from a direction from the first end toward the second end.

3. The conductive element according to claim 1, wherein: The conductive pattern layer includes a conductive material and is electrically insulated from the first semiconductor layer, the second semiconductor layer, and the active layer by the element insulating layer.

4. The conductive element according to claim 1, wherein: The conductive pattern layer exposes a first portion of the element insulating layer adjacent to the first end portion and a second portion of the element insulating layer adjacent to the second end portion.

5. The conductive element according to claim 1, wherein: The conductive pattern layer has a thickness in a range of about 200 nm to about 350 nm.

6. The conductive element according to claim 1, wherein: The conductive element has a first length in a direction from the first end toward the second end, The conductive pattern layer has a second length in the direction from the first end toward the second end, and A ratio of the first length to the second length is in a range from about 1.3 to about 1.

6.

7. A display device, comprising: pad lines, arranged on the base layer in the pad area, the pad lines comprising a first alignment pad line and a second alignment pad line; a conductive element including at least a portion disposed on the first alignment pad line and the second alignment pad line; as well as a chip on film comprising a first portion electrically connected to the conductive element and a second portion electrically connected to the flexible circuit assembly, Wherein, the conductive element comprises: a first semiconductor layer adjacent to the first end of the conductive element; a second semiconductor layer adjacent to the second end of the conductive element; an active layer, disposed between the first semiconductor layer and the second semiconductor layer; an element insulating layer covering the active layer and exposing the first end and the second end; and A conductive pattern layer is disposed on the element insulating layer, and the conductive pattern layer electrically connects the pad wire to the chip on film.

8. The display device according to claim 7, wherein: The first alignment pad line and the second alignment pad line are spaced apart from each other, and The conductive element includes a plurality of conductive elements disposed between the first alignment pad and the second alignment pad.

9. The display device according to claim 7, wherein: The conductive pattern layer physically contacts at least a portion of the pad line.

10. The display device according to claim 9, wherein: The pad line includes a first connection pad line and a second connection pad line, the first connection pad line is on the first alignment pad line, and the second connection pad line is on the second alignment pad line. The first alignment pad line and the second alignment pad line are spaced apart from each other, A first portion of the conductive pattern layer physically contacts the first connection pad line, and The second portion of the conductive pattern layer physically contacts the second connection pad line.

11. The display device according to claim 7, wherein: A distance between the first alignment pad line and the second alignment pad line is smaller than a length of the conductive pattern layer.

12. The display device according to claim 7, further comprising: a non-conductive bonding layer to bond the chip-on-film to at least some of the components disposed on the substrate layer; as well as A conductive connector is disposed between the chip on film and the conductive pattern layer, and the conductive connector electrically connects the chip on film to the conductive pattern layer.

13. The display device according to claim 7, further comprising: electrodes, arranged on the substrate layer in the display area, each electrode comprising a first electrode and a second electrode, Wherein, a portion of the conductive element is aligned between the first electrode and the second electrode to emit light in the display area.

14. The display device according to claim 13, further comprising: A first insulating layer is disposed on the first electrode and the second electrode; as well as The insulating pattern layer is disposed on the first insulating layer and protrudes in a thickness direction of the base layer.

15. The display device according to claim 13, further comprising: a first connecting electrode electrically connected to the first end of the conductive element in the display area; as well as a second connecting electrode electrically connected to the second end of the conductive element in the display area, Wherein, the first connecting electrode and the second connecting electrode are electrically insulated from the conductive pattern layer.

16. The display device according to claim 13, further comprising: a first connecting electrode electrically connected to the first end of the conductive element in the display area; as well as a second connecting electrode electrically connected to the second end of the conductive element in the display area, The first connection electrode and the second connection electrode are electrically insulated from the conductive pattern layer and are formed from the same layer.

17. The display device according to claim 13, further comprising: a first insulating layer, disposed on the first electrode and the second electrode, The conductive element and the first insulating layer in the display area form an empty space in an area where the conductive pattern layer is not provided.

18. The display device according to claim 17, further comprising: A second insulating layer completely covers the conductive pattern layer of the conductive element in the display area.

19. A display device, comprising: A first electrode and a second electrode are disposed on the substrate layer; A conductive element, disposed on the first electrode and the second electrode; a first connecting electrode electrically connected to a first end of the conductive element; as well as a second connecting electrode electrically connected to the second end of the conductive element, Wherein, the conductive element comprises: a first semiconductor layer adjacent to the first end; a second semiconductor layer adjacent to the second end; an active layer, disposed between the first semiconductor layer and the second semiconductor layer; an element insulating layer covering the active layer and exposing the first end and the second end; and The conductive pattern layer is arranged on the element insulating layer.

20. A display device, comprising: A pad line is arranged on the base layer; a plurality of conductive elements electrically connected to the pad wires; a chip on film including a first portion electrically connected to the plurality of conductive elements and a second portion electrically connected to the flexible circuit assembly; as well as A non-conductive bonding layer bonds the chip on film to some of the components disposed on the base layer.

21. A method for manufacturing a display device, the method comprising: Arranging electrodes on a substrate layer including a pad region and a display region, the electrodes including an alignment pad line arranged in the pad region and an alignment electrode arranged in the display region; disposing a conductive element on the alignment electrode in the display area; patterning connecting electrodes on the base layer; disposing the conductive element on the alignment pad line in the pad region; as well as A chip on film is electrically connected to the conductive elements in the pad area, the chip on film being electrically connected to a flexible circuit assembly.

22. The method according to claim 21, wherein: The step of disposing the conductive element in the display area comprises: supplying ink including the conductive element onto the base layer; applying an alignment signal to each of the electrodes; and The conductive elements are aligned on the electrodes by an electric field formed by the alignment signal.

23. The method according to claim 21, wherein: The apparatus for disposing the conductive element in the display area is substantially the same as the apparatus for disposing the conductive element in the pad area.

24. The method according to claim 21, wherein: The step of patterning the connecting electrode comprises: patterning a first connection electrode and a second connection electrode electrically connected to the conductive element in the display area; and The connection pad lines are patterned on the alignment pad lines in the pad area.

25. The method according to claim 24, wherein: Each of the conductive elements comprises: a first semiconductor layer adjacent to the first end of each conductive element; a second semiconductor layer adjacent to the second end of each conductive element; an active layer, disposed between the first semiconductor layer and the second semiconductor layer; an element insulating layer covering the active layer and exposing the first end and the second end; and A conductive pattern layer is disposed on the element insulating layer, and The step of arranging the conductive element in the pad area includes arranging the connection pad line to contact the conductive pattern layer.

26. The method according to claim 25, wherein: The step of electrically connecting the chip on film to the conductive element in the pad region includes electrically connecting the conductive pattern layer to the chip on film through a conductive connector.

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