Preparation method of shallow trench isolation structure and semiconductor structure

Abstract

The present invention provides a method for preparing a shallow trench isolation structure and a semiconductor structure, and specifically relates to the field of semiconductor technology. The method for preparing the shallow trench isolation structure comprises: providing a substrate, the substrate comprising a substrate and a trench oxide formed in the substrate, the trench oxide having a depression in a portion protruding from the substrate; forming a patterned hard mask layer on the substrate, the patterned hard mask layer having an opening in a region corresponding to the trench oxide; forming an oxide layer on the patterned hard mask layer, the oxide layer covering the trench oxide and filling the depression; using the patterned hard mask layer as a stop layer, flattening the oxide layer; and removing the patterned hard mask layer. The method can effectively improve the depression problem in the shallow trench isolation structure and improve the reliability of the device.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a preparation method of a shallow trench isolation structure and a semiconductor structure. Background Art

[0002] As the size of semiconductor devices continues to decrease, the size of the isolation region between devices is also reduced accordingly. Currently, most of the isolation between devices is achieved by using a shallow trench isolation (STI) structure.

[0003] In the prior art, during the removal of the pad oxide layer in the shallow trench isolation process, the sharp corners of the STI oxide edges will be eroded from both sides, accelerating the formation of a divot at the corner of the trench oxide, thereby affecting the reliability of the device. Summary of the invention

[0004] In view of the above shortcomings of the prior art, the present invention provides a method for preparing a shallow trench isolation structure and a semiconductor structure to improve the depression problem in the shallow trench isolation structure.

[0005] To achieve the above object and other related objects, the present invention provides a method for preparing a shallow trench isolation structure, the method comprising the following steps:

[0006] Providing a substrate, the substrate comprising a substrate and a trench oxide formed in the substrate, wherein a portion of the trench oxide protruding from the substrate has a recess;

[0007] forming a patterned hard mask layer on the substrate, the patterned hard mask layer having an opening in a region corresponding to the trench oxide;

[0008] forming an oxide layer on the patterned hard mask layer, the oxide layer covering the trench oxide and filling the recess;

[0009] Using the patterned hard mask layer as a stop layer, planarizing the oxide layer;

[0010] The patterned hard mask layer is removed.

[0011] In one embodiment of the present invention, forming a patterned hard mask layer on the substrate includes:

[0012] forming a hard mask layer on the substrate, wherein the hard mask layer covers the substrate and the trench oxide;

[0013] forming a patterned photoresist layer on the hard mask layer, wherein the patterned photoresist layer has a first opening exposing the hard mask layer at a position corresponding to the trench oxide;

[0014] The hard mask layer is etched using the patterned photoresist layer as a mask to form an opening in a region of the hard mask layer corresponding to the trench oxide.

[0015] In one embodiment of the present invention, the material of the hard mask layer includes silicon nitride, and the thickness of the silicon nitride is 300 to 400 angstroms.

[0016] In one embodiment of the present invention, the material of the oxide layer and the material of the trench oxide are both selected from silicon oxide, and the thickness of the oxide layer is greater than the thickness of the hard mask layer.

[0017] In an embodiment of the present invention, before removing the hard mask layer, the method further includes removing a portion of the oxide layer to adjust the height difference between the trench oxide and the substrate.

[0018] In one embodiment of the present invention, the method for removing part of the oxide layer includes removing part of the oxide layer by hydrofluoric acid wet etching.

[0019] In one embodiment of the present invention, the method for removing the hard mask layer includes removing the hard mask layer by wet etching using hot phosphoric acid.

[0020] In one embodiment of the present invention, the method for forming the oxide layer includes a high aspect ratio deposition process, and the thickness of the oxide layer is 800 to 1000 angstroms.

[0021] In one embodiment of the present invention, the process of providing a substrate comprises the following steps:

[0022] forming a pad oxide layer on the substrate;

[0023] forming a pad nitride layer on the pad oxide layer;

[0024] forming an isolation pattern on the pad nitride layer;

[0025] Using the isolation pattern as a mask, sequentially etching the pad nitride layer, the pad oxide layer and the substrate to form a shallow trench;

[0026] Filling oxide in the shallow trench to form a trench oxide;

[0027] The pad nitride layer and the pad oxide layer are removed.

[0028] Another aspect of the present invention provides a semiconductor structure, which includes a shallow trench isolation structure prepared by the above preparation method.

[0029] In summary, the present invention provides a method for preparing a shallow trench isolation structure. After removing the pad oxide layer, a patterned hard mask layer exposing the trench oxide is first formed on the substrate, and then an oxide layer covering the hard mask layer and the trench oxide is formed on the patterned hard mask layer, and the oxide layer is used to fill the depression on the trench oxide. The oxide layer is then planarized and the patterned hard mask layer is removed. The unexpected effect is that the formation of the oxide layer can repair and compensate for the depression on the trench oxide generated when the pad oxide layer is removed.

[0030] In addition, wet etching technology can be used to remove part of the oxide layer and precisely control the height difference between the shallow trench isolation oxide and the substrate active area to meet the target requirements. During the etching process of the oxide layer, the patterned hard mask layer can serve as a sidewall barrier to protect the trench oxide from damage, thereby improving the STI oxide depression problem.

[0031] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 is a flow chart of a method for preparing a shallow trench isolation structure in one embodiment of the present invention;

[0034] Figure 2 A schematic structural diagram of a substrate forming process in one embodiment of the present invention;

[0035] Figure 3 It is a structural schematic diagram of removing the pad oxide layer in one embodiment of the present invention;

[0036] Figure 4 This is a photo of a real object after the pad oxide layer is removed in one embodiment of the present invention;

[0037] Figure 5 It is a schematic diagram of a structure for forming a hard mask layer in one embodiment of the present invention;

[0038] Figure 6 It is a schematic diagram of a structure for forming an opening on a hard mask layer in one embodiment of the present invention;

[0039] Figure 7 A schematic diagram of a structure for forming an oxide layer in one embodiment of the present invention;

[0040] Figure 8 It is a schematic diagram of the structure after the oxide layer is planarized in one embodiment of the present invention;

[0041] Fig. 9 It is a schematic diagram of a structure in which a portion of an oxide layer is removed in one embodiment of the present invention;

[0042] Fig.10 It is a schematic structural diagram of removing a patterned hard mask layer in one embodiment of the present invention.

[0043] Description of labels:

[0044] 100, base; 110, substrate; 111, trench oxide; 112, recess; 120, pad oxide layer; 130, pad nitride layer; 140, patterned hard mask layer; 141, opening; 142, hard mask layer; 150, oxide layer. DETAILED DESCRIPTION

[0045] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0047] In the present invention, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0048] Shallow Trench Isolation (STI) structure is widely used in semiconductor devices to achieve physical isolation between devices. At present, the shallow trench isolation process is to first form a pad oxide layer and a pad nitride layer on the substrate in sequence, and then fill the shallow trench with trench oxide after etching to form a shallow trench. Finally, the pad nitride layer and the pad oxide layer are removed to form a shallow trench isolation structure. When removing the pad oxide layer, wet etching is generally used. Due to the isotropy of wet etching, the raised trench oxide will be eroded by etching liquid in multiple directions, and the trench oxide near the corner of the substrate will be eroded to form a depression (such as Figure 3 and Figure 4 as shown).

[0049] In order to improve the above problems, the present invention provides a method for preparing a shallow trench isolation structure. After the pad oxide layer is removed, a patterned hard mask layer exposing the trench oxide is formed on the substrate, and then an oxide layer is formed on the patterned hard mask layer. The oxide layer is used to fill the depressions on the trench oxide, thereby improving the depression problem on the STI oxide.

[0050] See also Figure 1 The present invention provides a method for preparing a shallow trench isolation structure, comprising the following steps:

[0051] S1. Provide a substrate 100, wherein the substrate 100 includes a substrate 110 and a trench oxide 111 formed in the substrate 110, wherein a portion of the trench oxide 111 protruding from the substrate 110 has a recess 112 (see Figure 3 );

[0052] S2, forming a patterned hard mask layer 140 on the substrate 110, wherein the patterned hard mask layer 140 has an opening 141 in a region corresponding to the trench oxide 111 (see Figure 6 );

[0053] S3, forming an oxide layer 150 on the patterned hard mask layer 140, wherein the oxide layer 150 covers the trench oxide 111 and fills the recess 112 (see Figure 7 );

[0054] S4, using the patterned hard mask layer 140 as a stop layer, planarizing the oxide layer 150 (see Figure 8 );

[0055] S5, removing the patterned hard mask layer 140 (see Fig.10 ).

[0056] Combine the following Figures 2 to 10 The steps of the preparation method of the shallow trench isolation structure are introduced in detail.

[0057] See also Figures 2 to 4 , the base 100 in step S1 includes a substrate 110 and a trench oxide 111 formed on the substrate 110. The substrate 110 may be any material suitable for forming a semiconductor device, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), aluminum nitride (AlN), indium nitride (InN), gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), silicon germanium (GeSi), sapphire or other semiconductor materials formed by III / V compounds; the substrate 110 may also be a stacked structure, such as silicon / germanium / silicon stacking; the substrate 110 may also be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. In this embodiment, the substrate 110 is, for example, a silicon substrate. The trench oxide 111 is an insulating material used to isolate devices, such as silicon oxide. The area of ​​the substrate 110 between adjacent trench oxides 111 is an active area. Each active area can be used to form a semiconductor device. As an example, the semiconductor device can be, for example, a transistor, a memory, a capacitor, etc.

[0058] The process of providing the substrate 100 in step S1 is specifically as follows:

[0059] A pad oxide layer 120 is formed on the substrate 110. The pad oxide layer 120, as a buffer layer, can improve the stress between the substrate 110 and the subsequently formed pad nitride layer 130. The pad oxide layer 120 is, for example, a dense silicon oxide material. The pad oxide layer 120 can be formed by dry oxidation, wet oxidation, or in-situ steam growth (ISSG).

[0060] A pad nitride layer 130 is formed on the pad oxide layer 120. The pad nitride layer 130 is, for example, silicon nitride (Si3N4). The pad nitride layer 130 can be used as a hard mask layer during trench etching to protect the substrate 110 from damage. The pad nitride layer 130 can be formed by a method such as low pressure chemical vapor deposition (LPCVD).

[0061] An isolation pattern (not shown in the figure) is formed on the pad nitride layer 130. For example, a photoresist is first spin-coated on the pad nitride layer 130 to cover the upper surface of the pad nitride layer 130. After exposure and development, an isolation pattern having an exposed portion of the pad nitride layer 130 is formed on the photoresist; the position of the exposed portion of the pad nitride layer 130 on the photoresist corresponds to the position of the shallow trench isolation structure.

[0062] Next, using the photoresist with the isolation pattern as a mask, the pad nitride layer 130, the pad oxide layer 120 and a portion of the substrate 110 are etched in sequence to form a shallow groove. In the present embodiment, for example, dry etching is used to form the shallow groove (not shown in the figure). After the etching is completed, the photoresist is removed. The removal method can be a dry stripping method, for example, using oxygen to react chemically with the photoresist to remove the photoresist. A wet stripping method can also be used, for example, a mixed solution of sulfuric acid and hydrogen peroxide can be used to remove the photoresist.

[0063] A trench oxide 111 is filled in the shallow trench until the trench oxide 111 covers the surface of the pad nitride layer 130. In this embodiment, the trench oxide 111 is, for example, silicon oxide. Silicon oxide can be formed, for example, by high aspect ratio chemical vapor deposition (High Aspect Ratio Process CVD, HARP-CVD). In other embodiments, the trench oxide 111 can also be formed by high density plasma chemical vapor deposition (High Density Plasma CVD, HDP-CVD) and other methods.

[0064] Then, a chemical mechanical polishing (CMP) process is used to planarize the trench oxide 111 to remove the trench oxide 111 on the pad nitride layer 130. Then, an etching process is performed to remove the pad nitride layer 130 and the pad oxide layer 120. The pad nitride layer 130 is removed by a hot phosphoric acid wet etching process; the pad oxide layer 120 is removed by a hydrofluoric acid wet etching process. Due to the isotropy of wet etching, when removing the pad oxide layer 120, the raised trench oxide 111 is eroded by the hydrofluoric acid etchant in multiple directions, and a recess 112 is formed on both sides of the trench oxide 111 close to the substrate 110, as shown in FIG. Figure 3 and Figure 4 The structure shown.

[0065] See also Figure 5 and Figure 6 , performing step S2 to form a patterned hard mask layer 140 on the substrate 110 , wherein the patterned hard mask layer 140 has an opening 141 in a region corresponding to the trench oxide 111 .

[0066] Specifically, a hard mask layer 142 is first formed on the substrate 110, and the hard mask layer 142 covers the substrate 110, the trench oxide 111, and the recess 112 on the trench oxide 111. The material of the hard mask layer 142 is, for example, silicon nitride (Si3N4), and it can be formed by processes such as plasma enhanced chemical vapor deposition (PECVD) and low pressure chemical vapor deposition (LPCVD). For example, the wafer structure after step S1 is placed in a chamber of a CVD machine filled with silane (SiH4) and ammonia (NH3), and reacts at a pressure of, for example, 2Torr~10Torr and a temperature of, for example, 300°C~500°C to deposit silicon nitride on the substrate 110. The thickness of silicon nitride can be adjusted by controlling the reaction time. In the present application, the deposition thickness of silicon nitride can at least completely cover the top of the trench oxide 111, and silicon nitride is not easy to be too thick, which will increase the difficulty of subsequent removal. In some embodiments, the thickness of silicon nitride is 300 to 400 angstroms, for example, 300 angstroms, 350 angstroms or 400 angstroms. Then, a patterned photoresist layer (not shown in the figure) is formed on the hard mask layer 142, wherein the patterned photoresist layer has a first opening exposing the hard mask layer 142 at the position corresponding to the trench oxide 111, and the patterned photoresist layer can be formed by spin coating photoresist, exposure and development process. Next, the hard mask layer 142 is etched using the patterned photoresist layer as a mask, and the hard mask layer 142 not covered by the photoresist layer is removed, thereby forming an opening 141 exposing the trench oxide 111 on the hard mask layer 142. The etching process of the hard mask layer 142 can be wet etching or dry etching. Afterwards, the photoresist layer can be removed by dry or wet stripping to form a patterned hard mask layer 140. Since the patterned hard mask layer 140 has an opening 141 in the area corresponding to the trench oxide 111 to completely expose the trench oxide 111, the same mask as that used in step S1 to form the shallow trench can be used in the exposure process of forming the patterned photoresist layer in this step without the need for an additional mask. In this way, while achieving the purpose of exposing the trench oxide 111, the mask can be reused without increasing the mask cost.

[0067] See also Figure 7 , performing step S3 to form an oxide layer 150 on the patterned hard mask layer 140 .

[0068] In this step, the oxide layer 150 is formed on the patterned hard mask layer 140, and since the patterned hard mask layer 140 has an opening 141, the oxide layer 150 will also fill in the opening 141 during the formation process to completely cover the trench oxide 111, thereby filling the recess 112 on the trench oxide 111. Further, the oxide layer 150 is made of the same material as the trench oxide 111, such as silicon oxide. The oxide layer 150 can be formed by a high aspect ratio chemical vapor deposition (HARP-CVD) method. In other embodiments, the oxide layer 150 can also be formed by a process such as high density plasma chemical vapor deposition (HDP-CVD). The deposition thickness of the oxide layer 150 should at least exceed the height of the patterned hard mask layer 140. In some embodiments, the thickness of the oxide layer 150 is 800 to 1000 angstroms, for example, 800 angstroms, 900 angstroms, 950 angstroms or 1000 angstroms.

[0069] See also Figure 8 After the deposition of the oxide layer 150 is completed, step S4 is performed to planarize the oxide layer 150 to remove the oxide layer 150 covering the patterned hard mask layer 140 to obtain a flat trench oxide 111 plane.

[0070] In this step, the planarization process adopts a chemical mechanical polishing (CMP) process, that is, the patterned hard mask layer 140 is used as a stop layer, and the oxide layer 150 is planarized by a CMP process to remove the oxide layer 150 covering the patterned hard mask layer 140 .

[0071] See also Fig. 9 In one embodiment, after the planarization process is completed, part of the oxide layer 150 in the opening 141 may be further removed to adjust the height difference between the trench oxide 111 and the active area of ​​the substrate 110 .

[0072] The removal thickness of the oxide layer 150 in the opening 141 can be set according to actual needs and is not limited here. The removal method of the oxide layer 150 can be, for example, wet etching, that is, the wet etching technology is used to remove part of the oxide layer 150 above the trench oxide 111 to achieve the target thickness, so as to adjust the height difference between the trench oxide 111 and the active area of ​​the substrate 110. The specific steps are: wet hydrofluoric acid etching is performed on the oxide layer 150 above the trench oxide 111. Due to the protective effect of the sidewall patterned hard mask layer 140, the wet etching will not produce isotropic drilling on the sidewall. It should be noted that isotropic drilling has no directional selectivity. In addition to the longitudinal reaction, the lateral reaction also occurs simultaneously. In this embodiment, due to the blocking of the sidewall patterned hard mask layer 140, the lateral reaction will not occur.

[0073] See also Fig.10 , executing step S5 to remove the patterned hard mask layer 140 .

[0074] In this step, the method for removing the patterned hard mask layer 140 is, for example, wet etching, which specifically includes: removing the patterned hard mask layer 140 by wet etching using hot phosphoric acid.

[0075] After step S5 is completed, a shallow trench isolation structure can be obtained. After removing the pad oxide layer, the shallow trench isolation structure prepared by the present invention forms a patterned hard mask layer on the substrate, and then forms an oxide layer on the patterned hard mask layer, and uses the oxide layer to fill the opening of the patterned hard mask layer to repair the depression problem of the trench oxide caused by the removal of the pad oxide layer; in addition, part of the oxide layer can be removed by wet etching technology to adjust the height difference between the shallow trench isolation oxide and the active area of ​​the substrate to meet the target requirements. During the etching process of the oxide layer, the hard mask layer can serve as a sidewall barrier layer to protect the trench oxide from damage, thereby improving the depression problem of the STI oxide.

[0076] The present invention also provides a semiconductor structure, which includes a shallow trench isolation structure prepared by the above preparation method. The shallow trench isolation structure is used for physical isolation between adjacent devices.

[0077] In some embodiments, the semiconductor structure includes but is not limited to one or more of semiconductor devices such as field effect transistor (FET), metal-oxide-semiconductor field-effect transistor (MOSFET), complementary metal oxide semiconductor (CMOS), insulated gate bipolar transistor (IGBT), gate turn off thyristor (GTO) or thyristor.

[0078] The preparation method of the shallow trench isolation structure of the present invention, after removing the pad oxide layer, first forms a patterned hard mask layer exposing the trench oxide on the substrate, and then forms an oxide layer covering the hard mask layer and the trench oxide on the patterned hard mask layer, and uses the oxide layer to fill the depression on the trench oxide. Then, the oxide layer is planarized and the hard mask layer is removed. The formation of the oxide layer can repair and compensate for the depression on the trench oxide when the pad oxide layer is removed. In addition, part of the oxide layer can be removed by wet etching technology, and the height difference between the shallow trench isolation structure and the substrate can be accurately controlled to meet the target requirements. During the etching process of the oxide layer, the hard mask layer can serve as a sidewall barrier layer, which can protect the trench oxide from damage, thereby improving the depression problem of the STI oxide. Therefore, the present invention effectively overcomes some practical problems in the prior art and has high utilization value and use significance.

[0079] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a shallow trench isolation structure, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising a substrate and a trench oxide formed in the substrate, wherein a portion of the trench oxide protruding from the substrate has a recess; forming a patterned hard mask layer on the substrate, the patterned hard mask layer having an opening in a region corresponding to the trench oxide; forming an oxide layer on the patterned hard mask layer, the oxide layer covering the trench oxide and filling the recess; Using the patterned hard mask layer as a stop layer, planarizing the oxide layer; removing a portion of the oxide layer to adjust the height difference between the trench oxide and the substrate; The patterned hard mask layer is removed.

2. The preparation method according to claim 1, characterized in that: Forming a patterned hard mask layer on the substrate, comprising: forming a hard mask layer on the substrate, wherein the hard mask layer covers the substrate and the trench oxide; forming a patterned photoresist layer on the hard mask layer, wherein the patterned photoresist layer has a first opening exposing the hard mask layer at a position corresponding to the trench oxide; The hard mask layer is etched using the patterned photoresist layer as a mask to form an opening in a region of the hard mask layer corresponding to the trench oxide.

3. The preparation method according to claim 1 or 2, characterized in that: The material of the hard mask layer includes silicon nitride, and the thickness of the silicon nitride is 300 to 400 angstroms.

4. The preparation method according to claim 1, characterized in that: The material of the oxide layer and the material of the trench oxide are both selected from silicon oxide, and the thickness of the oxide layer is greater than the thickness of the hard mask layer.

5. The preparation method according to claim 1, characterized in that: The method for removing part of the oxide layer includes removing part of the oxide layer by hydrofluoric acid wet etching.

6. The preparation method according to claim 1, characterized in that: The method of removing the hard mask layer includes removing the hard mask layer by wet etching using hot phosphoric acid.

7. The preparation method according to claim 1, characterized in that: The method for forming the oxide layer includes a high aspect ratio deposition process, and the thickness of the oxide layer is 800 to 1000 angstroms.

8. The preparation method according to claim 1, characterized in that: The process of providing a substrate comprises the following steps: forming a pad oxide layer on the substrate; forming a pad nitride layer on the pad oxide layer; forming an isolation pattern on the pad nitride layer; Using the isolation pattern as a mask, sequentially etching the pad nitride layer, the pad oxide layer and the substrate to form a shallow trench; Filling oxide in the shallow trench to form a trench oxide; The pad nitride layer and the pad oxide layer are removed.

9. A semiconductor structure, characterized in that: A shallow trench isolation structure prepared by the preparation method according to any one of claims 1 to 8.

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