Manufacturing method of biological pressure sensor chip

Abstract

The invention discloses a method for manufacturing a biological pressure sensor chip. The method comprises the following steps of: forming a pressure sensitive resistor with a relatively low resistance value in a substrate through a multi-ion implantation process; processing and forming a wafer layer at the bottom of the chip by using a dry etching process; and depositing a passivation layer on the surface of the chip by adopting a chemical vapor deposition process. According to the invention, the resistor obtained through a multi-ion implantation technology has relatively low conductivity and small bridge resistance, so that the chip has high sensitivity and precision; the dry etching directivity is good, and high-precision machining can be achieved; a compact Si3N4 passivation layer is formed on the surface of the chip by using a chemical deposition method, so that compactness and chemical stability are achieved, and the radiation resistance of the chip is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of biological pressure sensors, and in particular to a method for manufacturing a biological pressure sensor chip. Background Art

[0002] As an important branch of biomedicine, biomedical sensors are tools for obtaining physiological and pathological information of the human body. They can convert the measured physiological parameters into corresponding electrical signal outputs, providing the necessary data for the research and analysis of clinical diagnosis. Specifically, pressure sensors are used everywhere in the biopharmaceutical field, and are key components in filtration systems and monitoring systems. Therefore, in order to meet the needs of the biopharmaceutical field, the requirements for a series of parameters of pressure sensors should be higher, such as small size, high precision, sensitivity, reliability and stability. Summary of the invention

[0003] In view of the above technical problems, the purpose of the present invention is to provide a method for manufacturing a biological pressure sensor chip, wherein the substrate adopts a multiple ion implantation process to prepare a low-resistance pressure-sensitive resistor to achieve high precision and high sensitivity; the bottom wafer layer of the chip adopts dry etching to achieve high-precision processing; the chip adopts low-pressure chemical vapor deposition to form a dense Si3N4 passivation layer on the surface to improve the chip's radiation resistance.

[0004] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0005] A method for manufacturing a biological pressure sensor chip comprises the following steps:

[0006] A pressure sensitive resistor with a relatively low resistance value is formed in the substrate by a multiple ion implantation process;

[0007] The dry etching process is used to process and shape the wafer layer at the bottom of the chip;

[0008] A passivation layer is deposited on the chip surface using a chemical vapor deposition process.

[0009] In some technical solutions, the multiple ion implantation process is to form an implantation layer by injecting impurity gas into the substrate to change the resistivity of the substrate, thereby adjusting the resistance value of the pressure sensitive resistor.

[0010] In some technical solutions, the specific steps of injecting impurity gas into the substrate are:

[0011] A mask layer is made on the surface of the substrate, and the mask layer is patterned by photolithography or dry etching to form an ion implantation window, through which impurity gas is injected into the substrate.

[0012] In some technical solutions, the mask layer is a deposited oxide layer or a coated photoresist layer.

[0013] In some technical solutions, the multiple ion implantation process further includes:

[0014] Controlling the resistivity of the implanted layer by controlling the impurity dosage of each implantation; and / or,

[0015] The uniformity of impurity gas injection is ensured by scanning the substrate surface multiple times.

[0016] In some technical solutions, the dry etching process uses SF6 gas to etch the silicon bottom and side walls, then introduces C4F8 gas to passivate the etched cavity, and deposits a polymer film on the side walls and the silicon bottom surface.

[0017] In some technical solutions, the specific steps of the dry etching process are:

[0018] An appropriate amount of SF6 gas is injected into the plasma reaction chamber to obtain dissociated active fluorine atoms, which react with the silicon surface to generate SiF4, which is then pumped away by a vacuum pump to form a cavity structure after silicon etching;

[0019] Injecting C4F8 gas into the cavity structure to obtain dissociated active groups, which are polymerized at the bottom and sidewalls of the cavity structure to deposit a passivation layer;

[0020] SF6 gas is injected into the passivation layer again to attack the passivation layer at the bottom of the cavity. After the passivation layer at the bottom disappears, silicon etching is continued on the bottom of the cavity. This process is repeated so that the passivation layer on the side wall of the cavity is retained, and finally a silicon substrate with a target etching depth is obtained.

[0021] In some technical solutions, the chemical vapor deposition process refers to depositing a Si3N4 passivation layer onto the chip surface.

[0022] In some technical solutions, the specific steps of the chemical vapor deposition process are:

[0023] Performing a standard wet cleaning of the substrate using a cleaning solution;

[0024] Placing the cleaned wafer into a reaction chamber and evacuating the reaction chamber;

[0025] In a vacuum environment, dichlorosilane and ammonia are introduced to deposit a Si3N4 passivation layer.

[0026] In some technical solutions, the volume ratio of dichlorosilane to ammonia is controlled between 0.75 and 5.75; and / or,

[0027] During the reaction, the gas pressure in the reaction chamber was controlled below 100 Pa and the temperature was maintained at 750-810°C.

[0028] The present invention adopts the above technical solution to have at least the following beneficial effects:

[0029] The resistor obtained by the multiple ion implantation process in the present invention has a relatively lower conductivity and a smaller bridge resistance, so that the chip has higher sensitivity and precision; the dry etching has good directionality and can achieve high-precision processing; a dense Si3N4 passivation layer is formed on the chip surface by chemical deposition method, which has density and chemical stability, and the chip's radiation resistance is improved.

[0030] The present invention combines multiple ion implantation, dry etching and chemical vapor deposition to form a biopressure sensor chip with high sensitivity, high precision, high reliability and low power consumption. The combination of these technologies effectively improves the comprehensive performance of the sensor, making it particularly suitable for applications in the biomedical field for accurate monitoring of pressure changes. Its advantages in miniaturization, high integration and long-term stability provide innovative solutions for the development of biopressure sensor technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings and their marks required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 A schematic diagram of a multiple ion implantation process according to an embodiment of the present invention;

[0033] Figure 2 A schematic diagram of a dry etching process and a wet etching process according to an embodiment of the present invention;

[0034] Figure 3 Schematic diagram of the alternately implemented etching and passivation steps according to an embodiment of the present invention.

[0035] The meanings of the symbols in the figure are as follows:

[0036] 1—impurity gas, 2—mask layer, 3—implantation layer, 4—silicon substrate, 5—pressure sensitive resistor layer, 6—dry cavity, 7—wet cavity, 8—passivation layer, 9—SF6 gas. DETAILED DESCRIPTION

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0038] The present invention provides a method for manufacturing a biopressure sensor chip. The chip adopts a multiple ion implantation process to prepare a low-resistance pressure sensitive resistor; the bottom wafer layer of the chip adopts a dry etching process to process a silicon substrate 4; and the surface of the chip adopts a low-pressure chemical deposition method to form a Si3N4 passivation layer.

[0039] In a specific embodiment, the multiple ion implantation process is to form an implantation layer 3 by injecting impurity gas 1 into the substrate to change the resistivity of the substrate, thereby adjusting the resistance value of the pressure sensitive resistor.

[0040] In order to achieve the purpose of low resistance of the pressure sensitive resistor, the present invention uses multiple ion implantation to adjust the overall concentration distribution of doped ions in the ion implantation layer. The relevant formula is as follows:

[0041]

[0042] Where Q is the dose of doped ions, I is the flow rate of the ion beam, t is the implantation time, e is the electron charge, n is the ion charge, A is the implantation area, R is the resistor value, ρ is the resistivity, L is the resistor length, and S is the cross-sectional area.

[0043] By adjusting the ion implantation energy and implantation dose, the doping density of the implantation layer 3 can be controlled, thereby adjusting the resistivity. In particular, the ion implanter performs uniform ion implantation on the surface of the silicon wafer by scanning the surface of the silicon wafer multiple times during operation.

[0044] like Figure 1 , a mask layer 2 is made on the surface of the substrate, and the mask layer 2 is patterned by photolithography or dry etching process to form an ion implantation window, and the impurity gas 1 is injected into the substrate through the ion implantation window. Specifically, the mask layer 2 is a deposited oxide layer or a coated photoresist layer. Taking SiO2 as an example, under atmospheric pressure, chemical vapor deposition is used to deposit the reactants of SiH4 and N2O on the chip surface to form a SiO2 passivation layer, which can be used as a mask layer 2 for implementing multiple ion implantation operations.

[0045] In this scheme, ions or impurity gases are injected into the p-type silicon substrate by multiple scans to form an injection layer 3, which changes the resistivity of the substrate. In this way, the resistance of the pressure sensitive resistor can be accurately adjusted. The ion implantation process can accurately control the doping concentration and distribution, ensure the uniformity of the resistance, and thus improve the sensitivity and accuracy of the sensor to pressure changes. This technology enables the sensor to respond quickly to extremely small pressure changes and is suitable for high-precision biomedical SF6 gas applications.

[0046] In another specific embodiment, the dry etching process is to etch the silicon bottom and sidewalls using 9, and then introduce C4F8 gas to passivate the etched cavity, and deposit a polymer film on the sidewalls and the silicon bottom surface.

[0047] like Figure 2 , which is a schematic diagram of a dry etching process and a wet etching process, specifically shows the pressure sensitive resistor layer 5 and the dry cavity 6 after the dry etching process, and the pressure sensitive resistor layer 5 and the wet cavity 7 after the wet etching process. Wet etching is pure chemical etching, and the etching line width is above 3μm. It can only complete isotropic etching with poor uniformity and low precision, and will produce liquid that pollutes the environment; while dry etching uses gas etching, does not require liquid chemicals, and can reduce environmental pollution under certain circumstances; in addition, dry etching can complete anisotropic etching, can achieve more precise control, and is suitable for devices with smaller feature sizes.

[0048] Therefore, dry etching is preferred in this solution, using SF6 as etching gas and C4F8 as passivation gas. The dry etching process is carried out alternately through three steps of silicon etching, cavity passivation, and passivation layer etching as one cycle.

[0049] Combined with reference Figure 3 , specifically including the following steps:

[0050] An appropriate amount of SF6 gas 9 is injected into the plasma reaction chamber to obtain dissociated active fluorine atoms, which react with the silicon surface to generate SiF4, which is then pumped away by a vacuum pump to form a cavity structure after silicon etching;

[0051] Inject C4F8 gas into the cavity structure to obtain dissociated active groups, which polymerize at the bottom and sidewalls of the cavity structure to deposit a passivation layer 8;

[0052] SF6 gas 9 is injected onto the passivation layer 8 again to attack the passivation layer 8 at the bottom of the cavity. After the passivation layer 8 at the bottom disappears, silicon etching is continued on the bottom of the cavity. This process is repeated so that the passivation layer 8 on the side wall of the cavity is retained, and finally a silicon substrate 4 with a target etching depth is obtained.

[0053] In this solution, SF6 gas 9 is used to etch the silicon bottom and sidewalls, and then C4F8 gas is used for passivation to form a protective layer. The high directionality of dry etching technology allows the chip to achieve anisotropic etching, and can process precise cavity structures on the silicon substrate 4, which is particularly suitable for making micro-nano scale structures. The accuracy of this process is higher than that of traditional wet etching, avoiding the isotropic etching problem caused by chemical liquids and reducing environmental pollution. Through the alternating process of dry etching and passivation, high-precision processing of the silicon substrate 4 is achieved, ensuring that the geometric structure of the chip meets the design requirements and improving the consistency and controllability of processing.

[0054] In another embodiment, the chemical vapor deposition process refers to depositing a Si3N4 passivation layer on the chip surface. Si3N4 has compactness and chemical stability, and the radiation resistance of the chip is improved. The specific steps are:

[0055] Performing a standard wet cleaning of the substrate using a cleaning solution;

[0056] Placing the cleaned wafer into a reaction chamber and evacuating the reaction chamber;

[0057] In a vacuum environment, dichlorosilane and ammonia are introduced to deposit a Si3N4 passivation layer.

[0058] Preferably, the volume ratio of dichlorosilane to ammonia is controlled between 0.75 and 5.75.

[0059] Preferably, during the reaction process, the pressure in the reaction chamber is controlled below 100 Pa and the temperature is maintained at 750-810°C.

[0060] In this solution, a dense Si3N4 passivation layer is deposited on the surface of the chip, which improves the chemical stability and radiation resistance of the chip. The passivation layer 8 has excellent density and thermal stability, which can effectively prevent the influence of impurities or radiation in the environment on the chip, and ensure its performance stability in long-term use. At the same time, the process can accurately control the deposition process to ensure the thickness and uniformity of the passivation layer 8. The chip's radiation resistance is enhanced, and the service life of the chip is extended, especially in harsh environments or long-term use conditions, and its performance can be kept stable.

[0061] The present invention combines multiple ion implantation, dry etching and chemical vapor deposition to form a biopressure sensor chip with high sensitivity, high precision, high reliability and low power consumption. The combination of these technologies effectively improves the comprehensive performance of the sensor, making it particularly suitable for applications in the biomedical field for accurate monitoring of pressure changes. Its advantages in miniaturization, high integration and long-term stability provide innovative solutions for the development of biopressure sensor technology.

[0062] The purpose, advantages and features of the present invention will be illustrated and explained by the non-limiting description of the following preferred embodiments. These embodiments are only typical examples of the application of the technical solution of the present invention, and any technical solution formed by equivalent replacement or equivalent transformation falls within the scope of protection claimed by the present invention.

Claims

1. A method for manufacturing a biopressure sensor chip, characterized in that: The following steps are involved: A pressure sensitive resistor with a relatively low resistance value is formed in the substrate by a multiple ion implantation process; The dry etching process is used to process and shape the wafer layer at the bottom of the chip; A passivation layer is deposited on the chip surface using a chemical vapor deposition process.

2. The method according to claim 1, characterized in that: The multiple ion implantation process is to form an implantation layer by injecting impurity gas into the substrate to change the resistivity of the substrate, thereby adjusting the resistance value of the pressure sensitive resistor.

3. The method according to claim 2, characterized in that: The specific steps of injecting impurity gas into the substrate are: A mask layer is made on the surface of the substrate, and the mask layer is patterned by photolithography or dry etching to form an ion implantation window, through which impurity gas is injected into the substrate.

4. The method according to claim 3, characterized in that: The mask layer is a deposited oxide layer or a coated photoresist layer.

5. The method according to claim 2, characterized in that: The multiple ion implantation process further comprises: Controlling the resistivity of the implanted layer by controlling the impurity dosage of each implantation; and / or, The uniformity of impurity gas injection is ensured by scanning the substrate surface multiple times.

6. The method according to claim 1, characterized in that: The dry etching process uses SF6 gas to etch the silicon bottom and side walls, then introduces C4F8 gas to passivate the etched cavity, and deposits a polymer film on the side walls and the silicon bottom surface.

7. The manufacturing method according to claim 6, characterized in that: The specific steps of the dry etching process are: An appropriate amount of SF6 gas is injected into the plasma reaction chamber to obtain dissociated active fluorine atoms, which react with the silicon surface to generate SiF4, which is then pumped away by a vacuum pump to form a cavity structure after silicon etching; Injecting C4F8 gas into the cavity structure to obtain dissociated active groups, which are polymerized at the bottom and sidewalls of the cavity structure to deposit a passivation layer; SF6 gas is injected into the passivation layer again to attack the passivation layer at the bottom of the cavity. After the passivation layer at the bottom disappears, silicon etching is continued on the bottom of the cavity. This process is repeated so that the passivation layer on the side wall of the cavity is retained, and finally a silicon substrate with a target etching depth is obtained.

8. The manufacturing method according to claim 1, characterized in that: The chemical vapor deposition process refers to depositing a Si3N4 passivation layer onto the chip surface.

9. The manufacturing method according to claim 8, characterized in that: The specific steps of the chemical vapor deposition process are: Performing a standard wet cleaning of the substrate using a cleaning solution; Placing the cleaned wafer into a reaction chamber and evacuating the reaction chamber; In a vacuum environment, dichlorosilane and ammonia are introduced to deposit a Si3N4 passivation layer.

10. The manufacturing method according to claim 9, characterized in that: The volume ratio of dichlorosilane to ammonia is controlled between 0.75 and 5.75; and / or, During the reaction, the gas pressure in the reaction chamber was controlled below 100 Pa and the temperature was maintained at 750-810°C.

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