Sensor system and method of measuring pressure

Abstract

A sensor system and a method of measuring pressure are disclosed. A sensor system includes: a sensor including a sensing capacitor having a variable sensing capacitance; in one embodiment, a sensing circuit includes a sensing capacitor, and a readout integrated circuit, the readout integrated circuit including an analog-to-digital converter (ADC) having an ADC input connected to the sensing capacitor, where: a variable parasitic capacitance can be coupled to the ADC input; and when the sensor senses an input pressure, modulating the variable sensing capacitance, thereby generating one or more ADC output signals corresponding to the input pressure. Methods and apparatus for mitigating damage over time in a sensor are described. The application of such a method and apparatus to a pressure sensor confronting stray capacitance that varies over time due to water droplets is detailed. The benefits of auto-zeroing techniques employed in the disclosed apparatus are also described.

Description

[0001] This application is a divisional application of an invention patent application with an application date of February 25, 2020, an international application number of PCT / US2020 / 019762, a Chinese application number of 202080026861.0 after entering the Chinese national phase, and an invention name of “Parasitic Insensitive Sampling in Sensors”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to U.S. Patent Application No. 16 / 294,824, filed on March 6, 2019, entitled “Parasitic Insensitive Sampling InSensors,” the contents of which are incorporated by reference in their entirety. Background Art (1) Technical field

[0004] The present disclosure relates to parasitic insensitive sensors, and more particularly to methods and apparatus for sampling sensors having time-varying parasitics. (2) Background technology

[0006] Often, the performance of the electronic circuitry implementing the sensor may be degraded due to environmentally induced damage to the sensor. Such damage may be time-varying, thereby presenting additional design challenges. By way of example, a capacitive pressure sensor may be affected by time-varying parasitic capacitance created by water droplets present on such a pressure sensor when deployed. Solutions are needed to help mitigate the negative effects of time-varying damage on the performance of the circuitry implementing the sensor. The methods and apparatus described in the present disclosure address this problem and provide solutions to the problem.

[0007] Description of concepts and terms used throughout the disclosure

[0008] In the following, some concepts adopted by the methods and apparatus proposed later in this disclosure are defined and described.

[0009] a) Switched Capacitor Circuit

[0010] Throughout this disclosure, the term "switched capacitor circuit" will be used to describe an electronic circuit that includes a capacitor and a switch, where charge is moved into and out of the capacitor when the switch is opened or closed. Figure 1AAn exemplary switched capacitor circuit is shown in which three switches control operation: switch S1 and switch S3 connect the left plate of capacitor C1 to Vin and ground, respectively, and S2 provides unity gain feedback. During the charging phase, S1 and S2 are turned on and S3 is turned off, resulting in a voltage across C1 equal to Vin. This is because the inverting input appears as a virtual ground. During the integrating phase, S1 and S2 are turned off and S3 is turned on, pulling node A to ground. During this phase, and as Figure 1B As shown, the operational amplifier (OA) input differential voltage, and therefore the voltage across C1, is driven to zero via negative feedback through C2. The charge stored on C1 during the charging phase must then be transferred to C2, producing a voltage equal to In other words, within one clock cycle (corresponding to the two stages described above), Vout changes by

[0011] b) Automatic zeroing technology

[0012] Throughout this disclosure, the term "auto-zeroing" is used to describe a technique used in electronic circuits to eliminate possible offsets or noise present in such circuits. An example of an offset is the input voltage offset of an operational amplifier. FIG. 2A to FIG. 2B The technique is illustrated, where Vos represents the offset voltage at the input of the operational amplifier. In the first stage, switches S1 and S2 are closed and switch S3 is open, meaning that Vout=Vos. In other words, the offset voltage is stored in capacitor Caz. In the second stage, switch S3 is closed and switches S1 and S2 are open. In the second stage, the output is available. For an amplifier with a finite direct current (DC) gain of A, the residual offset can be calculated as Vos / (A+1). For most operational amplifiers, the gain A is a large number, and therefore this technique is mostly used to eliminate the residual offset.

[0013] c) Sigma-Delta Analog-to-Digital Converter (ADC) and Multi-Level Noise Shaping (MASH) Modulator

[0014] Throughout this disclosure, the term sigma-delta ADC is used to describe an ADC operating based on the sigma-delta modulation concept. Figure 3 A block diagram of a typical sigma-delta ADC is shown. Unlike more traditional ADCs, sigma-delta ADCs are oversampling converters that operate at a sampling rate greater than the Nyquist frequency of the input signal. Sigma-delta ADCs are primarily used to implement high-resolution and cost-effective ADCs for applications such as consumer and professional audio, communication systems, sensors, and precision measurement devices.

[0015] Throughout this disclosure, the term "MASH modulator" (where the acronym stands for Multi-Stage Noise Shaping) is used to describe an electronic circuit designed by cascading low-order sigma-delta modulators. The benefit of a MASH modulator is that some of the instability issues inherent to higher-order sigma-delta modulators are overcome. Examples of typical MASH modulators known in the art are 2-1, 2-2, 2-1-1 or higher order MASH modulators. This will also apply to other topologies of delta-sigma modulators, such as CIFF (chain of integrators with weighted feed-forward coefficients) with higher order (e.g. 3rd and 4th) modulators, for example. Summary of the invention

[0016] According to a first aspect of the present disclosure, a sensor system is provided, comprising: a sensor comprising a sensing capacitor having a variable sensing capacitance; and a readout integrated circuit comprising an analog-to-digital converter (ADC) having an ADC input connected to the sensing capacitor, wherein: a variable parasitic capacitance is capable of being coupled to the ADC input; and when the sensor senses an input pressure, the variable sensing capacitance is modulated to generate one or more ADC output signals corresponding to the input pressure.

[0017] According to a second aspect of the present disclosure, a method for measuring pressure is described, the method comprising: providing a sensing capacitor having a variable sensing capacitance; providing a readout circuit having an integrating capacitor, wherein a variable parasitic capacitance can be generated across an input of the readout circuit; in a charging phase, sampling a first reference voltage to store a first charge across the sensing capacitor; and in an integrating phase, transferring the first charge to the integrating capacitor, thereby generating a readout circuit output signal corresponding to the input pressure.

[0018] Other aspects of the disclosure can be found in the description, claims and drawings of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1A to Figure 1B A prior art switched capacitor circuit is shown.

[0020] FIG. 2A to FIG. 2B A prior art electronic circuit illustrating the auto-zero technique is shown.

[0021] Figure 3 A prior art sigma-delta analog-to-digital converter (ADC) is shown.

[0022] Figure 4 A sensor system according to an embodiment of the present disclosure is shown.

[0023] Figure 5A A MASH modulator is shown.

[0024] Figure 5B A second order sigma-delta modulator connected to a decimation filter is shown.

[0025] Figure 6 An electronic circuit according to an embodiment of the present disclosure is shown.

[0026] 7A to 7C A timing diagram is shown according to another embodiment of the present disclosure.

[0027] Fig. 8A A cross section of a pressure sensor according to the teachings of the present disclosure is shown.

[0028] Figure 8B shows a water droplet at the top Fig. 8A pressure sensor.

[0029] FIG. 9A to FIG. 9B Shown is a graph illustrating mitigating the effects of time-varying parasitic capacitance on an electronic circuit in accordance with the teachings of the present disclosure.

[0030] Fig.10 Various stages of the rapid onset of a water drop and the slow dissipation of a water drop on the pressure sensor are shown. DETAILED DESCRIPTION

[0031] Figure 4 A sensor system (400) according to an embodiment of the present disclosure is shown. The sensor system (400) includes a micro-electromechanical system (MEMS) sensor (410) connected to a readout integrated circuit (401) including an ADC (420). The MEMS sensor (410) includes sensing terminals, base terminals, and guard terminals represented by the letters S, B, and G, respectively. The time-varying capacitance of the MEMS sensor (410) is determined by a variable capacitor (C) connected across the terminals (S, B). S ), the parasitic capacitor (C BG ) and the parasitic capacitor (C SG ) indicates. According to an embodiment of the present disclosure, the MEMS sensor (410) is a pressure modulated variable capacitor (C S ) of a capacitive pressure sensor. As will be described in detail later, the capacitor (C S )'s capacitance changes and thereby generates a corresponding system output (430).

[0032] Reference Figure 4To FIG. 5 , and according to an embodiment of the present disclosure, the ADC (420) includes a MASH modulator (500) as shown in FIG. 5 . According to an embodiment of the present disclosure, the MASH modulator (500) may be a 2-1 MASH modulator including integrators (510, 511, 512) and comparators (520, 521). Also as shown in FIG. 5 , letters (-a1, -a2, -a3, b1, b2, and b3) represent the gains of their corresponding paths. The integrator (510) includes an integrator output node (530). According to an embodiment of the present disclosure, the MASH modulator (500) of FIG. 5 and thus Figure 4 The ADC (420) is configured to receive an input voltage (Vin) and generate two ADC outputs (d1, d0). According to another embodiment of the present disclosure, the outputs (d1, d0) of the two comparators may be Figure 4 The output of the MASH modulator is typically followed by a decimation filter to complete the system. In most implementations, the 1-bit data stream (d1, d0) will be further processed by a decimation filter, which is typically implemented in the digital portion of the system. The output of the decimation filter can be considered the final output of the ADC (430). In other embodiments, d0 can be ignored and only the output d1 is processed by the decimation filter in the digital portion. In such a case, and as Figure 5B As shown in , the modulator is reconfigured to be a second-order sigma-delta modulator (501) instead of a 2-1 MASH modulator. Figure 5B As shown in , the output d1 of the second order sigma-delta modulator (501) is used as the input of the decimation filter (502). After processing the input (d1), the decimation filter (502) generates an output (Vout). According to an embodiment of the present disclosure, the decimation filter output (Vout) can be a 24-bit output. Therefore, due to the decimation process, the output data rate is slower. According to other embodiments of the present disclosure, the 24-bit output of the decimation filter (502) can be at a rate of 32 Hz, 64 Hz, or 128 Hz.

[0033] Figure 6 An electronic circuit (600) is shown including an analog front end (641) of a sigma-delta modulator connected to a MEMS sensor (642). The analog front end (641) includes an integrator (610). According to an embodiment of the present disclosure, the integrator (610) is an exemplary implementation of the integrator (510) of FIG. 5. The capacitive frame (642) includes a capacitor (C) connected to the sense terminal, the base terminal, and the guard terminal (S, B, G). S , C BG , C SG), the sensing terminals, base terminals and guard terminals (S, B, G) are connected to the Figure 4 In other words, the capacitor (C S , C BG , C SG ) and terminals (S, B, G) may be components of a MEMS sensor (410). In this example, a MEMS sensor with a specific configuration (B, S, G) is used. However, other sensors may be used. For example, the sensor may be a MEMS or other type, the sensor may be a pressure type or a temperature type or an acceleration type, and the sensor may be configured differently. The analog front end (641) also includes an offset capacitor (C os ), feedback capacitor (C dac ) and a plurality of switches (S1, S1'...S4, S4', S5, S6, S7). According to an embodiment of the present disclosure, the switches (S1, S1'...S4, S4', S5, S6, S7) may include metal oxide semiconductor field effect transistor (MOSFET) switches. The state of such switches is controlled by a clock having various phases, each phase including a pulse stream of logic 1 and logic zero. Such a clock is used to manage the timing when certain capacitors sample the input voltage and how they transfer the stored charge to the integration capacitor (as will be described in detail later). Reference Figure 6 , the following convention is used to show each switch and the corresponding control clock: for each switch, the name of the clock that controls the switch is set below the switch. For example, the switch termed "Φ1" is shown below as being controlled by the clock (Φ1), such that when the clock (Φ1) is a logic 1, the switch is closed, and when the clock (Φ1) is a logic zero, the switch is open.

[0034] Further references Figure 6 , each clock is represented by a Greek letter (Φ) with its own index. The term "dd" used in the index represents delay. As an example, switch (S1) is switched by clock (Φ1) which is a delayed version of clock (Φ2). 1dd ) control. In addition, the dash used in the naming of the clock indicates reversal. By way of example, the clock is the clock (Ф 1dd ). In other words, when the clock (Ф 1dd ) is at logic 1, the clock is at logic zero, and vice versa, when the clock (Ф 1dd ) is at logic zero, the clock is at logic one. Each of the switches (S3, S3', S4, S4') is controlled by a clock generated by multiplying two pulse streams. As an example, Figure 6As shown, and referring to FIG. 5, the switch (S3) is driven by a clock (Ф 1dd d1) control, where the term "Ф 1dd d1" is the product of the pulse stream representing the clock (Φ1dd) and the pulse stream representing the output comparator (d1) of FIG. 5. Figure 6 The integrator (610) includes switches (S5 and S6), an integrating capacitor (C int ) and an operational amplifier (OA) (660) having a first input node (670) and a second input node (671). According to an embodiment of the present disclosure, the second input node (671) can be connected to a reference voltage (V refp ). According to another embodiment of the present disclosure, Figure 6 As shown, the reference voltage (V refn ) may be ground. According to another embodiment of the present disclosure, Figure 6 As shown, the reference voltage (V refn ) can.

[0035] Reference Figures 4 to 6 , the analog front end (641) is an exemplary implementation of the electronic block (541) of FIG. 5, and they essentially represent Figure 4 The analog front end of the ADC (420) receives the pressure to be measured as a result of sensing the pressure to be measured. Figure 4 and Figure 6 The sensing capacitor (C s ) generates an analog signal. In addition, Figure 6 The connection point (630) of is the counterpart of the integrator output node (530) of FIG. 5 , both of which show Figure 6 The interconnection between the integrator (610) of FIG. 5 (or the integrator (510) of FIG. 5) and the rest of the modulator (500) of FIG. 5.

[0036] Figure 6 The electronic circuit (600) is essentially a switched capacitor circuit in which the input voltage is sampled during a charging phase and the sampled data is integrated during an integration phase after the charging phase. According to an embodiment of the present disclosure, the electronic circuit (600) is configured to receive a reference voltage (V refp 、V refn According to another embodiment of the present disclosure, the reference voltage (V refp 、V refn ) are positive voltage and negative voltage, respectively. It is also possible to envision an embodiment according to the present disclosure, in which the reference voltage (V refn ) is the ground.

[0037] More specifically, Figure 6The electronic circuit (600) can be considered as a sensing capacitor (C s ) relative to the reference capacitance (C dac ) ratio sampling, where the same reference voltage (V refp and V refn ) is used to provide the charge during the sampling phase. The amount of charge captured depends on the value of the sensing capacitor (Cs), which in turn depends on the pressure. By implementing the analog front end of the sigma-delta modulator as a ratiometric comparison of capacitors, the performance of the ADC is improved relative to the reference voltage V refp and V refn The defect becomes more robust and reaches the first order. The offset capacitance (C OS ) is usually configured relative to the sensing capacitor (C s ) is charged or discharged out of phase. According to an embodiment of the present disclosure, the offset capacitor (C OS ) is used to convert the sensing capacitor (C S ) is centered (or aligned) to the center of the ADC’s ​​full-scale range, which is determined by the feedback capacitor (C dac ) settings. In a typical implementation, the available ADC full scale can be as determined by the feedback (or reference) capacitor (C dac ) is half the true full-scale range implied by the

[0038] FIG7 shows a timing diagram of various clocks controlling the states of switches of the electronic circuit (600). Without loss of generality, for the purpose of description and in the following, it is assumed that reference (V refn ) is ground. During the sampling or charging phase, the clock (Ф 1dd ) is at one and therefore, the switch (S1) is closed and the sensing capacitor (C s ) is connected to (V refp ) and on the other side is connected to the reference node (670) of the operational amplifier. Therefore, the capacitor (Cs) is charged to Q S =Cs x(V refp -V refn ). In this phase, the input-related op amp noise (flicker noise) and offset are also captured. This is achieved by closing S7 in phase Φ1. 1dd ) phase, capturing C in a similar manner but with opposite polarity os The charge on C os Connect to V refn and V ref This enables the full-scale excursion to be correctly achieved at the end of Phase 2.

[0039] During the integration phase, the clock (Ф 1dd) is at zero, and therefore, switch (S1) is open, while switch (S2) is closed. This forces the voltage stored on the sensing capacitor (C s ) moves toward the first input node (670) of OA (660) and forces the charge stored in the sensing capacitor (C s ) is transferred to the integrating capacitor (C int ). In order to complete the charge transfer, switches S5 and S6 are closed during this clock phase. As can be seen from FIG7, the sensing capacitor (C s ) compared to the capacitor (C os ) in reverse order at V refn (for example, ground) and a reference voltage (V refp ). In other words, and during the charging phase, switch (S2) is closed, and thus the bias capacitor bottom plate is charged to ground. During the integration phase, switches (S1, S2) are open, and based on the law of charge conservation, the equivalent charge is (C s -C os ). (V refp –V refn ) is therefore transferred to the integrating capacitor (C int ).

[0040] About the feedback capacitor (C dac ), with respect to the sensing capacitor (C s ) or offset capacitor (C os ) performs charge storage and transfer similarly to the description of the control and feedback capacitor (C dac )The clocks of the associated switches (S3, S3', S4, S4') are different and depend on the comparator output (d1).

[0041] 7A to 7C Shown with Figure 6 A timing diagram associated with the electronic circuit (600). Fig. 7A A high-level timing diagram is shown. FIG. 7B to FIG. 7C They are shown in Figure 6 A more detailed timing diagram is shown when zooming in on the area (71, 72) of the timing diagram. Figure 6 and Fig. 7A , during both the charging phase and the integration phase, depending on the state of the clock (Φ1, Φ2) and the output DAC (d1), the feedback capacitor (C dac ) can be connected to the first reference voltage (V refp ) or the second reference voltage (V refn The integrated charge-related data (d1) provides quantized negative feedback, which ensures that the comparator output bit stream accurately reflects the sensed capacitance (C S )’s average value.

[0042] According to an embodiment of the present disclosure, the offset capacitor (C os ) can be selected as the sensing capacitor (C s ) range, thereby centering such changes.

[0043] Further references FIG. 7A to FIG. 7B , and in line with previous FIG. 2A to FIG. 2B Similar to the description, an auto-zeroing technique is employed to minimize the negative effects of impairments such as OA offset or flicker noise and any other low frequency impairments that may be present on the input side of the OA (660). This is accomplished by 7A to 7C The timing diagram shown is executed with appropriate control of the switch (S7). The switch (S7) is closed before the charging phase begins, and thus the low frequency noise present at the input of the OA (660) is sampled. This is followed by the start of the charging phase, and then the integration phase. Return to reference Figure 6 , during the integration phase, substantially equal voltages are maintained at the first input node and the second input node (670, 671) of the OA (660), thereby compensating for the negative effects of low frequency parasitics at the first input (670) of the OA (660). FIG. 2A to FIG. 2B Similar to the description, in practice, the sampling noise is divided by the open loop gain of the OA and is therefore reduced to a negligible amount. This mechanism will also approximately cancel any slowly varying parasitic capacitance, such as C connected to node 670. P1 Such parasitic capacitances may also be present due to various obstacles in the environment surrounding the sensitive MEMS structure. The described auto-zeroing technique is essentially a filter with a transfer function such as (1-(z -1 )) high-pass filtering mechanism, which filters out various impairments, such as slowly changing capacitance (C P1 ) or DC offset and low frequency noise of the operational amplifier (660). According to an embodiment of the present disclosure, chopping techniques in differential topologies / circuits may be used instead of auto-zeroing to reduce the effects of impairments as described above.

[0044] As mentioned previously, damage associated with the pressure sensor may be time-varying. An example of a source of such damage is a water droplet that accidentally lands on the pressure sensor during measurement. In the following, more details about damage caused by water droplets and methods and apparatus for mitigating the negative effects of such damage are described.

[0045] Fig. 8AA cross section of a pressure sensor (800) is shown that includes a body (890), a MEMS sensor (810), and a waterproof gel (880). The waterproof gel (880) enables it to faithfully transmit air pressure from outside the body (890) to the MEMS (810) sensor, while protecting the MEMS sensor and ASIC (820) from damage by water or other external liquids to which the pressure sensor may be exposed. The MEMS sensor (810) is connected to the integrated circuit (820) via a first bonding wire (811). Also as shown in FIG. 8, the integrated circuit (820) is also connected to the substrate (881) via a bonding wire (812). The pressure to be measured is transferred to the integrated circuit (820) through the waterproof gel (880). According to an embodiment of the present disclosure, the bonding wires (811, 812) may be exposed to the waterproof gel (880). According to another embodiment of the present disclosure, the integrated circuit (820) may include Figure 4 ADC (420). Embodiments according to the present disclosure are also contemplated in which the pressure sensor (800) does not have a waterproof gel, but uses other methods of providing waterproof functionality to the ASIC.

[0046] Further referring to the water drop case, Figure 8B Shows Fig. 8A A pressure sensor (800) is shown in which a water (or liquid) droplet (895) is present on top of a transparent gel (880). The surface tension of the water (or liquid) may cause the water (or liquid) to spread as shown. However, the water droplet may also only be partially present on the surface of the gel. The water (or liquid) droplet (895) has a significantly different dielectric than air. This affects the value of the parasitic capacitance sensed by the very sensitive analog front end of the modulator. The water / liquid present in the vicinity of the gel and MEMS can be modeled as follows Figure 6 The various parasitic capacitances / damages shown in -C P1 , C P2 and C P3 The typical value of this parasitic capacitance is usually similar to the MEMS sensing capacitance C S The pressure changes considerably, resulting in a large pressure offset, i.e. an error in the pressure measurement. It should be mentioned that the term water or liquid is not limited to water. It can be salt water or various other liquids or residues. Water is used as an example due to its time-varying properties when it appears and then evaporates.

[0047] Reference Figure 6 The described damage due to the presence of water may be caused by the first parasitic capacitor, the second parasitic capacitor and the third parasitic capacitor (C p1 , C p2 , C p3) represents. According to an embodiment of the present disclosure, the second parasitic capacitor and the third parasitic capacitor (C p2 , C p3 ) compared to the negative impact of the first parasitic capacitor (C p1 ) can have a substantially greater negative impact on sensor performance. Parasitic capacitance (C p1 ) changes the value of the destruction of the C INT The charge injected and the C being measured S The parasitic capacitance C p2 is located between the ASIC ground and the chassis ground and does not affect the integrated C int C S The signal charge of the parasitic capacitance (C p3 ) is located between the reference buffer and ground. This capacitor is charged and discharged during each clock cycle but does not affect the int C S signal charge.

[0048] Reference Figure 6 , and according to an embodiment of the present disclosure, compared with various timings at which various circuits based on the ADC (420) function, the first parasitic capacitor (C pl ) has a time-varying capacitance that represents low-frequency damage.

[0049] Refer to Figures 5 to Figure 6 , and by way of example and not limitation, with the sigma-delta modulator (500) of FIG. 5 or Figure 6 The sampling frequency associated with the first electronic circuit (600) may be hundreds of KHz, which is equivalent to a sampling period of the order of microseconds. Continuing with the same example, the variation of the parasitic capacitor may range from a few pico-farads to 10 pF per millisecond. S This may be related to C S The changes themselves are just as big.

[0050] By means of a significantly larger parasitic capacitor (C pl ) is the sampling frequency of the rate of change of Figure 6 The auto-zeroing function described in the analog front end (641) of the embodiment of the present invention can combat and overcome the damage caused by water drops in the same way as other low frequency noise / damages such as flicker noise or OA offset are eliminated. According to the teachings of the present disclosure, the parasitic capacitance caused by the presence of water drops can be reduced by a factor of several thousand orders of magnitude.

[0051] FIG9 shows graphs (901, 902) according to an embodiment of the present disclosure. Graph (902) shows the time-dependent Figure 6 The parasitic capacitor (C p1 ). The curve (901) shows the change of Figure 4 The sensor system output (430) at a first voltage (V1) reacts to a sudden change in parasitic capacitance from zero to Cp1 as shown in FIG9 . The system output (430) first increases to a peak voltage (Vp) and then drops back to a second voltage (V2) substantially close to the first voltage (V1), with the small difference being due to secondary effects. Here, V1, V2, and Vp are referred to as voltages, but they are simply indicative of the C being measured at the ADC output (430). S The capacitance is directly related to the equivalent digital code, C S The capacitance is proportional to the pressure being sensed. Figure 4 , Figure 6 and FIG. 8A to FIG. 8B , those skilled in the art will appreciate that when the system output (430) is stable, the water droplets are still present and stuck to the gel. In other words, charge is constantly being removed from the first input node (670) of the OA (660) by the water droplets. However, by implementing an auto-zeroing mechanism in accordance with the teachings of the present disclosure, the described charge removal is counteracted by persistently injecting charge into the input node (670) to maintain the voltage at that node equal to the voltage at the other input of the OA (660), which is ground. This is a way to mitigate the damage caused by water droplets associated with parasitic capacitance. Without this mitigation, the voltage would vary from V1 to a larger value VP which could be as large as 1000 times - 7000 times. NEW , and the voltage will remain at this level until the water drop (or liquid) dissipates. Referring to FIG. 9 , according to the teachings of the present disclosure, the presence or absence of a water drop on the pressure sensor can be detected based on a comparison of the ADC output amplitude as shown by the curve ( 901 ) with a set expected amplitude threshold.

[0052] Regarding the water drop problem described above, and in accordance with the teachings of the present disclosure, as described by Fig.10 As shown in the graph (1000), the dissipation of water droplets is a very slow phenomenon. Return to reference Fig. 8A , a graph (1000) depicts a graph showing the parasitic capacitor (C p1 ) is a graph showing the change in capacitance. From left to right it shows Figure 8B A cross section of a pressure sensor (800) is shown, showing the Figure 8BThe arrows (1001b, 1002b, 1003b, 1004b) on both sides are used to show the correspondence between each of the cross sections shown and the corresponding graph portion (1001a, 1002a, 1003a, 1004a). From left to right, such graph portions represent the following situations: 1) at time T = 0, the water drop is located on the pressure sensor gel, 2) the amount of water decreases, 3) the contact between the water drop and the transparent gel decreases, and 4) the water disappears or separates from the sensor body. As mentioned previously, and as shown from Fig.10 As can be seen in the graph (1000) of FIG. 1 , the complete dissipation of water occurs at a much slower rate than the rate at which the parasitic capacitance caused by the water drop increases to its maximum value. Therefore, in view of what has been described previously, the auto-zeroing mechanism mitigates the parasitic capacitance generated during the life cycle of the corresponding water drop.

[0053] The parasitic capacitance caused by water drops in an application using a pressure sensor is merely an example used to describe some aspects of the teachings of the present disclosure. Those skilled in the art will understand that the teachings of the present disclosure are similarly applicable to sensors other than pressure sensors and to different time-varying impairments caused by sources other than water drops without departing from the spirit and scope of the present invention.

[0054] As used in this disclosure, the term "MOSFET" means any field effect transistor (FET) having an insulated gate and including metal or metal-like, insulator, and semiconductor structures. The term "metal" or "metal-like" includes at least one conductive material (e.g., aluminum, copper or other metals, or highly doped polysilicon, graphene or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric materials), and "semiconductor" includes at least one semiconductor material.

[0055] This application may include the following solutions:

[0056] 1. A sensor system comprising:

[0057] a sensor comprising a sensing capacitor having a variable sensing capacitance; and

[0058] a readout integrated circuit comprising an analog-to-digital converter (ADC) having an ADC input connected to the sensing capacitor,

[0059] in:

[0060] A variable parasitic capacitance can be coupled to the ADC input; and

[0061] When the sensor senses an input pressure, the variable sensing capacitor is modulated to generate one or more ADC output signals corresponding to the input pressure.

[0062] 2. The sensor system of claim 1 , wherein the sensing capacitor is connected in series with the ADC input.

[0063] 3. The sensor system of claim 1 , wherein the ADC comprises a sigma-delta modulator.

[0064] 4. The sensor system of claim 3, wherein the sigma-delta modulator is a multi-level noise shaping (MASH) modulator, the multi-level noise shaping (MASH) modulator comprising one or more integrators interconnected with one or more comparators.

[0065] 5. The sensor system according to claim 4 further comprises a decimation filter connected to the sigma-delta modulator.

[0066] 6. The sensor system of claim 1 , wherein the sensor further comprises an offset capacitor operable to charge or discharge out of phase with respect to the sensing capacitor.

[0067] 7. A sensor system according to Option 6, wherein the sensor also includes a feedback capacitor, and wherein the offset capacitor is configured to center the change of the sensing capacitor to the center of the full scale of the ADC, and the full scale of the ADC is set by the feedback capacitor.

[0068] 8. The sensor system of claim 1, wherein auto-zeroing or chopping techniques are used to reduce the effect of the variable parasitic capacitance on the one or more ADC output signals.

[0069] 9. The sensor system according to Option 7 further includes an integrator, which includes an operational amplifier and an integrating capacitor, and the operational amplifier input is the ADC input.

[0070] 10. The sensor system according to Option 9 is configured to receive multiple reference voltages and also includes a switching device, which is controlled by multiple clock signals to connect the sensing capacitor, the offset capacitor and the feedback capacitor to corresponding reference voltages of the multiple reference voltages / disconnect the sensing capacitor, the offset capacitor and the feedback capacitor from corresponding reference voltages of the multiple reference voltages.

[0071] 11. The sensor system of claim 10, wherein the plurality of clock signals comprises a clock signal generated based on the one or more ADC output signals.

[0072] 12. The sensor system of claim 11, wherein:

[0073] During the charging phase:

[0074] The switching device is configured such that the plurality of reference voltages are sampled to store charge across the sensing capacitor, the offset capacitor, and the feedback capacitor; and

[0075] During the integration phase:

[0076] A combination of the charges stored on the sense capacitor, the offset capacitor, and the feedback capacitor during the charging phase is transferred to the integration capacitor, thereby generating an integrator output signal corresponding to the input pressure.

[0077] 13. The sensor system of claim 12, wherein undesired charge due to the variable parasitic capacitance is sampled prior to the charging phase and compensated for while generating the integrator output signal.

[0078] 14. The sensor system of claim 12, wherein the plurality of clock signals have a clock period substantially smaller than a time period during which the variable parasitic capacitance changes by 1 pF.

[0079] 15. The sensor system of claim 12, wherein the plurality of clock signals have a clock rate in the range of hundreds of KHz, and the variable parasitic capacitance varies in the range of tens of pF and has a rate of change in the range of tens of pF / millisecond.

[0080] 16. The sensor system of claim 10, wherein the switching device comprises a metal oxide semiconductor field effect (MOSFET) transistor.

[0081] 17. The sensor system according to claim 1, wherein the sensor is a MEMS sensor.

[0082] 18. The sensor system of Option 1 further comprises a gel material configured to transfer the sensed pressure to the readout integrated circuit.

[0083] 19. The sensor system of claim 18, wherein the sensor is connected to the readout integrated circuit via bonding wires exposed to the gel material.

[0084] 20. A method for measuring pressure, comprising:

[0085] providing a sensing capacitor having a variable sensing capacitance;

[0086] Providing a readout circuit having an integrating capacitor, wherein a variable parasitic capacitance can be generated across an input of the readout circuit;

[0087] In a charging phase, a first reference voltage is sampled to store a first charge across the sensing capacitor; and

[0088] During the integration phase, the first charge is transferred to the integration capacitor, thereby generating a readout circuit output signal corresponding to the input pressure.

[0089] 21. The method of claim 20, further comprising, prior to the charging phase, sampling the readout circuit input to capture undesired charge due to the variable parasitic capacitance and compensating for the undesired charge during the integration phase.

[0090] 22. The method according to claim 21, further comprising:

[0091] providing bias capacitors;

[0092] configuring the offset capacitor to center the change in the sense capacitor to the center of a full scale of the readout integrated circuit;

[0093] In the charging phase, sampling a second reference voltage to store a second charge across the offset capacitor; and

[0094] During the integration phase, the second charge is transferred to the integration capacitor.

[0095] 23. The method according to claim 22, further comprising:

[0096] providing a feedback capacitor configured to set a full scale of the readout circuit;

[0097] In the charging phase, sampling the first reference voltage and the second reference voltage during a set time interval to store a third charge across the offset capacitor; and

[0098] During the integration phase, the third charge is transferred to the integration capacitor.

[0099] 24. The method according to claim 23, wherein the set time interval is defined based on the readout circuit output signal.

[0100] 25. The method according to claim 24, wherein the readout circuit further comprises one or more integrators interconnected with one or more comparators.

[0101] 26. A method for detecting the presence of a water droplet on a pressure sensor using the method described in Option 20, the method comprising comparing a measured value of an output signal of the readout circuit with a set threshold to detect the presence or absence of a water droplet.

[0102] As will be readily apparent to those skilled in the art, various embodiments of the present invention may be implemented to meet various specifications. Unless otherwise noted above, the selection of suitable component values ​​is a matter of design choice, and various embodiments of the present invention may be implemented in any suitable IC technology (including but not limited to MOSFET structures) or in the form of hybrid or discrete circuits. Integrated circuit implementations may be manufactured using any suitable substrate and process including but not limited to standard bulk silicon, silicon on insulator (SOI) and silicon on sapphire (SOS). Unless otherwise noted above, the present invention may be implemented in other transistor technologies such as bipolar, GaAs HBT, GaN HEMT, GaAs pHEMT and MESFET technologies. However, the above-mentioned inventive concept is particularly useful for SOI-based manufacturing processes (including SOS) and for manufacturing processes with similar characteristics. The manufacture of CMOS processes on SOI or SOS enables circuits to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity and high frequency operation (i.e., up to and exceeding 50GHz radio frequencies). A monolithic IC implementation is particularly useful since parasitic capacitance can usually be kept low (or kept at a minimum, consistent across all cells, thereby allowing compensation for parasitic capacitance) by careful design.

[0103] Voltage levels may be adjusted and / or voltage and / or logic signal polarity may be reversed according to specific specifications and / or implementation techniques (e.g., NMOS, PMOS, or CMOS and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adjusted as needed, such as by adjusting device size, "stacking" components (particularly FETs) in series to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or provide additional functionality without significantly changing the functionality of the disclosed circuits.

[0104] Many embodiments of the present invention have been described. It should be understood that various modifications may be made without departing from the spirit and scope of the present invention. For example, some of the above steps may be order-independent and, therefore, may be performed in an order different from that described. Furthermore, some of the above steps may be optional. The various activities described with respect to the above identified methods may be performed in a repeated, serial, or parallel manner.

[0105] It should be understood that the foregoing description is intended to illustrate and not limit the scope of the invention, which is defined by the scope of the appended claims, and that other implementations are also within the scope of the claims. (Note that parenthetical labels of claim elements are used to easily refer to such elements and do not, by themselves, indicate a particular claimed ordering or enumeration of elements; furthermore, such labels may be repeated in dependent claims to refer to additional elements without being construed as starting a mutually conflicting sequence of labels).

Claims

1. A sensor system comprising: a sensor comprising a sensing capacitor having a variable sensing capacitance; as well as a readout integrated circuit comprising an analog-to-digital converter (ADC) having an ADC input connected to the sensing capacitor, in: A variable parasitic capacitance can be coupled to the ADC input; as well as When the sensor senses an input pressure, the variable sensing capacitor is modulated to generate one or more ADC output signals corresponding to the input pressure.

2. The sensor system according to claim 1, wherein: The sensing capacitor is connected in series with the ADC input.

3. The sensor system according to claim 1, wherein: The ADC includes a sigma-delta modulator.

4. The sensor system according to claim 3, wherein: The sigma-delta modulator is a multi-level noise shaping (MASH) modulator comprising one or more integrators interconnected with one or more comparators. 5 . The sensor system of claim 4 , further comprising a decimation filter connected to the sigma-delta modulator.

6. The sensor system according to claim 1, wherein: The sensor also includes an offset capacitor operable to charge or discharge out of phase with respect to the sensing capacitor.

7. The sensor system according to claim 6, wherein: The sensor further includes a feedback capacitor, and wherein the offset capacitor is configured to center changes in the sense capacitor to the center of a full scale of the ADC, the full scale of the ADC being set by the feedback capacitor.

8. The sensor system according to claim 1, wherein: Auto-zeroing or chopping techniques are used to reduce the effect of the variable parasitic capacitance on the one or more ADC output signals. 9 . The sensor system of claim 7 , further comprising an integrator, the integrator comprising an operational amplifier and an integrating capacitor, the operational amplifier input being the ADC input.

10. A method for measuring pressure, comprising: providing a sensing capacitor having a variable sensing capacitance; Providing a readout circuit having an integrating capacitor, wherein a variable parasitic capacitance can be generated across an input of the readout circuit; In a charging phase, a first reference voltage is sampled to store a first charge across the sensing capacitor; and During the integration phase, the first charge is transferred to the integration capacitor, thereby generating a readout circuit output signal corresponding to the input pressure.

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