A multi-channel fast switching cyclic excitation device for inducing seismic waves in rock friction experiments

Abstract

The application discloses a kind of multi-channel fast switching cyclic excitation device for rock friction experiment induced seismic wave, including low-voltage logic control circuit and high-voltage square wave power transmitting circuit, low-voltage logic control circuit includes CPLD main controller circuit, USB2.0 logic circuit and isolation control circuit, USB2.0 logic circuit and isolation control circuit are connected with CLPD main control circuit, low-voltage logic control circuit is connected with high-voltage square wave power transmitting circuit, and USB2.0 logic circuit is connected with CLPD main control circuit using 16-bit wide Slavefifo bus connection.The application uses parallel 16-way high-voltage square wave power transmitting structure instead of single high-voltage square wave transmitting structure with switching device structure, and can realize zero-error at least 1ms interval multi-channel switching cyclic transmitting output, which cannot be achieved by single high-voltage square wave transmitting structure with switching device structure, to ensure zero-error transmitting-receiving time extraction in later stage of experiment analysis.

Description

Technical Field

[0001] This invention relates to the field of indoor earthquake simulation, specifically to a multi-channel rapid switching cyclic excitation device for inducing seismic waves in rock friction experiments. Background Technology

[0002] Currently, indoor earthquake simulations primarily utilize rock friction experiments. Changes in rock wave velocity during these experiments are a crucial method for determining when a simulated earthquake will occur. However, acoustic emission signals do not always appear at different stages of the rock friction deformation process; some stages exhibit strong signals, while others show very weak or no signals at all. This necessitates artificially applying a trigger signal from the outside to penetrate the rock fault, generating ultrasonic waves within the rock that propagate to the other side of the fault. An elastic wave acquisition device can then pick up these elastic waves on the other side of the fault and analyze their velocity changes.

[0003] Since the rock samples used in current rock friction experiments are mostly 30x30cm in size, and the frictional oblique fault is usually 45° with a length of about 42cm, and the contact sliding position of the frictional oblique fault is different at different deformation stages, the experiment usually needs to place excitation sensors and receiving sensors at different positions on both sides of the oblique fault. Therefore, the experiment requires a multi-channel external excitation device.

[0004] Rocks are anisotropic and non-homogeneous materials, and the attenuation of ultrasonic waves varies depending on the type and size of the rock. Generally, the more pores and the larger the size of the pores inside the rock, the greater the attenuation of ultrasonic waves. This requires the external excitation device to have sufficiently strong excitation energy.

[0005] The pre-slip phase in rock friction deformation experiments simulating indoor earthquakes typically lasts from tens to hundreds of seconds. These experiments are usually conducted in environments with high levels of electromagnetic radiation, necessitating data averaging at the acquisition and receiving end. The short pre-slip phase also means that subsequent data analysis requires highly accurate extraction of the ultrasonic information's first arrival time (milliseconds). Therefore, the external excitation device needs extremely precise, equally spaced excitation capabilities and repeatable excitation to facilitate time extraction and data averaging during subsequent data analysis. Currently available high-voltage transmitters typically operate on a single channel or a single channel combined with a high-voltage switching device to achieve switching between multiple channels. A single channel cannot achieve switching between multiple channels, and a single channel combined with a high-voltage switching device struggles to achieve highly precise, equally spaced excitation output due to the characteristics of the high-voltage switching device. This is because current high-voltage switching devices are composed of high-voltage relays, whose execution typically takes several milliseconds and exhibits jitter after execution. The jitter duration varies with each execution (from several milliseconds to tens of milliseconds), making precise equally spaced triggering and rapid inter-channel switching output (1-millisecond intervals) impossible. According to the experimental requirements, the device needs to have a precise and fast equal-interval multi-channel switching output capability of at least 1ms.

[0006] To address the aforementioned problems, this invention provides a multi-channel rapid switching cyclic excitation device for inducing seismic waves in rock friction experiments, capable of artificially inducing simulated seismic waves. Summary of the Invention

[0007] This invention provides a multi-channel rapid switching cyclic excitation device for inducing seismic waves in rock friction experiments, which can artificially induce simulated seismic waves.

[0008] The purpose of this invention is to provide a multi-channel rapid switching cyclic excitation device for inducing seismic waves in rock friction experiments. The device includes a low-voltage logic control circuit and a high-voltage square wave power transmission circuit. The low-voltage logic control circuit includes a CPLD main controller circuit, a USB 2.0 logic circuit, and an isolation control circuit. Both the USB 2.0 logic circuit and the isolation control circuit are connected to the CPLD main controller circuit. The low-voltage logic control circuit is connected to the high-voltage square wave power transmission circuit. The USB 2.0 logic circuit and the CPLD main controller circuit are connected via a 16-bit wide SlaveFIFO bus.

[0009] Furthermore, the low-voltage logic control circuit includes a CPLD chip, a power-on reset circuit, and an RC filter circuit. The power-on reset circuit includes a resistor R4 and a diode D1 connected in parallel to a 3.3V power supply. After being connected in parallel, they are connected to capacitor C1 to DGND digital ground and then to pin 143 of the CLPD chip. The RC filter circuit includes pin 2 of crystal oscillator CY1 connected to DGND, and pin 4 connected to a 3.3V power supply through a ferrite bead R5. Capacitors C2, C3, and C4 are connected in parallel and then in series with ferrite bead R5. Pin 30 of the CLPD chip is connected to pin 3 of crystal oscillator CY1. Pins 1, 8, 37, 42, 55, 73, 84, 109, 127, and 141 of the CLPD chip are connected to a 3.3V power supply. Pins 18, 27, 29, 36, 47, 62, 72, 89, 90, 99, 108, 114, 123, and 144 of the CLPD chip are connected to DGND digital ground.

[0010] Furthermore, the USB 2.0 logic circuit includes a USB microcontroller CYU1, a USB 2.0 port, a clock oscillation circuit, an RC filter circuit, and a power-on reset circuit. Pin 5 of the USB 2.0 port is connected to resistor R9 and capacitor C36. The clock oscillation circuit includes capacitors C26 and C27 and a passive crystal oscillator Y1 to provide the operating clock for the USB microcontroller CYU1. Pin 2 of the USB microcontroller CYU1 is connected in series with resistor R13 to DGND. Pin 22 of the USB microcontroller CYU1 is connected to a 3.3V power supply via resistor R14 and then to pin 5 of the LC1 memory chip. Pin 51 of the USB microcontroller CYU1 is connected in series with resistor R14 to a 3.3V power supply. Pin 49 of the USB microcontroller CYU1 is connected to diode D2, resistor R8, and capacitor C25 to form the power-on reset circuit. Pin 1 of the LC1 chip is connected in series with resistor R16. It is connected to pin 8 (VCC). The RC filter circuit, including a ferrite bead RC, capacitors C45, C46, ​​and C37, filters out high-frequency noise from the 3.3V power supply and is connected to pin 8 of the LC1 chip. Pins 6, 14, 18, 24, 34, 39, and 50 of the USB microcontroller CYU1 are connected to the 3.3V power supply. Pins 4, 7, 13, 17, 19, 33, 35, and 48 of the USB microcontroller CYU1 are connected to DGND (digital ground). Pins 25, 26, 27, 28, 29, 30, 31, 32, 52, 53, 54, 55, 56, 1, 2, and 3 of the USB microcontroller CYU1 are sequentially connected to USBFD1~USBFD16 of the slaveFIFO bus. Pins 44 and 45 of the USB microcontroller CYU1 are sequentially connected to FIFOADDR0~ of the slaveFIFO bus. FIFOADDR1, pins 37 and 38 of the USB microcontroller CYU1 are connected sequentially to FLAGB and FLAGC of the slavefifo bus, pins 42, 8, and 9 of the USB microcontroller CYU1 are connected sequentially to SLOE, SLRD, and SLWR of the slavefifo bus, and pin 20 of the data USB microcontroller CYU1 is connected to IFCLK of the slavefifo bus.

[0011] Furthermore, the isolation control circuit includes a digital isolation chip AD16 and an RC filter circuit. Pins 2 and 3 of the digital isolation chip AD16 are connected to pins 70 and 71 of the CLPD chip, respectively. For the other 15 isolation control circuits, pins 2 and 3 of the digital isolation chip AD16 are sequentially connected to pins 74 and 75 of the CPLD for channel 2, pins 76 and 77 for channel 3, pins 78 and 79 for channel 4, pins 80 and 81 for channel 5, pins 82 and 83 for channel 6, pins 85 and 86 for channel 7, pins 87 and 88 for channel 8, pins 91 and 92 for channel 9, pins 93 and 94 for channel 10, and pins 95 and 96 for channel 11. Pins 97 and 98 are channel 12, pins 100 and 101 are channel 13, pins 102 and 103 are channel 14, pins 105 and 106 are channel 15, and pins 107 and 110 are channel 16. Pins 6 and 7 of the digital isolation chip AD16 are connected to the on / off control pins of the high-voltage square wave power transmission circuit. The RC filter circuit, consisting of ferrite bead R183, capacitors C510, C511, and C512, filters out high-frequency noise from the 3.3V digital power supply and is connected to pin 1 of the digital isolation chip AD16. Pin 5 of the digital isolation chip AD16 is connected to the low-voltage isolation ground GND of the high-voltage square wave power transmission circuit.

[0012] Furthermore, the high-voltage square wave power transmission circuit includes a half-bridge control chip NSD1, an RC filter circuit, a first diode limiting circuit, a second diode limiting circuit, an LC filter circuit, a first RC circuit, and a second RC circuit. Pin 7 of the half-bridge control chip NSD1 is connected to a ferrite bead R6, capacitors C3, C4, and C5 to form an RC filter circuit, which is connected to a 12V operating power supply to filter out high-frequency digital noise from the 12V operating power supply. The ground of the RC filter circuit is connected to the high-voltage transmission ground TGND. Pin 3 of the half-bridge control chip NSD1 is the digital control ground, connected to the low-voltage isolation ground GND. Pin 5 of the half-bridge control chip NSD1 is the high-voltage ground, connected to the high-voltage transmission ground. Pin 1 of the NSD1 half-bridge control chip is the turn-on control pin for the high-side MOSFET of the half-bridge chip. It is connected in series with resistor R4 and the anode of diode D6, connected to a 5V isolation power supply. Resistor R4 is connected in series with the cathode of diode D5, connected to the low-voltage isolation ground GND. The first diode limiting circuit includes D5 and D6 in parallel. Pin 2 of the NSD1 half-bridge control chip is the turn-on control pin for the low-side MOSFET of the half-bridge chip. It is connected in series with resistor R9 and the anode of diode D4, connected to a 5V isolation power supply. R9 is connected in series with the cathode of diode D3, connected to the low-voltage isolation ground GND. The second diode limiting circuit includes diodes D3 and D4. Pins 1 and 2 of the half-bridge control chip NSD1 are respectively pulled down to low-voltage isolation ground by resistors R3 and R7. Pin 7 of the half-bridge control chip NSD1 is connected to the positive terminal of the high-voltage diode D1, and the negative terminal of the high-voltage diode D1 is connected to pin 13 of the half-bridge control chip NSD1. Pin 13 of the half-bridge control chip NSD1 is connected to capacitor C6, and the other end of capacitor C6 is connected to pin 11 of the half-bridge control chip NSD1. Pin 11 of the half-bridge control chip NSD1 is simultaneously connected to the drain pin 2 of the Q2 MOS transistor and the source pin 3 of the Q1 MOS transistor, and is connected to pin 1 of the high-voltage output port P1 for high-voltage pulse output. Pin 12 of the half-bridge control chip NSD1 is the high-side MOS transistor. The high-side MOSFET's output pin is connected to the gate pin 1 of the Q1 MOSFET via a series resistor R1. Pin 1 of the Q1 MOSFET is connected to pin 11 of the NSD1 half-bridge control chip via resistor R5, serving as the bleeder resistor for the gate-source capacitance between pins 1 and 3 of the Q1 MOSFET. The low-side MOSFET's output pin (pin 6 of the NSD1 half-bridge control chip) is connected to the gate pin 1 of the Q2 MOSFET via a series resistor R5. A diode D7 is connected in reverse parallel to resistor R5. Pin 1 of the Q2 MOSFET is connected to pin 2 via resistor R8 and the high-voltage emitter ground TGND, serving as the bleeder resistor for the gate-source capacitance between pins 1 and 3 of the Q2 MOSFET. The LC filter circuit consists of a 1000V 1A high-voltage power supply connected to pin 2 of the Q1 MOSFET via a solid-state inductor L1, capacitor C16, and high-voltage capacitor C2. The first RC circuit consists of a capacitor C18 and a resistor R15 connected in series, with capacitor C18 and resistor R15 connected in series to pin 2 of the Q2 MOSFET.Pin 3 of MOSFET Q2 is connected to the high-voltage emitter ground TGND. The second RC circuit consists of a high-voltage capacitor C17 and a resistor R13 connected in series and connected between pins 2 and 3 of MOSFET Q1. A ferrite bead R12 is connected between the low-voltage isolation ground GND and the high-voltage emitter ground TGND.

[0013] The present invention has the following advantages: The present invention adopts a parallel 16-channel high-voltage square wave power transmission structure instead of a single high-voltage square wave transmission with switching device, which can achieve zero error at least 1ms of equal interval multi-channel switching cyclic transmission output, which is impossible for a single high-voltage square wave transmission with switching device structure, thus ensuring zero error transmission-reception time extraction for data analysis in the later stage of the experiment.

[0014] This invention can be applied to active source-triggered simulated seismic waves in indoor simulated earthquake processes using rock friction experiments, providing a convenient and controllable technical means for studying fault wave velocity changes on a millisecond-scale time division scale during the deformation of different types of rock faults. Attached Figure Description

[0015] Figure 1 This is a flowchart of the process of the present invention;

[0016] Figure 2 This is a circuit diagram of the CLPD main controller of the present invention;

[0017] Figure 3 This is the USB 2.0 logic circuit diagram of the present invention;

[0018] Figure 4 This is a circuit diagram of one of the isolation control circuits of the present invention;

[0019] Figure 5 This is a high-voltage square wave power transmitting circuit diagram of the present invention;

[0020] Figure 6 This is a schematic diagram of the bus interface between the CLPD and the USB 2.0 chip of the present invention. Detailed Implementation

[0021] This invention provides a multi-channel rapid switching cyclic excitation device for inducing seismic waves in rock friction experiments, comprising a low-voltage logic control circuit and a high-voltage square wave power transmission circuit. The low-voltage logic control circuit includes a CPLD main controller circuit, a USB 2.0 logic circuit, and an isolation control circuit. Both the USB 2.0 logic circuit and the isolation control circuit are connected to the CPLD main controller circuit. The low-voltage logic control circuit is connected to the high-voltage square wave power transmission circuit. The USB 2.0 logic circuit and the CPLD main controller circuit are connected via a 16-bit wide Slavefifo bus.

[0022] In this embodiment, the low-voltage logic control circuit includes a CPLD chip, a power-on reset circuit, and an RC filter circuit. The power-on reset circuit includes a resistor R4 and a diode D1 connected in parallel to a 3.3V power supply. They are also connected in parallel to a capacitor C1 to DGND (digital ground) and then to pin 143 of the CLPD chip. The RC filter circuit includes a crystal oscillator CY1 whose pin 2 is connected to DGND, and whose pin 4 is connected to a 3.3V power supply via a ferrite bead R5. Capacitors C2, C3, and C4 are connected in parallel and then in series with the ferrite bead R5. Pin 30 of the CLPD chip is connected to pin 3 of the crystal oscillator CY1. Pins 1, 8, 37, 42, 55, 73, 84, 109, 127, and 141 of the CLPD chip are connected to a 3.3V power supply. Pins 18, 27, 29, 36, 47, 62, 72, 89, 90, 99, 108, 114, 123, and 144 of the CLPD chip are connected to DGND (digital ground).

[0023] In this embodiment, the USB 2.0 logic circuit includes a USB microcontroller CYU1, a USB 2.0 port, a clock oscillation circuit, an RC filter circuit, and a power-on reset circuit. Pin 5 of the USB 2.0 port is connected to resistor R9 and capacitor C36. The clock oscillation circuit includes capacitors C26 and C27 and a passive crystal oscillator Y1 to provide the operating clock for the USB microcontroller CYU1. Pin 2 of the USB microcontroller CYU1 is connected in series with resistor R13 to DGND. Pin 22 of the USB microcontroller CYU1 is connected to resistor R14 to a 3.3V power supply and then to pin 5 of the LC1 memory chip. Pin 51 of the USB microcontroller CYU1 is connected in series with resistor R14 to a 3.3V power supply. Pin 49 of the USB microcontroller CYU1 is connected to diode D2, resistor R8, and capacitor C25 to form a power-on reset circuit. Pin 1 of the LC1 chip is connected in series with resistor R16. It is connected to pin 8 (VCC). The RC filter circuit, including a ferrite bead RC, capacitors C45, C46, ​​and C37, filters out high-frequency noise from the 3.3V power supply and is connected to pin 8 of the LC1 chip. Pins 6, 14, 18, 24, 34, 39, and 50 of the USB microcontroller CYU1 are connected to the 3.3V power supply. Pins 4, 7, 13, 17, 19, 33, 35, and 48 of the USB microcontroller CYU1 are connected to DGND (digital ground). Pins 25, 26, 27, 28, 29, 30, 31, 32, 52, 53, 54, 55, 56, 1, 2, and 3 of the USB microcontroller CYU1 are sequentially connected to USBFD1~USBFD16 of the slaveFIFO bus. Pins 44 and 45 of the USB microcontroller CYU1 are sequentially connected to FIFOADDR0~ of the slaveFIFO bus. FIFOADDR1, pins 37 and 38 of the USB microcontroller CYU1 are connected sequentially to FLAGB and FLAGC of the slavefifo bus, pins 42, 8, and 9 of the USB microcontroller CYU1 are connected sequentially to SLOE, SLRD, and SLWR of the slavefifo bus, and pin 20 of the data USB microcontroller CYU1 is connected to IFCLK of the slavefifo bus.

[0024] In this embodiment, the isolation control circuit includes a digital isolation chip AD16 and an RC filter circuit. Pins 2 and 3 of the digital isolation chip AD16 are connected to pins 70 and 71 of the CLPD chip, respectively. For the other 15 isolation control circuits, pins 2 and 3 of the digital isolation chip AD16 are sequentially connected to pins 74 and 75 of the CPLD for channel 2, pins 76 and 77 for channel 3, pins 78 and 79 for channel 4, pins 80 and 81 for channel 5, pins 82 and 83 for channel 6, pins 85 and 86 for channel 7, pins 87 and 88 for channel 8, pins 91 and 92 for channel 9, pins 93 and 94 for channel 10, and pins 95 and 96 for channel 1. Pins 1, 97, and 98 are for channel 12; pins 100 and 101 are for channel 13; pins 102 and 103 are for channel 14; pins 105 and 106 are for channel 15; and pins 107 and 110 are for channel 16. Pins 6 and 7 of the digital isolation chip AD16 are connected to the on / off control pins of the high-voltage square wave power transmission circuit. The RC filter circuit, consisting of ferrite bead R183, capacitors C510, C511, and C512, filters out high-frequency noise from the 3.3V digital power supply and is connected to pin 1 of the digital isolation chip AD16. Pin 5 of the digital isolation chip AD16 is connected to the low-voltage isolation ground GND of the high-voltage square wave power transmission circuit.

[0025] In this embodiment, the high-voltage square wave power transmission circuit includes a half-bridge control chip NSD1, an RC filter circuit, a first diode limiting circuit, a second diode limiting circuit, an LC filter circuit, a first RC circuit, and a second RC circuit. Pin 7 of the half-bridge control chip NSD1 is connected to a ferrite bead R6, capacitors C3, C4, and C5 to form an RC filter circuit, which is connected to a 12V power supply to filter out high-frequency digital noise from the 12V power supply. The ground of the RC filter circuit is connected to the high-voltage transmission ground TGND. Pin 3 of the half-bridge control chip NSD1 is the digital control ground, connected to the low-voltage isolation ground GND. Pin 5 of the half-bridge control chip NSD1 is the high-voltage ground, connected to the high-voltage... The circuit originates at TGND. Pin 1 of the NSD1 half-bridge control chip is the enable pin for the high-side MOSFET of the half-bridge chip. It is connected in series with resistor R4 and the anode of diode D6, which is connected to a 5V isolation power supply. Resistor R4 is connected in series with the cathode of diode D5, which is connected to the low-voltage isolation ground GND. The first diode limiting circuit consists of D5 and D6 in parallel. Pin 2 of the NSD1 half-bridge control chip is the enable pin for the low-side MOSFET of the half-bridge chip. It is connected in series with resistor R9 and the anode of diode D4, which is connected to a 5V isolation power supply. R9 is connected in series with the cathode of diode D3, which is connected to the low-voltage isolation ground GND. The second diode limiting circuit consists of diodes D3 and D4. Pins 1 and 2 of the half-bridge control chip NSD1 are also pulled down to low-voltage isolation ground by resistors R3 and R7, respectively. Pin 7 of the half-bridge control chip NSD1 is connected to the positive terminal of the high-voltage diode D1, and the negative terminal of the high-voltage diode D1 is connected to pin 13 of the half-bridge control chip NSD1. Pin 13 of the half-bridge control chip NSD1 is connected to capacitor C6, and the other end of capacitor C6 is connected to pin 11 of the half-bridge control chip NSD1. Pin 11 of the half-bridge control chip NSD1 is simultaneously connected to the drain pin 2 of the Q2 MOS transistor and the source pin 3 of the Q1 MOS transistor, and is connected to pin 1 of the high-voltage output port P1 as a high-voltage pulse output. Pin 12 of the half-bridge control chip NSD1 is the high-side MOS transistor. A resistor R1 is connected in series to the high-side MOSFET's output pin, which is then connected to pin 1 of the gate of MOSFET Q1. Pin 1 of MOSFET Q1 is connected to resistor R5 and then to pin 11 of the half-bridge control chip NSD1, serving as the bleeder resistor for the gate-source capacitance between pins 1 and 3 of MOSFET Q1. Pin 6 of the half-bridge control chip NSD1, the low-side MOSFET's output pin, is connected in series with resistor R5 and then to pin 1 of the gate of MOSFET Q2. Resistor R5 is connected in reverse parallel with diode D7. Pin 1 of MOSFET Q2 is connected to resistor R8 and then to the high-voltage emitter ground TGND, serving as the bleeder resistor for the gate-source capacitance between pins 1 and 3 of MOSFET Q2. The LC filter circuit consists of a 1000V 1A high-voltage power supply connected to pin 2 of MOSFET Q1 via a solid-state inductor L1, capacitor C16, and high-voltage capacitor C2. The first RC circuit consists of capacitor C18 and resistor R15 connected in series, with capacitor C18 and resistor R15 connected in series to pin 2 of MOSFET Q2.Pin 3 of MOSFET Q2 is connected to the high-voltage emitter ground TGND. The second RC circuit consists of a high-voltage capacitor C17 and a resistor R13 connected in series and connected between pins 2 and 3 of MOSFET Q1. A ferrite bead R12 is connected between the low-voltage isolation ground GND and the high-voltage emitter ground TGND.

[0026] In this embodiment, as Figure 1 As shown, the workflow is as follows: the user sends instructions to the device's USB 2.0 logic circuit via the host computer software. The USB 2.0 logic circuit then transmits the instructions to the CPLD chip via the bus. The CPLD chip parses the corresponding switching channel and the transmission pulse time width, executes the corresponding action, and controls one of the 16 high-voltage square wave power transmission circuits to turn on / off at the current time to form a high-voltage transmission pulse. After that, the CPLD chip continues to execute commands to control the current transmission circuit to work or switches to the next transmission circuit to work according to the command, strictly following the time interval given by the host computer (a time interval on the order of milliseconds to seconds) to execute until the host computer software gives a new stop command. Then the entire device stops working and waits for a new host computer start command to be executed.

[0027] In this embodiment, as Figure 5 As shown, the high-voltage square wave power transmission circuit operates as follows: After power-on, the CPLD controls the I / O port of latch2 to output a high level by default. At this time, pin 6 of the AD16 isolation chip also outputs a high level by default. Then, pin 2 of NSD1 is high, turning on the low-side MOSFET Q2. After Q2 conducts to the low-voltage isolation ground, the 12V power supply charges C6 through diode D1. After a few microseconds, C6 is fully charged. At this time, if the USB interface receives a transmit command, the CPLD starts parsing and executes the action, outputting a 3.3V low-voltage pulse (pulse time width command adjustable) through the I / O port of latch1. The corresponding pin 7 of the AD16 isolation chip outputs a 5V isolated low-voltage pulse with the corresponding time width to pin 1 of the NSD1 chip. Then, the NSD1 chip turns on the high-side MOSFET Q1. After Q1 conducts for the corresponding pulse time width, it turns off and outputs a 1000V high-voltage pulse with the corresponding time width to pin 1 of port P1.

[0028] In this implementation, such as Figure 6As shown, the CPLD and the USB 2.0 chip are connected via a 16-bit wide slave FIFO bus. Specifically, the signals include 16-bit data lines USBFD1~USBFD16 (connected sequentially to pins 2~7, 9~17, and 19 of the CPLD), two address control lines FIFOADDR0~FIFOOADDR1 (connected sequentially to pins 20~21 of the CPLD), memory flag lines FLAGB (memory full) (connected to pin 22 of the CPLD) and FLAGC (memory empty) (connected to pin 23 of the CPLD), and read / write enable lines SLOE, SLRD, and SLWR (connected sequentially to pins 24~26 of the CPLD) and bus drive clock IFCLK (connected to pin 32 of the CPLD). The USB 2.0 logic circuit receives commands from the host computer software via the USB 2.0 interface and transmits them to the CPLD chip via the slave FIFO bus for execution.

[0029] In this embodiment, a circuit structure with low-voltage control and high-voltage transmission isolation is adopted. The low-voltage control uses a CPLD (Complex Programmable Logic Device) to achieve extremely precise timing and equal-interval transmission control through an external active clock crystal oscillator. Combined with a USB 2.0 interface and control software, zero-error transmission-reception time extraction can be achieved for subsequent data analysis, providing a solid technical foundation for millisecond-level wave velocity transformation observation of pre-seismic faults in rock deformation experiments.

[0030] In this embodiment, the high-voltage transmitting section adopts a parallel 16-channel structure instead of a single transmitting device combined with a switching device. This allows the CPLD to precisely control the opening / closing of any one of the 16 channels in terms of time. The structure of a single transmitting device combined with a high-voltage switching device is prone to jittering of the switching actuator before and after the switching action, making it difficult to achieve precise time control. Moreover, the known high-voltage switching devices, whether composed of high-voltage relays or other high-voltage switching devices, usually require at least several milliseconds to execute, and the jittering time after each execution is variable (several milliseconds to tens of milliseconds), making it difficult to achieve fast (1 millisecond) multi-channel high-voltage output switching.

[0031] Although specific embodiments of the present invention have been described in detail with reference to the accompanying drawings, this should not be construed as limiting the scope of protection of this patent. Various modifications and variations that can be made by those skilled in the art without inventive effort within the scope described in the claims still fall within the scope of protection of this patent.

Claims

1. A multi-channel rapid switching cyclic excitation device for inducing seismic waves in rock friction experiments, comprising a low-voltage logic control circuit and a high-voltage square wave power transmission circuit, characterized in that: The low-voltage logic control circuit includes a CPLD main controller circuit, a USB 2.0 logic circuit, and an isolation control circuit. The USB 2.0 logic circuit and the isolation control circuit are both connected to the CPLD main controller circuit. The low-voltage logic control circuit is connected to the high-voltage square wave power transmission circuit. The USB 2.0 logic circuit and the CPLD main controller circuit are connected via a 16-bit wide Slavefifo bus. The high-voltage square wave power transmission circuit includes a half-bridge control chip NSD1, an RC filter circuit, a first diode limiting circuit, a second diode limiting circuit, an LC filter circuit, a first RC circuit, and a second RC circuit. Pin 7 of the half-bridge control chip NSD1 is connected to a ferrite bead R6, capacitors C3, C4, and C5 to form an RC filter circuit, which is connected to a 12V power supply to filter out high-frequency digital noise from the 12V power supply. The ground of the RC filter circuit is connected to the high-voltage transmission ground TGND. Pin 3 of the half-bridge control chip NSD1 is the digital control ground, connected to the low-voltage isolation ground GND. Pin 5 of the half-bridge control chip NSD1 is the high-voltage ground, connected to the high-voltage generation ground TGN. D, Pin 1 of the half-bridge control chip NSD1 is the turn-on control pin for the high-side MOSFET of the half-bridge chip, and is connected in series with resistor R4 and the anode of diode D6 to a 5V isolation power supply. Resistor R4 is connected in series with the cathode of diode D5 to a low-voltage isolation ground GND. The first diode limiting circuit includes D5 and D6 in parallel. Pin 2 of the half-bridge control chip NSD1 is the turn-on control pin for the low-side MOSFET of the half-bridge chip, and is connected in series with resistor R9 and the anode of diode D4 to a 5V isolation power supply. R9 is connected in series with the cathode of diode D3 to a low-voltage isolation ground GND. The second diode limiting circuit includes diode D3 and diode D4. Pins 1 and 2 of the bridge control chip NSD1 are also pulled down to low-voltage isolation ground by resistors R3 and R7, respectively. Pin 7 of the half-bridge control chip NSD1 is connected to the positive terminal of the high-voltage diode D1, and the negative terminal of the high-voltage diode D1 is connected to pin 13 of the half-bridge control chip NSD1. Pin 13 of the half-bridge control chip NSD1 is connected to capacitor C6, and the other end of capacitor C6 is connected to pin 11 of the half-bridge control chip NSD1. Pin 11 of the half-bridge control chip NSD1 is simultaneously connected to the drain pin 2 of Q2 MOS transistor and the source pin 3 of Q1 MOS transistor, and is connected to pin 1 of the high-voltage output port P1 for high-voltage pulse output. Pin 12 of the half-bridge control chip NSD1 is the high-side MO The S-channel MOSFET, acting as the high-side turn-on output pin, is connected to the gate pin 1 of the Q1 MOSFET via a series resistor R1. Pin 1 of the Q1 MOSFET is connected to pin 11 of the NSD1 half-bridge control chip via resistor R5, serving as the bleeder resistor for the gate-source capacitance between pins 1 and 3 of the Q1 MOSFET. Pin 6 of the NSD1 half-bridge control chip, acting as the low-side turn-on output pin, is connected to the gate pin 1 of the Q2 MOSFET via a series resistor R5. A diode D7 is connected in reverse parallel to resistor R5. Pin 1 of the Q2 MOSFET is connected to a resistor R8, which is then connected to the high-voltage emitter ground TGND, serving as the bleeder resistor for the gate-source capacitance between pins 1 and 3 of the Q2 MOSFET. The LC filter circuit includes a 1000V high-voltage power supply connected to pin 2 of the Q1 MOSFET via a solid-state inductor L1, capacitor C16, and a high-voltage capacitor C2.The first RC circuit consists of a capacitor C18 and a resistor R15 connected in series. The capacitor C18 and resistor R15 are connected in series to pin 2 of the Q2 MOS transistor. Pin 3 of the Q2 MOS transistor is connected to the high-voltage emitter ground TGND. The second RC circuit consists of a high-voltage capacitor C17 and a resistor R13 connected in series and connected between pins 2 and 3 of the Q1 MOS transistor. A ferrite bead R12 is connected between the low-voltage isolation ground GND and the high-voltage emitter ground TGND. The isolation control circuit includes 16 isolation control circuits, and further includes a digital isolation chip AD16 and an RC filter circuit. Pins 2 and 3 of the digital isolation chip AD16 are connected to pins 70 and 71 of the CPLD chip, respectively. For the other 15 isolation control circuits, pins 2 and 3 of the digital isolation chip AD16 are sequentially connected to pins 74 and 75 of the CPLD for channel 2, pins 76 and 77 for channel 3, pins 78 and 79 for channel 4, pins 80 and 81 for channel 5, pins 82 and 83 for channel 6, pins 85 and 86 for channel 7, pins 87 and 88 for channel 8, pins 91 and 92 for channel 9, pins 93 and 94 for channel 10, and pins 95 and 96 for channel 10. Pin 96 is channel 11, pins 97 and 98 are channel 12, pins 100 and 101 are channel 13, pins 102 and 103 are channel 14, pins 105 and 106 are channel 15, and pins 107 and 110 are channel 16. Pins 6 and 7 of the digital isolation chip AD16 are connected to the on / off control pins of the high-voltage square wave power transmission circuit. The RC filter circuit, composed of ferrite bead R183, capacitors C510, C511, and C512, filters out high-frequency noise from the 3.3V digital power supply and is connected to pin 1 of the digital isolation chip AD16. Pin 5 of the digital isolation chip AD16 is connected to the low-voltage isolation ground GND of the high-voltage square wave power transmission circuit.

2. The multi-channel rapid switching cyclic excitation device for inducing seismic waves in rock friction experiments as described in claim 1, characterized in that: The low-voltage logic control circuit includes a CPLD chip, a power-on reset circuit, and an RC filter circuit. The power-on reset circuit includes a resistor R4 and a diode D1 connected in parallel to a 3.3V power supply. These are then connected in parallel to a capacitor C1, which is connected to digital ground (DGND) and to pin 143 of the CPLD chip. The RC filter circuit includes a crystal oscillator CY1 whose pin 2 is connected to DGND, and whose pin 4 is connected to a 3.3V power supply via a ferrite bead R5. Capacitors C2, C3, and C4 are connected in parallel and then in series with the ferrite bead R5. Pin 30 of the CPLD chip is connected to pin 3 of the crystal oscillator CY1. Pins 1, 8, 37, 42, 55, 73, 84, 109, 127, and 141 of the CPLD chip are connected to a 3.3V power supply. Pins 18, 27, 29, 36, 47, 62, 72, 89, 90, 99, 108, 114, 123, and 144 of the CPLD chip are connected to digital ground (DGND).

3. The multi-channel rapid switching cyclic excitation device for inducing seismic waves in rock friction experiments as described in claim 1, characterized in that: The USB 2.0 logic circuit includes a USB microcontroller CYU1, a USB 2.0 port, a clock oscillation circuit, an RC filter circuit, and a power-on reset circuit. Pin 5 of the USB 2.0 port is connected to resistor R9 and capacitor C36. The clock oscillation circuit includes capacitors C26 and C27 and a passive crystal oscillator Y1 to provide the operating clock for the USB microcontroller CYU1. Pin 2 of the USB microcontroller CYU1 is connected in series with resistor R13 to DGND. Pin 22 of the USB microcontroller CYU1 is connected to a 3.3V power supply via resistor R14 and then to pin 5 of the LC1 memory chip. Pin 51 of the USB microcontroller CYU1 is connected in series with resistor R14 to a 3.3V power supply. Pin 49 of the USB microcontroller CYU1 is connected to diode D2, resistor R8, and capacitor C25 to form the power-on reset circuit. Pin 1 of the LC1 memory chip is connected in series with resistor R1. Pin 6 is connected to pin 8 (VCC). The RC filter circuit includes a ferrite bead RC, capacitors C45, C46, ​​and C37 to filter out high-frequency noise from the 3.3V power supply and is connected to pin 8 of the LC1 chip. Pins 6, 14, 18, 24, 34, 39, and 50 of the USB microcontroller CYU1 are connected to the 3.3V power supply. Pins 4, 7, 13, 17, 19, 33, 35, and 48 of the USB microcontroller CYU1 are connected to DGND (digital ground). Pins 25, 26, 27, 28, 29, 30, 31, 32, 52, 53, 54, 55, 56, 1, 2, and 3 of the USB microcontroller CYU1 are sequentially connected to USBFD1~USBFD16 of the slaveFIFO bus. Pins 44 and 45 of the USB microcontroller CYU1 are sequentially connected to FIFOADDR0~ of the slaveFIFO bus. FIFOADDR1, pins 37 and 38 of the USB microcontroller CYU1 are sequentially connected to FLAGB and FLAGC of the slavefifo bus, pins 42, 8, and 9 of the USB microcontroller CYU1 are sequentially connected to SLOE, SLRD, and SLWR of the slavefifo bus, and pin 20 of the USB microcontroller CYU1 is connected to IFCLK of the slavefifo bus.

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