Method for reducing wafer edge defects

Abstract

A method of reducing wafer edge defects includes providing a wafer having a central region and a plurality of edge regions. A hard mask layer is formed on the wafer and a spacer pattern is formed on the hard mask layer. A photoresist layer is formed to cover the spacer pattern. Performing a wafer edge treatment process on the photoresist layer to form an annular photoresist pattern which selectively covers the spacer pattern in the at least one edge region and exposes the spacer pattern in the central region; and sequentially transferring the exposed spacer patterns to the hard mask layer and the wafer by taking the annular photoresist pattern as an etching mask so as to form a plurality of grooves in the wafer.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and more particularly to a method for reducing crystal edge defects. Background Art

[0002] In semiconductor processes, due to the limitations of photolithography technology, the edge of the wafer cannot usually be fully exposed, so the edge of the wafer is an invalid chip area. In addition, the edge of the wafer is also affected by the uniformity of film deposition, uniformity of photoresist coating, exposure defocus, and / or etch loading, etc., resulting in the edge of the wafer easily becoming a defect source, and then during the subsequent deposition or etching process, defects such as debris or particles are generated and sprinkled into the central area of ​​the wafer, resulting in a decrease in product yield.

[0003] The semiconductor lithography process has entered the era of graphic disassembly, that is, the patterns in the array area and the peripheral area are exposed separately. Generally speaking, in order to prevent the edge of the wafer from becoming a source of defects and maintain the consistency of chemical mechanical polishing, wafer edge processing such as edge bead removal (EBR) or wafer edge exposure (WEE) is usually performed to remove or retain the photoresist in the edge area to reduce the impact of defects caused by incomplete exposure of the edge of the wafer. However, this may form a circle of overlapping and / or non-overlapping parts at the junction of the array area and the peripheral area, which may cause the film layer and / or pattern to form unexpected height differences and produce a large number of defects, and the height differences cannot be overcome by flattening processing (for example, chemical mechanical polishing). Summary of the invention

[0004] An embodiment of the present invention provides a method for reducing crystal edge defects, comprising providing a wafer, wherein the wafer has a central area and an edge area surrounding the central area, wherein the edge area comprises a first edge area surrounding the central area, a second edge area surrounding the first edge area, and a third edge area surrounding the second edge area; forming a hard mask layer on the wafer; forming a spacer pattern on the hard mask layer; forming a photoresist layer to cover the spacer pattern; performing a crystal edge treatment process on the photoresist layer to form an annular photoresist pattern, wherein the annular photoresist pattern selectively covers the spacer pattern located in at least one of the first edge area, the second edge area, and the third edge area, and exposes the spacer pattern located in the central area; and using the annular photoresist pattern as an etching mask, sequentially transferring the exposed spacer pattern to the hard mask layer and the wafer to form a plurality of grooves in the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1FIG. 1 is a top view schematically showing a wafer according to an embodiment of the present invention.

[0006] Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A as well as Figure 7B FIG. 5 is a schematic cross-sectional view of a wafer in various process stages according to an embodiment of the present invention.

[0007] Figure 8 FIG. 1 is a top view schematically showing a wafer according to an embodiment of the present invention.

[0008] Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A as well as Fig. 13B FIG. 1 is a schematic cross-sectional view of a wafer in various process stages according to an embodiment of the present invention.

[0009] Fig.14 FIG. 4 is a top view schematically showing a wafer according to another embodiment of the present invention.

[0010] Fig.15 FIG. 4 is a cross-sectional schematic diagram of a wafer according to another embodiment of the present invention.

[0011] Fig.16 FIG. 4 is a top view schematically showing a wafer according to yet another embodiment of the present invention.

[0012] Fig.17 FIG. 4 is a cross-sectional schematic diagram of a wafer according to another embodiment of the present invention.

[0013] Fig.18 , Fig.19 , Fig. 20 as well as Fig.21 FIG. 4 is a schematic cross-sectional view of a wafer in various process stages according to yet another embodiment of the present invention.

[0014]

Explanation of symbols

[0015] 100: Wafer

[0016] 102: Marginal Area

[0017] 102A: First Marginal Area

[0018] 102B: Second marginal area

[0019] 102C: The Third Marginal Area

[0020] 104: Central District

[0021] 106: Hard mask layer

[0022] 108: Patterned mandrel

[0023] 110: spacer material layer

[0024] 112: Etching process

[0025] 114: Spacer pattern

[0026] 116: Photoresist layer

[0027] 118: Crystal edge processing technology

[0028] 120: Ring photoresist pattern

[0029] 122: First etching process

[0030] 124: Second etching process

[0031] 126: Groove

[0032] 128: Trench isolation structure

[0033] 130: Crystal edge processing technology

[0034] 132: Mandrel layer

[0035] 134: Photoresist layer

[0036] 136: Mandrel photoresist pattern

[0037] A-A': section line

[0038] B-B': Section line

[0039] X: coordinate axis

[0040] Y: coordinate axis

[0041] Z: coordinate axis DETAILED DESCRIPTION

[0042] The present application provides a method for combining an additional wafer edge processing process with a photolithography process station, which can form a multi-layer wafer edge structure in the current layer and eliminate the step difference at a specific position to improve the problem of unexpected defects on the edge of the wafer without the need for additional wafer edge bevel etching process or sacrificing the process margin of subsequent planarization processing.

[0043] Figure 1 FIG. 1 is a schematic top view of the wafer 100 . Figure 2A , Figure 2B Draw the diagrams along Figure 1 The wafer 100 is a schematic cross-sectional view of the edge region 102 along the section line A-A' and the section line BB' along the central region 104. The wafer 100 has a central region 104 and an edge region 102. The edge region 102 includes a first edge region 102A surrounding the central region 104, a second edge region 102B surrounding the first edge region 102A, and a third edge region 102C surrounding the second edge region 102B, but the number of edge regions is not limited thereto. Due to the characteristics of the photolithography process, the edge region 102 of the wafer 100 cannot be fully exposed, so the edge region 102 is defined as an invalid chip region. The width of each of the first, second and third edge regions 102A, 102B, and 102C depends on the process margin of the subsequent wafer edge processing process. In one embodiment, the width of each of the first, second and third edge regions 102A, 102B, and 102C is about 0.5 mm to 1.5 mm. In one embodiment, the width of the edge region 102 is about 3 mm to 3.5 mm.

[0044] See also Figure 2A , Figure 2B , forming a hard mask layer 106 on the wafer 100. The hard mask layer 106 may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The material of the hard mask layer 106 may include silicon oxide, silicon nitride, or silicon oxynitride formed by tetraethylorthosilicate (TEOS).

[0045] See also Figure 3A , Figure 3B, a self-aligned double patterning (SADP) process is performed to form a spacer pattern on the hard mask layer 106. In one embodiment, performing the self-aligned double patterning process includes forming a patterned mandrel 108 on the hard mask layer 106. A spin-on coating process may be used to form a mandrel layer (not shown) on the hard mask layer 106, and then the patterned mandrel 108 may be formed by photolithography and etching processes. Since the formation of the mandrel layer is affected by the uniformity of film deposition, the mandrel layer in the edge region 102 may have a non-uniform thickness that gradually decreases toward the edge of the wafer 100. Therefore, the patterned mandrel 108 in the edge region 102 may also have a non-uniform height that gradually decreases toward the edge of the wafer 100, while the patterned mandrel 108 in the central region 104 has the same height. In other embodiments, a trimming process may be additionally performed on the patterned mandrel 108 to further reduce the size of the patterned mandrel 108. In one embodiment, the patterned mandrel 108 may be a single-layer structure or a multi-layer structure, and the material of the patterned mandrel 108 may include carbon, silicon oxynitride, a bottom anti-reflective coating (BARC), or a combination thereof.

[0046] See also Figure 4A , Figure 4B The self-aligned double patterning process further includes conformingly forming a spacer material layer 110 on the hard mask layer 106 and the patterned mandrel 108. The spacer material layer 110 may be formed by chemical vapor deposition, atomic layer deposition, or a combination thereof. The material of the spacer material layer 110 may be an oxide such as silicon oxide.

[0047] See also Figure 5A , Figure 5B The self-aligned double patterning process further includes an etching-back process 112 on the spacer material layer 110 to form a spacer pattern 114 and expose the top surface of the patterned mandrel 108 and a portion of the top surface of the hard mask layer 106. The etching process 112 may include an anisotropic etching process (or a directional etching process), such as a reactive ion etching (RIE) process, plasma etching, inductively coupled plasma (ICP) etching, or dry etching of a combination thereof.

[0048] See also Fig. 6A , Figure 6BThe self-aligned double patterning process further includes removing the patterned mandrels 108 to leave the spacer patterns 114 on the hard mask layer 106. Since the patterned mandrels 108 have non-uniform heights in the edge region 102, the spacer patterns 114 originally located on the sidewalls of the patterned mandrels 108 in the edge region 102 also have non-uniform heights. The patterned mandrels 108 may be removed by an ashing process, wet etching, dry etching, or a combination thereof.

[0049] See also Fig. 7A , Figure 7B Then, a photoresist layer 116 is formed to cover the spacer pattern 114. The photoresist layer 116 can be formed by a spin coating process. In the present application, the photoresist layer 116 can be a positive photoresist or a negative photoresist, and the positive photoresist is defined as a portion exposed to be removed after the development process (that is, the photoresist becomes soluble after exposure), and the negative photoresist is defined as a portion exposed to be retained after the development process (that is, the photoresist becomes insoluble after exposure).

[0050] Continue to see Fig. 7A , Figure 7B and Figure 8 , then, a crystal edge treatment process 118 is performed on the photoresist layer 116 to form a ring-shaped photoresist pattern 120. In the present application, depending on the uneven height distribution of the spacer pattern 114 in the edge area 102, the ring-shaped photoresist pattern 120 can selectively cover the spacer pattern 114 located in at least one of the first edge area 102A, the second edge area 102B, and the third edge area 102C, and expose the spacer pattern 114 located in the central area 104. In some embodiments, the ring-shaped photoresist pattern 120 covers the spacer pattern 114 with a relatively low height in the edge area 102 to reduce the damage to this area caused by the subsequent etching process. In some embodiments, the ring-shaped photoresist pattern 120 is only formed on one of the first edge area 102A, the second edge area 102B, and the third edge area 102C. In other embodiments, the annular photoresist pattern 120 is formed on two adjacent or non-adjacent portions of the first edge region 102A, the second edge region 102B, and the third edge region 102C. In one embodiment, the photoresist layer 116 is a negative photoresist. In the present application, the crystal edge treatment process 118 includes a crystal edge exposure process or an edge glue removal process. In one embodiment, the crystal edge exposure process is performed on the photoresist layer 116 (negative photoresist) on the second edge region 102B to form an annular photoresist pattern 120 covering only the second edge region 102B after the development process. The photoresist layer 116 (negative photoresist) on the central region 104, the first edge region 102A, and the third edge region 102C is not exposed and is therefore removed after the development process.

[0051] See also Figure 8 , Fig. 9A and Fig. 9B Then, a development process is performed to leave the annular photoresist pattern 120 covering the second edge region 102B, while the photoresist layer 116 in the first edge region 102A, the third edge region 102C, and the central region 104 is removed after the development process.

[0052] It should be understood that in other embodiments, the photoresist layer 116 may also be a positive photoresist, and a ring-shaped photoresist pattern 120 that only covers the second edge area 102B may also be formed, but the difference is that the embodiment using positive photoresist performs a crystal edge exposure process on the photoresist layer 116 of the first edge area 102A and the third edge area 102C, so as to leave an unexposed photoresist layer 116 (positive photoresist) on the second edge area 102B after the development process.

[0053] Next, see Figure 8 , Fig. 10A , Fig. 10B After forming the annular photoresist pattern 120 above the second edge region 102B, the annular photoresist pattern 120 is used as an etching mask to sequentially transfer the exposed spacer pattern 114 to the hard mask layer 106 and the wafer 100 to form a plurality of grooves 126 in the wafer 100. The annular photoresist pattern 120 can protect the spacer pattern 114 covered by it, so that the subsequent pattern transfer process will not affect the area covered by the annular photoresist pattern 120. In one embodiment, a first etching process 122 is performed to transfer the spacer pattern 114 to the hard mask layer 106 first. In one embodiment, the first etching process 122 uses the spacer pattern 114 and the annular photoresist pattern 120 as etching masks to etch the hard mask layer 106, and transfers the exposed spacer pattern 114 to the hard mask layer 106 first. In one embodiment, the first etching process 122 may include dry etching, wet etching, or a combination thereof.

[0054] Next, see Fig.11A , Fig. 11B , the annular photoresist pattern 120 and the spacer pattern 114 are removed. In one embodiment, the hard mask layer 106 on the second edge region 102B covered by the annular photoresist pattern 120 is not affected by the first etching process 122, so the hard mask layer 106 on the second edge region 102B maintains a terrace structure after the first etching process 122. In one embodiment, the annular photoresist pattern 120 and the spacer pattern 114 can be removed by an ashing process, wet etching, dry etching, or a combination thereof.

[0055] Next, see Fig. 12A , Fig. 12BThe second etching process 124 is performed using the patterned hard mask layer 106 as an etching mask to transfer the pattern of the spacer pattern 114 from the hard mask layer 106 to the wafer 100. In one embodiment, the second etching process 124 may include dry etching, wet etching, or a combination thereof.

[0056] Next, see Fig.13A , Fig. 13B , a dielectric material layer (not shown) may be formed on the wafer 100 and filled into the trench 126, and then the dielectric material layer may be planarized to expose the top surface of the hard mask layer 106 on the wafer 100, thereby forming a trench isolation structure 128. It is worth noting that before forming the dielectric material layer filling the trench 126, a dielectric liner (not shown) may be conformably deposited on the trench 126. The dielectric liner may improve the interface characteristics between the substrate of the wafer 100 and the dielectric material layer, and may serve as an etch stop layer for subsequent planarization. In some embodiments, the material of the dielectric liner is silicon oxide, silicon oxynitride, or a combination thereof. In one embodiment, the dielectric material layer may be formed by a chemical vapor deposition process, an atomic layer deposition process, a spin coating process, or other suitable processes.

[0057] After the trench isolation structure 128 is formed, other semiconductor processes may be performed to form various components, which will not be described in detail here.

[0058] In the process of forming the trench isolation structure 128 in the prior art, due to the characteristics of the photolithography and etching processes, a spacer pattern 114 with uneven height distribution is formed in the edge region 102, which makes it impossible to form a complete trench 126 in the edge region 102. For example, in the edge region 102, if the height of the spacer pattern 114 is too low, the subsequent etching process may over-etch this region, thereby forming a trench 126 with a lower top surface than the central region 104 or making the top opening of the trench 126 too large, causing defects such as debris or particles to be easily generated during the deposition process or etching process of forming subsequent components and spilled into the central region 104 of the wafer 100, thereby affecting the product yield. In the present application, by forming a ring-shaped photoresist pattern 120 above the selected edge area 102 to cover the spacer pattern 114 having an uneven height or susceptible to over-etching due to etching characteristics, over-etching of this area by subsequent etching processes can be avoided, reducing the probability of defects such as fragments or particles in the invalid chip area, thereby avoiding affecting the components in the central area to maintain the performance of the product.

[0059] Fig.14 FIG. 1 is a top view of a wafer 100 after a ring-shaped photoresist pattern 120 is formed according to another embodiment of the present invention. Fig.15 Draw along Fig.14The embodiment is a schematic cross-sectional view of the edge region 102 along the section line AA'. The difference between the present embodiment and the aforementioned embodiment is that in the present embodiment, after performing a crystal edge exposure process (WEE) on the photoresist layer 116 (e.g., a negative photoresist) above the second edge region 102B and the third edge region 102C, a development process is performed to leave an annular photoresist pattern 120 covering the second edge region 102B and the third edge region 102C, while the photoresist layer 116 of the first edge region 102A and the central region 104 is removed after the development process.

[0060] Fig.16 FIG. 1 is a top view of a wafer 100 after a ring-shaped photoresist pattern 120 is formed according to another embodiment of the present invention. Fig.17 Draw along Fig.16 The embodiment is a schematic cross-sectional view of the edge region 102 along the section line AA'. The difference between the present embodiment and the aforementioned embodiment is that in the present embodiment, after performing a crystal edge exposure process (WEE) on the photoresist layer 116 (e.g., a negative photoresist) above the first edge region 102A and the third edge region 102C, a development process is performed to leave an annular photoresist pattern 120 covering the first edge region 102A and the third edge region 102C, while the photoresist layer 116 of the second edge region 102B and the central region 104 is removed after the development process.

[0061] Fig.18 , Fig.19 , Fig. 20 as well as Fig.21 According to another embodiment of the present invention, Figure 1 The difference between this embodiment and the above-mentioned embodiment is that during the formation of the patterned mandrel 108 (for example, Figure 3A as well as Figure 3B In the process described above, another edge treatment process 130 is additionally performed on the edge region 102 to prevent the spacer pattern 114 from being formed in this region. Fig.18 Similar to the first embodiment, in this embodiment, after forming the hard mask layer 106, a spin coating process is used to form a mandrel layer 132 on the hard mask layer 106. Subsequently, another photoresist layer 134 is formed on the mandrel layer 132. In this embodiment, the photoresist layer 134 is a positive photoresist.

[0062] In this embodiment, a crystal edge treatment process 130 (eg, a crystal edge exposure process or an edge resist removal process) is performed on the photoresist layer 134 above the third edge region 102C to remove the photoresist layer 134 above the third edge region 102C. Fig.19 Next, the remaining photoresist layer 134 is patterned to form a mandrel photoresist pattern 136 on the mandrel layer 132. Fig. 20 , the mandrel photoresist pattern 136 is transferred to the mandrel layer 132 through an etching process to form a patterned mandrel 108. In this embodiment, since the photoresist layer 134 above the third edge region 102C is removed, the patterned mandrel 108 is only formed above the first edge region 102A, the second edge region 102B, and the central region 104. Fig.21 , the self-aligned double patterning process described in the previous embodiment may be continued to form the spacer pattern 114. In the present embodiment, the spacer pattern 114 is also formed only on the first edge region 102A, the second edge region 102B, and the central region 104. In the present embodiment, after forming the spacer pattern 114 on the hard mask layer 106, the self-aligned double patterning process described in the previous embodiment may be continued to form the spacer pattern 114. 7A to 13A A process is performed to form a ring-shaped photoresist pattern 120 in the selected edge region 102 and further improve the defect problem of the groove 126 in the edge region 102, which will not be described in detail here.

[0063] It should be understood that, although the above embodiment is described by taking the formation of a trench isolation structure as an example, the method of the present invention can also be applied to other processes that require the formation of a trench structure, such as an internal connection trench, a buried word line, a trench capacitor, etc. Therefore, although not shown in the figure, before the hard mask layer 106 is formed, various components, such as doped regions, isolation regions, transistors, internal connection structures, etc., may have been formed on the wafer 100.

[0064] In summary, the present application can effectively improve the incomplete etching or over-etching of the grooves formed in the edge area of ​​the wafer by the self-aligned double patterning process combined with the formation of the annular photoresist pattern, and reduce the probability of defects such as debris or particles in the edge area. It should be understood that not all advantages are necessarily discussed here, and not all embodiments need to have specific advantages, and other embodiments may provide different advantages.

[0065] The features of several embodiments are summarized above so that those with ordinary knowledge in the technical field to which the present invention belongs can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that such equivalent structures do not deviate from the spirit and scope of the present invention, and various changes, substitutions, and replacements can be made without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the claims.

Claims

1. A method for reducing crystal edge defects, characterized in that: include: A wafer is provided, wherein the wafer has a central region and an edge region, wherein the edge region includes: a first edge region surrounding the central region, a second edge region surrounding the first edge region, and a third edge region surrounding the second edge region; forming a hard mask layer on the wafer; forming a spacer pattern on the hard mask layer; forming a photoresist layer to cover the spacer pattern; Performing a crystal edge treatment process on the photoresist layer to form an annular photoresist pattern, wherein the annular photoresist pattern selectively covers the spacer pattern located in at least one of the first edge region, the second edge region, and the third edge region, and exposes the spacer pattern located in the central region; and The annular photoresist pattern is used as an etching mask to sequentially transfer the exposed spacer pattern to the hard mask layer and the wafer to form a plurality of grooves in the wafer.

2. The method for reducing crystal edge defects according to claim 1, characterized in that: After forming the hard mask layer, performing a self-aligned double patterning process to form the spacer pattern on the hard mask, the self-aligned double patterning process comprising: forming a patterned mandrel on the hard mask layer; conformably forming a spacer material layer on the hard mask layer and the patterned mandrel; etching the spacer material layer to expose top surfaces of the patterned mandrels; and The patterned mandrel is removed to form the spacer pattern.

3. The method for reducing crystal edge defects according to claim 2, characterized in that: The steps of forming the patterned mandrel include: forming a mandrel layer on the hard mask layer; forming another photoresist layer on the mandrel layer; Performing a crystal edge exposure process or an edge photoresist removal process on the other photoresist layer to remove the other photoresist layer located in the edge area; patterning the remaining another photoresist layer to form a mandrel photoresist pattern; and The mandrel photoresist pattern is transferred to the mandrel layer to form the patterned mandrels.

4. The method for reducing crystal edge defects according to claim 1, characterized in that: The annular photoresist pattern is formed on two adjacent ones of the first edge region, the second edge region, and the third edge region.

5. The method for reducing crystal edge defects according to claim 1, characterized in that: The annular photoresist pattern is formed on two non-adjacent ones of the first edge region, the second edge region, and the third edge region.

6. The method for reducing crystal edge defects according to claim 1, characterized in that: The annular photoresist pattern is formed only on one of the first edge region, the second edge region, and the third edge region.

7. The method for reducing crystal edge defects according to claim 1, characterized in that: The spacer pattern has a non-uniform height in the edge region, and the ring-shaped photoresist pattern covers the spacer pattern having a relatively lower height in the edge region.

8. The method for reducing crystal edge defects according to claim 1, characterized in that: The edge region further includes a fourth edge region surrounding the third edge region, and the annular photoresist pattern covers at least one of the first edge region, the second edge region, the third edge region, and the fourth edge region.

9. The method for reducing crystal edge defects according to claim 1, characterized in that: After forming the plurality of grooves, the method further comprises: forming a dielectric material layer on the wafer and filling the plurality of trenches; and A planarization process is performed on the dielectric material layer to expose the top surface of the wafer and form a trench isolation structure.

10. The method for reducing crystal edge defects according to claim 1, characterized in that: Transferring the exposed spacer pattern to the hard mask layer and the wafer in sequence further comprises: performing a first etching process to transfer the spacer pattern to the hard mask layer; removing the annular photoresist pattern and the spacer pattern; and A second etching process is performed using the patterned hard mask layer as an etching mask to transfer the spacer pattern to the wafer.

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