Control method, electronic equipment, chip and storage medium

Abstract

The invention relates to a control method, electronic equipment, a chip and a storage medium. The method is applied to an integrated circuit device. The integrated circuit device monitors communication data between the first device and the second device in the bus; if the working state of the integrated circuit device is determined to be a first working state according to the communication data and the bus is in an idle state, simulating a second device to perform bus arbitration on the first device, simulating the first device to perform bus arbitration on the second device, and controlling a switch module to perform switching, enabling the integrated circuit device to be respectively connected with the first device and the second device; and when it is determined that the first device preempts the bus with the highest priority, sending the resending data to the second device. The integrated circuit device switches the switch module after the first device and the second device are both subjected to bus arbitration, so that the influence of burrs generated in the switching process of the switch module on the operation of the SPMI bus can be avoided, and the control of the external integrated circuit device on the data of the slave is realized.

Description

Technical Field

[0001] The present application relates to the field of bus communication technology, and in particular to a control method, an electronic device, a chip and a storage medium. Background Art

[0002] The existing System Power Management Interface (SPMI) is a two-wire serial interface, usually used as a power management interface, through which the host and the slave can be connected. For example, the host can be a system-on-a-Chip (SOC) and the slave can be a power management chip (PMIC). Through the SPMI bus, the processor performance level required for a given workload or application of the relevant equipment can be accurately monitored and controlled, and the power supply voltage can be dynamically controlled in real time according to the performance level. However, the data in the master-slave system based on the SPMI bus must be controlled by the host, and the data in the master-slave system cannot be stably controlled by external devices. Summary of the invention

[0003] In view of the above, it is necessary to provide a bus monitoring and control method, electronic device, chip and storage medium to solve the problem that data in a master-slave system based on the SPMI bus cannot be stably controlled by an external device.

[0004] In a first aspect, an embodiment of the present application provides a bus monitoring and control method, which is applied to an integrated circuit device, wherein the integrated circuit device is connected to a host, and the host, the integrated circuit device, and the slave are respectively connected to a switch module through a system power management interface SPMI bus, and the method comprises: monitoring the communication data between the host and the slave in the SPMI bus; if it is determined according to the communication data that the working state of the integrated circuit device is a first working state, sending preset reissued data to the slave; wherein the sending of the preset reissued data to the slave comprises: if it is monitored that the SPMI bus is in an idle state, simulating the slave to perform bus arbitration on the host, and simulating the host to perform bus arbitration on the slave; controlling the switch module to switch so that the integrated circuit device is connected to the host and the slave, respectively; and when it is determined that the host preempts the SPMI bus with the highest priority, sending the reissued data to the slave. In the above technical solution, when the integrated circuit device is in the first working state, it detects whether the SPMI bus is idle. When the SPMI bus is idle, the integrated circuit device first simulates the slave to perform bus arbitration on the host, and simulates the host to perform bus arbitration on the slave. When both the host and the slave perform bus arbitration, the switch module is switched. In this way, the burrs generated during the switching of the switch module can be prevented from affecting the correct operation of the SPMI bus, and at the same time, it is ensured that no other host or slave will simultaneously preempt the bus when the switch module is switched, thereby realizing the external integrated circuit device to stably control the data of the slave.

[0005] In one embodiment of the present application, the method further includes: if it is determined according to the communication data that the working state of the integrated circuit device is the second working state, controlling the switch module to switch so that the host and the slave are connected. In the above scheme, the host establishes a communication channel with the slave through the switch module, and transmits the communication data directly to the slave through the switch module.

[0006] In one embodiment of the present application, determining the working state of the integrated circuit device according to the communication data includes: if it is determined that the communication data includes a preset instruction, determining the working state of the integrated circuit device to be the first working state; or if it is determined that the communication data does not include a preset instruction, determining the working state of the integrated circuit device to be the second working state. In the above technical solution, the working state of the integrated circuit device can be determined according to the preset instruction included in the communication data.

[0007] In one embodiment of the present application, the bus arbitration of simulating the slave to the host and the bus arbitration of simulating the host to the slave include: simulating the slave to perform bus arbitration by pulling up the data signal line of the SPMI bus connected to the upper port of the integrated circuit device, wherein the upper port is connected to the host through the SPMI bus; simulating the slave to perform bus arbitration by pulling up the data signal line of the SPMI bus connected to the lower port of the integrated circuit device, wherein the lower port is connected to the slave through the SPMI bus. In the above technical solution, the integrated circuit device simulates the slave to pull up the data signal line to initiate bus arbitration for the host, and pulls up the integrated circuit device to initiate bus arbitration for the slave to simulate the host, and the switch module is switched after both sides are pulled up, so as to avoid the burrs generated during the switching process of the switch from affecting the operation of the SPMI bus.

[0008] In one embodiment of the present application, when it is determined that the host preempts the SPMI bus with the highest priority, sending the reissued data to the slave includes: writing the reissued data value to the slave through an external register write instruction. In the above technical solution, the integrated circuit device can write the reissued data from the non-host into the slave through an external register write instruction.

[0009] In one embodiment of the present application, after the host simulates the slave to perform bus arbitration, the method further includes: if the SPMI bus instruction cycle of the slave performing bus arbitration reaches the stage where the slave preempts the SPMI bus with the highest priority, sending a preset slave address to the host. In the above technical solution, when the host simulates the slave to perform bus arbitration, if the SPMI bus instruction cycle reaches the stage where the slave preempts the SPMI bus with the highest priority, the preset slave address is sent to the host to ensure the correct operation of the SPMI bus instruction cycle.

[0010] In one embodiment of the present application, after sending the preset slave address to the host, the method further includes: if the SPMI bus instruction cycle of the slave performing bus arbitration reaches the stage of frame sequence, writing preset data to the host with the preset host address. In the above technical solution, when the host simulates the slave to perform bus arbitration, if the SPMI bus instruction cycle reaches the stage of frame sequence, writing preset data to the host with the preset host address further ensures the correct operation of the SPMI bus instruction cycle.

[0011] In one embodiment of the present application, the writing of preset data to a host having a preset host address comprises: writing the preset data to a register of the host having the preset host address through a master write instruction. In the above technical solution, the integrated circuit device can transmit the preset data to the host having the preset host address through the master write instruction.

[0012] In an embodiment of the present application, the retransmission data is data determined according to the type of the slave.

[0013] In a second aspect, some embodiments of the present application provide an electronic device, which includes a memory and a processor: wherein the memory is used to store program instructions; the processor is used to read and execute the program instructions stored in the memory, and when the program instructions are executed by the processor, the electronic device executes the above-mentioned bus monitoring and control method.

[0014] In a third aspect, some embodiments of the present application provide a chip comprising a processor and a memory; wherein the processor is connected to the memory; the memory is used to store program instructions; and the processor is used to read the program instructions stored in the memory to implement the above-mentioned bus monitoring and control method.

[0015] In a fourth aspect, some embodiments of the present application provide a computer storage medium storing program instructions. When the program instructions are executed on an electronic device, the electronic device executes the above-mentioned bus monitoring and control method.

[0016] In addition, the technical effects brought about by the second to fourth aspects can be found in the descriptions related to the methods of each design in the above method part, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the architecture of the SPMI bus in the related technology.

[0018] Figure 2 It is a schematic diagram of the instruction cycle of the SPMI bus in one embodiment of the present application.

[0019] Figure 3 Schematic diagram of the architecture of the SPMI bus in one embodiment of the present application.

[0020] Figure 4 It is a functional module diagram of an integrated circuit device in one embodiment of the present application.

[0021] Figure 5 This is a schematic diagram of the connection between an integrated circuit device and a host and a slave in an embodiment of the present application.

[0022] Figure 6This is a schematic diagram of the connection between an integrated circuit device and a host and a slave in another embodiment of the present application.

[0023] Figure 7 Flow chart of a bus monitoring and control method in one embodiment of the present application.

[0024] Figure 8 This is a schematic diagram of the connection between an integrated circuit device and a host and a slave in another embodiment of the present application.

[0025] Fig. 9 Schematic diagram of a flow chart of a method for monitoring an SPMI bus in an embodiment of the present application.

[0026] Fig.10 This is a flow chart of a bus monitoring and control method in another embodiment of the present application.

[0027] Fig.11 Schematic diagram of the hardware structure of an electronic device in one embodiment of the present application. DETAILED DESCRIPTION

[0028] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of some embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in some embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field in this application. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. It should be understood that, unless otherwise specified in this application, " / " means or. For example, A / B can represent A or B. "And / or" in some embodiments of the present application is only a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. "At least one" means one or more. "Multiple" means two or more than two. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c, a, b and c seven situations.

[0030] refer to Figure 1As shown, it is a schematic diagram of the architecture of the System Power Management Interface (SPMI) bus in the related art. The SPMI bus is an asynchronous bus that can connect multiple hosts 11 and multiple slaves 12, and multiple hosts 11 and multiple slaves 12 exchange data through the SPMI bus. In one embodiment of the present application, the host 11 and the slave 12 perform bus preemption through arbitration to resolve the conflict problem. When the bus is in an idle state, multiple hosts 11 or slaves 12 can access the bus through bus arbitration requests, and the host 11 of the bus monitors the bus arbitration request and grants the bus to a requester.

[0031] When the bus is in an idle state, multiple hosts 11 or slaves 12 can access the bus through a bus arbitration request. A host 11 of the bus (the host is the current owner of the bus) monitors the bus arbitration request and grants the bus to a requester. Generally, the SPMI bus can include a clock signal line and a data signal line. The clock signal line is used to transmit the clock signal SCLK (Serial Clock), and the data signal line is used to transmit the data signal SDATA (Serial Data). The SPMI bus can support the simultaneous connection of 4 hosts 11 and the access of 16 slaves 12. For example, the SPMI bus can be connected to one or more hosts 11 on a system-on-a-Chip (SOC), or to one or more slaves 12 on a power management chip (PMIC).

[0032] Figure 1 The architecture shown is for illustrative purposes only and is not limited to this in actual applications.

[0033] refer to Figure 2As shown, it is a schematic diagram of the instruction cycle of the SPMI bus in one embodiment of the present application. In one embodiment of the present application, the SPMI bus instruction cycle includes the following multiple stages: bus arbitration, sequence start, frame sequence, and bus stop cycle. In the bus arbitration stage, when the data signal line of the SPMI bus is pulled high, the host 11 currently occupying the SPMI bus releases the clock signal SCLK through the clock signal line. The host 11 or the slave 12 connected to the SPMI bus pulls up the data signal line under the corresponding clock signal SCLK to declare its own priority. If there is a device with a higher priority requesting to occupy the SPMI bus, the host 11 currently occupying the SPMI bus releases the bus to the device with a higher priority according to the priority. After the host 11 or the slave 12 and other devices seize the SPMI bus and become the controller of the SPMI bus, they obtain the control right of the clock signal SCLK of the SPMI bus and provide the clock signal SCLK of the SPMI bus. After completing the bus arbitration, the SPMI bus enters the sequence start stage. The sequence start stage can be a bus buffer stage. In the sequence start phase, the device that wins the bus preemption will pull down the clock signal SCLK, and at the same time control the data signal line to first pull up the data signal SDATA, and then pull down the data signal SDATA, generating a sequence start condition (SSC). After the slave 12 on the SPMI bus, such as the power management chip, detects the start timing, it is ready to receive the subsequent frame sequence.

[0034] In one embodiment of the present application, a frame sequence is used to execute a data transmission instruction. The data transmission instruction includes information such as a transmission command, a transmission address, and transmission data. In one embodiment of the present application, the types of transmission commands include, but are not limited to: the host 11 reads the register of the slave 12, the host 11 writes the register of the slave 12, and the slave 12 writes the register of the host 11. In one embodiment of the present application, the transmission address includes the address of the slave 12 and the address of the register of the slave 12. For example, a specific data transmission instruction may be a command for the host to write 01 data to the 0011 register of the slave with an address of 0001. After completing the data transmission instruction in the frame sequence, the SPMI bus enters a bus stop cycle.

[0035] In one embodiment of the present application, the bus stop cycle phase of the SPMI bus is a process of bus stop, and the SPMI bus is in an idle state. When the SPMI bus is in the bus stop cycle phase, the clock signal SCLK and the transmission data signal SDATA of the SPMI bus are both pulled low, for example, the clock signal SCLK and the transmission data signal SDATA of the SPMI bus are pulled low to a low level.

[0036] However, in the related art, Figure 1The data interaction between the host 11 and the slave 12 on the SPMI bus shown is controlled by the host 11 and cannot be controlled by an external device. In order to solve the problem that the data interaction between the host 11 and the slave 12 on the SPMI bus cannot be controlled by an external device, the embodiment of the present application provides another SPMI bus architecture. Figure 3 As shown, it is a schematic diagram of the architecture of the SPMI bus in an embodiment of the present application. In an embodiment of the present application, multiple hosts 11 are connected to an integrated circuit (IC) device 13. For example, multiple hosts 11 are connected to the integrated circuit device 13 via the SPMI bus. Multiple hosts 11, multiple slaves 12, and the integrated circuit device 13 are connected to the switch module 14 via the SPMI bus respectively. The integrated circuit device 13 can control the switch module 14 to switch between the first channel and the second channel. If the switch module 14 is switched to the first channel, the host 11 and the slave 12 are connected to the integrated circuit device 13 via the SPMI bus respectively. If the switch module 14 is switched to the second channel, the host 11 is directly connected to the slave 12 via the SPMI bus.

[0037] In one embodiment of the present application, the switch module 14 includes a first switch 141 and a second switch 142. The first switch 141 and the second switch 142 are dual-channel high-speed switches. The first channel of the first switch 141 and the first channel of the second switch 142 are both connected to the integrated circuit device 13, and the second channel of the first switch 141 is connected to the second channel of the second switch 142. In this way, if the first switch 141 and the second switch 142 are both switched to the first channel, the integrated circuit device 13 is respectively connected to the host 11 and the slave 12 through the SPMI bus, and if the first switch 141 and the second switch 142 are both switched to the second channel, the host 11 is directly connected to the slave 12 through the SPMI bus.

[0038] In one embodiment of the present application, the working state of the integrated circuit device 13 includes a first working state and a second working state. The first working state indicates that the integrated circuit device 13 sends data from the non-host to the slave 12, that is, the integrated circuit device 13 resends data to the slave 12. In multiple embodiments of the present application, the data from the non-host 11 is used as resending data, and the resending data is sent to the slave 12. The second working state indicates that the integrated circuit device 13 controls the host 11 to directly interact with the slave 12.

[0039] refer to Figure 4 , which is a functional module diagram of an integrated circuit device 13 in an embodiment of the present application. The integrated circuit device 13 includes a bus monitoring module 131, a data retransmission module 132 and a switch control module 133. Figure 5, which is a schematic diagram of the connection between the integrated circuit device and the host and the slave in one embodiment of the present application. In one embodiment of the present application, if the integrated circuit device 13 works in the first working state, the first switch 141 switches to the first channel, and the second switch 142 switches to the first channel. In this way, the host 11 communicates with the integrated circuit device 13 through the first channel of the first switch 141, and the slave 12 communicates with the integrated circuit device 13 through the first channel of the second switch 142. Figure 6 FIG. 1 is a schematic diagram of the connection between the integrated circuit device and the host and the slave in another embodiment of the present application. In one embodiment of the present application, if the integrated circuit device 13 works in the second working state, the first switch 141 switches to the second channel, and the second switch 142 switches to the second channel. The host 11 directly exchanges data with the slave 12 through the second channel of the first switch 141 through the second channel of the second switch 142.

[0040] In one embodiment of the present application, the bus monitoring module 131 is connected to the data retransmission module 132 and the switch control module 133 respectively. The switch control module 133 is connected to the first switch 141 and the second switch 142, and is used to control the first switch 141 and the second switch 142 to switch between the first channel and the second channel. The data retransmission module 132 is connected to the first channel of the first switch 141 and the first channel of the second switch 142 respectively. The bus monitoring module 131 is used to monitor the communication data between the host 11 and the slave 12, and determine the working state of the integrated circuit device 13 according to the monitored communication data. If it is determined that the communication data between the host 11 and the slave 12 includes a preset instruction, the working state of the integrated circuit device 13 is determined to be the first working state. If it is determined that the communication data between the host 11 and the slave 12 does not include a predetermined instruction, the working state of the integrated circuit device 13 is determined to be the second working state. The predetermined instruction includes but is not limited to: an instruction for the host 11 to read the slave 12, an instruction for the host 11 to write the slave 12, and an instruction for the slave 12 to write the host 11. When the bus monitoring module 131 determines that the working state of the integrated circuit device 13 is the second working state, it determines the switch switching time and notifies the switch control module 133 of the switch switching time. The switch control module 133 controls the first switch 141 and the second switch 142 to switch according to the switch switching time to switch the channel of the switch conduction. For example, when the integrated circuit device 13 is working in the second working state, the switch control module 133 controls the first switch 141 and the second switch 142 to switch to the second channel according to the switch switching time. When the integrated circuit device 13 is working in the first working state, the switch control module 133 controls the first switch 141 and the second switch 142 to switch to the first channel according to the switch switching time. When the bus monitoring module 131 determines that the working state of the integrated circuit device 13 is the first working state, it sends a data retransmission notification to the data retransmission module 132. The data retransmission module 132 determines the retransmission data according to the data retransmission notification, and sends the retransmission data to the slave 12. The retransmission data is data pre-set according to the type of the slave 12. For example, if the slave device 12 is a power management chip, the retransmitted data is voltage or current data.

[0041] In the embodiment of the present application, the integrated circuit device 13 monitors the communication data between the host 11 and the slave 12 on the SPMI bus. When it is determined that the working state of the integrated circuit device 13 is the second working state according to the monitored communication data, the host 11 and the slave 12 can communicate directly by switching the first switch 141 and the second switch 142 to the second channel, thereby ensuring the interaction of original data between the host 11 and the slave 12; when it is determined that the working state of the integrated circuit device 13 is the first working state according to the monitored communication data, the retransmission data is determined and sent to the slave 12, thereby realizing the control of the data of the slave 12 by the integrated circuit device 13.

[0042] refer to Figure 7 FIG. 1 is a flow chart of a bus monitoring and control method in an embodiment of the present application. The bus monitoring and control method is applied to an integrated circuit device 13. The method specifically includes the following steps.

[0043] Step S701, pre-set a predetermined instruction.

[0044] In one embodiment of the present application, the bus monitoring module 131 pre-sets a predetermined instruction. For example, the predetermined instruction may be at least one of an instruction for the host 11 to read the slave 12, an instruction for the host 11 to write to the slave 12, and an instruction for the slave 12 to write to the host 11. The above is only an example and is not limited to this in actual applications. For example, the predetermined instruction may be an instruction for the host 11 with a source address of 0001 to write a value of "01" to the slave 12 with a destination address of 1111.

[0045] Step S702, monitoring the communication data on the SPMI bus and determining whether the working state of the integrated circuit device 13 is the first working state.

[0046] In one embodiment of the present application, the bus monitoring module 131 monitors the communication data on the SPMI bus, such as the communication data sent by the host 11 to the slave 12, and determines whether the communication data includes a predetermined instruction. If it is determined that the communication data does not include a predetermined instruction, the bus monitoring module 131 determines that the integrated circuit device 13 is in the second working state and executes step S703. If it is determined that the communication data includes a predetermined instruction, the monitoring module 133 determines that the integrated circuit device 13 is in the first working state and executes step S704. When the bus monitoring module 131 determines that the communication data includes a predetermined instruction, it continues to monitor the SPMI bus to ensure that the subsequent data retransmission module 132 successfully seizes the bus.

[0047] Step S703 , controlling the host to send the communication data directly to the slave 12 .

[0048] In one embodiment of the present application, when the integrated circuit device 13 operates in the second operating state, the switch control module 133 controls the first switch 141 and the second switch 142 to switch to the second channel. In this way, the host 11 establishes a communication channel with the slave 12 through the first switch 141 and the second switch 142, and transmits the communication data directly to the slave through the first switch 141 and the second switch 142.

[0049] Step S704, determining resending data according to the communication data.

[0050] In one embodiment of the present application, when the bus monitoring module 131 determines that the working state of the integrated circuit device 13 is the first working state according to the predetermined instruction in the communication data, the data retransmission notification is sent to the data retransmission module 132. The data retransmission module 132 determines the retransmission data according to the data retransmission notification. The retransmission data is data pre-set according to the type of the slave 12. For example, if the slave 12 is a power management chip, the retransmission data is voltage or current data.

[0051] Step S705, monitoring whether the SPMI bus is in an idle state.

[0052] In one embodiment of the present application, if the bus monitoring module 131 monitors that the clock signal line and the data signal line of the SPMI bus are both in a high-impedance state, it is determined that the SPMI bus is in an idle state. If the SPMI bus is in an idle state, steps S706 and S707 can be executed synchronously. In one embodiment of the present application, synchronous execution means execution at the same time point. If the SPMI bus is not in an idle state, step S705 is repeated until the SPMI bus is monitored to enter an idle state.

[0053] Step S706, performing bus arbitration on the host simulating the slave.

[0054] refer to Figure 8 As shown, it is a schematic diagram of the connection between the integrated circuit device and the host and the slave in another embodiment of the present application. The upper port of the integrated circuit device 13 is connected to the host 11 through the SPMI bus, and the lower port of the integrated circuit device 13 is connected to the slave 11 through the SPMI bus. The data reissue module 132 simulates the bus arbitration of the slave 12 for the host 11 by pulling up the data signal line of the SPMI bus connected to the upper port. Pulling up the data signal line of the SPMI bus connected to the upper port represents setting the data signal line of the SPMI bus connected to the upper port to a high potential, such as a potential above 1.5V. The data reissue module 132 simulates the bus arbitration of the slave 12 for the host 11, which can ensure that the integrated circuit device 13 will not be interfered by the bus operation of the host 11 when performing data reissue.

[0055] Step S707, performing bus arbitration on the slave simulating the master.

[0056] In one embodiment of the present application, the data retransmission module 132 simulates the host 11 to perform bus arbitration on the slave 12 by pulling up the data signal line of the SPMI bus connected to the lower port. Pulling up the data signal line of the SPMI bus connected to the lower port indicates that the data signal line of the SPMI bus connected to the lower port is set to a high potential.

[0057] Step S708, controlling the integrated circuit device to be connected to the host and the slave respectively.

[0058] In one embodiment of the present application, the switch control module 133 controls the first switch 141 and the second switch 142 to switch to the first channel, so that the integrated circuit device 13 establishes a communication channel with the host 11 and the slave 12 through the first switch 141 and the second switch 142. After step S708 is executed, the process continues to execute steps S709 and S713.

[0059] Step S709, determining whether the SPMI bus instruction cycle of the slave performing bus arbitration has reached the stage where the slave preempts the SPMI bus with the highest priority.

[0060] In one embodiment of the present application, if the SPMI bus instruction cycle for bus arbitration of the slave machine reaches the stage where the slave machine preempts the SPMI bus with the highest priority, step S710 is executed; if the SPMI bus instruction cycle for bus arbitration of the slave machine has not reached the stage where the slave machine preempts the SPMI bus with the highest priority, step S709 is repeated until the stage where the slave machine preempts the SPMI bus with the highest priority is reached, and the process executes step S710.

[0061] Step S710, when the slave occupies the SPMI bus with the highest priority, the slave sends a preset slave address to the host.

[0062] In one embodiment of the present application, the preset slave address is different from the addresses of all slaves 12 connected to the integrated circuit device 13. For example, the addresses of all slaves 12 connected to the SPMI bus include Address0 to Address15, and the data retransmission module 132 sends a preset slave address Address16 that is different from Address0 to Address15 to the host 11.

[0063] Step S711, determining whether the SPMI bus instruction cycle of the slave performing bus arbitration has reached the frame sequence stage.

[0064] In one embodiment of the present application, if the SPMI bus instruction cycle for bus arbitration of the slave machine reaches the frame sequence stage, step S712 is executed; if the SPMI bus instruction cycle for bus arbitration of the slave machine does not reach the frame sequence stage, step S712 is repeated until the frame sequence stage arrives.

[0065] Step S712, writing preset data to a host with a preset host address.

[0066] In one embodiment of the present application, the data re-issuing module 132 writes preset data, such as 00, to the register of the host having the preset host address through the master write instruction. In one embodiment of the present application, the preset host address is different from the addresses of all hosts 12 connected to the integrated circuit device 13. For example, the addresses of all hosts 12 connected to the SPMI bus include address0 to address3, and the data re-issuing module 132 writes preset data to the host 11 having the preset host address address4 which is different from address0 to address3.

[0067] Step S713, determining whether the SPMI bus instruction cycle of the host performing bus arbitration has reached the stage where the host preempts the SPMI bus with the highest priority.

[0068] In one embodiment of the present application, if the SPMI bus instruction cycle of the host performing bus arbitration reaches the stage where the host preempts the SPMI bus with the highest priority, step S714 is executed; if the SPMI bus instruction cycle of the host performing bus arbitration has not reached the stage where the host preempts the SPMI bus with the highest priority, step S713 is repeated until the stage where the host preempts the SPMI bus with the highest priority is reached.

[0069] Step S714, when the host preempts the SPMI bus with the highest priority, the retransmitted data is sent to the slave.

[0070] In one embodiment of the present application, the data retransmission module 132 sends the retransmission data to any one or more slaves 12 connected to the SPMI bus. In one embodiment of the present application, the data retransmission module 132 writes the retransmission data value to the target slave through an externalregister write instruction.

[0071] In one embodiment of the present application, after the retransmission data is sent to the target slave, the switch control module 133 controls the first switch 141 and the second switch 142 to switch from the first channel to the second channel, so that the host 11 re-establishes a communication channel with the slave 12 through the first switch 141 and the second switch 142, and transmits the communication data directly to the slave 12 through the first switch 141 and the second switch 142.

[0072] In order to maintain the stable operation of the SPMI bus when the integrated circuit device 13 switches between the first working state and the second working state, the integrated circuit device 13 in the embodiment of the present application first detects whether the SPMI bus is idle when it detects that data retransmission is required (i.e., the working state of the integrated circuit device 13 is the first working state). When the SPMI bus is idle, the integrated circuit device 13 first simulates the slave to pull up the data signal line to initiate bus arbitration for the host, and simulates the host to pull up the integrated circuit device 13 to initiate bus arbitration for the slave. After both sides are pulled up, the first switch 141 and the second switch 142 are switched to the first channel. This can prevent the first switch 141 and the second switch 142 from generating glitches during the switching process that affect the correct operation of the SPMI bus, and at the same time ensure that there will be no abnormalities caused by other hosts or slaves performing bus preemption at the same time when the first switch 141 and the second switch 142 are switched. During the process of the integrated circuit device 13 retransmitting data to the slave, the host is preempted with the highest priority to ensure that no host performs bus operations during the data retransmission period.

[0073] In an embodiment of the present application, the integrated circuit device 13 monitors the communication data of the SPMI bus, and after detecting that there is a predetermined instruction in the communication data and the SPMI bus is idle, the integrated circuit device 13 first simulates the host to pull up the data signal line of the slave to initiate bus arbitration, simulates the host to pull up the integrated circuit device 13 to initiate bus arbitration, and writes the re-sent data value into the target slave, thereby realizing the external integrated circuit device 13 to transmit the data of the slave 12 stably.

[0074] In one embodiment of the present application, when the integrated circuit device 13 works in the first working state, the integrated circuit device 13 can accurately identify the current state of the SPMI bus, thereby ensuring that the SPMI can pull up the data signal line with the highest priority at the rising edge of the clock signal line of the host 11 to seize the bus. When the integrated circuit device 13 works in the second working state, the integrated circuit device 13 can identify and store the communication data between the host and the slave, and identify whether the communication data contains a predetermined instruction that requires data retransmission.

[0075] refer to Fig. 9FIG. 1 is a flow chart of a method for monitoring an SPMI bus in an embodiment of the present application. The method for monitoring an SPMI bus is applied in the bus arbitration phase of an SPMI bus instruction cycle. The method comprises the following steps.

[0076] Step S901, monitoring the bus start condition.

[0077] In one embodiment of the present application, if it is detected that the data signal line of the SPMI bus is pulled high and the clock signal line is kept at a low level, it is determined that the bus start condition is detected.

[0078] Step S902, monitoring the status of the BUS Park of the SPMI bus.

[0079] In one implementation of the present application, BUS Park represents a bus stop period.

[0080] Step S903, monitoring whether the slave machine preempts the SPMI bus with the secondary priority. If the slave machine preempts the SPMI bus with the secondary priority, executing step S904, if the slave machine does not preempt the SPMI bus with the secondary priority, executing step S905.

[0081] Step S904, executing a bus connection sequence.

[0082] In one embodiment of the present application, the bus connection sequence represents that other hosts 11 access the SPMI bus.

[0083] Step S905, monitoring whether the slave machine preempts the SPMI bus with the highest priority. If the slave machine preempts the SPMI bus with the highest priority, executing step S906; if the slave machine does not preempt the SPMI bus with the highest priority, executing step S907.

[0084] Step S906, identifying the slave address sent by the slave. After step S906 is executed, the process goes to step S917.

[0085] Step S907, monitoring whether the host preempts the SPMI bus with the highest priority. If the host does not preempt the SPMI bus with the highest priority, execute step S908, if the host preempts the SPMI bus with the highest priority, execute step S917.

[0086] Step S908, monitoring whether the host preempts the SPMI bus with the first priority. If the host does not preempt the SPMI bus with the first priority, execute step S909, if the host preempts the SPMI bus with the first priority, execute step S917. The priority level of the first priority is lower than the priority level of the highest priority.

[0087] Step S909, monitoring whether the host preempts the SPMI bus with the second priority. If the host does not preempt the SPMI bus with the second priority, execute step S910, if the host preempts the SPMI bus with the second priority, execute step S917. The priority level of the second priority is lower than the priority level of the first priority.

[0088] Step S910, monitoring whether the host preempts the SPMI bus with the third priority. If the host does not preempt the SPMI bus with the third priority, execute step S911, if the host preempts the SPMI bus with the third priority, execute step S917. The priority level of the third priority is lower than the priority level of the second priority.

[0089] Step S911, monitor whether the slave machine preempts the SPMI bus with the second-second priority; if the slave machine preempts the SPMI bus with the second-second priority, execute step S906; if the slave machine does not preempt the SPMI bus with the second-second priority, execute step S912.

[0090] Step S912, monitoring whether the host preempts the SPMI bus with the highest priority. If the host does not preempt the SPMI bus with the highest priority, execute step S913, if the host preempts the SPMI bus with the highest priority, execute step S917.

[0091] Step S913, monitoring whether the host preempts the SPMI bus with the first priority. If the host does not preempt the SPMI bus with the first priority, execute step S914, if the host preempts the SPMI bus with the first priority, execute step S917.

[0092] Step S914, monitoring whether the host preempts the SPMI bus with the second priority. If the host does not preempt the SPMI bus with the second priority, executing step S915, if the host preempts the SPMI bus with the second priority, executing step S917.

[0093] Step S915, monitoring whether the host preempts the SPMI bus with the third priority. If the host does not preempt the SPMI bus with the third priority, executing step S916, if the host preempts the SPMI bus with the third priority, executing step S917.

[0094] Step S916: Determine that no device has seized the SPMI bus, and the SPMI bus enters an idle state.

[0095] Step S917: the bus arbitration phase ends, and the SPMI bus enters the SSC phase.

[0096] In an embodiment of the present application, the integrated circuit device 13 adopts a sampling method triggered by the falling edge of the clock to monitor and identify the stage of the SPMI bus instruction cycle in which the SPMI bus is currently located, so that the delay in sending the monitoring result and the communication data of the host is within a preset time range, for example, within 5ns.

[0097] refer to Fig.10 FIG. 2 is a flow chart of a bus monitoring and control method in another embodiment of the present application. The method comprises the following steps.

[0098] Step S1001, monitoring the communication data between the host and the slave in the SPMI bus.

[0099] In one embodiment of the present application, the specific implementation steps of step S1001 are as follows: Figure 7 The step S702 is not described again here.

[0100] Step S1002: if it is determined according to the communication data that the working state of the integrated circuit device is the first working state, the retransmission data is sent to the slave device.

[0101] In one embodiment of the present application, if it is monitored that the SPMI bus is in an idle state, the host 11 simulates the slave 12 to perform bus arbitration, and the slave 12 simulates the host 11 to perform bus arbitration; the control switch module 14 is switched so that the integrated circuit device 13 is connected to the host 11 and the slave 12 respectively; when it is determined that the host 11 preempts the SPMI bus with the highest priority, the re-sent data is sent to the slave 12, thereby realizing the control of the external integrated circuit device 13 over the data of the slave 12.

[0102] refer to Fig.11, which is a schematic diagram of the hardware structure of the electronic device 100 in an embodiment of the present application. The electronic device 100 may include a processor 110, an integrated circuit device 13, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0103] It is to be understood that the structure illustrated in the embodiment of the present invention does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown in the figure, or combine some components, or separate some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0104] The processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0105] The controller can generate operation control signals according to the instruction operation code and timing signal to complete the control of instruction fetching and execution.

[0106] The processor 110 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may store instructions or data that the processor 110 has just used or cyclically used. If the processor 110 needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0107] In some embodiments, the processor 110 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0108] The I2C interface is a bidirectional synchronous serial bus, including a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the processor 110 may include multiple groups of I2C buses. The processor 110 may be coupled to the touch sensor 180K, the charger, the flash, the camera 193, etc. through different I2C bus interfaces. For example: the processor 110 may be coupled to the touch sensor 180K through the I2C interface, so that the processor 110 communicates with the touch sensor 180K through the I2C bus interface, thereby realizing the touch function of the electronic device 100.

[0109] The I2S interface can be used for audio communication. In some embodiments, the processor 110 can include multiple I2S buses. The processor 110 can be coupled to the audio module 170 via the I2S bus to achieve communication between the processor 110 and the audio module 170. In some embodiments, the audio module 170 can transmit an audio signal to the wireless communication module 160 via the I2S interface to achieve the function of answering a call through a Bluetooth headset.

[0110] The PCM interface can also be used for audio communication, sampling, quantizing and encoding analog signals. In some embodiments, the audio module 170 and the wireless communication module 160 can be coupled via a PCM bus interface. In some embodiments, the audio module 170 can also transmit audio signals to the wireless communication module 160 via the PCM interface to realize the function of answering calls via a Bluetooth headset. Both the I2S interface and the PCM interface can be used for audio communication.

[0111] The UART interface is a universal serial data bus for asynchronous communication. The bus can be a bidirectional communication bus. It converts the data to be transmitted between serial communication and parallel communication. In some embodiments, the UART interface is generally used to connect the processor 110 and the wireless communication module 160. For example, the processor 110 communicates with the Bluetooth module in the wireless communication module 160 through the UART interface to implement the Bluetooth function. In some embodiments, the audio module 170 can transmit an audio signal to the wireless communication module 160 through the UART interface to implement the function of playing music through a Bluetooth headset.

[0112] The MIPI interface can be used to connect the processor 110 with peripheral devices such as the display screen 194 and the camera 193. The MIPI interface includes a camera serial interface (CSI), a display serial interface (DSI), etc. In some embodiments, the processor 110 and the camera 193 communicate via the CSI interface to implement the shooting function of the electronic device 100. The processor 110 and the display screen 194 communicate via the DSI interface to implement the display function of the electronic device 100.

[0113] The GPIO interface can be configured by software. The GPIO interface can be configured as a control signal or as a data signal. In some embodiments, the GPIO interface can be used to connect the processor 110 with the camera 193, the display 194, the wireless communication module 160, the audio module 170, the sensor module 180, etc. The GPIO interface can also be configured as an I2C interface, an I2S interface, a UART interface, a MIPI interface, etc.

[0114] The USB interface 130 is an interface that complies with the USB standard specification, and can be a Mini USB interface, a Micro USB interface, a USB Type C interface, etc. The USB interface 130 can be used to connect a charger to charge the electronic device 100, and can also be used to transfer data between the electronic device 100 and a peripheral device. It can also be used to connect headphones to play audio through the headphones. The interface can also be used to connect other electronic devices 100, such as AR devices, etc.

[0115] It is understandable that the interface connection relationship between the modules illustrated in the embodiment of the present invention is only a schematic illustration and does not constitute a structural limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0116] The charging management module 140 is used to receive charging input from a charger. The charger may be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 may receive charging input from a wired charger through the USB interface 130. In some wireless charging embodiments, the charging management module 140 may receive wireless charging input through a wireless charging coil of the electronic device 100. While the charging management module 140 is charging the battery 142, it may also power the electronic device 100 through the power management module 141.

[0117] The power management module 141 is used to connect the battery 142, the charging management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and supplies power to the processor 110, the internal memory 121, the display screen 194, the camera 193, and the wireless communication module 160. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle number, battery health status (leakage, impedance), etc. In some other embodiments, the power management module 141 can also be set in the processor 110. In other embodiments, the power management module 141 and the charging management module 140 can also be set in the same device.

[0118] The wireless communication function of the electronic device 100 can be implemented through the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor and the baseband processor.

[0119] Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve the utilization of antennas. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In some other embodiments, the antenna can be used in combination with a tuning switch.

[0120] The mobile communication module 150 can provide solutions for wireless communications including 2G / 3G / 4G / 5G, etc., applied to the electronic device 100. The mobile communication module 150 may include at least one filter, a switch, a power amplifier, a low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves from the antenna 1, and filter, amplify, and process the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves for radiation through the antenna 1. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the same device as at least some of the modules of the processor 110.

[0121] The modem processor may include a modulator and a demodulator. Among them, the modulator is used to modulate the low-frequency baseband signal to be sent into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After the low-frequency baseband signal is processed by the baseband processor, it is passed to the application processor. The application processor outputs a sound signal through an audio device (not limited to a speaker 170A, a receiver 170B, etc.), or displays an image or video through a display screen 194. In some embodiments, the modem processor may be an independent device. In other embodiments, the modem processor may be independent of the processor 110 and be set in the same device as the mobile communication module 150 or other functional modules.

[0122] The wireless communication module 160 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc., which are applied to the electronic device 100. The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, modulates the frequency of the electromagnetic wave signal and performs filtering, and sends the processed signal to the processor 110. The wireless communication module 160 can also receive the signal to be sent from the processor 110, modulate the frequency of it, amplify it, and convert it into electromagnetic waves for radiation through the antenna 2.

[0123] In some embodiments, the antenna 1 of the electronic device 100 is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the electronic device 100 can communicate with the network and other devices through wireless communication technology. The wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technology. The GNSS may include a global positioning system (GPS), a global navigation satellite system (GLONASS), a Beidou navigation satellite system (BDS), a quasi-zenith satellite system (QZSS) and / or a satellite based augmentation system (SBAS).

[0124] The electronic device 100 implements the display function through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, which connects the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

[0125] The display screen 194 is used to display images, videos, etc. The display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode or an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), Miniled, MicroLed, Micro-oLed, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the electronic device 100 may include 1 or N display screens 194, where N is a positive integer greater than 1.

[0126] The electronic device 100 can realize the shooting function through ISP, camera 193, video codec, GPU, display screen 194 and application processor.

[0127] ISP is used to process the data fed back by camera 193. For example, when taking a photo, the shutter is opened, and the light is transmitted to the camera photosensitive element through the lens. The light signal is converted into an electrical signal, and the camera photosensitive element transmits the electrical signal to ISP for processing and converts it into an image visible to the naked eye. ISP can also perform algorithm optimization on the noise, brightness, and skin color of the image. ISP can also optimize the exposure, color temperature and other parameters of the shooting scene. In some embodiments, ISP can be set in camera 193.

[0128] The camera 193 is used to capture still images or videos. The object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, and then passes the electrical signal to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV or other format. In some embodiments, the electronic device 100 may include 1 or N cameras 193, where N is a positive integer greater than 1.

[0129] The digital signal processor is used to process digital signals, and can process not only digital image signals but also other digital signals. For example, when the electronic device 100 is selecting a frequency point, the digital signal processor is used to perform Fourier transform on the frequency point energy.

[0130] Video codecs are used to compress or decompress digital videos. The electronic device 100 may support one or more video codecs. Thus, the electronic device 100 may play or record videos in a variety of coding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

[0131] NPU is a neural network (NN) computing processor. By drawing on the structure of biological neural networks, such as the transmission mode between neurons in the human brain, it can quickly process input information and can also continuously self-learn. Through NPU, applications such as intelligent cognition of electronic device 100 can be realized, such as image recognition, face recognition, voice recognition, text understanding, etc.

[0132] The internal memory 121 may include one or more random access memories (RAM) and one or more non-volatile memories (NVM).

[0133] Random access memory may include static random-access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM, for example, the fifth generation DDR SDRAM is generally referred to as DDR5 SDRAM), etc.; non-volatile memory may include disk storage devices and flash memory.

[0134] Flash memory can be divided into NOR FLASH, NAND FLASH, 3D NAND FLASH, etc. according to the operating principle; single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), etc. according to the storage unit potential level; universal flash storage (UFS), embedded multi media card (eMMC), etc. according to the storage specification.

[0135] The random access memory can be directly read and written by the processor 110, and can be used to store executable programs (such as machine instructions) of the operating system or other running programs, and can also be used to store user and application data, etc.

[0136] The non-volatile memory may also store executable programs and user and application data, etc., and may be loaded into the random access memory in advance for direct reading and writing by the processor 110 .

[0137] The external memory interface 120 can be used to connect to an external non-volatile memory to expand the storage capacity of the electronic device 100. The external non-volatile memory communicates with the processor 110 through the external memory interface 120 to implement a data storage function. For example, files such as music and videos are stored in the external non-volatile memory.

[0138] The internal memory 121 or the external memory interface 120 is used to store one or more computer programs. The one or more computer programs are configured to be executed by the processor 110. The one or more computer programs include multiple instructions. When the multiple instructions are executed by the processor 110, the bus monitoring and control method executed on the electronic device 100 in the above embodiment can be implemented to implement the bus monitoring and control function of the electronic device 100.

[0139] The electronic device 100 can implement audio functions such as music playing and recording through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone jack 170D, and the application processor.

[0140] The audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. The audio module 170 can also be used to encode and decode audio signals. In some embodiments, the audio module 170 can be arranged in the processor 110, or some functional modules of the audio module 170 can be arranged in the processor 110.

[0141] The speaker 170A, also called a "speaker", is used to convert an audio electrical signal into a sound signal. The electronic device 100 can listen to music or listen to a hands-free call through the speaker 170A.

[0142] The receiver 170B, also called a "earpiece", is used to convert audio electrical signals into sound signals. When the electronic device 100 receives a call or voice message, the voice can be received by placing the receiver 170B close to the human ear.

[0143] Microphone 170C, also called "microphone" or "microphone", is used to convert sound signals into electrical signals. When making a call or sending a voice message, the user can speak by putting their mouth close to microphone 170C to input the sound signal into microphone 170C. The electronic device 100 can be provided with at least one microphone 170C. In other embodiments, the electronic device 100 can be provided with two microphones 170C, which can not only collect sound signals but also realize noise reduction function. In other embodiments, the electronic device 100 can also be provided with three, four or more microphones 170C to collect sound signals, reduce noise, identify the sound source, realize directional recording function, etc.

[0144] The earphone interface 170D is used to connect a wired earphone and can be a USB interface 130 or a 3.5 mm open mobile terminal platform (OMTP) standard interface or a cellular telecommunications industry association of the USA (CTIA) standard interface.

[0145] The pressure sensor 180A is used to sense the pressure signal and can convert the pressure signal into an electrical signal. In some embodiments, the pressure sensor 180A can be set on the display screen 194. There are many types of pressure sensors 180A, such as resistive pressure sensors, inductive pressure sensors, capacitive pressure sensors, etc. The capacitive pressure sensor can be a parallel plate including at least two conductive materials. When a force acts on the pressure sensor 180A, the capacitance between the electrodes changes. The electronic device 100 determines the intensity of the pressure according to the change in capacitance. When a touch operation acts on the display screen 194, the electronic device 100 detects the touch operation intensity according to the pressure sensor 180A. The electronic device 100 can also calculate the touch position according to the detection signal of the pressure sensor 180A. In some embodiments, touch operations acting on the same touch position but with different touch operation intensities can correspond to different operation instructions. For example: when a touch operation with a touch operation intensity less than the first pressure threshold acts on the short message application icon, an instruction to view the short message is executed. When a touch operation with a touch operation intensity greater than or equal to the first pressure threshold acts on the short message application icon, an instruction to create a new short message is executed.

[0146] The gyro sensor 180B can be used to determine the motion posture of the electronic device 100. In some embodiments, the angular velocity of the electronic device 100 around three axes (i.e., x, y, and z axes) can be determined by the gyro sensor 180B. The gyro sensor 180B can be used for anti-shake shooting. For example, when the shutter is pressed, the gyro sensor 180B detects the angle of the electronic device 100 shaking, calculates the distance that the lens module needs to compensate based on the angle, and allows the lens to offset the shaking of the electronic device 100 through reverse movement to achieve anti-shake. The gyro sensor 180B can also be used for navigation and somatosensory game scenes.

[0147] The pressure sensor 180C is used to measure air pressure. In some embodiments, the electronic device 100 calculates the altitude through the air pressure value measured by the pressure sensor 180C to assist positioning and navigation. The magnetic sensor 180D includes a Hall sensor. The electronic device 100 can use the magnetic sensor 180D to detect the opening and closing of the flip leather case. In some embodiments, when the electronic device 100 is a flip phone, the electronic device 100 can detect the opening and closing of the flip cover according to the magnetic sensor 180D. Then, according to the detected opening and closing state of the leather case or the opening and closing state of the flip cover, the characteristics such as automatic unlocking of the flip cover are set. The acceleration sensor 180E can detect the magnitude of the acceleration of the electronic device 100 in all directions (generally three axes). When the electronic device 100 is stationary, the magnitude and direction of gravity can be detected. It can also be used to identify the posture of the electronic device 100, and is applied to horizontal and vertical screen switching, pedometers and other applications. Distance sensor 180F, used to measure distance. The electronic device 100 can measure distance through infrared or laser. In some embodiments, when photographing a scene, the electronic device 100 may utilize the distance sensor 180F to measure distance to achieve fast focusing.

[0148] The proximity light sensor 180G may include, for example, a light emitting diode (LED) and a light detector, such as a photodiode. The light emitting diode may be an infrared light emitting diode. The electronic device 100 emits infrared light outward through the light emitting diode. The electronic device 100 uses a photodiode to detect infrared reflected light from nearby objects. When sufficient reflected light is detected, it can be determined that there is an object near the electronic device 100. When insufficient reflected light is detected, the electronic device 100 can determine that there is no object near the electronic device 100. The electronic device 100 can use the proximity light sensor 180G to detect that the user holds the electronic device 100 close to the ear to talk, so as to automatically turn off the screen to save power. The proximity light sensor 180G can also be used in leather case mode and pocket mode to automatically unlock and lock the screen.

[0149] The ambient light sensor 180L is used to sense the ambient light brightness. The electronic device 100 can adaptively adjust the brightness of the display screen 194 according to the perceived ambient light brightness. The ambient light sensor 180L can also be used to automatically adjust the white balance when taking pictures. The ambient light sensor 180L can also cooperate with the proximity light sensor 180G to detect whether the electronic device 100 is in a pocket to prevent accidental touches.

[0150] The fingerprint sensor 180H is used to collect fingerprints. The electronic device 100 can use the collected fingerprint characteristics to implement fingerprint unlocking, access application locks, fingerprint photography, fingerprint call answering, etc.

[0151] The temperature sensor 180J is used to detect temperature. In some embodiments, the electronic device 100 uses the temperature detected by the temperature sensor 180J to execute a temperature processing strategy. For example, when the temperature reported by the temperature sensor 180J exceeds a threshold, the electronic device 100 reduces the performance of a processor located near the temperature sensor 180J to reduce power consumption and implement thermal protection. In other embodiments, when the temperature is lower than another threshold, the electronic device 100 heats the battery 142 to avoid abnormal shutdown of the electronic device 100 due to low temperature. In other embodiments, when the temperature is lower than another threshold, the electronic device 100 performs a boost on the output voltage of the battery 142 to avoid abnormal shutdown caused by low temperature.

[0152] The touch sensor 180K is also called a "touch control device". The touch sensor 180K can be set on the display screen 194. The touch sensor 180K and the display screen 194 form a touch screen, also called a "touch control screen". The touch sensor 180K is used to detect touch operations acting on or near it. The touch sensor can pass the detected touch operation to the application processor to determine the type of touch event. Visual output related to the touch operation can be provided through the display screen 194. In other embodiments, the touch sensor 180K can also be set on the surface of the electronic device 100, which is different from the position of the display screen 194.

[0153] The bone conduction sensor 180M can obtain a vibration signal. In some embodiments, the bone conduction sensor 180M can obtain a vibration signal of a vibrating bone block of the vocal part of the human body. The bone conduction sensor 180M can also contact the human pulse to receive a blood pressure beat signal. In some embodiments, the bone conduction sensor 180M can also be set in an earphone and combined into a bone conduction earphone. The audio module 170 can parse out a voice signal based on the vibration signal of the vibrating bone block of the vocal part obtained by the bone conduction sensor 180M to realize a voice function. The application processor can parse the heart rate information based on the blood pressure beat signal obtained by the bone conduction sensor 180M to realize a heart rate detection function.

[0154] The key 190 includes a power key, a volume key, etc. The key 190 may be a mechanical key or a touch key. The electronic device 100 may receive key input and generate key signal input related to user settings and function control of the electronic device 100.

[0155] Motor 191 can generate vibration prompts. Motor 191 can be used for incoming call vibration prompts, and can also be used for touch vibration feedback. For example, touch operations acting on different applications (such as taking pictures, audio playback, etc.) can correspond to different vibration feedback effects. For touch operations acting on different areas of the display screen 194, motor 191 can also correspond to different vibration feedback effects. Different application scenarios (for example: time reminders, receiving messages, alarm clocks, games, etc.) can also correspond to different vibration feedback effects. The touch vibration feedback effect can also support customization.

[0156] The indicator 192 may be an indicator light, which may be used to indicate the charging status, power changes, messages, missed calls, notifications, etc.

[0157] The SIM card interface 195 is used to connect a SIM card. The SIM card can be connected to and separated from the electronic device 100 by inserting it into the SIM card interface 195 or pulling it out from the SIM card interface 195. The electronic device 100 can support 1 or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 195 can support Nano SIM cards, Micro SIM cards, SIM cards, and the like. Multiple cards can be inserted into the same SIM card interface 195 at the same time. The types of the multiple cards can be the same or different. The SIM card interface 195 can also be compatible with different types of SIM cards. The SIM card interface 195 can also be compatible with external memory cards. The electronic device 100 interacts with the network through the SIM card to implement functions such as calls and data communications. In some embodiments, the electronic device 100 uses an eSIM, i.e., an embedded SIM card. The eSIM card can be embedded in the electronic device 100.

[0158] This embodiment also provides a computer program product. When the computer program product is run on a computer, the computer is enabled to execute the above-mentioned related steps to implement the bus monitoring and control method in the above-mentioned embodiment.

[0159] In addition, some embodiments of the present application also provide a device, which may specifically be a chip, component or module, and the device may include a connected processor and memory; wherein the memory is used to store computer-executable instructions, and when the device is running, the processor may execute the computer-executable instructions stored in the memory so that the chip executes the bus monitoring and control methods in the above-mentioned method embodiments.

[0160] Among them, the electronic device, computer storage medium, computer program product or chip provided in this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above and will not be repeated here.

[0161] Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0162] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0163] The unit described as a separate component may or may not be physically separated, and the component displayed as a unit may be a physical unit or multiple physical units, that is, it may be located in one place, or it may be distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, each functional unit in each embodiment of the present application may be integrated in a processing unit, or each unit may exist physically separately, or two or more units may be integrated in one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0164] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of some embodiments of the present application are essentially or partly contributed to the prior art or all or part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to perform all or part of the steps of the methods of each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), disk or optical disk and other media that can store program codes.

[0165] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of some embodiments of the present application and are not limiting. Although some embodiments of the present application are described in detail with reference to the preferred embodiments, ordinary technicians in this field should understand that the technical solutions of some implementation examples of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of some embodiments of the present application.

Claims

1. A control method, applied to an integrated circuit device, characterized in that: The integrated circuit device is connected to a first device, and the first device, the integrated circuit device, and the second device are respectively connected to a switch module via a bus. The method includes: monitoring communication data between the first device and the second device in the bus; If it is determined according to the communication data that the working state of the integrated circuit device is the first working state, sending the preset reissued data to the second device; Wherein, sending the preset reissued data to the second device comprises: confirming that the bus is in an idle state; Controlling the switch module to switch so that the integrated circuit device is connected to the first device and the second device respectively; Simulating the second device to perform bus arbitration on the first device, and simulating the first device to perform bus arbitration on the second device; When it is determined that the first device preempts the bus with the highest priority, the retransmission data is sent to the second device.

2. The control method according to claim 1, characterized in that: The method further comprises: If it is determined according to the communication data that the working state of the integrated circuit device is the second working state, the switch module is controlled to switch so that the first device is connected to the second device.

3. The control method according to claim 2, characterized in that: Determining the working state of the integrated circuit device according to the communication data comprises: If it is determined that the communication data includes a predetermined instruction, determining that the working state of the integrated circuit device is the first working state; or If it is determined that the communication data does not include a predetermined instruction, the operating state of the integrated circuit device is determined to be the second operating state.

4. The control method according to claim 1, characterized in that: The step of simulating the second device to perform bus arbitration on the first device and simulating the first device to perform bus arbitration on the second device comprises: By pulling up a data signal line of a bus connected to an upper port of the integrated circuit device, bus arbitration is performed on the first device simulating the second device, wherein the upper port is connected to the first device through the bus, and pulling up the data signal line of the bus connected to the upper port of the integrated circuit device represents setting the data signal line of the bus connected to the upper port to a high potential; By pulling up the data signal line of the bus connected to the lower port of the integrated circuit device, bus arbitration is simulated for the second device to simulate the first device, wherein the lower port is connected to the second device through the bus, and pulling up the data signal line of the bus connected to the lower port of the integrated circuit device represents setting the data signal line of the bus connected to the lower port to a high potential.

5. The control method according to claim 1, characterized in that: The bus is a system power management interface SPMI bus.

6. The control method according to claim 5, characterized in that: When it is determined that the first device preempts the bus with the highest priority, sending the retransmitted data to the second device comprises: The reissued data value is written into the second device through an external register write instruction.

7. The control method according to claim 5, characterized in that: After simulating the second device to perform bus arbitration on the first device, the method further includes: If the SPMI bus instruction cycle in which the second device performs bus arbitration reaches the stage where the second device preempts the bus with the highest priority, a preset second device address is sent to the first device.

8. The control method according to claim 7, characterized in that: After sending the preset second device address to the first device, the method further includes: If the SPMI bus instruction cycle of the bus arbitration performed by the second device reaches the frame sequence stage, preset data is written to the first device having the preset first device address.

9. The control method according to claim 8, characterized in that: Writing preset data to a first device having a preset first device address comprises: The preset data is written into the register of the first device having the preset first device address through a master write instruction.

10. The control method according to claim 5, characterized in that: The confirming that the bus is in an idle state comprises: If it is monitored that the bus enters a bus stop cycle, it is confirmed that the bus is in the idle state.

11. The control method according to claim 1, characterized in that: The switch module includes a first switch and a second switch, the first switch is connected to the first device, the second switch is connected to the second device, the first channel of the first switch and the first channel of the second switch are connected to the integrated circuit device, and the second channel of the first switch is connected to the second channel of the second switch.

12. The control method according to claim 1, characterized in that: The reissued data is data determined according to the type of the second device.

13. The control method according to claim 1, characterized in that: The first device is a system on chip (SOC), and the second device is a power management chip (PMIC).

14. A chip, characterized in that: It includes a processor and a memory; wherein the processor is connected to the memory; The memory is used to store program instructions; The processor is used to read the program instructions stored in the memory to implement the control method according to any one of claims 1 to 13.

15. An electronic device, characterized in that: The electronic device includes a first device, a second device and an integrated circuit device, the integrated circuit device is connected to the first device, the first device, the integrated circuit device and the second device are respectively connected to a switch module via a bus, wherein the integrated circuit device is used to execute the control method as described in any one of claims 1 to 13.

16. A computer storage medium, characterized in that: The computer storage medium stores program instructions, and when the program instructions are executed on an electronic device, the electronic device executes the control method according to any one of claims 1 to 13.

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