Control method, electronic device, chip, and storage medium

Abstract

The application relates to a control method, an electronic device, a chip and a storage medium, and the method is applied to an integrated circuit device. The integrated circuit device listens to communication data between a first device and a second device in a bus; if it is determined according to the communication data that the working state of the integrated circuit device is a first working state and the bus is in an idle state, the first device is simulated as the second device to perform bus arbitration, the second device is simulated as the first device to perform bus arbitration, and a switch module is controlled to switch, so that the integrated circuit device is connected with the first device and the second device respectively; when it is determined that the first device occupies the bus with the highest priority, the second device is sent with the data to be re-sent. The integrated circuit device switches the switch module after the first device and the second device both perform bus arbitration, so that the glitch generated in the switching process of the switch module can be avoided to affect the operation of the SPMI bus, and the data control of the external integrated circuit device on the slave device is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of bus communication, and particularly relates to a control method, an electronic device, a chip and a storage medium. BACKGROUND

[0002] The existing system power management interface (SPMI) is a two-wire serial interface, which is usually used as a power management interface. The host and the slave can be connected through the SPMI interface. For example, the host can be a system-on-a-chip (SOC), and the slave can be a power management IC (PMIC). Through the SPMI bus, the processor performance level required by the given workload or application of the related device can be accurately monitored and controlled, and the power voltage can be dynamically controlled in real time according to the performance level. However, in the master-slave system based on the SPMI bus, the data needs to be controlled by the host, and the data in the master-slave system cannot be stably controlled by the external device. SUMMARY

[0003] In view of the above, it is necessary to provide a bus monitoring and control method, an electronic device, a chip and a storage medium to solve the problem that the data in the master-slave system based on the SPMI bus cannot be stably controlled by the external device.

[0004] In a first aspect, an embodiment of the present application provides a bus monitoring and control method applied to an integrated circuit device, the integrated circuit device being connected with a host, the host, the integrated circuit device and a slave being connected with a switch module through a system power management interface (SPMI) bus, the method comprising: monitoring communication data between the host and the slave in the SPMI bus; if it is determined according to the communication data that a working state of the integrated circuit device is a first working state, sending preset retransmission data to the slave; wherein the sending of the preset retransmission data to the slave comprises: if it is monitored that the SPMI bus is in an idle state, simulating the slave for bus arbitration of the host and simulating the host for bus arbitration of the slave; controlling the switch module to switch so that the integrated circuit device is connected with the host and the slave respectively; and when it is determined that the host occupies the SPMI bus with the highest priority, sending the retransmission data to the slave. The above technical solution, when the integrated circuit device is in the first working state, detects whether the SPMI bus is idle, and when the SPMI bus is idle, the integrated circuit device first simulates the slave for bus arbitration of the host and simulates the host for bus arbitration of the slave, and then switches the switch module when the host and the slave both perform bus arbitration, so as to avoid the glitch generated in the switching process of the switch module from affecting the correct operation of the SPMI bus, and at the same time, ensure that the switch module is not switched while other hosts or slaves perform bus occupation, so as to realize stable control of the data of the slave by the external integrated circuit device.

[0005] In an embodiment of the present application, the method further comprises: if it is determined according to the communication data that the working state of the integrated circuit device is a second working state, controlling the switch module to switch so that the host and the slave are connected. In the above solution, the host establishes a communication channel with the slave through the switch module, and directly transmits communication data to the slave through the switch module.

[0006] In an embodiment of the present application, determining the working state of the integrated circuit device according to the communication data comprises: if it is determined that the communication data includes a preset instruction, determining that the working state of the integrated circuit device is the first working state; or if it is determined that the communication data does not include a preset instruction, determining that the working state of the integrated circuit device is the second working state. In the above technical solution, the working state of the integrated circuit device can be determined according to the preset instruction included in the communication data.

[0007] In one embodiment of this application, the bus arbitration performed by the host simulating the slave and by the slave simulating the host includes: performing bus arbitration by pulling high the data signal line of the SPMI bus connected to the upper port of the integrated circuit device, wherein the upper port is connected to the host through the SPMI bus; and performing bus arbitration by pulling high the data signal line of the SPMI bus connected to the lower port of the integrated circuit device, wherein the lower port is connected to the slave through the SPMI bus. In the above technical solution, the integrated circuit device initiates bus arbitration by pulling high the data signal line of the host simulating the slave, and the integrated circuit device initiates bus arbitration by pulling high the data signal line of the slave simulating the host. After both sides are pulled high, the switch module is switched. This can avoid the glitches generated during the switch switching process affecting the operation of the SPMI bus.

[0008] In one embodiment of this application, sending the retransmission data to the slave device when it is determined that the master device preempts the SPMI bus with the highest priority includes: writing the retransmission data value to the slave device using an external register write instruction. In the above technical solution, the integrated circuit device can write retransmission data from a non-master device into the slave device using an external register write instruction.

[0009] In one embodiment of this application, after the host simulates the slave for bus arbitration, the method further includes: if the SPMI bus instruction cycle of the slave for bus arbitration reaches the stage where the slave preempts the SPMI bus with the highest priority, a preset slave address is sent to the host. In the above technical solution, when the host simulates the slave for bus arbitration, if the SPMI bus instruction cycle reaches the stage where the slave preempts the SPMI bus with the highest priority, a preset slave address is sent to the host to ensure the correct operation of the SPMI bus instruction cycle.

[0010] In one embodiment of this application, after sending a preset slave address to the host, the method further includes: if the SPMI bus instruction cycle for bus arbitration performed by the slave reaches the frame sequence stage, writing preset data to the host with the preset host address. In the above technical solution, when the host simulates the slave for bus arbitration, writing preset data to the host with the preset host address when the SPMI bus instruction cycle reaches the frame sequence stage further ensures the correct operation of the SPMI bus instruction cycle.

[0011] In one embodiment of this application, writing preset data to a host with a preset host address includes: writing preset data to a register of the host with the preset host address using a master write instruction. In the above technical solution, the integrated circuit device can transmit preset data to the host with the preset host address using the master write instruction.

[0012] In one embodiment of this application, the reissued data is data determined according to the type of the slave device.

[0013] Secondly, some embodiments of this application provide an electronic device, which includes a memory and a processor: wherein the memory is used to store program instructions; and the processor is used to read and execute the program instructions stored in the memory, and when the program instructions are executed by the processor, the electronic device performs the above-described bus monitoring and control method.

[0014] Thirdly, some embodiments of this application provide a chip including a processor and a memory; wherein the processor is connected to the memory; the memory is used to store program instructions; and the processor is used to read the program instructions stored in the memory to implement the above-described bus monitoring and control method.

[0015] Fourthly, some embodiments of this application provide a computer storage medium storing program instructions that, when executed on an electronic device, cause the electronic device to perform the aforementioned bus monitoring and control method.

[0016] Furthermore, the technical effects brought about by the second to fourth aspects can be found in the descriptions of the methods in the above-mentioned method section, and will not be repeated here. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the SPMI bus architecture in related technologies.

[0018] Figure 2 This is a schematic diagram of the instruction cycle of the SPMI bus in one embodiment of this application.

[0019] Figure 3 This is a schematic diagram of the SPMI bus architecture in one embodiment of this application.

[0020] Figure 4 This is a functional block diagram of an integrated circuit device in one embodiment of this application.

[0021] Figure 5 This is a schematic diagram showing the connection between an integrated circuit device and a host and slave device in one embodiment of this application.

[0022] Figure 6This is a schematic diagram showing the connection between the integrated circuit device and the host and slave devices in another embodiment of this application.

[0023] Figure 7 This is a flowchart of a bus monitoring and control method in one embodiment of this application.

[0024] Figure 8 This is a schematic diagram showing the connection between the integrated circuit device and the host and slave devices in another embodiment of this application.

[0025] Figure 9 This is a flowchart illustrating a method for monitoring the SPMI bus in one embodiment of this application.

[0026] Figure 10 This is a flowchart of a bus monitoring and control method in another embodiment of this application.

[0027] Figure 11 This is a schematic diagram of the hardware structure of an electronic device in one embodiment of this application. Detailed Implementation

[0028] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of some embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in some embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. It should be understood that, unless otherwise stated, " / " in this application means "or". For example, A / B can mean A or B. In some embodiments of this application, "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. "At least one" refers to one or more. "More than one" refers to two or more. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, and a, b, and c (seven cases).

[0030] refer to Figure 1The diagram shows the architecture of a System Power Management Interface (SPMI) bus in related technologies. The SPMI bus is an asynchronous bus that can connect multiple hosts 11 and multiple slaves 12, allowing data exchange between them. In one embodiment of this application, hosts 11 and slaves 12 resolve conflicts by arbitrating bus access. When the bus is idle, multiple hosts 11 or slaves 12 can request access to the bus through bus arbitration. The host 11 monitors the arbitration request and grants the bus to a requester.

[0031] When the bus is idle, multiple master 11 or slave 12 can access the bus through bus arbitration requests. One master 11 (the current owner of the bus) monitors the bus arbitration request and grants the bus to the requester. Typically, the SPMI bus includes clock signal lines and data signal lines. The clock signal lines are used to transmit the clock signal SCLK (Serial Clock), and the data signal lines are used to transmit the data signal SDATA (Serial Data). The SPMI bus can support simultaneous connection of 4 master 11s and 16 slave 12s. For example, the SPMI bus can be connected to one or more master 11s on a System-on-a-Chip (SOC), or to one or more slave 12s on a Power Management IC (PMIC).

[0032] Figure 1 The architecture shown is for illustrative purposes only and is not limited to this in actual applications.

[0033] refer to Figure 2The diagram illustrates the instruction cycle of the SPMI bus in one embodiment of this application. In one embodiment, the SPMI bus instruction cycle includes several stages: bus arbitration, sequence start, frame sequence, and bus stop. During the bus arbitration stage, when the data signal line of the SPMI bus is pulled high, the host 11 currently holding the SPMI bus releases the clock signal SCLK via the clock signal line. The host 11 or slave 12 connected to the SPMI bus pulls the data signal line high under the corresponding clock signal SCLK to declare its priority. If a higher-priority device requests to occupy the SPMI bus, the host 11 currently holding the SPMI bus releases the bus to the higher-priority device according to its priority. After the host 11 or slave 12, etc., seizes the SPMI bus and becomes the controller of the SPMI bus, it gains control of the SPMI bus clock signal SCLK and provides the SPMI bus clock signal SCLK. After completing the bus arbitration, the SPMI bus enters the sequence start stage. The sequence start stage can be a bus buffer stage. During the sequence start phase, the device that wins the bus preemption pulls the clock signal SCLK low and simultaneously controls the data signal line to first pull the data signal SDATA high and then pull it low, generating the sequence start condition (SSC). Once the power management chip of slave device 12 on the SPMI bus detects the start condition, it prepares to receive subsequent frame sequences.

[0034] In one embodiment of this application, the frame sequence is used to execute data transmission instructions. The data transmission instructions include information such as transmission commands, transmission addresses, and transmission data. In one embodiment of this application, the types of transmission commands include, but are not limited to: master 11 reading the register of slave 12, master 11 writing to the register of slave 12, and slave 12 writing to the register of master 11. In one embodiment of this application, the transmission address includes the address of slave 12 and the address of the slave 12's register. For example, a specific data transmission instruction could be a command from master to write 01 data to register 0011 of slave at address 0001. After the data transmission instruction is completed in the frame sequence, the SPMI bus enters a bus stop cycle.

[0035] In one embodiment of this application, the bus stop cycle phase of the SPMI bus is a process of bus stopping, during which the SPMI bus is in an idle state. When the SPMI bus is in the bus stop cycle phase, both the SPMI bus clock signal SCLK and the transmission data signal SDATA are pulled low, for example, the SPMI bus clock signal SCLK and the transmission data signal SDATA are pulled low.

[0036] However, in related technologies, such as Figure 1The data interaction between the master 11 and slave 12 on the SPMI bus shown is controlled entirely by the master 11 and cannot be controlled by external devices. To address the issue that the data interaction between the master 11 and slave 12 on the SPMI bus cannot be controlled by external devices, this application provides another SPMI bus architecture. (See reference...) Figure 3 The diagram shown is a schematic of the SPMI bus architecture in one embodiment of this application. In this embodiment, multiple host devices 11 are connected to integrated circuit (IC) devices 13. For example, multiple host devices 11 are connected to integrated circuit devices 13 via an SPMI bus. Multiple host devices 11, multiple slave devices 12, and integrated circuit devices 13 are respectively connected to a switching module 14 via an SPMI bus. The integrated circuit device 13 can control the switching module 14 to switch between a first channel and a second channel. When the switching module 14 switches to the first channel, the host devices 11 and slave devices 12 are respectively connected to the integrated circuit device 13 via the SPMI bus. When the switching module 14 switches to the second channel, the host device 11 is directly connected to the slave device 12 via the SPMI bus.

[0037] In one embodiment of this application, the switch module 14 includes a first switch 141 and a second switch 142. The first switch 141 and the second switch 142 are dual-channel high-speed switches. The first channel of both the first switch 141 and the first channel of the second switch 142 are connected to the integrated circuit device 13, and the second channel of the first switch 141 is connected to the second channel of the second switch 142. Thus, when both the first switch 141 and the second switch 142 are switched to the first channel, the integrated circuit device 13 is connected to the host device 11 and the slave device 12 respectively via the SPMI bus; when both the first switch 141 and the second switch 142 are switched to the second channel, the host device 11 is directly connected to the slave device 12 via the SPMI bus.

[0038] In one embodiment of this application, the operating states of the integrated circuit device 13 include a first operating state and a second operating state. The first operating state indicates that the integrated circuit device 13 sends non-master data to the slave device 12, that is, the integrated circuit device 13 performs data retransmission to the slave device 12. In several embodiments of this application, data from the non-master device 11 is used as retransmission data and sent to the slave device 12. The second operating state indicates that the integrated circuit device 13 controls the master device 11 to directly interact with the slave device 12.

[0039] refer to Figure 4 The diagram shown is a functional block diagram of an integrated circuit device 13 according to an embodiment of this application. The integrated circuit device 13 includes a bus monitoring module 131, a data transmission module 132, and a switch control module 133. (See reference...) Figure 5The diagram shown illustrates the connection between an integrated circuit device and a host and slave device in one embodiment of this application. In one embodiment, if the integrated circuit device 13 is operating in a first operating state, the first switch 141 switches to the first channel, and the second switch 142 switches to the first channel. Thus, the host 11 communicates with the integrated circuit device 13 through the first channel of the first switch 141, and the slave 12 communicates with the integrated circuit device 13 through the first channel of the second switch 142. (Reference) Figure 6 The diagram shown is a schematic of the connection between the integrated circuit device and the host and slave devices in another embodiment of this application. In one embodiment of this application, if the integrated circuit device 13 is operating in the second operating state, the first switch 141 switches to the second channel, the second switch 142 switches to the second channel, and the host 11 and the slave 12 directly interact with each other through the second channel of the first switch 141 and the second switch 142, respectively.

[0040] In one embodiment of this application, the bus monitoring module 131 is connected to the data transmission module 132 and the switch control module 133, respectively. The switch control module 133 is connected to the first switch 141 and the second switch 142, and is used to control the switching of the first switch 141 and the second switch 142 between the first channel and the second channel. The data transmission module 132 is connected to the first channel of the first switch 141 and the first channel of the second switch 142, respectively. The bus monitoring module 131 is used to monitor the communication data between the master 11 and the slave 12, and determine the working state of the integrated circuit device 13 based on the monitored communication data. If it is determined that the communication data between the master 11 and the slave 12 includes a preset instruction, the working state of the integrated circuit device 13 is determined to be the first working state. If it is determined that the communication data between the master 11 and the slave 12 does not include the preset instruction, the working state of the integrated circuit device 13 is determined to be the second working state. The preset instruction includes, but is not limited to: the master 11 reading the slave 12's instruction, the master 11 writing the slave 12's instruction, and the slave 12 writing the master 11's instruction. When the bus monitoring module 131 determines that the integrated circuit device 13 is in the second operating state, it determines the switch switching time and notifies the switch control module 133 of the switching time. The switch control module 133 controls the first switch 141 and the second switch 142 to switch the channel being turned on based on the switching time. For example, when the integrated circuit device 13 is operating in the second operating state, the switch control module 133 controls both the first switch 141 and the second switch 142 to switch to the second channel based on the switching time. When the integrated circuit device 13 is operating in the first operating state, the switch control module 133 controls both the first switch 141 and the second switch 142 to switch to the first channel based on the switching time. When the bus monitoring module 131 determines that the integrated circuit device 13 is in the first operating state, it sends a data retransmission notification to the data retransmission module 132. The data retransmission module 132 determines the retransmission data based on the data retransmission notification and sends the retransmission data to the slave device 12. The retransmission data is pre-set data according to the type of the slave device 12. For example, if slave device 12 is a power management chip, the supplementary data will be voltage or current data.

[0041] In this embodiment, the integrated circuit device 13 monitors the communication data between the host 11 and the slave 12 on the SPMI bus. When the monitored communication data determines that the working state of the integrated circuit device 13 is the second working state, the host 11 and the slave 12 can communicate directly by switching both the first switch 141 and the second switch 142 to the second channel, thus ensuring the interaction of the original data between the host 11 and the slave 12. When the monitored communication data determines that the working state of the integrated circuit device 13 is the first working state, the device determines to send supplementary data and sends the supplementary data to the slave 12, thus realizing the control of the data of the slave 12 by the integrated circuit device 13.

[0042] refer to Figure 7 The diagram shown is a flowchart of a bus monitoring and control method according to an embodiment of this application. The bus monitoring and control method is applied to integrated circuit device 13. The method specifically includes the following steps.

[0043] Step S701: Preset a predetermined instruction.

[0044] In one embodiment of this application, the bus monitoring module 131 pre-sets a predetermined instruction. For example, the predetermined instruction may be at least one of the following: a master 11 reading from the slave 12, a master 11 writing to the slave 12, or a slave 12 writing to the master 11. This is merely an example and is not limited to this in practical applications. For instance, the predetermined instruction may be a command from the master 11 with a source address of 0001 to the slave 12 with a destination address of 1111, writing the value "01".

[0045] Step S702: Monitor the communication data on the SPMI bus and determine whether the working state of the integrated circuit device 13 is the first working state.

[0046] In one embodiment of this application, the bus monitoring module 131 monitors communication data on the SPMI bus, such as communication data sent from the host 11 to the slave 12, and determines whether the communication data includes a predetermined instruction. If it is determined that the communication data does not include a predetermined instruction, the bus monitoring module 131 determines that the integrated circuit device 13 is in a second operating state and executes step S703. If it is determined that the communication data includes a predetermined instruction, the monitoring module 133 determines that the integrated circuit device 13 is in a first operating state and executes step S704. When the bus monitoring module 131 determines that the communication data includes a predetermined instruction, it continues to monitor the SPMI bus to ensure that the subsequent data retransmission module 132 successfully preempts the bus.

[0047] In step S703, the control host sends communication data directly to the slave device 12.

[0048] In one embodiment of this application, when the integrated circuit device 13 is operating in the second operating state, the switch control module 133 controls the first switch 141 and the second switch 142 to switch to the second channel. In this way, the host 11 establishes a communication channel with the slave 12 through the first switch 141 and the second switch 142, and transmits the communication data directly to the slave through the first switch 141 and the second switch 142.

[0049] Step S704: Determine the resend data based on the communication data.

[0050] In one embodiment of this application, when the bus monitoring module 131 determines that the operating state of the integrated circuit device 13 is a first operating state based on a predetermined instruction in the communication data, it sends a data retransmission notification to the data retransmission module 132. The data retransmission module 132 determines the retransmission data based on the data retransmission notification. The retransmission data is data pre-set according to the type of the slave device 12. For example, if the slave device 12 is a power management chip, the retransmission data is voltage or current data.

[0051] Step S705: Monitor whether the SPMI bus is in an idle state.

[0052] In one embodiment of this application, if the bus monitoring module 131 detects that both the clock signal line and the data signal line of the SPMI bus are in a high-impedance state, it determines that the SPMI bus is in an idle state. If the SPMI bus is in an idle state, steps S706 and S707 can be executed synchronously. In one embodiment of this application, synchronous execution means execution at the same time. If the SPMI bus is not in an idle state, step S705 is repeated until the SPMI bus is detected to have entered an idle state.

[0053] Step S706: Perform bus arbitration on the host simulating the slave.

[0054] refer to Figure 8 The diagram shown illustrates the connection between an integrated circuit device and a host and slave device in another embodiment of this application. The upper port of the integrated circuit device 13 is connected to the host 11 via an SPMI bus, and the lower port of the integrated circuit device 13 is connected to the slave device 11 via an SPMI bus. The data retransmission module 132 performs bus arbitration between the host 11 and the simulated slave device 12 by pulling the data signal line of the SPMI bus connected to the upper port high. Pulling the data signal line of the SPMI bus connected to the upper port high indicates setting the data signal line of the SPMI bus connected to the upper port to a high potential, for example, a potential above 1.5V. The bus arbitration performed by the data retransmission module 132 on the simulated slave device 12 by the host 11 ensures that the integrated circuit device 13 is not interfered with by the bus operation of the host 11 when performing data retransmission.

[0055] Step S707: Perform bus arbitration on the slave device simulating the master device.

[0056] In one embodiment of this application, the data retransmission module 132 performs bus arbitration between the slave 12 and the host 11 by pulling the data signal line of the SPMI bus connected to the lower port high. Pulling the data signal line of the SPMI bus connected to the lower port high indicates that the data signal line of the SPMI bus connected to the lower port is set to a high potential.

[0057] Step S708: Control the integrated circuit devices to connect to the host and slave devices respectively.

[0058] In one embodiment of this application, the switch control module 133 controls both the first switch 141 and the second switch 142 to switch to the first channel. Thus, through the first switch 141 and the second switch 142, the integrated circuit device 13 establishes a communication channel with the host 11 and the slave 12. After step S708 is completed, the process continues to execute steps S709 and S713.

[0059] Step S709: Determine whether the SPMI bus command cycle for bus arbitration by the slave device has reached the stage where the slave device preempts the SPMI bus with the highest priority.

[0060] In one embodiment of this application, if the SPMI bus instruction cycle for bus arbitration by the slave device reaches the stage where the slave device preempts the SPMI bus with the highest priority, step S710 is executed. If the SPMI bus instruction cycle for bus arbitration by the slave device does not reach the stage where the slave device preempts the SPMI bus with the highest priority, step S709 is repeated until the stage where the slave device preempts the SPMI bus with the highest priority arrives, and then step S710 is executed.

[0061] Step S710: When the slave device preempts the SPMI bus with the highest priority, it sends a preset slave address to the master device.

[0062] In one embodiment of this application, the preset slave address is different from the addresses of all slave devices 12 connected to the integrated circuit device 13. For example, the addresses of all slave devices 12 connected on the SPMI bus include Address0 to Address15. The data retransmission module 132 sends the preset slave address Address16, which is different from Address0 to Address15, to the host 11.

[0063] Step S711: Determine whether the SPMI bus instruction cycle for bus arbitration performed by the slave device has reached the frame sequence stage.

[0064] In one embodiment of this application, if the SPMI bus instruction cycle for bus arbitration performed by the slave device reaches the frame sequence stage, step S712 is executed; if the SPMI bus instruction cycle for bus arbitration performed by the slave device has not reached the frame sequence stage, step S712 is repeated until the frame sequence stage arrives.

[0065] Step S712: Write preset data to the host with the preset host address.

[0066] In one embodiment of this application, the data retransmission module 132 writes preset data, such as 00, to the register of a host with a preset host address via a master write instruction. In another embodiment of this application, the preset host address is different from the addresses of all hosts 12 connected to the integrated circuit device 13. For example, the addresses of all hosts 12 connected on the SPMI bus include address0 to address3, and the data retransmission module 132 will write the preset data to the host 11 with a preset host address 4, which is different from addresses0 to address3.

[0067] Step S713: Determine whether the SPMI bus instruction cycle for bus arbitration performed by the host has reached the stage where the host preempts the SPMI bus with the highest priority.

[0068] In one embodiment of this application, if the SPMI bus instruction cycle for bus arbitration by the host reaches the stage where the host preempts the SPMI bus with the highest priority, step S714 is executed. If the SPMI bus instruction cycle for bus arbitration by the host does not reach the stage where the host preempts the SPMI bus with the highest priority, step S713 is repeated until the stage where the host preempts the SPMI bus with the highest priority arrives.

[0069] In step S714, when the host preempts the SPMI bus with the highest priority, the supplementary data is sent to the slave.

[0070] In one embodiment of this application, the data retransmission module 132 sends retransmission data to any one or more slave devices 12 connected in the SPMI bus. In another embodiment of this application, the data retransmission module 132 writes the retransmission data value to the target slave device using an external register write instruction.

[0071] In one embodiment of this application, after the resend data is sent to the target slave device, the switch control module 133 controls the first switch 141 and the second switch 142 to switch from the first channel to the second channel. In this way, the host 11 re-establishes a communication channel with the slave device 12 through the first switch 141 and the second switch 142, and transmits the communication data directly to the slave device 12 through the first switch 141 and the second switch 142.

[0072] To maintain stable operation of the SPMI bus during the switching between the first and second operating states of the integrated circuit device 13, in this embodiment, when the integrated circuit device 13 detects the need for data retransmission (i.e., the operating state of the integrated circuit device 13 is the first operating state), it first checks whether the SPMI bus is idle. When the SPMI bus is idle, the integrated circuit device 13 first initiates bus arbitration by pulling the data signal line high for the master simulating the slave, and then initiates bus arbitration by pulling the integrated circuit device 13 high for the slave simulating the master. After both sides are pulled high, the first switch 141 and the second switch 142 are switched to the first channel. This prevents glitches from occurring during the switching of the first switch 141 and the second switch 142, which could affect the correct operation of the SPMI bus. It also ensures that no other master or slave will preempt the bus during the switching of the first switch 141 and the second switch 142, preventing any abnormalities caused by simultaneous bus preemption. During the data retransmission process for the slave, the integrated circuit device 13 simultaneously preempts the master's SPMI bus with the highest priority, ensuring that no master performs bus operations during the data retransmission period.

[0073] In the embodiments of this application, the integrated circuit device 13 monitors the communication data of the SPMI bus. After detecting that there is a predetermined instruction in the communication data and the SPMI bus is idle, the integrated circuit device 13 first initiates bus arbitration by pulling the data signal line high for the master to simulate the slave, and initiates bus arbitration by pulling the integrated circuit device 13 high for the slave to simulate the master, and writes the supplementary data value to the target slave. In this way, the external integrated circuit device 13 can stably transmit data to the slave 12.

[0074] In one embodiment of this application, when the integrated circuit device 13 operates in a first operating state, it can accurately identify the current state of the SPMI bus, thus ensuring that SPMI can pull the data signal line high with the highest priority on the rising edge of the clock signal line of the host 11 to preempt the bus. When the integrated circuit device 13 operates in a second operating state, it can identify and store the communication data between the host and the slave, and identify whether the communication data contains a predetermined instruction that requires data retransmission.

[0075] refer to Figure 9The diagram shown is a flowchart illustrating a method for monitoring the SPMI bus according to an embodiment of this application. The method for monitoring the SPMI bus is applied during the bus arbitration phase of the SPMI bus instruction cycle. The method includes the following steps.

[0076] Step S901: Listen for bus start conditions.

[0077] In one embodiment of this application, the bus start condition is determined to be detected when the data signal line of the SPMI bus is pulled high and the clock signal line is kept low.

[0078] Step S902: Monitor the status of the BUS Park on the SPMI bus.

[0079] In one embodiment of this application, BUS Park represents the bus stop cycle.

[0080] Step S903: Monitor whether the slave device is preempting the SPMI bus with secondary priority. If the slave device is preempting the SPMI bus with secondary priority, proceed to step S904; if the slave device is not preempting the SPMI bus with secondary priority, proceed to step S905.

[0081] Step S904: Execute the bus connection sequence.

[0082] In one embodiment of this application, the bus connection sequence indicates that other hosts 11 are connected to the SPMI bus.

[0083] Step S905: Monitor whether the slave device is preempting the SPMI bus with the highest priority. If the slave device preempts the SPMI bus with the highest priority, proceed to step S906; if the slave device does not preempt the SPMI bus with the highest priority, proceed to step S907.

[0084] Step S906: Identify the slave address sent by the slave device. After step S906 is completed, the process proceeds to step S917.

[0085] Step S907: Monitor whether the host is preempting the SPMI bus with the highest priority. If the host is not preempting the SPMI bus with the highest priority, proceed to step S908; if the host is preempting the SPMI bus with the highest priority, proceed to step S917.

[0086] Step S908: Monitor whether the host preempts the SPMI bus with the first priority. If the host does not preempt the SPMI bus with the first priority, proceed to step S909; if the host preempts the SPMI bus with the first priority, proceed to step S917. The first priority is lower than the highest priority.

[0087] Step S909: Monitor whether the host preempts the SPMI bus with the second priority. If the host does not preempt the SPMI bus with the second priority, proceed to step S910; if the host does preempt the SPMI bus with the second priority, proceed to step S917. The second priority is lower than the first priority.

[0088] Step S910: Monitor whether the host preempts the SPMI bus with the third priority. If the host does not preempt the SPMI bus with the third priority, proceed to step S911; if the host does preempt the SPMI bus with the third priority, proceed to step S917. The third priority is lower than the second priority.

[0089] Step S911: Listen to whether the slave device preempts the SPMI bus with the second-lowest priority; if the slave device preempts the SPMI bus with the second-lowest priority, execute step S906; if the slave device does not preempt the SPMI bus with the second-lowest priority, execute step S912.

[0090] Step S912: Monitor whether the host preempts the SPMI bus with the highest priority. If the host does not preempt the SPMI bus with the highest priority, proceed to step S913; if the host preempts the SPMI bus with the highest priority, proceed to step S917.

[0091] Step S913: Monitor whether the host preempts the SPMI bus with the first priority. If the host does not preempt the SPMI bus with the first priority, proceed to step S914; if the host preempts the SPMI bus with the first priority, proceed to step S917.

[0092] Step S914: Monitor whether the host preempts the SPMI bus with the second priority. If the host does not preempt the SPMI bus with the second priority, proceed to step S915; if the host preempts the SPMI bus with the second priority, proceed to step S917.

[0093] Step S915: Monitor whether the host preempts the SPMI bus with the third priority. If the host does not preempt the SPMI bus with the third priority, proceed to step S916; if the host does preempt the SPMI bus with the third priority, proceed to step S917.

[0094] Step S916: After confirming that no device is preempting the SPMI bus, the SPMI bus enters an idle state.

[0095] Step S917: The bus arbitration phase ends, and the SPMI bus enters the SSC phase.

[0096] In this embodiment, the integrated circuit device 13 uses a sampling method triggered by the falling edge of the clock to monitor and identify the current stage of the SPMI bus instruction cycle, so that the transmission delay between the monitoring result and the host communication data is within a preset time range, such as within 5ns.

[0097] refer to Figure 10 The diagram shown is a flowchart of a bus monitoring and control method according to another embodiment of this application. The method includes the following steps.

[0098] Step S1001: Monitor the communication data between the master and slave devices on the SPMI bus.

[0099] In one embodiment of this application, the specific implementation steps of step S1001 are as follows: Figure 7 The steps in S702 are described again here.

[0100] Step S1002: If the working state of the integrated circuit device is determined to be the first working state based on the communication data, the supplementary data is sent to the slave device.

[0101] In one embodiment of this application, if the SPMI bus is detected to be idle, bus arbitration is performed on the host 11 simulating the slave 12, and bus arbitration is performed on the slave 12 simulating the host 11; the control switch module 14 is switched so that the integrated circuit device 13 is connected to the host 11 and the slave 12 respectively; when it is determined that the host 11 preempts the SPMI bus with the highest priority, the supplementary data is sent to the slave 12, thus realizing the control of the data of the slave 12 by the external integrated circuit device 13.

[0102] refer to Figure 11The diagram illustrates the hardware structure of an electronic device 100 according to an embodiment of this application. The electronic device 100 may include a processor 110, an integrated circuit device 13, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, antenna 1, antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor module 180, buttons 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, a barometric pressure sensor 180C, a magnetic sensor 180D, an accelerometer sensor 180E, a distance sensor 180F, a proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0103] It is understood that the structures illustrated in the embodiments of the present invention do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0104] Processor 110 may include one or more processing units, such as application processors (APs), modem processors, graphics processing units (GPUs), image signal processors (ISPs), controllers, video codecs, digital signal processors (DSPs), baseband processors, and / or neural network processing units (NPUs). These different processing units may be independent devices or integrated into one or more processors.

[0105] The controller can generate operation control signals based on the instruction opcode and timing signals to complete the control of instruction fetching and execution.

[0106] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory can store instructions or data that the processor 110 has just used or that are used repeatedly. If the processor 110 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0107] In some embodiments, the processor 110 may include one or more interfaces. Interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0108] The I2C interface is a bidirectional synchronous serial bus, including a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the processor 110 may include multiple I2C buses. The processor 110 can couple to the touch sensor 180K, charger, flash, camera 193, etc., through different I2C bus interfaces. For example, the processor 110 can couple to the touch sensor 180K through the I2C interface, enabling the processor 110 and the touch sensor 180K to communicate through the I2C bus interface, thereby realizing the touch function of the electronic device 100.

[0109] The I2S interface can be used for audio communication. In some embodiments, the processor 110 may include multiple I2S buses. The processor 110 can be coupled to the audio module 170 via the I2S bus to enable communication between the processor 110 and the audio module 170. In some embodiments, the audio module 170 can transmit audio signals to the wireless communication module 160 via the I2S interface to enable the function of answering phone calls through a Bluetooth headset.

[0110] The PCM interface can also be used for audio communication, sampling, quantizing, and encoding analog signals. In some embodiments, the audio module 170 and the wireless communication module 160 can be coupled via the PCM bus interface. In some embodiments, the audio module 170 can also transmit audio signals to the wireless communication module 160 via the PCM interface, enabling the function of answering phone calls through a Bluetooth headset. Both the I2S interface and the PCM interface can be used for audio communication.

[0111] The UART interface is a universal serial data bus used for asynchronous communication. This bus can be a bidirectional communication bus. It converts the data to be transmitted between serial and parallel communication. In some embodiments, the UART interface is typically used to connect the processor 110 and the wireless communication module 160. For example, the processor 110 communicates with the Bluetooth module in the wireless communication module 160 via the UART interface to implement Bluetooth functionality. In some embodiments, the audio module 170 can transmit audio signals to the wireless communication module 160 via the UART interface to enable music playback through Bluetooth headphones.

[0112] The MIPI interface can be used to connect the processor 110 to peripheral devices such as the display screen 194 and the camera 193. The MIPI interface includes a camera serial interface (CSI) and a display serial interface (DSI). In some embodiments, the processor 110 and the camera 193 communicate via the CSI interface to enable the electronic device 100 to capture images. The processor 110 and the display screen 194 communicate via the DSI interface to enable the electronic device 100 to display images.

[0113] The GPIO interface can be configured via software. It can be configured as a control signal or a data signal. In some embodiments, the GPIO interface can be used to connect the processor 110 to a camera 193, a display screen 194, a wireless communication module 160, an audio module 170, a sensor module 180, etc. The GPIO interface can also be configured as an I2C interface, an I2S interface, a UART interface, a MIPI interface, etc.

[0114] USB port 130 is a USB standard compliant interface, specifically a Mini USB port, Micro USB port, USB Type-C port, etc. USB port 130 can be used to connect a charger to charge electronic device 100, and can also be used for data transfer between electronic device 100 and peripheral devices. It can also be used to connect headphones for audio playback. This interface can also be used to connect other electronic devices 100, such as AR devices.

[0115] It is understood that the interface connection relationships between the modules illustrated in the embodiments of the present invention are merely illustrative and do not constitute a structural limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may also employ different interface connection methods or combinations of multiple interface connection methods as described in the above embodiments.

[0116] The charging management module 140 receives charging input from a charger. The charger can be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 receives charging input from the wired charger via a USB interface 130. In some wireless charging embodiments, the charging management module 140 receives wireless charging input via the wireless charging coil of the electronic device 100. While charging the battery 142, the charging management module 140 can also supply power to the electronic device 100 via the power management module 141.

[0117] The power management module 141 connects the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, providing power to the processor 110, internal memory 121, display screen 194, camera 193, and wireless communication module 160, etc. The power management module 141 can also monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage current, impedance). In some other embodiments, the power management module 141 may also be located within the processor 110. In other embodiments, the power management module 141 and the charging management module 140 may be located in the same device.

[0118] The wireless communication function of electronic device 100 can be realized through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor, etc.

[0119] Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 100 can be used to cover one or more communication frequency bands. Different antennas can also be multiplexed to improve antenna utilization. For example, antenna 1 can be multiplexed as a diversity antenna for a wireless local area network. In some other embodiments, the antennas can be used in conjunction with tuning switches.

[0120] The mobile communication module 150 can provide solutions for wireless communication, including 2G / 3G / 4G / 5G, applied to the electronic device 100. The mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves via antenna 1, and perform filtering, amplification, and other processing on the received electromagnetic waves before transmitting them to a modem processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves for radiation via antenna 1. In some embodiments, at least some functional modules of the mobile communication module 150 may be housed in the processor 110. In some embodiments, at least some functional modules of the mobile communication module 150 and at least some modules of the processor 110 may be housed in the same device.

[0121] The modem processor may include a modulator and a demodulator. The modulator modulates the low-frequency baseband signal to be transmitted into a mid-to-high frequency signal. The demodulator demodulates the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After processing by the baseband processor, the low-frequency baseband signal is transmitted to the application processor. The application processor outputs sound signals through an audio device (not limited to speaker 170A, receiver 170B, etc.) or displays images or videos through the display screen 194. In some embodiments, the modem processor may be a separate device. In other embodiments, the modem processor may be independent of the processor 110 and may be housed in the same device as the mobile communication module 150 or other functional modules.

[0122] The wireless communication module 160 can provide solutions for wireless communication applications on the electronic device 100, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies. The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via antenna 2, performs frequency modulation and filtering of the electromagnetic wave signals, and sends the processed signal to processor 110. The wireless communication module 160 can also receive signals to be transmitted from processor 110, perform frequency modulation and amplification, and convert them into electromagnetic waves for radiation via antenna 2.

[0123] In some embodiments, antenna 1 of electronic device 100 is coupled to mobile communication module 150, and antenna 2 is coupled to wireless communication module 160, enabling electronic device 100 to communicate with networks and other devices via wireless communication technology. The wireless communication technology may include Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technologies, etc. The GNSS may include the Global Positioning System (GPS), the Global Navigation Satellite System (GLONASS), the BeiDou Navigation Satellite System (BDS), the Quasi-Zenith Satellite System (QZSS), and / or satellite-based augmentation systems (SBAS).

[0124] Electronic device 100 implements display functions through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, connected to the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 110 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0125] Display screen 194 is used to display images, videos, etc. Display screen 194 includes a display panel. The display panel may be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a miniature LED, a microLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, electronic device 100 may include one or N displays 194, where N is a positive integer greater than 1.

[0126] Electronic device 100 can perform shooting functions through ISP, camera 193, video codec, GPU, display 194 and application processor.

[0127] The ISP (Image Signal Processor) is used to process data fed back from the camera 193. For example, when taking a picture, the shutter is opened, and light is transmitted through the lens to the camera's photosensitive element. The light signal is converted into an electrical signal, and the camera's photosensitive element transmits the electrical signal to the ISP for processing, transforming it into an image visible to the naked eye. The ISP can also perform algorithmic optimization of image noise, brightness, and skin tone. The ISP can also optimize parameters such as exposure and color temperature of the shooting scene. In some embodiments, the ISP can be set in the camera 193.

[0128] Camera 193 is used to capture still images or videos. An object is projected onto a photosensitive element by generating an optical image through the lens. The photosensitive element can be a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, which is then passed to an ISP for conversion into a digital image signal. The ISP outputs the digital image signal to a DSP for processing. The DSP converts the digital image signal into image signals in standard RGB, YUV, or other formats. In some embodiments, the electronic device 100 may include one or N cameras 193, where N is a positive integer greater than 1.

[0129] Digital signal processors (DSPs) are used to process digital signals. Besides digital image signals, they can also process other digital signals. For example, when electronic device 100 selects a frequency, the DSP can perform Fourier transforms on the frequency energy.

[0130] Video codecs are used to compress or decompress digital video. Electronic device 100 may support one or more video codecs. Thus, electronic device 100 can play or record videos in various encoding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

[0131] An NPU (Neural Processing Unit) is a computational processor for neural networks (NNs). By borrowing the structure of biological neural networks, such as the transmission patterns between neurons in the human brain, it can rapidly process input information and continuously learn on its own. NPUs enable intelligent cognitive applications in electronic devices, such as image recognition, facial recognition, speech recognition, and text understanding.

[0132] Internal memory 121 may include one or more random access memory (RAM) and one or more non-volatile memory (NVM).

[0133] Random access memory can include static random-access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and double data rate synchronous dynamic random access memory (DDR SDRAM, such as fifth-generation DDR SDRAM, which is generally called DDR5 SDRAM). Non-volatile memory can include disk storage devices and flash memory.

[0134] Flash memory can be classified according to its operating principle, including NOR FLASH, NAND FLASH, 3D NAND FLASH, etc.; according to the level of the storage cell, including single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), etc.; and according to the storage specification, including universal flash storage (UFS) and embedded multimedia card (eMMC), etc.

[0135] The random access memory can be directly read and written by the processor 110. It can be used to store executable programs (such as machine instructions) of the operating system or other running programs, as well as user and application data.

[0136] Non-volatile memory can also store executable programs and user and application data, and can be pre-loaded into random access memory for direct reading and writing by the processor 110.

[0137] The external memory interface 120 can be used to connect to external non-volatile memory, thereby expanding the storage capacity of the electronic device 100. The external non-volatile memory communicates with the processor 110 through the external memory interface 120 to perform data storage functions. For example, music, video, and other files can be stored in the external non-volatile memory.

[0138] Internal memory 121 or external memory interface 120 is used to store one or more computer programs. The one or more computer programs are configured to be executed by processor 110. The one or more computer programs include multiple instructions, which, when executed by processor 110, can implement the bus monitoring and control method executed on electronic device 100 in the above embodiments, so as to realize the bus monitoring and control function of electronic device 100.

[0139] Electronic device 100 can implement audio functions, such as music playback and recording, through audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, and application processor.

[0140] The audio module 170 is used to convert digital audio information into analog audio signals for output, and also to convert analog audio input into digital audio signals. The audio module 170 can also be used for encoding and decoding audio signals. In some embodiments, the audio module 170 may be located in the processor 110, or some functional modules of the audio module 170 may be located in the processor 110.

[0141] The speaker 170A, also known as a "loudspeaker," is used to convert audio electrical signals into sound signals. The electronic device 100 can listen to music or make hands-free calls through the speaker 170A.

[0142] The receiver 170B, also known as the "earpiece," is used to convert audio electrical signals into sound signals. When the electronic device 100 answers a telephone call or voice message, the receiver 170B can be brought close to the ear to listen to the voice.

[0143] Microphone 170C, also known as a "microphone" or "voice transducer," is used to convert sound signals into electrical signals. When making a phone call or sending a voice message, the user can speak by bringing their mouth close to microphone 170C, inputting the sound signal into microphone 170C. Electronic device 100 may have at least one microphone 170C. In some embodiments, electronic device 100 may have two microphones 170C, which, in addition to collecting sound signals, can also perform noise reduction. In other embodiments, electronic device 100 may also have three, four, or more microphones 170C, which can collect sound signals, reduce noise, identify the sound source, and perform directional recording, etc.

[0144] The 170D headphone jack is used to connect wired headphones. The 170D headphone jack can be a USB 130 interface or a 3.5mm Open Mobile Terminal Platform (OMTP) standard interface, a CTIA (Cellular Telecommunications Industry Association of the USA) standard interface.

[0145] Pressure sensor 180A is used to sense pressure signals and convert them into electrical signals. In some embodiments, pressure sensor 180A can be disposed on display screen 194. There are many types of pressure sensors 180A, such as resistive pressure sensors, inductive pressure sensors, and capacitive pressure sensors. A capacitive pressure sensor may include at least two parallel plates with conductive material. When force is applied to pressure sensor 180A, the capacitance between the electrodes changes. Electronic device 100 determines the pressure intensity based on the change in capacitance. When a touch operation is applied to display screen 194, electronic device 100 detects the intensity of the touch operation based on pressure sensor 180A. Electronic device 100 can also calculate the touch position based on the detection signal from pressure sensor 180A. In some embodiments, touch operations applied to the same touch position but with different touch operation intensities can correspond to different operation commands. For example, when a touch operation with an intensity less than a first pressure threshold is applied to the SMS application icon, a command to view an SMS is executed. When a touch operation with an intensity greater than or equal to the first pressure threshold is applied to the SMS application icon, a command to create a new SMS is executed.

[0146] The gyroscope sensor 180B can be used to determine the motion attitude of the electronic device 100. In some embodiments, the gyroscope sensor 180B can determine the angular velocity of the electronic device 100 about three axes (i.e., the x, y, and z axes). The gyroscope sensor 180B can be used for image stabilization. For example, when the shutter is pressed, the gyroscope sensor 180B detects the angle of the shake of the electronic device 100, calculates the distance that the lens module needs to compensate based on the angle, and allows the lens to counteract the shake of the electronic device 100 by moving in the opposite direction, thus achieving image stabilization. The gyroscope sensor 180B can also be used in navigation and motion-sensing game scenarios.

[0147] A barometric pressure sensor 180C is used to measure air pressure. In some embodiments, the electronic device 100 calculates altitude using the air pressure value measured by the barometric pressure sensor 180C, assisting in positioning and navigation. A magnetic sensor 180D includes a Hall effect sensor. The electronic device 100 can use the magnetic sensor 180D to detect the opening and closing of a flip cover. In some embodiments, when the electronic device 100 is a flip phone, it can detect the opening and closing of the flip cover using the magnetic sensor 180D. Based on the detected opening and closing state of the cover or the flip cover, features such as automatic flip unlocking can be set. An accelerometer 180E can detect the magnitude of the acceleration of the electronic device 100 in various directions (generally three axes). When the electronic device 100 is stationary, the magnitude and direction of gravity can be detected. It can also be used to identify the posture of the electronic device 100, applicable to applications such as screen orientation switching and pedometers. A distance sensor 180F is used to measure distance. The electronic device 100 can measure distance using infrared or laser. In some embodiments, during a shooting scenario, the electronic device 100 can utilize the distance sensor 180F for distance measurement to achieve fast focusing.

[0148] The proximity sensor 180G may include, for example, a light-emitting diode (LED) and a light detector, such as a photodiode. The LED may be an infrared LED. The electronic device 100 emits infrared light outward through the LED. The electronic device 100 uses the photodiode to detect infrared reflected light from nearby objects. When sufficient reflected light is detected, it can be determined that there is an object near the electronic device 100. When insufficient reflected light is detected, the electronic device 100 can determine that there is no object near the electronic device 100. The electronic device 100 may use the proximity sensor 180G to detect when a user holds the electronic device 100 close to their ear for a call, so as to automatically turn off the screen to save power. The proximity sensor 180G can also be used in holster mode and pocket mode for automatic unlocking and locking of the screen.

[0149] The ambient light sensor 180L is used to sense the brightness of ambient light. The electronic device 100 can adaptively adjust the brightness of the display screen 194 based on the sensed ambient light brightness. The ambient light sensor 180L can also be used to automatically adjust the white balance when taking pictures. The ambient light sensor 180L can also work with the proximity sensor 180G to detect whether the electronic device 100 is in a pocket to prevent accidental touches.

[0150] The fingerprint sensor 180H is used to collect fingerprints. The electronic device 100 can utilize the characteristics of the collected fingerprints to achieve fingerprint unlocking, accessing application locks, taking photos with fingerprints, answering calls with fingerprints, etc.

[0151] Temperature sensor 180J is used to detect temperature. In some embodiments, electronic device 100 uses the temperature detected by temperature sensor 180J to execute a temperature handling strategy. For example, when the temperature reported by temperature sensor 180J exceeds a threshold, electronic device 100 performs thermal protection by reducing the performance of a processor located near temperature sensor 180J to reduce power consumption. In other embodiments, when the temperature is below another threshold, electronic device 100 heats battery 142 to prevent abnormal shutdown of electronic device 100 due to low temperature. In still other embodiments, when the temperature is below yet another threshold, electronic device 100 boosts the output voltage of battery 142 to prevent abnormal shutdown due to low temperature.

[0152] Touch sensor 180K, also known as a "touch device," can be located on display screen 194. The touch sensor 180K and display screen 194 together form a touchscreen, also known as a "touchscreen." Touch sensor 180K detects touch operations applied to or near it. The touch sensor can transmit the detected touch operation to the application processor to determine the type of touch event. Visual output related to the touch operation can be provided through display screen 194. In other embodiments, touch sensor 180K may also be located on the surface of electronic device 100, in a different position than display screen 194.

[0153] The bone conduction sensor 180M can acquire vibration signals. In some embodiments, the bone conduction sensor 180M can acquire vibration signals from the vibrating bone segments of the human vocal cords. The bone conduction sensor 180M can also contact the human pulse to receive blood pressure signals. In some embodiments, the bone conduction sensor 180M can also be incorporated into headphones to form bone conduction headphones. The audio module 170 can parse the voice signals from the vibrating bone segments of the vocal cords acquired by the bone conduction sensor 180M to realize voice functionality. The application processor can parse heart rate information from the blood pressure signals acquired by the bone conduction sensor 180M to realize heart rate detection functionality.

[0154] Buttons 190 include a power button, volume buttons, etc. Buttons 190 can be mechanical buttons or touch-sensitive buttons. Electronic device 100 can receive button input and generate key signal inputs related to user settings and function control of electronic device 100.

[0155] Motor 191 can generate vibration alerts. Motor 191 can be used for incoming call vibration alerts or for touch vibration feedback. For example, different vibration feedback effects can correspond to touch operations performed on different applications (such as taking photos, playing audio, etc.). Motor 191 can also correspond to different vibration feedback effects for touch operations performed on different areas of the display screen 194. Different application scenarios (such as time reminders, receiving messages, alarm clocks, games, etc.) can also correspond to different vibration feedback effects. The touch vibration feedback effect can also be customized.

[0156] Indicator 192 can be an indicator light, used to indicate charging status, power changes, or to indicate messages, missed calls, notifications, etc.

[0157] The SIM card interface 195 is used to connect a SIM card. The SIM card can be inserted into or removed from the SIM card interface 195 to make contact with and separate from the electronic device 100. The electronic device 100 can support one or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 195 can support Nano SIM cards, Micro SIM cards, SIM cards, etc. Multiple cards can be inserted into the same SIM card interface 195 simultaneously. The multiple cards can be of the same or different types. The SIM card interface 195 is also compatible with different types of SIM cards. The SIM card interface 195 is also compatible with external memory cards. The electronic device 100 interacts with the network through the SIM card to realize functions such as calls and data communication. In some embodiments, the electronic device 100 uses an eSIM, i.e., an embedded SIM card. The eSIM card can be embedded in the electronic device 100.

[0158] This embodiment also provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned steps to implement the bus monitoring and control method described in the above embodiment.

[0159] In addition, some embodiments of this application also provide an apparatus, which may specifically be a chip, component or module. The apparatus may include a connected processor and a memory. The memory is used to store computer execution instructions. When the apparatus is running, the processor can execute the computer execution instructions stored in the memory to cause the chip to execute the bus monitoring and control methods in the above-described method embodiments.

[0160] In this embodiment, the electronic device, computer storage medium, computer program product or chip are all used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects of the corresponding method provided above, and will not be repeated here.

[0161] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0162] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0163] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units.

[0164] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of some embodiments of this application, essentially or in other words, the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0165] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of some embodiments of this application and are not intended to limit it. Although some embodiments of this application have been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of some implementation examples of this application without departing from the spirit and scope of the technical solutions of some embodiments of this application.

Claims

1. A control method applied to an integrated circuit device, characterized by, The integrated circuit device is connected with a first device, the first device, the integrated circuit device and a second device are connected with a switch module through a bus respectively, and the method comprises: listening to communication data between the first device and the second device in the bus; if it is determined according to the communication data that the working state of the integrated circuit device is a first working state, sending preset retransmission data to the second device; wherein the sending of the preset retransmission data to the second device comprises: confirming that the bus is in an idle state; controlling the switch module to switch so that the integrated circuit device is connected with the first device and the second device respectively; simulating the second device for the first device to perform bus arbitration, and simulating the first device for the second device to perform bus arbitration; when it is determined that the first device occupies the bus with the highest priority, sending the retransmission data to the second device, wherein the switch module comprises a first switch and a second switch, the first switch is connected with the first device, the second switch is connected with the second device, a first channel of the first switch and a first channel of the second switch are connected with the integrated circuit device, and a second channel of the first switch and a second channel of the second switch are connected.

2. The control method according to claim 1, characterized by, The method further comprises: if it is determined according to the communication data that the working state of the integrated circuit device is a second working state, controlling the switch module to switch so that the first device and the second device are connected.

3. The control method according to claim 2, characterized by, determining the working state of the integrated circuit device according to the communication data comprises: if it is determined that the communication data includes a predetermined instruction, determining that the working state of the integrated circuit device is the first working state; or if it is determined that the communication data does not include a predetermined instruction, determining that the working state of the integrated circuit device is the second working state.

4. The control method according to claim 1, characterized by, The bus arbitration of the first device simulating the second device, and the bus arbitration of the second device simulating the first device comprises: simulating the second device for the first device to perform bus arbitration by pulling up the data signal line of the bus connected with the upper port of the integrated circuit device, wherein the upper port is connected with the first device through the bus, and pulling up the data signal line of the bus connected with the upper port of the integrated circuit device means setting the data signal line of the bus connected with the upper port to high potential; simulating the first device for the second device to perform bus arbitration by pulling up the data signal line of the bus connected with the lower port of the integrated circuit device, wherein the lower port is connected with the second device through the bus, and pulling up the data signal line of the bus connected with the lower port of the integrated circuit device means setting the data signal line of the bus connected with the lower port to high potential.

5. The control method according to claim 1, characterized by, The bus is a system power management interface (SPMI) bus.

6. The control method according to claim 5, characterized by, The sending of the retransmission data to the second device when it is determined that the first device occupies the bus with the highest priority comprises: write the retransmission data value to the second device via an external register write instruction.

7. The control method according to claim 5, characterized by, After simulating the second device performing bus arbitration on the bus, the method further includes: if the SPMI bus instruction cycle in which the second device performs bus arbitration proceeds to a stage in which the second device preempts the bus with the highest priority, sending a preset second device address to the first device.

8. The control method according to claim 7, characterized by, After sending the preset second device address to the first device, the method further includes: if the SPMI bus instruction cycle in which the second device performs bus arbitration proceeds to a stage in which a frame sequence, write preset data to the first device with the preset first device address.

9. The control method according to claim 8, characterized by, The writing of the preset data to the first device with the preset first device address includes: writing the preset data to a register of the first device with the preset first device address via a master write instruction.

10. The control method according to claim 5, characterized by, The confirming that the bus is in an idle state includes: if the bus is detected to enter a bus stop period, confirming that the bus is in the idle state.

11. The control method according to claim 1, characterized by, The retransmission data is data determined according to a type of the second device.

12. The control method according to claim 1, characterized by, The first device is a system on chip (SOC), and the second device is a power management integrated circuit (PMIC).

13. A chip, characterized by The electronic device includes a processor and a memory, wherein the processor is connected to the memory. The memory is configured to store program instructions. The processor is configured to read the program instructions stored in the memory to implement the control method according to any one of claims 1 to 12.

14. An electronic device, comprising: The electronic device includes a first device, a second device, and an integrated circuit device, the integrated circuit device is connected to the first device, and the first device, the integrated circuit device, and the second device are connected to a switch module through a bus, wherein the integrated circuit device is configured to implement the control method according to any one of claims 1 to 12.

15. A computer storage medium, comprising, The computer storage medium stores program instructions, and when the program instructions run on the electronic device, the electronic device is caused to implement the control method according to any one of claims 1 to 12. The computer storage medium stores program instructions, and when the program instructions run on the electronic device, the electronic device is caused to implement the control method according to any one of claims 1 to 12.

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