A data processing device, method and related equipment

Abstract

The present application proposes a data processing device, method and related equipment, the device includes a control module, a first address translation bypass buffer and a plurality of second address translation bypass buffers; the control module is configured to: receive a DMA request, determine the descriptor physical address corresponding to the DMA request based on the first address translation bypass buffer; send a DMA request to a memory module based on the descriptor physical address corresponding to the DMA request; receive the descriptor returned by the memory module; determine the target physical address corresponding to the DMA request based on the target virtual address in the descriptor and the second address translation bypass buffer corresponding to the DMA request; process the DMA request based on the target physical address. The present application sets different second address translation bypass buffers for different types of requests according to the type of DMA request, and when processing a request, performs address conversion based on the corresponding second address translation bypass buffer according to the type of request, and the efficiency and success rate of the conversion are higher.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a data processing device, method and related equipment. Background Art

[0002] When a computer system processes a Direct Memory Access (DMA) request, it needs to first convert the target virtual address of the DMA request into a target physical address, and then process the DMA request based on the target physical address. The process of converting the target virtual address into the target physical address can be implemented through a page table, where the page table records the mapping relationship between the target virtual address and the target physical address corresponding to various DMA requests. However, the page table is large and contains many mapping relationships. Therefore, when performing traversal query conversion based on the page table, the efficiency is low.

[0003] Therefore, a Translation Lookaside Buffer (TLB) is often used to cache the mapping relationship between the target virtual address and the target physical address that has been used most recently or is most likely to be accessed. During conversion, query conversion is performed based on the TLB first. If the TLB caches the mapping relationship between the target virtual address and the target physical address corresponding to the DMA request, the conversion can be performed quickly.

[0004] However, the storage space of the TLB is limited and can only cache a small amount of mapping relationships, which restricts the success rate of query conversion through the TLB. Summary of the invention

[0005] The main purpose of the present application is to propose a data processing device, method and related equipment, aiming to solve the problem in the prior art that the storage space of TLB is limited and the success rate of querying and converting virtual addresses and physical addresses based on TLB is low.

[0006] To achieve the above object, the present application proposes a data processing device, comprising: a control module, a first address translation bypass buffer and a plurality of second address translation bypass buffers;

[0007] The first address translation bypass buffer is used to cache a first mapping relationship, wherein a first mapping relationship includes a corresponding relationship between a source address corresponding to a DMA request and a descriptor physical address; each second address translation bypass buffer is used to cache a second mapping relationship, wherein each second mapping relationship includes a corresponding relationship between a target virtual address corresponding to a type of DMA request and a target physical address; wherein the descriptor in the memory module is used to store a target virtual address of a DMA request;

[0008] The control module is configured to: in response to receiving a DMA request, determine a descriptor physical address corresponding to the DMA request based on the first address translation bypass buffer;

[0009] Sending the DMA request to the memory module based on a descriptor physical address corresponding to the DMA request;

[0010] Receiving a descriptor corresponding to the DMA request returned by the memory module;

[0011] Determine a target physical address corresponding to the DMA request based on a target virtual address in the descriptor and a second address translation bypass buffer corresponding to the DMA request;

[0012] The DMA request is processed based on the target physical address.

[0013] In an embodiment of the present application, the data processing device also includes a queue module, which includes multiple queue units, each queue unit is used to cache DMA requests, the DMA requests in the same queue unit are of the same type, and the DMA requests in the same queue unit correspond to the same source address.

[0014] In an embodiment of the present application, the memory module is further configured to: store multiple descriptors in a storage space for storing descriptors corresponding to a same source address;

[0015] The memory module is further configured to determine the number of descriptors to be returned to the control module based on the size of the target data requested by the DMA request.

[0016] In the embodiment of the present application, the DMA request includes the following types: Magic request, Direct Write request, Infeed request, Outfeed request and Debug request;

[0017] There are two second address translation bypass buffers, and the two second address translation bypass buffers are used to cache the second mapping relationship corresponding to the Infeed request and the second mapping relationship corresponding to the Outfeed request respectively;

[0018] The data processing device is not provided with a second address translation bypass buffer corresponding to the Magic request, Direct Write request and Debug request.

[0019] In the embodiment of the present application, the queue module is further configured to: configure a first number of queue units for Infeed requests, configure a second number of queue units for Outfeed requests, configure a third number of queue units for Direct Write requests, and configure a fourth number of queue units for both Magic requests and Debug requests;

[0020] The first number is greater than the second number, the second number is greater than the third number, and the third number is greater than the fourth number.

[0021] In the embodiment of the present application, the control module is further configured to: when receiving the descriptor corresponding to the Magic request, the Direct Write request or the Debug request, search the page table based on the target virtual address in the descriptor to determine the target physical address corresponding to each DMA request.

[0022] The present application also proposes a data processing method, the method comprising:

[0023] receiving a DMA request, and determining a descriptor physical address corresponding to the DMA request based on a first address translation bypass buffer;

[0024] Sending the DMA request to a memory module based on a descriptor physical address corresponding to the DMA request;

[0025] Receiving a descriptor corresponding to the DMA request returned by the memory module;

[0026] Determine a target physical address corresponding to the DMA request based on a target virtual address in the descriptor and a second address translation bypass buffer corresponding to the DMA request;

[0027] Processing the DMA request based on the target physical address;

[0028] Among them, the first address translation bypass buffer is used to cache a first mapping relationship, which includes the source address of each DMA request and the correspondence between the physical address of the descriptor corresponding to each DMA request in the memory module; each second address translation bypass buffer is used to cache a second mapping relationship, and each second mapping relationship includes the correspondence between the target virtual address and the target physical address corresponding to a type of DMA request; the descriptor in the memory module is used to store the target virtual address of the DMA request.

[0029] In an embodiment of the present application, before receiving a DMA request and determining a descriptor physical address corresponding to the DMA request based on a first address translation bypass buffer, the method further includes:

[0030] A queue module is preconfigured, wherein the queue module includes a plurality of queue units; wherein DMA requests of the same type are configured in the same queue unit; and the DMA requests in the same queue unit are set with the same source address.

[0031] In the embodiment of the present application, multiple descriptors are stored in the storage descriptor physical address corresponding to the same source address;

[0032] The number of descriptors returned to the control module is determined based on the size of target data requested by the DMA request sent to the memory module.

[0033] In the embodiment of the present application, the DMA request includes the following types: Magic request, Direct Write request, Infeed request, Outfeed request and Debug request;

[0034] Before receiving a DMA request and determining a descriptor physical address corresponding to the DMA request based on a first address conversion bypass buffer, the data processing method further includes:

[0035] A second address translation bypass buffer is set for the Infeed request and the Outfeed request respectively to cache the second mapping relationship corresponding to the Infeed request and the Outfeed request respectively, and there is no need to set a second address translation bypass buffer for the Magic request, Direct Write request and Debug request.

[0036] In an embodiment of the present application, the pre-configured queue module includes:

[0037] A first number of queue units is configured for the Infeed request, a second number of queue units is configured for the Outfeed request, a third number of queue units is configured for the Direct Write request, and a fourth number of queue units is configured for both the Magic request and the Debug request; wherein the first number is greater than the second number, the second number is greater than the third number, and the third number is greater than the fourth number.

[0038] In the embodiment of the present application, after receiving the descriptor corresponding to the DMA request returned by the memory module, the method further includes:

[0039] When the descriptor corresponding to the Magic request, the Direct Write request or the Debug request is received, a page table is searched based on the target virtual address in the descriptor corresponding to each DMA request to determine the target physical address corresponding to each DMA request.

[0040] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements any of the above-described methods when executed by a processor.

[0041] An embodiment of the present application further provides a chip, which includes the data processing device described in any of the above embodiments.

[0042] In an embodiment of the present application, different second address translation bypass buffers are set according to the type of DMA request for the mapping relationship between the target virtual address and the target physical address corresponding to different types of DMA requests. When processing the DMA request, the target virtual address and the target physical address are converted based on the corresponding second address translation bypass buffer according to the type of DMA request. Since the second address translation bypass buffer corresponding to the DMA request caches the mapping relationship of the DMA request type and there is no mapping relationship corresponding to other DMA request types, the efficiency and success rate of traversing and searching for conversions are higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0044] Figure 1 This is a schematic diagram of an application scenario of a data processing device in an embodiment of the present application;

[0045] Figure 2 A schematic diagram of a memory module in an embodiment of the application;

[0046] Figure 3 is a schematic diagram of a first mapping relationship in an embodiment of the present application;

[0047] Figure 4 A schematic diagram of a first storage area in an embodiment of the present application;

[0048] Figure 5 is a schematic diagram of a queue module in an embodiment of the present application;

[0049] Figure 6 A schematic diagram of the correspondence between the first storage area and the second storage area in an embodiment of the present application;

[0050] Figure 7 A step diagram of a data processing method in an embodiment of the present application;

[0051] Figure 8A module diagram of a computer-readable storage medium in an embodiment of the present application.

[0052] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0053] The terms "including" and "having" in the specification and claims of the embodiments of the present application and the above-mentioned drawings and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or modules is not necessarily limited to those steps or modules clearly listed, but may include other steps or modules that are not clearly listed or inherent to these processes, methods, products or devices. The division of modules appearing in the embodiments of the present application is only a logical division. There may be other division methods when implemented in actual applications. For example, multiple modules can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling between modules, and the communication connection can be electrical or other similar forms, which are not limited in the embodiments of the present application. In addition, the modules or submodules described as separate components may or may not be physically separated, may or may not be physical modules, or may be distributed in multiple circuit modules, and some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiment of the present application.

[0054] The principles and spirit of the present application are explained in detail below with reference to several representative implementations of the present application.

[0055] Exemplary Devices

[0056] The present application proposes a data processing device, such as Figure 1 As shown, Figure 1 The present invention is a schematic diagram of an application scenario of a data processing device in an embodiment of the present application, wherein the data processing device is used in a host, the host is, for example, a computer, a CPU and a memory module are provided in the host, the CPU is a processor with processing functions, the memory module is a storage device with read and write functions, the control module can process access requests of external devices to the memory module in the host, for example, the control module can be a memory management unit (Memory Management Unit, ‌MMU), the external device is connected to the host through a PCIe communication protocol, the external device can be hardware deployed with an application, or refers to a device connected to a host other than the host, such as an input device (such as a keyboard, a mouse), an output device (such as a display, a printer) and an external storage device (such as a hard disk, a USB flash drive), etc.

[0057] Continue to refer to Figure 1, in an embodiment of the present application, the data processing device includes: a control module, a first address translation bypass buffer and a plurality of second address translation bypass buffers;

[0058] The first address translation bypass buffer is used to cache a first mapping relationship, wherein a first mapping relationship includes a corresponding relationship between a source address corresponding to a DMA request and a descriptor physical address; each second address translation bypass buffer is used to cache a second mapping relationship, wherein each second mapping relationship includes a corresponding relationship between a target virtual address corresponding to a type of DMA request and a target physical address; wherein the descriptor in the memory module includes a target virtual address of the DMA request;

[0059] The control module is configured to: in response to receiving a DMA request, determine a descriptor physical address corresponding to the DMA request based on the first address translation bypass buffer;

[0060] Sending the DMA request to the memory control module based on the descriptor physical address corresponding to the DMA request;

[0061] Receiving a descriptor corresponding to the DMA request returned by the memory module;

[0062] Determine a target physical address corresponding to the DMA request based on a target virtual address in the descriptor and a second address translation bypass buffer corresponding to the DMA request;

[0063] The DMA request is processed based on the target physical address.

[0064] In the embodiment of the present application, the data processing device is deployed on a host (such as a computer), and when an external device needs to access the memory module, it accesses the memory module through the data processing device.

[0065] In an embodiment of the present application, the control module can receive a DMA request initiated by an external device and forward it to the memory module based on each DMA request received; the address translation bypass buffer (Translation Lookaside Buffer, TLB) can be a buffer commonly used in the prior art for caching the mapping relationship between virtual addresses and physical addresses.

[0066] In an embodiment of the present application, when an external device needs to access a memory module, the host generates a target virtual address for the DMA request corresponding to the access. The target virtual address corresponds to a target physical address, and the target physical address is the physical address of the target data to be read by the DMA request in the memory module, or the physical address of the storage space to be written.

[0067] In the embodiment of the present application, the correspondence between the target virtual address and the target physical address is the second mapping relationship, and the second mapping relationship is cached in the second address translation bypass buffer. It should be noted that there are multiple second address translation bypass buffers, and the DMA request of the external device has multiple types. In the embodiment of the present application, the same second address translation bypass buffer is only used to cache the most recently used or commonly used second mapping relationship in the DMA request of the same type.

[0068] like Figure 2 As shown, in an embodiment of the present application, in order to ensure the security of data transmission, the memory module can be divided into a first storage area and a second storage area, wherein the first storage area is used to store the target virtual address corresponding to each DMA request, and the target virtual address corresponding to each DMA request is stored in the first storage area in the form of a descriptor, and the second storage area is used to store the data to be read by the read request in the DMA request, or to provide storage space for write data for the write request in each DMA request. When an external device initiates a DMA request, it is necessary to first obtain the target virtual address corresponding to the DMA request in the first storage area, and then query the target physical address corresponding to the target virtual address in the second address translation bypass buffer corresponding to the DMA request type.

[0069] In an embodiment of the present application, when an external device sends a DMA request, the control module generates a source address for each DMA request. The source address has a corresponding relationship with the descriptor of the target virtual address corresponding to the DMA request, and the physical address in the memory module, that is, the first mapping relationship. The first mapping relationship is cached in the first address translation bypass buffer.

[0070] like Figure 3 As shown, Figure 3 This is a schematic diagram of the first mapping relationship in an embodiment of the present application, which includes the correspondence between source addresses 1-n and descriptor physical addresses 1-n. For example, source address 1 corresponds to descriptor physical address 1, and source address 2 corresponds to descriptor physical address 2. When each external device initiates a DMA request, the control module will generate a source address for it, where different DMA requests can correspond to the same source address, and each source address corresponds to a descriptor physical address in the first mapping relationship. Figure 4 As shown, Figure 4 for Figure 3 A schematic diagram of the descriptors stored in each descriptor physical address in the first mapping relationship is shown, wherein each descriptor is stored in the first storage area of ​​the storage module, and multiple descriptors can be stored in the storage space corresponding to one descriptor physical address.

[0071] In an embodiment of the present application, when an external device initiates a DMA request, the control module determines the descriptor physical address corresponding to the source address based on the first mapping relationship according to the source address of the DMA request, and then sends a read request to the memory module according to the descriptor physical address. The memory module returns the descriptor corresponding to the DMA request to the control module based on the descriptor physical address in the DMA request. After receiving the returned descriptor, the control module obtains the target virtual address corresponding to the read request from the descriptor. Then, the control module queries the target physical address corresponding to the target virtual address based on the second address conversion bypass buffer corresponding to the DMA request type, thereby processing the DMA request based on the target physical address, for example, writing data to the target physical address or reading data from the target physical address.

[0072] In an embodiment of the present application, different second address translation bypass buffers are set according to the type of DMA request for the mapping relationship between the target virtual address and the target physical address corresponding to different types of DMA requests. When processing the DMA request, the target virtual address and the target physical address are converted based on the corresponding second address translation bypass buffer according to the type of DMA request. Since the second address translation bypass buffer corresponding to the DMA request caches the mapping relationship of the DMA request type and there is no mapping relationship corresponding to other DMA request types, the efficiency and success rate of traversing and searching for conversions are higher.

[0073] like Figure 2 As shown, in an embodiment of the present application, the data processing device also includes a queue module, which includes multiple queue units, each queue unit is used to cache DMA requests, the DMA requests in the same queue unit are of the same type, and the DMA requests in the same queue unit correspond to the same source address.

[0074] Generally speaking, a host is equipped with multiple external devices, and the multiple external devices run in parallel. In order to increase the operating speed of each external device, the embodiment of the present application sets a queue module in the data processing device to cache DMA requests issued by multiple external devices.

[0075] like Figure 5 As shown, in an embodiment of the present application, the queue module includes multiple queue units, each queue unit is used to cache DMA requests of the same type.

[0076] For example, in the embodiment of the present application, the DMA requests issued by each external device can be divided into:

[0077] Magic request refers to a call request to a specific interface when using the Magic-API framework in a programming or development environment.

[0078] Direct Write request refers to the request to read and write data directly from PGA (Process Global Area) to data files or temporary files when processing data, without going through SGA (System Global Area);

[0079] Infeed request refers to a request to write data from an external device to the host;

[0080] Outfeed request refers to the request to read data from the host;

[0081] Debug request refers to the process of debugging requests during software development, which is mainly used to track and locate problems in code execution.

[0082] Then, in the embodiment of the present application, the queue module may be provided with five queue units, which are respectively used to cache the second mapping relationships corresponding to the five types of DMA requests.

[0083] In addition, since different types of DMA requests are issued at different frequencies, for example, most of the DMA requests issued by external devices are Infeed requests and Outfeed requests, followed by Direct Write requests, and finally Magic requests and Debug requests, then, in the embodiment of the present application, the queue module can also be configured as follows: a first number of queue units are configured for Infeed requests, a second number of queue units are configured for Outfeed requests, a third number of queue units are configured for Direct Write requests, and a fourth number of queue units are configured for both Magic requests and Debug requests, the first number is greater than the second number, the second number is greater than the third number, and the third number is greater than the fourth number. That is, more queue units are set for DMA request types with higher issuance frequencies, and fewer queue units are set for DMA request types with lower issuance frequencies.

[0084] In an embodiment of the present application, the source addresses of each DMA request in the same queue unit are the same. For example, a queue source address can be generated for each queue unit, and the source addresses of the DMA requests located in the same queue unit are all set to the queue source address corresponding to the queue unit. When processing the DMA requests in each queue unit, the control module can search based on the first address conversion bypass buffer according to the queue source address corresponding to the queue unit currently being processed, and determine the descriptor physical address corresponding to the DMA request.

[0085] In addition, in the embodiment of the present application, a queue module is set, and when multiple queue units are set in the queue module, since the source addresses of the DMA requests in the same queue unit are all queue source addresses, that is, the first mapping relationship is the correspondence between the queue source address and the descriptor physical address, the first mapping relationship cached by the first address translation bypass buffer is the mapping relationship between the queue source address and the descriptor physical address. At this time, the storage address of the descriptor in the first storage area in the memory module can be maintained by the host, so that the first mapping relationship cached by the first address translation bypass buffer can remain unchanged. For example, the host can store the target virtual address generated for each DMA request in the corresponding descriptor, so as to keep the first mapping relationship unchanged.

[0086] In an embodiment of the present application, two second address translation bypass buffers are provided, and the two second address translation bypass buffer tables are respectively used to cache the second mapping relationship corresponding to the Infeed request and the second mapping relationship corresponding to the Outfeed request, and no corresponding second address translation bypass buffer is set for the Magic request, the Direct Write request and the Debug request.

[0087] Among them, most of the DMA requests issued by external devices are Infeed requests and Outfeed requests, while Magic requests, Direct Write requests and Debug requests are relatively few. The space used to set the address translation bypass buffer is limited, that is, if five address translation bypass buffers are set to cache the second mapping relationships corresponding to the five DMA request types respectively, then the space of the five address translation bypass buffers is relatively limited. For any DMA request type, the corresponding address translation bypass buffer can only cache a small number of commonly used mapping relationships, and the success rate of searching and converting virtual addresses and physical addresses based on them is low.

[0088] Therefore, in the embodiment of the present application, for the second mapping relationship corresponding to Magic request, Direct Write request and Debug request, the address translation bypass buffer is not used for caching, and the space used to set the address translation bypass buffer is all used to cache the second mapping relationship corresponding to Infeed request and the second mapping relationship corresponding to Outfeed request, so that the cache space of the address translation bypass buffer corresponding to Infeed and Outfeed requests can be increased. The address translation bypass buffer corresponding to Infeed request can cache more second mapping relationships corresponding to Infeed request, and the address translation bypass buffer corresponding to Outfeed request can cache more second mapping relationships corresponding to Outfeed request. Therefore, when converting the target virtual address and the target physical address, for Infeed and Outfeed requests whose initiation frequency is much higher than other types of DAM requests, the success rate is higher when searching and converting based on their respective corresponding address translation bypass buffers.

[0089] In an embodiment of the present application, when the second mapping relationship corresponding to the Magic request, Direct Write request and Debug request is not cached by the address translation bypass buffer, the control module does not need to search in the second address translation bypass buffer after receiving the descriptors corresponding to the Magic request, DirectWrite request and Debug request and determining the target virtual address. Instead, it can directly search in the page table based on the target virtual address in the descriptor to determine the target physical address corresponding to each DMA request.

[0090] In an embodiment of the present application, the memory control module is further configured to: determine the number of descriptors to be returned to the control module based on the size of the target data requested by the DMA request.

[0091] Among them, when the control module requests a descriptor from the memory module based on the physical address of the descriptor corresponding to the DMA request, the memory module can determine the size of the target data requested according to the DMA request, and the target data is stored in the memory module in the form of page frames, and the physical address of each page frame corresponds to a target virtual address in a descriptor. Therefore, based on the size of the target data requested by the DMA request, the memory module can determine the number of descriptors corresponding to the DMA request, and then return the corresponding number of descriptors to the control module.

[0092] For example, Figure 6 As shown, Figure 6 The corresponding relationship between the descriptor and the page frame of the memory module in an embodiment of the present application. The first storage area includes multiple descriptor physical addresses. Figure 6Taking descriptor physical address 1 as an example only, descriptor physical address 1 stores descriptors 1-7. In addition, descriptor physical address 1 corresponds to queue source address 1 and is stored in the first address translation bypass buffer. Assuming that the queue unit corresponding to queue source address 1 is queue unit A, when the control module receives a DMA request in queue unit A, it can be determined based on the first address translation bypass buffer that the physical address of the descriptor corresponding to queue source address 1 is descriptor physical address 1. Then the control module sends a DMA request to the memory module based on descriptor physical address 1. The DMA request includes the size of the requested target data. Assuming that the target data size is the size of three page frames, after receiving the DMA request sent by the control module, the memory module determines that the physical address of the descriptor requested by the DMA request is descriptor physical address 1, and then determines the starting target virtual address corresponding to the descriptor according to the DMA request. Assuming Set it as descriptor 3, and then according to the size of the target data, it is divided into three page frames, that is, three descriptors are needed. At this time, descriptors 3, 4, and 5 can be returned to the control module. After receiving descriptors 3, 4, and 5, the control module can determine the three virtual addresses contained in descriptors 3, 4, and 5, that is, the three target virtual addresses. Then the control module determines the second address translation bypass buffer according to the type of DMA request in queue unit A, and then searches for the three target physical addresses corresponding to the three target virtual addresses based on the second address translation bypass buffer, that is, the physical addresses corresponding to page frames 3, 4, and 5, and then reads the target data based on the physical addresses corresponding to page frames 3, 4, and 5, or writes the target data.

[0093] In an embodiment of the present application, different second address translation bypass buffers are set according to the mapping relationship between the target virtual address and the target physical address corresponding to different types of DMA requests according to the type of DMA request. When processing the DMA request, the target virtual address and the target physical address are converted based on the corresponding second address translation bypass buffer according to the type of DMA request. Since the corresponding second address translation bypass buffer caches the mapping relationship of the DMA request type and there is no mapping relationship corresponding to other DMA request types, the efficiency and success rate of traversing and searching for conversions are higher.

[0094] Exemplary Methods

[0095] like Figure 7 As shown, the present application also proposes a data processing method, which is applied to the data processing device in each embodiment of the above exemplary device, and the data processing method includes the following steps:

[0096] Step S100: receiving a DMA request, and determining a descriptor physical address corresponding to the DMA request based on a first address conversion bypass buffer.

[0097] Step S200: Sending the DMA request to a memory module based on the descriptor physical address corresponding to the DMA request.

[0098] Step S300: receiving a descriptor corresponding to the DMA request returned by the memory control module.

[0099] Step S400: Determine a target physical address corresponding to the DMA request based on the target virtual address in the descriptor and a second address translation bypass buffer corresponding to the DMA request.

[0100] Step S500: Processing the DMA request based on the target physical address.

[0101] The specific implementation methods of steps S100 - S500 refer to the various embodiments of the above-mentioned data processing device, which will not be described in detail here.

[0102] In the embodiment of the present application, the data processing method further includes:

[0103] Before receiving the DMA request and determining the descriptor physical address corresponding to the DMA request based on the first address translation bypass buffer, the method further includes:

[0104] A queue module is preconfigured, wherein the queue module includes a plurality of queue units; wherein DMA requests of the same type are configured in the same queue unit; and the DMA requests in the same queue unit are set with the same source address.

[0105] In the embodiment of the present application, multiple descriptors are stored in the storage descriptor physical address corresponding to the same source address;

[0106] The number of descriptors returned to the control module is determined based on the size of target data requested by the DMA request sent to the memory module.

[0107] In the embodiment of the present application, the DMA request includes the following types: Magic request, Direct Write request, Infeed request, Outfeed request and Debug request;

[0108] Before receiving a DMA request and determining a descriptor physical address corresponding to the DMA request based on a first address conversion bypass buffer, the data processing method further includes:

[0109] A second address translation bypass buffer is set for the Infeed request and the Outfeed request respectively to cache the second mapping relationship corresponding to the Infeed request and the Outfeed request respectively, and there is no need to set a second address translation bypass buffer for the Magic request, Direct Write request and Debug request.

[0110] In an embodiment of the present application, the pre-configured queue module includes:

[0111] A first number of queue units is configured for the Infeed request, a second number of queue units is configured for the Outfeed request, a third number of queue units is configured for the Direct Write request, and a fourth number of queue units is configured for both the Magic request and the Debug request; wherein the first number is greater than the second number, the second number is greater than the third number, and the third number is greater than the fourth number.

[0112] In the embodiment of the present application, after receiving the descriptor corresponding to the DMA request returned by the memory module, the method further includes:

[0113] When the descriptor corresponding to the Magic request, the Direct Write request or the Debug request is received, a page table is searched based on the target virtual address in the descriptor corresponding to each DMA request to determine the target physical address corresponding to each DMA request.

[0114] The data processing method of the embodiment of the present application is applied to the data processing device of any of the above embodiments, and therefore includes all the beneficial effects of the data processing device described in any of the above embodiments, which will not be elaborated here one by one.

[0115] Exemplary Media

[0116] After introducing the method and device of the exemplary embodiment of the present application, next, refer to Figure 8 For a description of the computer-readable storage medium of the exemplary embodiment of the present application, please refer to Figure 8, the computer-readable storage medium shown is a CD 70, on which a computer program (i.e., a program product) is stored. When the computer program is executed by the processor, it will implement the steps recorded in the above method implementation, for example, receiving a DMA request, and determining the descriptor physical address corresponding to the DMA request based on the first address translation bypass buffer; sending the DMA request to the memory module based on the descriptor physical address corresponding to the DMA request; receiving the descriptor corresponding to the DMA request returned by the memory module; determining the target physical address corresponding to the DMA request based on the target virtual address in the descriptor and the second address translation bypass buffer corresponding to the DMA request; and processing the DMA request based on the target physical address. The specific implementation of each step will not be repeated here. It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical or magnetic storage media, which are not listed here one by one.

[0117] Exemplary Chips

[0118] After introducing the apparatus, method, and medium according to the exemplary embodiments of the present application, next, a chip according to the exemplary embodiments of the present application will be introduced.

[0119] A chip is proposed in an embodiment of the present application, including the data processing device described in any of the above embodiments, and therefore has all the beneficial effects of the data processing device described in the above embodiments, which will not be described one by one here.

[0120] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

[0121] In addition, although the operations of the method of the present application are described in a specific order in the drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

Claims

1. A data processing device, comprising: A control module, a first address translation bypass buffer, and a plurality of second address translation bypass buffers; The first address translation bypass buffer is used to cache a first mapping relationship, wherein a first mapping relationship includes a corresponding relationship between a source address corresponding to a DMA request and a descriptor physical address; each second address translation bypass buffer is used to cache a second mapping relationship, wherein each second mapping relationship includes a corresponding relationship between a target virtual address corresponding to a type of DMA request and a target physical address; wherein the descriptor in the memory module is used to store a target virtual address of a DMA request; The control module is configured to: in response to receiving a DMA request, determine a descriptor physical address corresponding to the DMA request based on the first address translation bypass buffer; Sending the DMA request to the memory module based on a descriptor physical address corresponding to the DMA request; Receiving a descriptor corresponding to the DMA request returned by the memory module; Determine a target physical address corresponding to the DMA request based on a target virtual address in the descriptor and a second address translation bypass buffer corresponding to the DMA request; Processing the DMA request based on the target physical address; The DMA request includes the following types: Magic request, Direct Write request, Infeed request, Outfeed request and Debug request; There are two second address translation bypass buffers, and the two second address translation bypass buffers are used to cache the second mapping relationship corresponding to the Infeed request and the second mapping relationship corresponding to the Outfeed request respectively; The data processing device is not provided with a second address translation bypass buffer corresponding to the Magic request, Direct Write request and Debug request.

2. The data processing device as described in claim 1 further includes a queue module, wherein the queue module includes multiple queue units, each queue unit is used to cache DMA requests, the DMA requests in the same queue unit are of the same type, and the DMA requests in the same queue unit correspond to the same source address.

3. The data processing device according to claim 2, wherein the memory module is further configured to: store a plurality of descriptors in a storage space for storing descriptors corresponding to a same source address; The memory module is further configured to determine the number of descriptors to be returned to the control module based on the size of the target data requested by the DMA request.

4. The data processing device according to claim 2, wherein the queue module is further configured to: configure a first number of queue units for Infeed requests, configure a second number of queue units for Outfeed requests, configure a third number of queue units for Direct Write requests, and configure a fourth number of queue units for both Magic requests and Debug requests; The first number is greater than the second number, the second number is greater than the third number, and the third number is greater than the fourth number.

5. The data processing device as described in claim 1, wherein the control module is further configured to: when receiving a descriptor corresponding to the Magic request, the Direct Write request or the Debug request, search the page table based on the target virtual address in the descriptor to determine the target physical address corresponding to each DMA request.

6. A data processing method, the method comprising: receiving a DMA request, and determining a descriptor physical address corresponding to the DMA request based on a first address translation bypass buffer; Sending the DMA request to a memory module based on a descriptor physical address corresponding to the DMA request; Receiving a descriptor corresponding to the DMA request returned by the memory module; Determine a target physical address corresponding to the DMA request based on a target virtual address in the descriptor and a second address translation bypass buffer corresponding to the DMA request; Processing the DMA request based on the target physical address; The first address translation bypass buffer is used to cache a first mapping relationship, wherein the first mapping relationship includes a source address of each DMA request and a correspondence relationship between a descriptor corresponding to each DMA request and a physical address in a memory module; each second address translation bypass buffer is used to cache a second mapping relationship, wherein each second mapping relationship includes a correspondence relationship between a target virtual address and a target physical address corresponding to a type of DMA request; and the descriptor in the memory module is used to store a target virtual address of a DMA request; The DMA request includes the following types: Magic request, Direct Write request, Infeed request, Outfeed request and Debug request; Before receiving a DMA request and determining a descriptor physical address corresponding to the DMA request based on a first address conversion bypass buffer, the data processing method further includes: A second address translation bypass buffer is set for the Infeed request and the Outfeed request respectively to cache the second mapping relationship corresponding to the Infeed request and the Outfeed request respectively, and there is no need to set a second address translation bypass buffer for the Magic request, Direct Write request and Debug request.

7. The data processing method according to claim 6, before receiving a DMA request and determining the descriptor physical address corresponding to the DMA request based on the first address translation bypass buffer, the method further comprises: A queue module is preconfigured, wherein the queue module includes a plurality of queue units; wherein DMA requests of the same type are configured in the same queue unit; and the DMA requests in the same queue unit are set with the same source address.

8. The data processing method according to claim 7, wherein: Multiple descriptors are stored in the storage descriptor physical address corresponding to the same source address; The number of descriptors returned to the control module is determined based on the size of target data requested by the DMA request sent to the memory module.

9. The data processing method according to claim 7, wherein the pre-configured queue module comprises: A first number of queue units is configured for the Infeed request, a second number of queue units is configured for the Outfeed request, a third number of queue units is configured for the Direct Write request, and a fourth number of queue units is configured for both the Magic request and the Debug request; wherein the first number is greater than the second number, the second number is greater than the third number, and the third number is greater than the fourth number.

10. The data processing method according to claim 6, after receiving the descriptor corresponding to the DMA request returned by the memory module, the method further comprises: When the descriptor corresponding to the Magic request, the Direct Write request or the Debug request is received, a page table is searched based on the target virtual address in the descriptor corresponding to each DMA request to determine the target physical address corresponding to each DMA request.

11. A computer-readable storage medium comprising instructions, which, when executed on a computer, enables the computer to execute the data processing method according to any one of claims 6 to 10.

12. A chip, comprising the data processing device according to any one of claims 1 to 5.

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