High-speed interface signal detection circuit

Abstract

The invention discloses a high-speed interface signal detection circuit. An input signal of a differential comparison amplifier is amplified, and an output signal is converted into a signal D2S through a double-to-single amplifier; the signal D2S is reversed to form a signal RSTB to the low-pass filter, and the low-pass filter realizes a filtering function; if the differential comparison amplifier detects data '1', the state of the signal RSTB is' 0 ', the capacitor array is charged, and the voltage signal VLPF output by the low-pass filter is set to' 1 '; if the input of the differential comparison amplifier is always data '1', the voltage signal VLPF is kept at a high level '1', and when the input is switched to data '0', the state of the signal RSTB is' 1 ', and the voltage signal VLPF discharges through the current array; and selecting proper current and capacitance, and ensuring that the VLPF voltage is kept above the threshold voltage of the Schmitt trigger when the RSTB state is 1, so that the output of the Schmitt trigger is always at a high level, and the detection of an RX signal of a receiving end is realized. The circuit can be used in a high-speed mode and a low-speed mode, and is adaptive to various interface circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-speed interface signal detection circuit. Background Art

[0002] In high-speed serial interface circuit applications, when the transmitter TX no longer transmits data, the receiver RX is usually in power saving mode to save power; when the transmitter TX transmits data again, the receiver RX must be awakened again. Therefore, the receiver RX is usually configured with a signal detection module, whose function is to detect whether the transmitter TX of the upstream port is transmitting data, thereby waking up the receiver RX of the downstream port.

[0003] There are many implementation modes for the signal detection module of the receiving end RX, so there is an urgent need for a wide-band signal detector that is compatible with multiple working modes and adapts to multiple interface protocols. Summary of the invention

[0004] The object of the present invention is to provide a high-speed interface signal detection circuit to solve the problems in the background technology.

[0005] In order to solve the above technical problems, the present invention provides a high-speed interface signal detection circuit, which detects the data signal of the receiving end RX and outputs a high level, supports high and low frequency modes, The high-speed interface signal detection circuit includes: a differential comparison amplifier, a dual-to-single amplifier, a low-pass filter, and a Schmitt trigger; The input signals INP and INN of the differential comparator amplifier come from the receiving end RX, and after being amplified by the differential comparator amplifier, the output signals O1P and O1N are obtained. The signals O1P and O1N are converted into single-ended full-swing signals D2S through a dual-to-single amplifier; The single-ended full-swing signal D2S is inverted to form a signal RSTB and input to the low-pass filter. The low-pass filter realizes the filtering function by charging and discharging the capacitor array. If the differential comparator amplifier detects data "1", the signal RSTB state is "0", the capacitor array is charged, and the voltage signal VLPF output by the low-pass filter is set to "1". If the differential comparator amplifier input is always data "1", the voltage signal VLPF maintains a high level "1". When the input switches to data "0", the signal RSTB state is "1", and the voltage signal VLPF is discharged through the current array. When the appropriate current and capacitance are selected, it can be ensured that when the RSTB state is "1", the VLPF voltage remains above the threshold voltage of the Schmitt trigger, so that the Schmitt trigger output is always high, thereby realizing the detection of the RX signal at the receiving end.

[0006] In one embodiment, the differential comparison amplifier includes PMOS tubes MP1-MP2, resistors R1-R4, NMOS tubes MN1-MN4, two Hall switches HS, a limit switch LS, and two current sources; the dual-turn single amplifier includes PMOS tubes MP3-MP4 and NMOS tubes MN5-MN6; the low-pass filter includes PMOS tube MP5, a current array, and a capacitor array; The source end of the PMOS tube MP1 and the source end of the PMOS tube MP2 are both connected to the power supply voltage AVDD, the gate end of the PMOS tube MP1 is connected to the first end of the resistor R1 through a Hall switch HS, and the gate end of the PMOS tube MP2 is connected to the second end of the resistor R4 through another Hall switch HS; the drain end of the PMOS tube MP1 is simultaneously connected to the second end of the resistor R1 and the first end of the resistor R2, and the drain end of the PMOS tube MP2 is simultaneously connected to the second end of the resistor R3 and the first end of the resistor R4; the second end of the resistor R2 and the first end of the resistor R3 are connected via a limit switch LS; The gate terminal of the NMOS tube MN1 is connected to the signal INP, and the drain terminal is connected to the drain terminal of the PMOS tube MP1 and the drain terminal of the NMOS tube MN3 at the same time; the gate terminal of the NMOS tube MN2 is connected to the comparison threshold voltage VREFP, and the drain terminal is connected to the drain terminal of the PMOS tube MP2 and the drain terminal of the NMOS tube MN4 at the same time; the source terminal of the NMOS tube MN1 and the source terminal of the NMOS tube MN2 are both grounded through a current source; The gate terminal of the NMOS tube MN3 is connected to the comparison threshold voltage VREFN, and the drain terminal is connected to the gate terminal of the PMOS tube MP4; the gate terminal of the NMOS tube MN4 is connected to the signal INN, and the drain terminal is connected to the gate terminal of the PMOS tube MP3; the source terminal of the NMOS tube MN3 and the source terminal of the NMOS tube MN4 are both grounded through another current source; The source end of the PMOS tube MP3 and the source end of the PMOS tube MP4 are both connected to the power supply voltage AVDD, the drain end of the PMOS tube MP3 is connected to the drain end of the NMOS tube MN5, and the drain end of the PMOS tube MP4 is connected to the drain end of the NMOS tube MN6; the gate end of the NMOS tube MN5 is connected to its own drain end, and the source end is grounded to Vss, the gate end of the NMOS tube MN6 is connected to the gate end of the NMOS tube MN5, and the source end is grounded to Vss; The connection between the drain end of the PMOS tube MP4 and the drain end of the NMOS tube MN6 generates a D2S signal, which is connected to the gate end of the PMOS tube MP5 through an inverter INV. The source end of the PMOS tube MP5 is connected to the power supply voltage AVDD, and the drain end is connected to the current array and the capacitor array at the same time; the input end of the Schmitt trigger is connected to the drain end of the PMOS tube MP5, and the output end outputs the OUT signal.

[0007] In one embodiment, the input data of the receiving end RX is divided into two cases, "1" and "0". When the input data is "1", when INP-INN is greater than the comparison threshold voltage VREFP-VREFN of the differential comparator amplifier, the input is amplified and the signal D2S is at a "1" level; when the input is less than the comparison threshold voltage, the signal D2S is at a "0" level; when the input data is "0", the signal D2S is always at a "0" level; thereby realizing the detection of data "1".

[0008] The invention provides a high-speed interface signal detection circuit, which can quickly detect the signal sent by the upstream transmitter TX and report the detection result to the digital logic, thereby controlling the opening of the analog part of the interface circuit, and realizing the low-power working mode of the interface circuit. The detection circuit can effectively suppress the noise while detecting the high-frequency signal, thereby preventing the noise from false triggering, and can be used in both high-speed and low-speed modes, and is suitable for a variety of interface circuits. The circuit has simple functions, clear logic, is easy to implement, and is convenient to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 The present invention provides a high-speed interface signal detection circuit structure schematic diagram. DETAILED DESCRIPTION

[0010] The following is a further detailed description of a high-speed interface signal detection circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0011] The present invention provides a high-speed interface signal detection circuit, the structure of which is as follows Figure 1 As shown, INP / INN is the signal from the receiving end RX, VREF / VREN is the comparison threshold voltage. This circuit detects the data signal of the receiving end RX and outputs a high level, supporting high and low frequency modes. The specific functions are described as follows: The circuit is divided into four functional modules, namely differential comparison amplifier, dual-to-single amplifier, low-pass filter, and Schmitt trigger. The differential comparison amplifier includes PMOS tubes MP1~MP2, resistors R1~R4, NMOS tubes MN1~MN4, two Hall switches HS, limit switch LS, and two current sources; the dual-to-single amplifier includes PMOS tubes MP3~MP4, NMOS tubes MN5~MN6; the low-pass filter includes PMOS tube MP5, current array, and capacitor array.

[0012] The source end of the PMOS tube MP1 and the source end of the PMOS tube MP2 are both connected to the power supply voltage AVDD, the gate end of the PMOS tube MP1 is connected to the first end of the resistor R1 through a Hall switch HS, and the gate end of the PMOS tube MP2 is connected to the second end of the resistor R4 through another Hall switch HS; the drain end of the PMOS tube MP1 is simultaneously connected to the second end of the resistor R1 and the first end of the resistor R2, and the drain end of the PMOS tube MP2 is simultaneously connected to the second end of the resistor R3 and the first end of the resistor R4; the second end of the resistor R2 and the first end of the resistor R3 are connected through a limit switch LS. The gate end of the NMOS tube MN1 is connected to the signal INP, and the drain end is simultaneously connected to the drain end of the PMOS tube MP1 and the drain end of the NMOS tube MN3; the gate end of the NMOS tube MN2 is connected to the comparison threshold voltage VREFP, and the drain end is simultaneously connected to the drain end of the PMOS tube MP2 and the drain end of the NMOS tube MN4; the source end of the NMOS tube MN1 and the source end of the NMOS tube MN2 are both grounded through a current source. The gate terminal of the NMOS tube MN3 is connected to the comparison threshold voltage VREFN, and the drain terminal is connected to the gate terminal of the PMOS tube MP4; the gate terminal of the NMOS tube MN4 is connected to the signal INN, and the drain terminal is connected to the gate terminal of the PMOS tube MP3; the source terminal of the NMOS tube MN3 and the source terminal of the NMOS tube MN4 are both grounded through another current source. The source terminal of the PMOS tube MP3 and the source terminal of the PMOS tube MP4 are both connected to the power supply voltage AVDD, the drain terminal of the PMOS tube MP3 is connected to the drain terminal of the NMOS tube MN5, and the drain terminal of the PMOS tube MP4 is connected to the drain terminal of the NMOS tube MN6; the gate terminal of the NMOS tube MN5 is connected to its own drain terminal, and the source terminal is grounded to Vss, and the gate terminal of the NMOS tube MN6 is connected to the gate terminal of the NMOS tube MN5, and the source terminal is grounded to Vss. The connection between the drain end of the PMOS tube MP4 and the drain end of the NMOS tube MN6 generates a D2S signal, which is connected to the gate end of the PMOS tube MP5 through an inverter INV. The source end of the PMOS tube MP5 is connected to the power supply voltage AVDD, and the drain end is connected to the current array and the capacitor array at the same time; the input end of the Schmitt trigger is connected to the drain end of the PMOS tube MP5, and the output end outputs the OUT signal.

[0013] When the Hall switch HS is closed and the limit switch LS is disconnected, the resistor R1, the PMOS tube MP1 and the resistor R4, the PMOS tube MP2 are equivalent to an active inductor, which can widen the bandwidth of the comparator and is used in the high-speed working mode; when the limit switch LS is closed and the Hall switch HS is disconnected, the comparator bandwidth is relatively narrow and is used in the low-speed working mode.

[0014] The input signal INP / INN of the differential comparator amplifier comes from the receiving end RX. Since the amplitude of the signal received by the receiving end RX is attenuated, it must first be amplified by the differential comparator amplifier and output O1P / O1N; then it is converted into a single-ended full-swing signal D2S through a double-to-single amplifier. The input data is divided into two cases: "1" and "0". When the input data is "1", that is, the differential input INP-INN>0, when INP-INN is greater than the comparison threshold voltage VREFP-VREFN of the differential comparator amplifier, the input is amplified, and D2S outputs a "1" level. When the input data is "0", that is, the differential input INP-INN<0, the D2S output is always a "0" level. Thus, the detection of data "1" is realized. D2S is inverted to form a signal RSTB input to the low-pass filter, and the low-pass filter realizes the filtering function by charging and discharging the capacitor array. Once the differential comparator amplifier detects data "1", the RSTB state is "0", and the capacitor array is charged by controlling the opening of the PMOS tube MP5. The voltage signal VLPF output by the low-pass filter is quickly set to "1". When the differential comparator amplifier input is always data "1", the voltage signal VLPF maintains a high level "1". When the input switches to data "0", the RSTB state is "1", and the PMOS tube MP5 is turned off and maintained for a period of time. At this time, the voltage signal VLPF will discharge through the current array. When the appropriate current and capacitance size are selected, it can be ensured that during the shutdown period of the PMOS tube MP5, the VLPF voltage remains above the threshold voltage of the Schmitt trigger, so that the Schmitt trigger output is always high. This realizes the detection of the receiving end RX signal.

[0015] The circuit of the present invention supports two working modes, a low-speed working mode (LS) and a high-speed working mode (HS). In the low-speed working mode, the LS switch is closed, the HS switch is opened, and the first-stage differential comparison amplifier works in a high-gain and low-bandwidth mode. In the high-speed working mode, the HS switch is closed, the LS switch is opened, the gate-end parasitic capacitance of the load tube of the first-stage differential comparison amplifier is connected in series with the resistor to form an inductive inductor, and a zero point is added to the output end of the differential comparison amplifier, thereby increasing the bandwidth of the differential comparison amplifier, so that the differential comparison amplifier works in a low-gain and high-bandwidth mode.

[0016] The signal detection circuit provided by the present invention has a simple circuit structure, and realizes high-speed and low-speed working modes only by changing the connection mode of the gate terminal resistance of the load tube of the first-stage differential comparison amplifier, which has a great advantage over the detection circuit that can only work at low frequency. The present invention has a good anti-noise function through the setting of the threshold voltage of the differential comparison amplifier, which can prevent false triggering by noise; the low-pass filter adopts a non-traditional approach to save area, and the capacitor and current array provide a variety of low-pass filter bandwidth options, so that it can adapt to interface circuits of various rates, enhancing the applicability of the circuit.

[0017] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A high-speed interface signal detection circuit, characterized in that: Detect the data signal of the receiving end RX and output a high level, supporting high and low frequency modes. The high-speed interface signal detection circuit includes: a differential comparison amplifier, a dual-to-single amplifier, a low-pass filter, and a Schmitt trigger; The input signals INP and INN of the differential comparator amplifier come from the receiving end RX, and after being amplified by the differential comparator amplifier, the output signals O1P and O1N are obtained. The signals O1P and O1N are converted into single-ended full-swing signals D2S through a dual-to-single amplifier; The single-ended full-swing signal D2S is inverted to form a signal RSTB and input to the low-pass filter. The low-pass filter realizes the filtering function by charging and discharging the capacitor array. If the differential comparator amplifier detects data "1", the signal RSTB state is "0", the capacitor array is charged, and the voltage signal VLPF output by the low-pass filter is set to "1". If the differential comparator amplifier input is always data "1", the voltage signal VLPF maintains a high level "1". When the input switches to data "0", the signal RSTB state is "1", and the voltage signal VLPF is discharged through the current array. When the appropriate current and capacitance are selected, it can be ensured that when the RSTB state is "1", the VLPF voltage remains above the threshold voltage of the Schmitt trigger, so that the Schmitt trigger output is always high, thereby realizing the detection of the RX signal at the receiving end.

2. The high-speed interface signal detection circuit according to claim 1, characterized in that: The differential comparison amplifier includes PMOS tubes MP1-MP2, resistors R1-R4, NMOS tubes MN1-MN4, two Hall switches HS, a limit switch LS, and two current sources; the dual-turn single amplifier includes PMOS tubes MP3-MP4 and NMOS tubes MN5-MN6; the low-pass filter includes PMOS tube MP5, a current array, and a capacitor array; The source end of the PMOS tube MP1 and the source end of the PMOS tube MP2 are both connected to the power supply voltage AVDD, the gate end of the PMOS tube MP1 is connected to the first end of the resistor R1 through a Hall switch HS, and the gate end of the PMOS tube MP2 is connected to the second end of the resistor R4 through another Hall switch HS; the drain end of the PMOS tube MP1 is simultaneously connected to the second end of the resistor R1 and the first end of the resistor R2, and the drain end of the PMOS tube MP2 is simultaneously connected to the second end of the resistor R3 and the first end of the resistor R4; the second end of the resistor R2 and the first end of the resistor R3 are connected via a limit switch LS; The gate terminal of the NMOS tube MN1 is connected to the signal INP, and the drain terminal is connected to the drain terminal of the PMOS tube MP1 and the drain terminal of the NMOS tube MN3 at the same time; the gate terminal of the NMOS tube MN2 is connected to the comparison threshold voltage VREFP, and the drain terminal is connected to the drain terminal of the PMOS tube MP2 and the drain terminal of the NMOS tube MN4 at the same time; the source terminal of the NMOS tube MN1 and the source terminal of the NMOS tube MN2 are both grounded through a current source; The gate terminal of the NMOS tube MN3 is connected to the comparison threshold voltage VREFN, and the drain terminal is connected to the gate terminal of the PMOS tube MP4; the gate terminal of the NMOS tube MN4 is connected to the signal INN, and the drain terminal is connected to the gate terminal of the PMOS tube MP3; the source terminal of the NMOS tube MN3 and the source terminal of the NMOS tube MN4 are both grounded through another current source; The source end of the PMOS tube MP3 and the source end of the PMOS tube MP4 are both connected to the power supply voltage AVDD, the drain end of the PMOS tube MP3 is connected to the drain end of the NMOS tube MN5, and the drain end of the PMOS tube MP4 is connected to the drain end of the NMOS tube MN6; the gate end of the NMOS tube MN5 is connected to its own drain end, and the source end is grounded to Vss, the gate end of the NMOS tube MN6 is connected to the gate end of the NMOS tube MN5, and the source end is grounded to Vss; The connection between the drain end of the PMOS tube MP4 and the drain end of the NMOS tube MN6 generates a D2S signal, which is connected to the gate end of the PMOS tube MP5 through an inverter INV. The source end of the PMOS tube MP5 is connected to the power supply voltage AVDD, and the drain end is connected to the current array and the capacitor array at the same time; the input end of the Schmitt trigger is connected to the drain end of the PMOS tube MP5, and the output end outputs the OUT signal.

3. The high-speed interface signal detection circuit according to claim 1, characterized in that: The input data of the receiving end RX is divided into two cases, "1" and "0". When the input data is "1", when INP-INN is greater than the comparison threshold voltage VREFP-VREFN of the differential comparator amplifier, the input is amplified and the signal D2S is at a "1" level; when the input is less than the comparison threshold voltage, the signal D2S is at a "0" level; when the input data is "0", the signal D2S is always at a "0" level; thereby realizing the detection of the data "1".

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