Time synchronization method, chip and computer equipment

Abstract

The embodiment of the invention discloses a time synchronization method, a chip and computer equipment, and belongs to the technical field of computers. The method is applied to the chip, the chip comprises a first function module, a second function module and an on-chip bus, the first function module and the second function module are electrically connected with the on-chip bus, and the first function module is electrically connected with the second function module. The first function module obtains the transmission delay of the electric connection with the second function module; the first function module sends a time synchronization request to the second function module through electric connection, and the second function module receives the time synchronization request and updates local timing of the second function module based on a first time point carried by the time synchronization request. According to the embodiment of the invention, the method does not need to carry out the time synchronization through an on-chip total chip, can guarantee the accuracy of the time synchronization among a plurality of function modules, and improves the usability and efficiency of a chip.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a time synchronization method, chip, and computer device. Background Art

[0002] A chip is an integrated circuit that integrates multiple modules such as a processor, a memory, and an input / output interface. The multiple modules contained in the chip are electrically connected to an on-chip bus, and the multiple modules can communicate through the electrical connection with the on-chip bus. However, since the management module in the chip needs to process the information of other modules according to the sending time of each message, once the time sequence is disordered, it may cause the operation of the chip to malfunction. However, at present, the sending time of each message is determined by the transmission delay of the on-chip bus. However, the transmission delay of the on-chip bus is not fixed and depends on the current busyness of the on-chip bus, resulting in poor accuracy of the determined sending time. Summary of the invention

[0003] The embodiment of the present application provides a time synchronization method, chip and computer device, which can ensure the accuracy of time synchronization between multiple functional modules. The technical solution is as follows:

[0004] On the one hand, a time synchronization method is provided, which is applied to a chip, wherein the chip includes a first functional module, a second functional module and an on-chip bus, wherein the first functional module and the second functional module are both electrically connected to the on-chip bus, and the first functional module is electrically connected to the second functional module, and the method includes:

[0005] When the chip is powered on, the first functional module acquires a transmission delay of an electrical connection with the second functional module;

[0006] The first functional module sends a time synchronization request to the second functional module through the electrical connection, the time synchronization request carries a first time point, the first time point is the sum of the second time point and the transmission delay, and the second time point indicates the local timing when the first functional module sends the time synchronization request;

[0007] The second functional module receives the time synchronization request, and updates the local timing of the second functional module based on the first time point carried in the time synchronization request.

[0008] On the other hand, a schematic diagram of the structure of a chip is provided, the chip comprising a first functional module, a second functional module and an on-chip bus, the first functional module and the second functional module are both electrically connected to the on-chip bus, and the first functional module is electrically connected to the second functional module;

[0009] The first functional module is configured to obtain a transmission delay of an electrical connection with the second functional module when the chip is powered on; send a time synchronization request to the second functional module through the electrical connection, wherein the time synchronization request carries a first time point, the first time point is a sum of a second time point and the transmission delay, and the second time point indicates a local timing when the first functional module sends the time synchronization request;

[0010] The second functional module is configured to receive the time synchronization request, and update the local timing of the second functional module based on the first time point carried in the time synchronization request.

[0011] In a possible implementation, the first functional module is configured to send a delay determination request to the second functional module through the electrical connection when the chip is powered on, the delay determination request carrying a third time point, the third time point indicating a local timing when the first functional module sends the delay determination request;

[0012] The second functional module is further configured to receive the delay determination request and send the third time point to the first functional module;

[0013] The first functional module is used to receive the third time point, and determine the transmission delay based on the difference between a fourth time point and the third time point, wherein the fourth time point indicates the local timing when the first functional module receives the third time point.

[0014] In another possible implementation, the second functional module is further configured to send a processing request to the first functional module, where the processing request carries a sending time point, and the sending time point indicates a local timing when the second functional module sends the processing request;

[0015] The first functional module is further configured to receive a processing request sent by the second functional module, and in the case of receiving multiple processing requests, respond to the multiple processing requests in the order of the sending time points carried by the multiple processing requests.

[0016] In another possible implementation, the local timings of the second functional module and the first functional module are both represented by a time code of the first digit; the sending time point is represented by a time code of the second digit of the local timing when the second functional module sends the processing request, and the second digit is smaller than the first digit;

[0017] The first functional module is further used to determine a third time code of the processing request based on the first time code and the second time code, the first time code indicating the time code of the second digit carried by the processing request, the second time code and the third time code are both time codes of the first digit, the second time code indicates the local timing when the first functional module receives the processing request, and the third time code indicates the local timing when the second functional module sends the processing request; and respond to the multiple processing requests based on the order of the third time codes of the multiple processing requests.

[0018] In another possible implementation, the first functional module is used to replace the time code of the second last digit in the first time code with the first time code when the first time code is not greater than the time code of the second last digit in the first time code, so as to obtain the third time code of the processing request; and to replace the time code of the second last digit in the first time code with the first time code when the first time code is greater than the time code of the second last digit in the first time code, and determine the difference between the replaced time code and the time interval as the third time code of the processing request.

[0019] In another possible implementation, the second functional module is used to send the processing request to the first functional module through the on-chip bus when the data amount of the processing request is not less than a threshold; or, when the data amount of the processing request is less than the threshold, the second functional module sends the processing request to the first functional module through an electrical connection between the second functional module and the first functional module.

[0020] In another possible implementation, the second functional module is used to send the processing request to the first functional module through the on-chip bus when the processing request belongs to a first request type; or, when the processing request belongs to a second request type, the second functional module sends the processing request to the first functional module through an electrical connection between the first functional module and the first request type, and the first request type is different from the second request type.

[0021] In another possible implementation, the second functional module is configured to send the processing request to the on-chip bus through an electrical connection between the second functional module and the on-chip bus;

[0022] The on-chip bus is used to send the processing request to the first functional module through an electrical connection with the first functional module.

[0023] In another possible implementation, the first functional module is electrically connected to the second functional module via a serial communication bus.

[0024] On the other hand, a computer device is provided, which includes a chip, the chip includes a processor and a memory, the memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the operations performed by the time synchronization method described in the above aspects.

[0025] In the solution provided in the embodiment of the present application, the first functional module and the second functional module included in the chip are not only electrically connected to the online bus, but an additional electrical connection is added between the first functional module and the second functional module. The electrical connection is a single-shared communication link, which can only realize the interaction between the first functional module and the second functional module, and will not be interfered by the communication of other modules. The electrical connection has a fixed transmission delay, so that when the chip is powered on, the first functional module and the second functional module interact through the electrical connection between them using the transmission delay of the electrical connection to achieve time synchronization between the first functional module and the second functional module. There is no need to use the on-chip master chip for time synchronization, and the accuracy of time synchronization between multiple functional modules can be guaranteed, so that the functional modules included in the chip can subsequently interact based on the synchronized time to ensure the normal operation of the chip, thereby improving the ease of use and efficiency of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 is a schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0028] Figure 2 is a flow chart of a time synchronization method provided by an embodiment of the present application;

[0029] Figure 3 is a flowchart of another time synchronization method provided by an embodiment of the present application;

[0030] Figure 4 is a flowchart of another time synchronization method provided by an embodiment of the present application;

[0031] Figure 5 is a schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0032] Figure 6 is a schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0033] Figure 7 is a flowchart of another time synchronization method provided by an embodiment of the present application;

[0034] Figure 8 is a flowchart of another time synchronization method provided by an embodiment of the present application;

[0035] Fig. 9 is a schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0036] Fig.10 is a schematic diagram of the structure of a terminal provided in an embodiment of the present application;

[0037] Fig.11 It is a structural diagram of a server provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0039] The terms "first", "second", "third", "fourth", etc. used in this application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, a first time point may be referred to as a second time point, and similarly, a second time point may be referred to as a first time point without departing from the scope of this application.

[0040] The terms "at least one", "a plurality", "each", and "any" used in this application include one, two or more than two, a plurality includes two or more than two, each refers to each of the corresponding plurality, and any refers to any one of the plurality. For example, the plurality of processing requests include three processing requests, and each refers to each of the three processing requests, and any refers to any one of the three processing requests, which can be the first processing request, the second processing request, or the third processing request.

[0041] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions. For example, the requests or other information transmitted between the various functional modules in the chip involved in this application are all obtained with full authorization.

[0042] The time synchronization method provided in the embodiment of the present application is applied to a chip, wherein the chip includes a first functional module, a second functional module and an on-chip bus, wherein the first functional module and the second functional module are both electrically connected to the on-chip bus, and the first functional module is electrically connected to the second functional module. In some embodiments, the chip is disposed in a computer device. Optionally, the computer device is a terminal or a server. Optionally, the server is an independent physical server, or a server cluster or distributed system consisting of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. Optionally, the terminal is a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, an intelligent voice interaction device, a smart home appliance, and a vehicle-mounted terminal, but is not limited thereto.

[0043] Figure 1 Schematic diagram of the structure of a chip provided in an embodiment of the present application. Figure 1 As shown, the chip includes a first functional module 101, a second functional module 102 and an on-chip bus 103. The first functional module 101 and the second functional module 102 are both electrically connected to the on-chip bus 103, and the first functional module 101 is electrically connected to the second functional module 102.

[0044] The first functional module 101 can interact with the second functional module 102 through the electrical connection between the first functional module 101 and the second functional module 102, or the second functional module 102 can interact with the second functional module 102 through the on-chip bus 103. When the chip is powered on, the local timing of the first functional module 101 is started, and the local timing of the second functional module 102 can be updated through the electrical connection between the first functional module 101 and the second functional module 102, so that the local timings of the first functional module 101 and the second functional module 102 are synchronized.

[0045] In some embodiments, the chip includes multiple second functional modules 102, and the first functional module 102 is electrically connected to each second functional module 102. For each second functional module 102, in accordance with the above-mentioned manner, the first functional module 102 interacts with each second functional module 102 through the electrical connection between the first functional module 102 to update the local timing of each second functional module 102 so as to synchronize the local timing of the first functional module 101 with that of each second functional module 102.

[0046] Figure 2 : is a flow chart of a time synchronization method provided by an embodiment of the present application, which is applied to a chip, wherein the chip includes a first functional module, a second functional module and an on-chip bus, wherein the first functional module and the second functional module are both electrically connected to the on-chip bus, and the first functional module is electrically connected to the second functional module, such as Figure 2 As shown, the method includes:

[0047] 201. When the chip is powered on, the first functional module obtains a transmission delay of the electrical connection between the first functional module and the second functional module.

[0048] In an embodiment of the present application, the first functional module and the second functional module are both electrically connected to the on-chip bus, and the first functional module and the second functional module can interact through the on-chip bus. For example, when the second functional module sends information to the first functional module through the on-chip bus, the second functional module sends information to the on-chip bus through the electrical connection between the on-chip bus, and the on-chip bus sends the information to the first functional module through the electrical connection between the first functional module. In addition, there is also a separate electrical connection between the first functional module and the second functional module, which is a single-shared communication link between the first functional module and the second functional module, that is, the electrical connection can only realize the interaction between the first functional module and the second functional module, and will not be interfered by the communication of other modules, so the first functional module can also interact through the electrical connection between the second functional module.

[0049] In an embodiment of the present application, the electrical connection between the first functional module and the second functional module can be realized by any communication line. Since the communication line has a fixed transmission delay and the communication line is only used to realize the interaction between the first functional module and the second functional module, the electrical connection between the first functional module and the second functional module has a fixed transmission delay. Therefore, the first functional module will obtain the transmission delay of the electrical connection between the first functional module and the second functional module so that the influence of the transmission delay can be taken into account in the subsequent time synchronization, thereby ensuring the accuracy of the subsequent time synchronization.

[0050] Among them, the transmission delay is used to indicate the delay when the first functional module and the second functional module interact through the electrical connection between them. For example, the first functional module sends a certain information to the second functional module through the electrical connection between the first functional module and the second functional module. The difference between the time point when the second functional module receives the information and the time point when the first functional module sends the information is the transmission delay of the electrical connection. The first functional module is an arbitrary functional module. For example, the first functional module is a management module in a chip, and the management module is used to manage the second functional module in the chip. The second functional module is an arbitrary functional module. For example, the second functional module is a processing module, an interface module, a storage module, etc. in a chip. The chip is any type of chip. For example, the chip is a SOC (System On Chip). The on-chip bus in the chip is a shared data path. The multiple functional modules contained in the chip are all electrically connected to the on-chip bus, so the multiple functional modules contained in the chip can interact through the on-chip bus.

[0051] 202. The first functional module sends a time synchronization request to the second functional module through an electrical connection. The time synchronization request carries a first time point, where the first time point is the sum of the second time point and a transmission delay. The second time point indicates a local timing when the first functional module sends the time synchronization request.

[0052] In the embodiment of the present application, when the chip is powered on, the local timing of the first functional module will start, and the local timing of the first functional module will change over time. Since there is a transmission delay in the electrical connection between the first functional module and the second functional module, that is, after the first functional module sends a time synchronization request to the second functional module, the second functional module can only receive it after a period of time, and this period of time is the transmission delay. Therefore, when the first functional module sends a time synchronization request to the second functional module through the electrical connection between the first functional module and the second functional module, the influence of the transmission delay of the electrical connection is taken into account, and therefore, the time point when the second functional module receives the time synchronization request, that is, the first time point, is predicted, so that the second functional module can realize the local timing synchronization of the first functional module and the second functional module based on the first time point.

[0053] For example, when the first functional module sends a time synchronization request to the second functional module through the electrical connection between the first functional module and the second functional module, the local timing is T, and the transmission delay of the electrical connection between the first functional module and the second functional module is 20 clock cycles. Then, the first time point carried by the time synchronization request sent to the second functional module is T+20.

[0054] 203. The second functional module receives the time synchronization request, and updates the local timing of the second functional module based on the first time point carried in the time synchronization request.

[0055] In an embodiment of the present application, when the second functional module receives a time synchronization request, the local timing of the first functional module is the first time point. Therefore, the second functional module updates the local timing of the second functional module based on the first time point, that is, the current time point of the local timing of the second functional module is set to the first time point, and the timing continues from the first time point to synchronize the local timing of the first functional module with the local timing of the second functional module.

[0056] In the solution provided in the embodiment of the present application, the first functional module and the second functional module included in the chip are not only electrically connected to the online bus, but an additional electrical connection is added between the first functional module and the second functional module. The electrical connection is a single-shared communication link, which can only realize the interaction between the first functional module and the second functional module, and will not be interfered by the communication of other modules. The electrical connection has a fixed transmission delay, so that when the chip is powered on, the first functional module and the second functional module interact through the electrical connection between them using the transmission delay of the electrical connection to achieve time synchronization between the first functional module and the second functional module. There is no need to use the on-chip master chip for time synchronization, and the accuracy of time synchronization between multiple functional modules can be guaranteed, so that the functional modules included in the chip can subsequently interact based on the synchronized time to ensure the normal operation of the chip, thereby improving the ease of use and efficiency of the chip.

[0057] exist Figure 2 On the basis of the illustrated embodiment, in an embodiment of the present application, the first functional module can interact with the second functional module to determine the transmission delay of the electrical connection, and the specific process is detailed in the following embodiment.

[0058] Figure 3 : is a flow chart of a time synchronization method provided by an embodiment of the present application, which is applied to a chip, wherein the chip includes a first functional module, a second functional module and an on-chip bus, wherein the first functional module and the second functional module are both electrically connected to the on-chip bus, and the first functional module is electrically connected to the second functional module, such as Figure 3 As shown, the method includes:

[0059] 301. When the chip is powered on, the first functional module sends a delay determination request to the second functional module through the electrical connection between the first functional module and the second functional module. The delay determination request carries a third time point, and the third time point indicates the local timing when the first functional module sends the delay determination request.

[0060] In an embodiment of the present application, when the chip is powered on, the first functional module interacts with the second functional module through the electrical connection between the first functional module and the second functional module to update the local timing of the second functional module. However, in order to ensure the accuracy of time synchronization, an interactive method is first adopted to determine the transmission delay of the electrical connection between the first functional module and the second functional module.

[0061] The third time point is the local time point when the first functional module sends the delay determination request. For example, when the first functional module sends the delay determination request to the second functional module, the local time point of the first functional module is 10:10, then the third time point is 10:10.

[0062] In one possible implementation, the chip includes a first functional module and a plurality of second functional modules, each of the second functional modules is electrically connected to an on-chip bus, and the first functional module is electrically connected to each of the second functional modules. For example, the first functional module is a management module, and the plurality of second functional modules include a processing module, an interface module, a storage module, etc.

[0063] In one possible implementation, the first functional module is electrically connected to the second functional module via a serial communication bus. The serial communication bus can be any communication bus, for example, the serial communication bus is SPI (Serial Peripheral Interface, a serial communication bus), IIC (Inter-Integrated Circuit, a serial communication bus), UART (Universal Asynchronous Receiver / Transmitter protocol, a serial communication protocol), etc. In an embodiment of the present application, the electrical connection between the first functional module and the second functional module is realized through a serial communication bus, so that the serial communication bus serves as a single-shared communication link between the first functional module and the second functional module, which can ensure that the first functional module and the second functional module can communicate and the communication is stable.

[0064] In a possible implementation, once the chip is powered on, the first functional module immediately sends a delay determination request to the second functional module through the electrical connection between the first functional module and the second functional module.

[0065] In one possible implementation, step 301 includes: when the chip is powered on, the first functional module queries the transmission delay of the electrical connection between the first functional module and the second functional module, and if the transmission delay of the electrical connection between the first functional module and the second functional module is not found, a delay determination request is sent to the second functional module.

[0066] In an embodiment of the present application, the chip may store the transmission delay of the electrical connection between each functional module. Therefore, when the chip is powered on, the first functional module preferentially queries whether the transmission delay of the electrical connection between the first functional module and the second functional module is stored. Only when the transmission delay of the electrical connection with the second functional module is not found, a delay determination request is sent to the second functional module, so as to interact with the second functional module and further determine the transmission delay of the electrical connection with the second functional module.

[0067] Optionally, the transmission delay stored in the chip is stored after being input when the chip is manually set, or is stored after the transmission delay of the electrical connection between the first functional module and the second functional module is historically determined.

[0068] In the embodiment of the present application, when the chip is manually set, the transmission delay is input into the chip so that the chip can store it. Alternatively, each time the chip is powered on, the first functional module will obtain the transmission delay of the electrical connection with the second functional module. When the chip is powered on before the current chip is powered on, the first functional module will obtain the transmission delay of the electrical connection with the second functional module and store the transmission delay in the chip. When the chip is powered on at other times, the first functional module will obtain the transmission delay of the electrical connection with the second functional module from the stored transmission delay.

[0069] Optionally, the transmission delay is stored in the first functional module, or the second functional module in the chip includes a storage module, and the transmission delay is stored in the storage module.

[0070] In an embodiment of the present application, the transmission delay is stored in a storage module included in the chip. When the chip is powered on, the first functional module interacts with the storage module to query whether the transmission delay of the electrical connection with the second functional module is stored.

[0071] 302. The second functional module receives the delay determination request and sends a third time point to the first functional module.

[0072] In an embodiment of the present application, the delay determination request is used to determine the transmission delay of the electrical connection between the first functional module and the second functional module. After receiving the delay determination request, the second functional module sends a third time point to the first functional module so that the first functional module determines the transmission delay of the electrical connection based on the third time point.

[0073] In a possible implementation, after receiving the delay determination request, the second functional module immediately sends the third time point carried in the delay determination request to the first functional module.

[0074] In an embodiment of the present application, after receiving the delay determination request, the second functional module immediately sends the third time point carried by the delay determination request to the first functional module, so as to avoid delays in sending the third time point to the second functional module as much as possible, so as to ensure the accuracy of the subsequently determined transmission delay.

[0075] In one possible implementation, the second functional module sends the third time point to the first functional module only when it receives the time extraction request from the first functional module. That is, the process of the second functional module sending the third time point to the first functional module includes: the first functional module receives the delay determination request, stores the third time point carried by the delay determination request, the first functional module sends the time extraction request to the second functional module, the second functional module receives the time extraction request, and based on the time extraction request, sends the stored third time point to the first functional module, so that the first functional module can receive the third time point.

[0076] 303. The first functional module receives a third time point, and determines a transmission delay of an electrical connection between the first functional module and the second functional module based on a difference between a fourth time point and the third time point, wherein the fourth time point indicates a local timing when the first functional module receives the third time point.

[0077] In the embodiment of the present application, the third time point received by the first functional module is the time point when the first functional module sends a delay determination request to the second functional module. The third time point when the first functional module receives the return of the second functional module is equivalent to receiving the feedback of the second functional module. The fourth time point is equivalent to the time point when the first functional module receives the feedback of the second functional module. Therefore, the difference between the fourth time point and the third time point can reflect the transmission delay of the electrical connection between the first functional module and the second functional module, and then determine the transmission delay. In the embodiment of the present application, the first functional module interacts with the second functional module through the electrical connection between the first functional module and the second functional module, so as to determine the transmission delay of the electrical connection between the first functional module and the second functional module by sending the time point of the delay determination request and the time point when receiving the feedback of the second functional module, thereby realizing a new way to determine the transmission delay, so as to match the transmission delay with the actual transmission situation of the electrical connection, and ensure the accuracy of the transmission delay.

[0078] In one possible implementation, the process of determining the transmission delay includes: when the third time point is sent immediately by the second functional module upon receiving the delay determination request, half of the difference between the fourth time point and the third time point is determined as the transmission delay of the electrical connection between the first functional module and the second functional module.

[0079] In an embodiment of the present application, the first functional module sends a delay determination request to the second functional module. After receiving the delay determination request, the second functional module immediately sends the third time point to the first functional module. The difference between the fourth time point and the third time point is twice the transmission delay. Therefore, half of the difference is determined as the transmission delay to ensure the accuracy of the transmission delay.

[0080] For example, in the process of determining the transmission delay of the electrical connection between the first functional module and the second functional module, as shown in FIG. Figure 4 As shown, the first functional module sends a third time point to the second functional module. After receiving the third time point, the second functional module immediately returns the third time point to the first functional module. The first functional module receives the third time point sent by the second functional module, and records a fourth time point of local timing when the third time point is received, determines the difference between the fourth time point and the third time point, and determines the ratio of the difference to 2 as the transmission delay of the electrical connection between the first functional module and the second functional module.

[0081] In one possible implementation, the process of determining the transmission delay includes: when the third time point is sent by the second functional module when receiving the time extraction request, determining the first difference and the second difference, the first difference being the difference between the fourth time point and the third time point, the second difference being the difference between the fifth time point and the third time point, the fifth time point indicating the local timing when the first functional module sends the time extraction request, and determining half of the difference between the second difference and the first difference as the transmission delay of the electrical connection between the first functional module and the second functional module.

[0082] In an embodiment of the present application, since there is a period of time between the first functional module sending the delay determination request and the time extraction request, the delay transmission delay is determined in the above manner to avoid the influence of the time interval between the delay determination request and the time extraction request, so as to ensure the accuracy of the transmission delay.

[0083] In a possible implementation, when the first functional module determines the transmission delay of the electrical connection between the first functional module and the second functional module, the first functional module stores the transmission delay in the chip.

[0084] It should be noted that the embodiment of the present application only determines the transmission delay of the electrical connection between the first functional module and any second functional module in the above manner. In another embodiment, when the chip includes multiple second functional modules, the transmission delay of the electrical connection between the first functional module and each second functional module can be determined in the above manner.

[0085] It should be noted that in the embodiment of the present application, the first functional module interacts with the second functional module through the electrical connection to determine the transmission delay of the electrical connection. In another embodiment, there is no need to perform the above steps 301-303, but other methods are adopted, and the first functional module obtains the transmission delay of the electrical connection between the first functional module and the second functional module.

[0086] 304. The first functional module sends a time synchronization request to the second functional module through the electrical connection between the first functional module and the second functional module. The time synchronization request carries a first time point, which is the sum of the second time point and the transmission delay. The second time point indicates the local timing when the first functional module sends the time synchronization request.

[0087] 305. The second functional module receives the time synchronization request, and updates the local timing of the second functional module based on the first time point carried in the time synchronization request.

[0088] It should be noted that the embodiment of the present application is only to update the local timing of the second functional module by the first functional module and the second functional module in the chip through the electrical connection interaction between them, and in another embodiment, the chip includes a plurality of second functional modules, and there is an electrical connection between the first functional module and each second functional module. Figure 3 In the embodiment shown, the first functional module interacts with each second functional module through the electrical connection therebetween to update the local timing of each second functional module, so that the local timing of the first functional module and multiple functional modules included in the chip are synchronized, that is, each functional module included in the chip has a globally identical timestamp. Even if the transmission delay of the electrical connection between the first functional module and multiple second functional modules is different, the local timing synchronization of the first functional module and multiple functional modules can be achieved in the above manner.

[0089] For example, the chip includes a first functional module, five second functional modules and an on-chip bus, such as Figure 5 As shown, the first functional module included in the chip is a management module 501, and the five second functional modules included in the chip include a processing module 502, a processing module 503, an interface module 504, a storage module 505 and a storage module 506. The management module 501 and the processing module 502, the processing module 503, the interface module 504, the storage module 505 and the storage module 506 are all electrically connected through a serial communication bus, and the chip includes an on-chip bus 507.

[0090] In the solution provided in the embodiment of the present application, the first functional module and the second functional module included in the chip are not only electrically connected to the online bus, but an additional electrical connection is added between the first functional module and the second functional module. The electrical connection is a single-shared communication link, which can only realize the interaction between the first functional module and the second functional module, and will not be interfered by the communication of other modules. The electrical connection has a fixed transmission delay, so that when the chip is powered on, the first functional module and the second functional module interact through the electrical connection between them using the transmission delay of the electrical connection to achieve time synchronization between the first functional module and the second functional module. There is no need to use the on-chip master chip for time synchronization, and the accuracy of time synchronization between multiple functional modules can be guaranteed, so that the functional modules included in the chip can subsequently interact based on the synchronized time to ensure the normal operation of the chip, thereby improving the ease of use and efficiency of the chip.

[0091] In addition, the first functional module interacts with the second functional module through the electrical connection between the first functional module and the second functional module to determine the time point of sending the delay determination request and the time point of receiving feedback from the second functional module, thereby determining the transmission delay of the electrical connection between the first functional module and the second functional module, thereby realizing a new method of determining the transmission delay so as to match the transmission delay with the actual transmission situation of the electrical connection, thereby ensuring the accuracy of the transmission delay.

[0092] In the embodiment of the present application, the local timing synchronization process between multiple functional modules included in the chip is a one-time behavior executed after the chip is powered on. In the process of local timing synchronization between multiple functional modules, low frequency communication can be used. That is, each time the chip is powered on, according to the above Figures 2 to 3 In the embodiment shown in the figure, the local timing synchronization between the multiple functional modules included in the chip is realized. After that, when the chip is powered on, the local timing between the multiple functional modules included in the chip is always synchronized. Once the chip is powered off, the local timing between the functional modules included in the chip cannot continue to run. When the chip is powered on again, the local timing between the functional modules included in the chip is synchronized according to the above Figures 2 to 3 The illustrated embodiment again implements local timing synchronization between multiple functional modules included in the chip.

[0093] For example, a computer device includes a chip, and the chip includes a first functional module and multiple second functional modules. When the computer device is started, the chip can be powered on, and the local timing of the first functional module starts. The local timing of the first functional module can start from any initial time, or start from the time of the device, that is, the local timing of the first functional module is synchronized with the time of the device. Figure 6As shown, taking the transmission delay of the electrical connection between the first functional module and each second functional module as 20 clock cycles as an example, after the local timing of the first functional module starts, the local timing when the first functional module sends a time synchronization request to each second functional module is T, then according to the above Figures 2 to 3 In the embodiment shown, the first functional module sends a time synchronization request to each second functional module at the same time through the electrical connection between the first functional module and each second functional module. The first time point carried in the time synchronization request is T+20. After receiving the time synchronization request, each second functional module updates the local timing to T+20 and continues timing, so that the updated local timing of each first functional module is synchronized with the local timing of the second functional module.

[0094] It should be noted that the above is Figure 3 In the embodiment shown, the first functional module determines the transmission delay of the electrical connection by interacting with the second functional module. In another embodiment, the chip stores the transmission delay of the electrical connection between the various functional modules. When time synchronization is performed between multiple functional modules, the first functional module queries the stored transmission delay and then, according to the above steps 304 and 305, local timing synchronization of the first functional module and multiple functional modules can be achieved.

[0095] In the above Figures 2 to 3 On the basis of the shown embodiment, in the embodiment of the present application, when the local timing of multiple functional modules included in the chip is synchronized, the requests sent by the multiple functional modules during interaction will carry timestamps so that the request recipient can respond to the request based on the order of the timestamps carried by the request. The specific process is detailed in the following embodiment.

[0096] Figure 7 This is a time synchronization method provided by an embodiment of the present application, such as Figure 7 As shown, the method includes:

[0097] 701. The second functional module sends a processing request to the first functional module. The processing request carries a sending time point, and the sending time point indicates a local timing when the second functional module sends the processing request.

[0098] In an embodiment of the present application, when the local timing of multiple functional modules included in the chip is synchronized, the multiple functional modules will also interact. Taking the interaction between the first functional module and the second functional module as an example, the processing request sent by the second functional module to the first functional module carries a sending time point, so that when the second functional module receives multiple processing requests, it can respond according to the sending time point of each processing request.

[0099] The processing request is an arbitrary request, for example, the processing request is used to request processing of a certain signal, or to request storage of certain information, etc.

[0100] In one possible implementation, step 701 includes: when the data amount of the processing request is not less than a threshold, the second functional module sends the processing request to the first functional module through the on-chip bus; or, when the data amount of the processing request is less than the threshold, the second functional module sends the processing request to the first functional module through an electrical connection between the first functional module and the second functional module.

[0101] The threshold is an arbitrary value. In the embodiment of the present application, the threshold is equivalent to the upper limit of the amount of data transmitted by the electrical connection between the first functional module and the second functional module. Once the amount of data of the processing request reaches the threshold, the electrical connection may not be able to transmit the processing request or the transmission speed of the processing request is slow. Therefore, the second functional module sends the processing request to the first functional module via the on-chip bus.

[0102] Since there is an electrical connection between the first functional module and the second functional module, and both the first functional module and the second functional module are electrically connected to the on-chip bus, the first functional module and the second functional module can adopt two transmission methods to transmit the processing request, one is transmission through electrical connection, and the other is transmission through the on-chip bus, and the data volume of different processing requests may be different. Considering that different functional modules in the chip can transmit data through the on-chip bus, when the second functional module sends a processing request to the first functional module, it determines the data volume of the processing request, so as to select different transmission methods according to the data volume of the processing request, so as to reduce the data transmitted by the on-chip bus as much as possible, so as to weaken the load of the on-chip bus, and ensure the performance of the chip while ensuring the normal transmission of the processing request.

[0103] In one possible implementation, step 701 includes: when the processing request belongs to a first request type, the second functional module sends the processing request to the first functional module through the on-chip bus; or, when the processing request belongs to a second request type, the second functional module sends the processing request to the first functional module through an electrical connection between the first functional module, and the first request type is different from the second request type.

[0104] The first request type and the second request type are both arbitrary types. For example, the first request type is an information transmission type, that is, the processing request of the first request type is used to transmit information, and the second request type is a notification type, that is, the processing request of the second request type only has a notification function.

[0105] In the embodiment of the present application, considering that the first functional module and the second functional module can adopt two transmission methods to transmit processing requests, different request types are used to distinguish processing requests, and the transmission method is selected according to the request type of the processing request to minimize the data transmitted by the on-chip bus and weaken the load of the on-chip bus. While ensuring the normal transmission of processing requests, the performance of the chip can be guaranteed.

[0106] In one possible implementation, the process of the second functional module sending a processing request to the first functional module through the on-chip bus includes: the second functional module sending the processing request to the on-chip bus through an electrical connection between the second functional module and the on-chip bus; the on-chip bus sending the processing request to the first functional module through an electrical connection between the second functional module and the on-chip bus.

[0107] In an embodiment of the present application, each functional module included in the chip is electrically connected to the on-chip bus. Through the on-chip bus, multiple functional modules can transmit data, so that different functional modules in the chip can transmit, thereby ensuring the function of the chip.

[0108] 702. The first functional module receives a processing request sent by the second functional module.

[0109] 703. The first functional module determines a third time code of the processing request based on the first time code and the second time code, where the first time code indicates the time code of the second digit carried by the processing request, the second time code and the third time code are both time codes of the first digit, the second time code indicates the local timing when the first functional module receives the processing request, the third time code indicates the local timing when the second functional module sends the processing request, and the second digit is smaller than the first digit.

[0110] In an embodiment of the present application, the local timing of multiple functional modules in the chip is represented by the time code of the first digit, and the first digit is an arbitrary value, for example, the first digit is 64 bits, that is, the local timing of each functional module is a 64-bit time code. The first digit is as large as possible so that the local timing of each functional module does not overflow when the chip is used for a long time. The second functional module can send a processing request to the first functional module through the electrical connection between the first functional module or through the on-chip bus, and the transmission delay of the electrical connection between all functional modules in the chip or the transmission delay of the on-chip bus is less than the time interval, that is, the transmission delay of all electrical connections or on-chip buses in the chip will not exceed the time interval, which is an arbitrary value, for example, the time interval is 1000 clock cycles or 65536. Since the data volume of the time code of the first digit is large, if the sending time point carried by the processing request is represented by the time code of the first digit, the data volume of the processing request will increase, and the sending time point carried by the processing request will have redundant information, resulting in large communication overhead. Therefore, the sending time point carried by the processing request transmitted by each functional module in the chip is represented by the time code of the second digit to reduce the data volume of the processing request and thereby reduce the communication overhead.

[0111] In an embodiment of the present application, the sending time point carried by the processing request sent by the second functional module to the first functional module is represented by a second-digit time code, and the sending time point indicates the local timing when the second functional module sends the processing request, and the local timing of the second functional module is represented by a first-digit time code, and the sending time point is the time code after the second digit of the local timing of the second functional module.

[0112] Since the sending time point carried by the processing request is represented by a second-digit time code, after the first functional module receives the processing request sent by the second functional module, the sending time point carried by the processing request is restored to recover the first-digit time code to represent the sending time point of the processing request, so as to determine the sending time point of the processing request based on the first-digit time code to ensure the accuracy of the determined sending time point of the processing request.

[0113] In the case of local timing synchronization of multiple functional modules included in the chip, in the process of recovering the first-digit time code to represent the sending time point of the processing request, since the duration between the time point when the first functional module receives the processing request and the time point when the second functional module sends the processing request will not be greater than the time interval, and the maximum duration that can be represented by the second-digit time code is not greater than the time interval, therefore, when the first functional module obtains the first time code, based on the second time code and the first time code of the local timing when the processing request is received, the first-digit time code can be recovered to represent the sending time point of the processing request, so as to ensure the accuracy of the recovered third time code.

[0114] In one possible implementation, step 703 includes: when the first time code is not greater than the time code of the second last digit in the first time code, the first functional module replaces the time code of the second last digit in the first time code with the first time code to obtain a third time code for processing the request; when the first time code is greater than the time code of the second last digit in the first time code, the first time code replaces the time code of the second last digit in the first time code, and determines the difference between the replaced time code and the time interval as the third time code for processing the request.

[0115] In the embodiment of the present application, since the duration between the time point when the first functional module receives the processing request and the time point when the second functional module sends the processing request will not exceed the maximum duration that the second-digit time code can represent, when the first time code is not greater than the time code of the second digit after the first time code, it indicates that the time code has not been carried, and the first time code is directly replaced with the time code of the second digit after the first time code to obtain the third time code of the processing request; and when the first time code is greater than the time code of the second digit after the first time code, it indicates that in the process of sending the processing request, from the time when the second functional module sends the processing request to the process when the processing request is received, the local timing of the first functional module carries forward to the position of the first digit + 1, and the time interval is the duration corresponding to the time code of the first digit carrying forward to the previous position, therefore, the first time code is replaced with the time code of the second digit after the first time code, and the difference between the replaced time code and the time interval is determined as the third time code of the processing request to ensure the accuracy of the determined third time code.

[0116] like Figure 8As shown, the first digit is 64 bits and the second digit is 16 bits. In the case where the first time code is not greater than the time code of the second digit after the first time code, it means that the local timing of the first functional module has not been carried forward from the time when the second functional module sends the processing request to the time when the processing request is received, then the last 16 bits of the second time code are directly replaced with the first time code, and the time code of the first digit can be restored to indicate the sending time point of the processing request, that is, the first 48 bits of the second time code and the first time code constitute the time code of the first digit. In the case where the first time code is greater than the time code of the second digit after the first time code, it means that the local timing of the first functional module has been carried forward from the time when the second functional module sends the processing request to the time when the processing request is received, that is, the local timing of the first functional module is carried forward to the 17th bit, and the time interval is the time length corresponding to the 16-bit time code carrying forward to the 17th bit, after the last 16 bits of the second time code are replaced with the first time code, the replaced time code is subtracted from the time interval to obtain the third time code.

[0117] 704. When receiving multiple processing requests, the first functional module responds to the multiple processing requests based on the order of the third time codes of the multiple processing requests.

[0118] In an embodiment of the present application, in the process of the second functional module sending a processing request to the first functional module, other second functional modules may also send processing requests to the first functional module, or, the second functional module sends multiple processing requests to the first functional module, then the first functional module may receive multiple processing requests. When receiving multiple processing requests, the multiple processing requests are responded to in the order of the third time codes of the multiple processing requests to avoid disorder of the order of the responded processing requests, avoid chip operation failures, and ensure the normal operation of the chip.

[0119] It should be noted that the embodiment of the present application is described by taking the local timing as the time code with the first digit and the sending time point carried by the processing request as the time code with the second digit as an example. In another embodiment, there is no need to execute the above steps 703-704, but other methods are adopted. When multiple processing requests are received, the multiple processing requests are responded to in the order of the sending time points carried by the multiple processing requests.

[0120] In the solution provided in the embodiment of the present application, the first functional module and the second functional module included in the chip are not only electrically connected to the online bus, but an additional electrical connection is added between the first functional module and the second functional module. The electrical connection is a single-shared communication link, which can only realize the interaction between the first functional module and the second functional module, and will not be interfered by the communication of other modules. The electrical connection has a fixed transmission delay, so that when the chip is powered on, the first functional module and the second functional module interact through the electrical connection between them using the transmission delay of the electrical connection to achieve time synchronization between the first functional module and the second functional module. There is no need to use the on-chip master chip for time synchronization, and the accuracy of time synchronization between multiple functional modules can be guaranteed, so that the functional modules included in the chip can subsequently interact based on the synchronized time to ensure the normal operation of the chip, thereby improving the ease of use and efficiency of the chip.

[0121] In an embodiment of the present application, when the local timing of multiple functional modules included in the chip is synchronized, the multiple functional modules will also interact. Taking the interaction between the first functional module and the second functional module as an example, the processing request sent by the second functional module to the first functional module carries a sending time point, so that when the second functional module receives multiple processing requests, it can respond according to the sending time point of each processing request, so as to avoid the situation where the chip operation failure is caused by not processing according to the sending time point, thereby ensuring the normal operation of the chip.

[0122] In the embodiment of the present application, since the data volume of the time code of the first digit is large, if the sending time point carried by the processing request is represented by the time code of the first digit, the data volume of the processing request will increase, and the sending time point carried by the processing request will have redundant information, resulting in large communication overhead. Therefore, the sending time point carried by the processing request transmitted by each functional module in the chip is represented by the time code of the second digit to reduce the data volume of the processing request, thereby reducing the communication overhead. Since the time length between the time point when the first functional module receives the processing request and the time point when the second functional module sends the processing request will not be greater than the time interval, and the maximum time length that the time code of the second digit can represent is not greater than the time interval, therefore, when the first functional module obtains the first time code, based on the second time code and the first time code of the local timing when the processing request is received, the time code of the first digit can be restored to represent the sending time point of the processing request, so as to ensure the accuracy of the restored third time code. The embodiment of the present application not only proposes a low-cost time synchronization solution, but also reduces the cost of timestamp transmission in the chip.

[0123] It should be noted that the above Figure 7The illustrated embodiment is merely described by taking the second functional module transmitting a processing request to the first functional module as an example. In another embodiment, the second functional module can also transmit other information to the first functional module.

[0124] It should be noted that the above Figure 7 The embodiment shown is only described by taking the second functional module transmitting a processing request to the first functional module as an example. In another embodiment, any two functional modules included in the chip can be processed according to the above Figure 5 For example, according to the above Figure 7 In the illustrated embodiment, the second functional module can also transmit processing requests or other information to other second functional modules; or, the first functional module transmits processing requests or other information to the second functional module; or, other second functional modules transmit processing requests or other information to the second functional module.

[0125] Fig. 9 is a schematic diagram of the structure of a chip provided in an embodiment of the present application, such as Fig. 9 As shown, the chip includes a first functional module 901, a second functional module 902 and an on-chip bus 903, the first functional module 901 and the second functional module 902 are both electrically connected to the on-chip bus 903, and the first functional module 901 is electrically connected to the second functional module 902;

[0126] The first functional module 901 is used to obtain the transmission delay of the electrical connection 904 between the first functional module 901 and the second functional module 902 when the chip is powered on; send a time synchronization request to the second functional module 902 through the electrical connection 904, the time synchronization request carries a first time point, the first time point is the sum of the second time point and the transmission delay, and the second time point indicates the local timing when the first functional module 901 sends the time synchronization request;

[0127] The second functional module 902 is configured to receive a time synchronization request, and update a local timing of the second functional module 902 based on a first time point carried in the time synchronization request.

[0128] In a possible implementation, the first functional module 901 is used to send a delay determination request to the second functional module 902 through the electrical connection 904 when the chip is powered on, the delay determination request carries a third time point, and the third time point indicates a local timing when the first functional module 901 sends the delay determination request;

[0129] The second functional module 902 is further configured to receive a delay determination request and send a third time point to the first functional module 901;

[0130] The first functional module 901 is configured to receive a third time point, and determine a transmission delay based on a difference between a fourth time point and the third time point, wherein the fourth time point indicates a local timing when the first functional module 901 receives the third time point.

[0131] In another possible implementation, the second functional module 902 is further configured to send a processing request to the first functional module 901, the processing request carries a sending time point, and the sending time point indicates a local timing when the second functional module 902 sends the processing request;

[0132] The first functional module 901 is further configured to receive a processing request sent by the second functional module 902, and in the case of receiving multiple processing requests, respond to the multiple processing requests in the order of the sending time points carried by the multiple processing requests.

[0133] In another possible implementation, the local timings of the second functional module 902 and the first functional module 901 are both represented by the time code of the first digit; the sending time point is represented by the time code of the second digit after the local timing when the second functional module 902 sends the processing request, and the second digit is smaller than the first digit;

[0134] The first functional module 901 is also used to determine the third time code of the processing request based on the first time code and the second time code, the first time code indicates the time code of the second digit carried by the processing request, the second time code and the third time code are both time codes of the first digit, the second time code indicates the local timing when the first functional module 901 receives the processing request, and the third time code indicates the local timing when the second functional module 902 sends the processing request; based on the order of the third time codes of the multiple processing requests, respond to multiple processing requests.

[0135] In another possible implementation, the first functional module 901 is used to replace the time code of the second last digit in the first time code with the first time code when the first time code is not greater than the time code of the second last digit in the first time code, so as to obtain a third time code for processing the request; and to replace the time code of the second last digit in the first time code with the first time code when the first time code is greater than the time code of the second last digit in the first time code, and determine the difference between the replaced time code and the time interval as the third time code for processing the request.

[0136] In another possible implementation, the second functional module 902 is used to send a processing request to the first functional module 901 through the on-chip bus 903 when the data amount of the processing request is not less than a threshold; or, when the data amount of the processing request is less than a threshold, the second functional module 902 sends a processing request to the first functional module 901 through the electrical connection 904 between the first functional module 901.

[0137] In another possible implementation, the second functional module 902 is used to send a processing request to the first functional module 901 through the on-chip bus 903 when the processing request belongs to a first request type; or, when the processing request belongs to a second request type, the second functional module 902 sends a processing request to the first functional module 901 through the electrical connection 904 between the first functional module 901, and the first request type is different from the second request type.

[0138] In another possible implementation, the second functional module 902 is configured to send a processing request to the on-chip bus 903 via an electrical connection 904 between the second functional module 902 and the on-chip bus 903;

[0139] The on-chip bus 903 is used to send a processing request to the first functional module 901 through an electrical connection 904 between the first functional module 901 and the first functional module 901 .

[0140] In another possible implementation, the first functional module 901 is electrically connected to the second functional module 902 via a serial communication bus.

[0141] It should be noted that the chip and time synchronization method embodiments provided in the above embodiments belong to the same concept, and their specific implementation processes are detailed in the method embodiments, which will not be repeated here.

[0142] An embodiment of the present application also provides a computer device, which includes a chip, the chip includes a processor and a memory, and the memory stores at least one computer program, which is loaded and executed by the processor to implement the operations performed by the time synchronization method of the above embodiment.

[0143] Optionally, the computer device is provided as a terminal. Fig.10 The structure block diagram of a terminal 1000 provided by an exemplary embodiment of the present application is shown. The terminal 1000 includes a chip, and the chip includes a processor 1001 and a memory 1002, that is, the processor 1001 and the memory 1002 are integrated on the same chip.

[0144] The processor 1001 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 1001 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 1001 may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 1001 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 1001 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0145] The memory 1002 may include one or more computer-readable storage media, which may be non-transitory. The memory 1002 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 1002 is used to store at least one computer program, which is used to be executed by the processor 1001 to implement the time synchronization method provided in the method embodiment of the present application.

[0146] In some embodiments, the terminal further includes at least one peripheral device, and the chip further includes: a peripheral device interface 1003. The processor 1001, the memory 1002, and the peripheral device interface 1003 are integrated on the same chip, and the processor 1001, the memory 1002, and the peripheral device interface 1003 can be connected through an on-chip bus or signal line included in the chip. Each peripheral device can be connected to the peripheral device interface 1003 through an on-chip bus, a signal line, or a circuit board. Specifically, the peripheral device includes: at least one of a radio frequency circuit 1004, a display screen 1005, a camera assembly 1006, an audio circuit 1007, and a power supply 1008.

[0147] The peripheral device interface 1003 may be used to connect at least one peripheral device related to I / O (Input / Output) to the processor 1001 and the memory 1002 .

[0148] The radio frequency circuit 1004 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The radio frequency circuit 1004 communicates with the communication network and other communication devices through electromagnetic signals. The radio frequency circuit 1004 converts the electrical signal into an electromagnetic signal for transmission, or converts the received electromagnetic signal into an electrical signal. Optionally, the radio frequency circuit 1004 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, etc. The radio frequency circuit 1004 can communicate with other terminals through at least one wireless communication protocol. The wireless communication protocol includes but is not limited to: the World Wide Web, a metropolitan area network, an intranet, various generations of mobile communication networks (2G, 3G, 4G and 5G), a wireless local area network and / or a WiFi (Wireless Fidelity) network. In some embodiments, the radio frequency circuit 1004 may also include circuits related to NFC (Near Field Communication), which is not limited in this application.

[0149] The display screen 1005 is used to display a UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen 1005 is a touch display screen, the display screen 1005 also has the ability to collect touch signals on the surface or above the surface of the display screen 1005. The touch signal can be input to the processor 1001 as a control signal for processing. At this time, the display screen 1005 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen 1005 can be one, arranged on the front panel of the terminal 1000; in other embodiments, the display screen 1005 can be at least two, respectively arranged on different surfaces of the terminal 1000 or in a folding design; in other embodiments, the display screen 1005 can be a flexible display screen, arranged on a curved surface or a folding surface of the terminal 1000. Even, the display screen 1005 can also be arranged as a non-rectangular irregular figure, that is, a special-shaped screen. The display screen 1005 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0150] The camera assembly 1006 is used to capture images or videos. Optionally, the camera assembly 1006 includes a front camera and a rear camera. The front camera is arranged on the front panel of the terminal, and the rear camera is arranged on the back of the terminal. In some embodiments, there are at least two rear cameras, which are any one of a main camera, a depth of field camera, a wide-angle camera, and a telephoto camera, so as to realize the fusion of the main camera and the depth of field camera to realize the background blur function, the fusion of the main camera and the wide-angle camera to realize panoramic shooting and VR (Virtual Reality) shooting function or other fusion shooting functions. In some embodiments, the camera assembly 1006 may also include a flash. The flash can be a monochrome temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.

[0151] The audio circuit 1007 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals and input them into the processor 1001 for processing, or input them into the radio frequency circuit 1004 to achieve voice communication. For the purpose of stereo acquisition or noise reduction, there may be multiple microphones, which are respectively arranged at different parts of the terminal 1000. The microphone may also be an array microphone or an omnidirectional acquisition microphone. The speaker is used to convert the electrical signal from the processor 1001 or the radio frequency circuit 1004 into sound waves. The speaker may be a traditional film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert the electrical signal into sound waves audible to humans, but also convert the electrical signal into sound waves inaudible to humans for purposes such as ranging. In some embodiments, the audio circuit 1007 may also include a headphone jack.

[0152] The power supply 1008 is used to power various components in the terminal 1000. The power supply 1008 can be an alternating current, a direct current, a disposable battery, or a rechargeable battery. When the power supply 1008 includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery charged through a wired line, and a wireless rechargeable battery is a battery charged through a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0153] Those skilled in the art will understand that Fig.10 The structure shown in the figure does not constitute a limitation on the terminal 1000, and the terminal 1000 may include more or less components than those shown in the figure, or combine some components, or adopt a different component arrangement.

[0154] Optionally, the computer device is provided as a server. Fig.11This is a schematic diagram of the structure of a server provided in an embodiment of the present application. The server 1100 may have relatively large differences due to different configurations or performances, and may include a chip, which includes one or more processors (Central Processing Units, CPU) 1101 and one or more memories 1102, wherein the memory 1102 stores at least one computer program, and at least one computer program is loaded and executed by the processor 1101 to implement the methods provided in the above-mentioned various method embodiments. Of course, the server may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output, and the server may also include other components for implementing device functions, which will not be described in detail here.

[0155] A person of ordinary skill in the art will appreciate that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk, or an optical disk, etc.

[0156] The above description is only an optional embodiment of the embodiments of the present application and is not intended to limit the embodiments of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the protection scope of the present application.

Claims

1. A time synchronization method, characterized in that: Applied to a chip, the chip includes a first functional module, a second functional module and an on-chip bus, the first functional module and the second functional module are both electrically connected to the on-chip bus, the first functional module is electrically connected to the second functional module, and the method includes: When the chip is powered on, the first functional module acquires a transmission delay of an electrical connection with the second functional module; The first functional module sends a time synchronization request to the second functional module through the electrical connection, the time synchronization request carries a first time point, the first time point is the sum of the second time point and the transmission delay, and the second time point indicates the local timing when the first functional module sends the time synchronization request; The second functional module receives the time synchronization request, and updates the local timing of the second functional module based on the first time point carried in the time synchronization request.

2. The method according to claim 1, characterized in that The first functional module acquires a transmission delay of an electrical connection with the second functional module, including: When the chip is powered on, the first functional module sends a delay determination request to the second functional module through the electrical connection, the delay determination request carries a third time point, and the third time point indicates a local timing when the first functional module sends the delay determination request; The second functional module receives the delay determination request and sends the third time point to the first functional module; The first functional module receives the third time point, and determines the transmission delay based on a difference between a fourth time point and the third time point, wherein the fourth time point indicates a local timing when the first functional module receives the third time point.

3. The method according to claim 1, characterized in that After the second functional module receives the time synchronization request and updates the local timing of the second functional module based on the first time point carried in the time synchronization request, the method further includes: The second functional module sends a processing request to the first functional module, the processing request carries a sending time point, and the sending time point indicates a local timing when the second functional module sends the processing request; The first functional module receives the processing request sent by the second functional module, and in the case of receiving multiple processing requests, responds to the multiple processing requests in the order of the sending time points carried by the multiple processing requests.

4. The method according to claim 3, characterized in that The local timings of the second functional module and the first functional module are both represented by the time code of the first digit; the sending time point is represented by the time code of the second digit of the local timing when the second functional module sends the processing request, and the second digit is smaller than the first digit; The step of responding to the multiple processing requests in the order of the sending time points carried by the multiple processing requests upon receiving the multiple processing requests includes: The first functional module determines a third time code of the processing request based on the first time code and the second time code, the first time code indicates a time code of the second digit carried by the processing request, the second time code and the third time code are both time codes of the first digit, the second time code indicates a local timing when the first functional module receives the processing request, and the third time code indicates a local timing when the second functional module sends the processing request; The plurality of processing requests are responded to based on a third time-coded order of the plurality of processing requests.

5. The method according to claim 4, characterized in that The first function module determines a third time code of the processing request based on the first time code and the second time code, including: The first function module replaces the time code of the second last digit in the first time code with the first time code when the first time code is not greater than the time code of the second last digit in the first time code to obtain a third time code for the processing request; When the first time code is greater than the time code of the second last digit in the first time code, the first time code is used to replace the time code of the second last digit in the first time code, and the difference between the replaced time code and the time interval is determined as the third time code of the processing request.

6. The method according to claim 3, characterized in that: The second function module sends a processing request to the first function module, including: When the data amount of the processing request is not less than a threshold, the second functional module sends the processing request to the first functional module through the on-chip bus; or When the data volume of the processing request is smaller than the threshold, the second functional module sends the processing request to the first functional module through the electrical connection between the second functional module and the first functional module.

7. The method according to claim 3, characterized in that The second function module sends a processing request to the first function module, including: In the case where the processing request belongs to the first request type, the second functional module sends the processing request to the first functional module through the on-chip bus; or In the case where the processing request belongs to a second request type, the second functional module sends the processing request to the first functional module through the electrical connection between the second functional module and the first request type, and the first request type is different from the second request type.

8. The method according to claim 6 or 7, characterized in that: The second functional module sends the processing request to the first functional module through the on-chip bus, including: The second functional module sends the processing request to the on-chip bus through an electrical connection with the on-chip bus; The on-chip bus sends the processing request to the first functional module through the electrical connection between the on-chip bus and the first functional module.

9. The method according to claim 1, characterized in that: The first functional module is electrically connected to the second functional module via a serial communication bus.

10. A chip, characterized in that: The chip includes a first functional module, a second functional module and an on-chip bus, the first functional module and the second functional module are both electrically connected to the on-chip bus, and the first functional module is electrically connected to the second functional module; The first functional module is configured to obtain a transmission delay of an electrical connection with the second functional module when the chip is powered on; send a time synchronization request to the second functional module through the electrical connection, wherein the time synchronization request carries a first time point, the first time point is a sum of a second time point and the transmission delay, and the second time point indicates a local timing when the first functional module sends the time synchronization request; The second functional module is configured to receive the time synchronization request, and update the local timing of the second functional module based on the first time point carried in the time synchronization request.

11. A computer device, characterized in that: The computer device includes a chip, the chip includes a processor and a memory, the memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the operations performed by the time synchronization method as described in any one of claims 1 to 9.

Images