IP encryption method based on ZYNQ

Abstract

The invention provides an IP encryption method based on ZYNQ. The method comprises the following steps that an integrated ARM processing system issues licence data to an encryption verification module through a GP port; a device ID acquisition module, a key generation module and a key verification module are arranged in the encryption verification module; the device ID acquisition module is powered on to automatically acquire the device ID, supplements the device ID to 128 bits and outputs the device ID to the key generation module; the key generation module calculates a product key according to the 128-bit device ID and an encryption algorithm; the secret key verification module comprises a logical operation unit and a logical judgment unit; the binary single-bit control signal is interconnected with a target IP; and the target IP enables or disables the IP according to the value of the binary single-bit control signal. According to the method, the encryption of the IP is realized, and the IP core is prevented from being copied or used by an unauthorized third party, so that the design and intellectual property are effectively protected.

Description

Technical Field

[0001] The present invention relates to the technical field of FPGA IP core encryption, and in particular to an IP encryption method based on ZYNQ. Background Art

[0002] As FPGAs are widely used in various applications, the market demand for protecting the uniqueness and innovation of designs is growing, which has prompted manufacturers to take encryption measures to remain competitive. FPGA application companies invest a lot of R&D resources in the development and design of IP. In order to protect these investments and ensure that the design results are not illegally copied or stolen, IP encryption is usually also required.

[0003] At the same time, the encrypted IP core can usually be parameterized through header files or graphical user interfaces (GUIs), so that users can easily customize and maintain them without having to understand the underlying implementation details. In addition, by encrypting the IP core, it can ensure that the uniqueness and innovation of the design cannot be easily imitated, helping designers stay competitive in the market. Encrypting the IP core of the FPGA is not only to protect the design and intellectual property rights, but also to improve the security and maintainability of the system, and to adapt to the ever-changing technical environment and market needs. However, the prior art lacks a ZYNQ-based IP encryption method, which cannot effectively prevent the IP core from being copied or used by unauthorized third parties. Summary of the invention

[0004] In view of the shortcomings of the prior art, the purpose of the present invention is to provide an IP encryption method based on ZYNQ to solve the problems raised in the above background technology. The present invention realizes the encryption of IP, which can effectively prevent the IP core from being copied or used by unauthorized third parties and protect the design and intellectual property rights.

[0005] In order to achieve the above object, the present invention is implemented by the following technical solution: a ZYNQ-based IP encryption method, comprising the following steps:

[0006] Step 1: The integrated ARM processing system sends the license data to the encryption verification module through the GP port;

[0007] Step 2: Setting a device ID acquisition module, a key generation module and a key verification module in the encryption verification module;

[0008] Step 3: The device ID acquisition module automatically acquires the device ID when powered on, pads it to 128 bits, and outputs it to the key generation module;

[0009] Step 4: The key generation module calculates the product key based on the 128-bit device ID and encryption algorithm;

[0010] Step 5: The key verification module includes a logic operation unit and a logic judgment unit;

[0011] Step 6: The binary single-bit control signal is interconnected with the target IP;

[0012] Step 7: The target IP enables or disables the IP according to the value of the binary single-bit control signal.

[0013] Furthermore, in step 4, the encryption algorithm generates a 128-bit product key and outputs it to the key verification module.

[0014] Furthermore, in step five, the logic operation unit obtains 80 bits of the 128 bits of the product key through logic operation.

[0015] Furthermore, the logic operation unit is used for comparison with license data.

[0016] Furthermore, the logic judgment unit generates a corresponding binary single-bit control signal by judging whether the product key generated by the key generation module is consistent with the license data sent by the integrated ARM processing system through the GP port.

[0017] Furthermore, the integrated ARM processing system accesses the programmable logic terminal through the AXI bus of the GP port for issuing license data.

[0018] Furthermore, the programmable logic is used for logical implementation of encrypted IP.

[0019] Furthermore, the encrypted IP includes an encryption verification module and a target IP.

[0020] Furthermore, the encryption verification module is interconnected with the target IP via a control signal to control whether the target IP is working.

[0021] Beneficial effects of the present invention:

[0022] 1. The ZYNQ-based IP encryption method integrates an ARM processing system to access the PL end through the AXI bus of the GP port for issuing license data, and utilizes programmable logic to encrypt the logical implementation of IP. The encryption verification module is interconnected with the target IP through a control signal to control whether the target IP is working, and finally realizes the encryption of IP to prevent the IP core from being copied or used by unauthorized third parties, thereby effectively protecting the design and intellectual property rights. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a principle block diagram of a ZYNQ-based IP encryption method of the present invention;

[0024] Figure 2 Schematic diagram of a key generation system in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further explained below in conjunction with specific implementation methods.

[0026] See also Figure 1 to Figure 2 The present invention provides the following technical solutions: a ZYNQ-based IP encryption method, comprising an integrated ARM processing system (PS), wherein the integrated ARM processing system accesses a programmable logic terminal through an AXI bus of a GP port for issuing license data; a programmable logic (PL) for implementing the logic of an encrypted IP, wherein the encrypted IP comprises an encryption verification module and a target IP, wherein the encryption verification module is interconnected with the target IP through a control signal for controlling whether the target IP is working.

[0027] This encryption method can encrypt IP and prevent the IP core from being copied or used by unauthorized third parties, thereby effectively protecting the design and intellectual property rights.

[0028] In this embodiment, Figure 2 This is a schematic diagram of the key generation system. In this system, the 64-bit ID number of the device is input. If it is less than 64 bits, the high bits can be filled with 0s. Click to generate 80-bit license data. And send it to the encryption verification module through the GP port.

[0029] This embodiment also provides the following steps to further illustrate the above ZYNQ-based IP encryption method:

[0030] 1. The integrated ARM processing system sends the 80-bit license data to the encryption verification module through the GP port.

[0031] 2. The encryption verification module includes a device ID acquisition module, a key generation module and a key verification module.

[0032] 3. The device ID acquisition module automatically acquires the device ID when powered on, pads it to 128 bits, and outputs it to the key generation module.

[0033] 4. The key generation module calculates the product key based on the 128-bit device ID and encryption algorithm. The encryption algorithm includes but is not limited to using the AES128 algorithm to generate a 128-bit product key and output it to the key verification module.

[0034] 5. The key verification module includes a logic operation unit and a logic judgment unit. The logic operation unit obtains 80 bits of the 128 bits of the product key through logic operation for comparison with the license data; the logic judgment unit generates a corresponding binary single-bit control signal by judging whether the product key generated by the key generation module is consistent with the license data sent by the integrated ARM processing system through the GP port.

[0035] 6. The binary single-bit control signal is interconnected with the target IP.

[0036] 7. The target IP enables or disables the IP according to the value of the binary single-bit control signal.

[0037] The present invention adopts the above method to realize IP encryption, preventing the IP core from being copied or used by an unauthorized third party, thereby effectively protecting the design and intellectual property rights.

[0038] The basic principles and main features of the present invention and the advantages of the present invention are shown and described above. For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention.

[0039] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A ZYNQ-based IP encryption method, characterized in that: The following steps are involved: Step 1: The integrated ARM processing system sends the license data to the encryption verification module through the GP port; Step 2: Setting a device ID acquisition module, a key generation module and a key verification module in the encryption verification module; Step 3: The device ID acquisition module automatically acquires the device ID when powered on, pads it to 128 bits, and outputs it to the key generation module; Step 4: The key generation module calculates the product key based on the 128-bit device ID and encryption algorithm; Step 5: The key verification module includes a logic operation unit and a logic judgment unit; Step 6: The binary single-bit control signal is interconnected with the target IP; Step 7: The target IP enables or disables the IP according to the value of the binary single-bit control signal.

2. The ZYNQ-based IP encryption method according to claim 1, characterized in that: In the step 4, the encryption algorithm generates a 128-bit product key and outputs it to the key verification module.

3. The ZYNQ-based IP encryption method according to claim 1, characterized in that: In the step 5, the logic operation unit obtains 80 bits of the 128 bits of the product key through logic operation.

4. The ZYNQ-based IP encryption method according to claim 3, characterized in that: The logic operation unit is used for comparison with license data.

5. The ZYNQ-based IP encryption method according to claim 1, characterized in that: The logic judgment unit generates a corresponding binary single-bit control signal by judging whether the product key generated by the key generation module is consistent with the license data sent by the integrated ARM processing system through the GP port.

6. The ZYNQ-based IP encryption method according to claim 1, characterized in that: The integrated ARM processing system accesses the programmable logic terminal through the AXI bus of the GP port for issuing license data.

7. The ZYNQ-based IP encryption method according to claim 6, characterized in that: The programmable logic is used for the logical implementation of the encryption IP.

8. The ZYNQ-based IP encryption method according to claim 7, characterized in that: The encrypted IP includes an encryption verification module and a target IP.

9. The ZYNQ-based IP encryption method according to claim 8, characterized in that: The encryption verification module is interconnected with the target IP through a control signal to control whether the target IP is working.

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