Analysis method and device for system-on-chip deployment numerical model, electronic equipment and medium

Abstract

The invention provides an analysis method and device for a system-on-chip deployment numerical model, electronic equipment and a medium. The method comprises the steps that at least one deployment architecture of a current algorithm is designed; respectively obtaining the operation time consumption of each module on the ARM side, the operation relative time consumption of the FPGA side and the absolute time consumption of the algorithm in the first deployment architecture; obtaining time consumed by interaction of an ARM side module and an FPGA side module when the algorithm runs in the first deployment architecture; constraining the total consumed time by using a time constraint threshold value; constraining the resource consumption of the system by using the resource upper limit; calculating the design complexity of the deployment architecture based on the interaction times of the ARM side memory and the FPGA side memory of the first deployment architecture, the module setting position, the resource consumption of the system and the total consumption time; and selecting the deployment architecture with the minimum design complexity as a final deployment architecture scheme. According to the method, the performance of the hybrid numerical model architecture can be fully exerted, and the algorithm acceleration effect is maximized.

Description

Technical Field

[0001] The present invention relates to the field of hardware acceleration technology, and in particular to an analysis method, device, electronic equipment and medium for deploying a numerical model of a system on a chip. Background Art

[0002] Algorithm acceleration has always been a topic of great concern in the field of technology. When the algorithm model has good accuracy, it is extremely valuable to find a faster way to get the calculation results. Currently known algorithm acceleration methods include model optimization compression, mixed precision, hardware acceleration, etc. In the field of hardware acceleration, the industry often uses FPGA, GPU, NPU, AI professional SOC, etc. For different hardware characteristics, specific optimization of the algorithm is required. How to give full play to the characteristics of GPU and FPGA in a general scenario and maximize the algorithm acceleration effect is a hot topic in current research.

[0003] The Zynq architecture is a unique system-level chip design. The platform combines ARM processors and FPGA architecture to provide a new system-level solution. Under the Zynq architecture, there are three possible deployment structures: pure C language model architecture, pure FPGA numerical model architecture, and hybrid numerical model architecture.

[0004] At present, there are relatively few model deployment methods under the hybrid numerical model architecture. How to give full play to the performance of the hybrid numerical model architecture and maximize the algorithm acceleration effect is also the focus and difficulty of current research. Summary of the invention

[0005] The present invention provides an analysis method, device, electronic device and medium for deploying numerical models in a system on a chip, so as to give full play to the performance of a hybrid numerical model architecture and maximize the algorithm acceleration effect.

[0006] According to one aspect of the present invention, a method for analyzing a system-on-chip deployment numerical model is provided, comprising: Designing at least one deployment architecture of the current algorithm, wherein the deployment architecture includes at least one parallel module and at least one pipeline module; Obtaining respectively the running time of each module on the ARM side of the algorithm running in the first deployment architecture, and the relative running time and absolute running time of each module on the FPGA side; the first deployment architecture is any one of the at least one deployment architecture; Obtain the time consumed by the algorithm running in the first deployment architecture for the interaction between the ARM side module and the FPGA side module; The total consumption time is constrained by a time constraint threshold; the total consumption time at least includes the operation consumption time of each module on the ARM side, the operation consumption time of each module on the FPGA side, and the time consumed by the interaction between the ARM side module and the FPGA side module; the operation consumption time of each module on the FPGA side is related to the relative time consumption and the absolute time consumption of each module operation; Using a resource cap to constrain system resource consumption when the algorithm runs on the first deployment architecture; Calculate the design complexity of the first deployment architecture based on the number of interactions between the ARM side memory and the FPGA side memory of the first deployment architecture, the module setting position, the resource consumption of the system, and the total consumption time; And select the first deployment architecture with the smallest design complexity as the final deployment architecture solution.

[0007] Optionally, the at least one deployment architecture of the designing current algorithm includes: The algorithm logic is disassembled into multiple execution steps; each execution step corresponds to a parallel module or a pipeline module; the parallel module executes the steps that can be performed simultaneously, and the pipeline module executes the steps that are performed sequentially; At least one of the deployment architectures is formed based on the disassembled execution steps.

[0008] Optionally, the relative time consumption of the overall operation on the FPGA side is at least related to the actual number of clocks used by each module, the number of parallel modules and the number of pipelined modules.

[0009] Optionally, the relative time-consuming time of the overall operation on the FPGA side is related to the relative clock number of the overall operation of each module on the FPGA side, and the relative clock number of the overall operation is: , The actual number of clocks for each module, is the number of parallel modules, is the number of pipelined modules.

[0010] Optionally, the time consumed for the interaction between the ARM side module and the FPGA side module is at least related to the actual transmission data length, thread usage, logic timing of the FPGA internal design, and interface protocol type.

[0011] Optionally, constraining the total consumed time by using a time constraint threshold includes: The time constraint threshold is used to constrain the sum of the running time of each module on the ARM side, the sum of the running time of each module on the FPGA side, and the sum of the time consumed by the interaction between each module and the ARM side module or the FPGA side module.

[0012] Optionally, the design complexity of the deployment architecture is calculated by the following formula, which includes: Complexity = w1*interaction logic complexity + w2*module complexity + w3*resource consumption + w4*computation time Wherein, w1, w2, w3 and w4 represent weighted coefficients; the interaction logic complexity is related to the number of interactions between the ARM side memory and the FPGA side memory; the module complexity is related to the module setting position, which includes the ARM side and the FPGA side.

[0013] According to another aspect of the present invention, there is provided an analysis device for a system-on-chip deployment numerical model, comprising: A design unit, used to design at least one deployment architecture of the current algorithm, wherein the deployment architecture includes at least one parallel module and at least one pipeline module; A first acquisition unit is used to respectively acquire the running time of each module on the ARM side of the algorithm running in the first deployment architecture, and the relative running time and absolute running time of each module on the FPGA side of the first deployment architecture; the first deployment architecture is any one of the at least one deployment architecture; A second acquisition unit is used to acquire the time consumed by the algorithm running in the first deployment architecture for the interaction between the ARM side module and the FPGA side module; A first constraint unit is used to constrain the total consumption time with a time constraint threshold; the total consumption time at least includes the operation consumption time of each module on the ARM side, the operation consumption time of each module on the FPGA side, and the time consumed by the interaction between the ARM side module and the FPGA side module; the operation consumption time of each module on the FPGA side is related to the relative time consumption and the absolute time consumption of each module operation; A second constraint unit, used to constrain the resource consumption of the system when the algorithm runs in the first deployment architecture with a resource upper limit; A complexity calculation unit is used to calculate the design complexity of the first deployment architecture based on the number of interactions between the ARM side memory and the FPGA side memory of the first deployment architecture, the module setting position, the resource consumption of the system and the total consumption time; and select the first deployment architecture with the smallest design complexity as the final deployment architecture solution.

[0014] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the analysis method of the on-chip system deployment numerical model described in any embodiment of the present invention.

[0015] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to implement the analysis method of the on-chip system deployment numerical model described in any embodiment of the present invention when executed by a processor.

[0016] The technical solution of the embodiment of the present invention is to design at least one deployment architecture of the current algorithm; obtain the running time of each module on the ARM side, the relative running time and the absolute running time on the FPGA side when the algorithm runs in the first deployment architecture; obtain the time consumed by the interaction between the ARM side module and the FPGA side module when the algorithm runs in the first deployment architecture; constrain the total consumption time with a time constraint threshold; constrain the resource consumption of the system with a resource upper limit; calculate the design complexity of the deployment architecture based on the number of interactions between the ARM side memory and the FPGA side memory of the first deployment architecture, the module setting position, the system resource consumption and the total consumption time; and select the deployment architecture with the smallest design complexity as the final deployment architecture solution, so as to give full play to the performance of the hybrid numerical model architecture and maximize the algorithm acceleration effect.

[0017] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A schematic diagram of a structure using a pure C language model architecture in an embodiment of the Zynq architecture; Figure 2A schematic diagram of a structure of a pure FPGA model architecture in an embodiment of a Zynq architecture; Figure 3 A schematic diagram of a structure of a hybrid numerical model architecture in an embodiment of a Zynq architecture; Figure 4 is a flow chart of an analysis method for a system-on-chip deployment numerical model provided according to Embodiment 1 of the present invention; Figure 5 A schematic diagram of the structure of a deployment architecture of an algorithm provided in Embodiment 1 of the present invention; Figure 6 A schematic diagram of system resource consumption when the first deployment architecture runs an algorithm in one embodiment of the present invention; Figure 7 A schematic diagram of power consumption of a first deployment architecture when running an algorithm in an embodiment of the present invention; Figure 8 A schematic diagram of the structure of an analysis device for a system-on-chip deployment numerical model provided in the second embodiment of the present invention; Fig. 9 It is a schematic diagram of the structure of an electronic device for implementing the analysis method of the system-on-chip deployment numerical model according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0022] The Zynq architecture is a unique system-level chip design. The platform combines ARM processors and FPGA architecture to provide a new system-level solution. Under the Zynq architecture, there are three possible deployment structures: pure C language model architecture, pure FPGA numerical model architecture, and hybrid numerical model architecture.

[0023] Among them, in the pure C language model architecture, the model calculation is completed by the Arm processor, and FPGA participation is not required. The advantage of its architecture is that the model is relatively easy to implement, and the resource consumption of a model is very low for the development board, so many models can be deployed. The disadvantage is that the pipeline calculation is time-consuming when calculating some modules. Figure 1 shown.

[0024] In the pure FPGA model architecture, the model is generated by Verilog, VHDL or HLS high-level synthesis tools, and the Arm processor does not participate in the calculation. Its architectural advantage is that it is based on specific optimization of the algorithm, can achieve structural parallelization and pipeline design, and the calculation time is significantly less than the pure C language model architecture, and the time can be shortened by dozens of times; but the disadvantage is that the FPGA core resources are limited, the number of deployed models is limited, and the development cycle is significantly longer than the pure C language model architecture. Figure 2 shown.

[0025] In the hybrid numerical model architecture, part of the model calculation is completed by the Arm side, and part of the calculation is completed by the FPGA. Its advantage is that more models can be placed on the Zynq development board with limited FPGA resources, which is more economical. The model calculation time is less than the pure C architecture, and generally longer than the pure FPGA design architecture. Its disadvantage is that the segmentation of the model needs to be processed, and the interaction between the Arm side and the FPGA side will be more frequent, making the interaction design more difficult, but the difficulty of model module design is lower than that of the pure FPGA architecture, such as Figure 3 shown.

[0026] The technical solution of the embodiment of the present invention is to design at least one deployment architecture of the current algorithm; obtain the running time of each module on the ARM side, the relative running time and the absolute running time on the FPGA side when the algorithm runs in the first deployment architecture; obtain the time consumed by the interaction between the ARM side module and the FPGA side module when the algorithm runs in the first deployment architecture; constrain the total consumption time with a time constraint threshold; constrain the resource consumption of the system with a resource upper limit; calculate the design complexity of the deployment architecture based on the number of interactions between the ARM side memory and the FPGA side memory of the first deployment architecture, the module setting position, the system resource consumption and the total consumption time; and select the deployment architecture with the smallest design complexity as the final deployment architecture solution, so as to give full play to the performance of the hybrid numerical model architecture and maximize the algorithm acceleration effect.

[0027] Embodiment 1 Figure 4 A flowchart of an analysis method for a system-on-chip deployment numerical model is provided for the first embodiment of the present invention. Figure 4 As shown, the method includes: S101. Design at least one deployment architecture of the current algorithm, wherein the deployment architecture includes at least one parallel module and at least one pipeline module.

[0028] In order to give full play to the performance of the algorithm, the algorithm can be divided into modules according to logic. For example, if there are parallel logical operations in the algorithm, the steps that can be executed simultaneously can be divided into parallel modules, and the parallel modules can be placed in the modules of the same level for execution; if the algorithm is a pipelined logic operation, that is, the next execution step can only be executed after the previous execution step is completed, the steps that are executed in sequence can be divided into pipelined modules. Figure 5 The model structure shown can logically divide the deployment architecture originally built by pipeline modules into parallel modules and pipeline module hierarchical execution structures. Figure 5 Step 1 and step 2 are parallel modules, and both are in the first level; step 1, step 3 and step 4 are pipelined modules. For the actual algorithm, for example, for the P2D electrochemical model algorithm, the first level contains three parallel modules, namely, the electric decoupling module, the solid phase module, and the liquid phase module. The second level module includes the module iteration module, the OCP (overcurrent protection) voltage calculation module, the solid-liquid phase matrix update module, etc.

[0029] And because the pipeline module and the parallel module can be executed on the ARM side as well as on the FPGA side, the deployment architecture can include multiple types, that is, the deployment architecture can be divided into multiple types according to the different locations of the pipeline module and the parallel module.

[0030] In one embodiment, due to the resource limitation of the system, there may be an insufficient number of modules in the first level. When the number of modules in the first level is insufficient, a module can be selected from the modules in the second level to execute the logical steps that should have been parallel logic, that is, step 1 and step 2 can be executed at the same time, but due to insufficient system resources, the execution action of step 2 is placed after the execution of step 1 is completed. At this time, step 1 and step 2 are transformed from the original parallel modules into pipeline modules.

[0031] S102. Obtain respectively the running time of each module on the ARM side of the algorithm in the first deployment architecture, and the relative running time and absolute running time of each module on the FPGA side; the first deployment architecture is any one of the at least one deployment architecture.

[0032] Since each module is located in a different position, it may be on the ARM side or on the FPGA side. On the ARM side, steps are usually executed in a pipeline mode, while on the FPGA side, it may be a parallel processing mode, a pipeline processing mode, or a hybrid processing mode. Therefore, it is necessary to calculate the running time of each module on the ARM side when the algorithm is running, as well as the relative running time and absolute running time of each module on the FPGA side. Among them, the absolute running time is the actual running time of each module, and the relative running time can be related to the actual number of clocks used by each module, the number of parallel modules, and the number of pipeline modules to calculate the running time of each module in the hybrid processing mode.

[0033] S103: Obtain the time consumed by the algorithm running in the first deployment architecture for the interaction between the ARM side module and the FPGA side module.

[0034] After the algorithm is divided into levels, each module may run on the ARM side or on the FPGA side, so there will be data interaction between the modules on the ARM side and the modules on the FPGA side. The more data interaction, the more time it consumes, and the slower the algorithm execution speed will be. The time consumed by the interaction between modules can be timed by timing the calling module driver interface.

[0035] In addition, the time consumed by data interaction is also related to the actual transmission data length, thread usage, logic timing of the FPGA internal design, interface protocol, etc. For example, for 32-bit data transmission, 1024 groups are used to determine the transmission performance. By calling the driver interface to perform timing tracking, the time taken for a data transmission and reception loop is obtained. The transmission performance can also be tested when different interface protocols are selected.

[0036] S104: Constrain the total consumed time using a time constraint threshold.

[0037] Among them, the total consumed time at least includes the running time of each module on the ARM side, the running time of each module on the FPGA side, and the time consumed for the interaction between the ARM side module and the FPGA side module; the running time of each module on the FPGA side is related to the relative running time and the absolute running time of each module.

[0038] S105: Using a resource upper limit to constrain system resource consumption when the algorithm runs in the first deployment architecture.

[0039] The resource consumption of the algorithm running on the system with the first deployment architecture can be directly obtained and retrieved. In one embodiment, Figure 6 A schematic diagram of system resource consumption when the first deployment architecture runs the algorithm; Figure 6 The system resources in the MCU include at least Look-Up Table, Look-Up Table Random Access Memory, Flip-Flop, Block RAM, Digital Signal Processor, Input / Output, Global Clock Buffer, and Mixed-Mode Clock Manager. Figure 7 This is a schematic diagram of the power consumption of the first deployment architecture when running the algorithm. Figure 7 The power consumption includes total chip power consumption, junction temperature, thermal margin, light efficiency, power provided to off-chip devices, and confidence level. At the same time, the resource upper limit of the development board can be obtained to constrain the resource consumption when the first deployment architecture runs the algorithm.

[0040] S106. Calculate the design complexity of the first deployment architecture based on the number of interactions between the ARM-side memory and the FPGA-side memory of the first deployment architecture, the module setting position, the resource consumption of the system, and the total consumption time; select the first deployment architecture with the smallest design complexity as the final deployment architecture solution.

[0041] The design complexity of the algorithm can be related to the number of interactions between the ARM side memory and the FPGA side memory. In this case, any module and the N associated modules are allocated on different platforms, that is, a module is allocated on the ARM module, and its N related modules are allocated on the FPGA side. Then the module needs to interact N times with its N related modules. The more interactions there are, the longer it takes and the higher the complexity.

[0042] The complexity of the algorithm is also related to the location of the module, which can be placed on the ARM side or the FPGA side. Modules with less computation per cycle can be placed on the ARM side, while modules with more computation per cycle can be placed on the FPGA side to complete the computation faster.

[0043] The complexity of each deployment structure for executing the algorithm can be obtained through a preset calculation formula, and the deployment structure with the lowest design complexity can be selected as the final deployment structure of the algorithm.

[0044] The technical solution of the embodiment of the present invention is to design at least one deployment architecture of the current algorithm; obtain the running time of each module on the ARM side, the relative running time and the absolute running time on the FPGA side when the algorithm runs in the first deployment architecture; obtain the time consumed by the interaction between the ARM side module and the FPGA side module when the algorithm runs in the first deployment architecture; constrain the total consumption time with a time constraint threshold; constrain the resource consumption of the system with a resource upper limit; calculate the design complexity of the deployment architecture based on the number of interactions between the ARM side memory and the FPGA side memory of the first deployment architecture, the module setting position, the system resource consumption and the total consumption time; and select the deployment architecture with the smallest design complexity as the final deployment architecture solution, so as to give full play to the performance of the hybrid numerical model architecture and maximize the algorithm acceleration effect.

[0045] In one embodiment, the running time of each module on the ARM side can be calculated by embedding points for each marking module of the model, adding a timing module, recording the time taken by each marking module, and running the algorithm multiple times to obtain multiple timing times of each model, and taking the average of the multiple timing times to calculate the final time taken by each marking module.

[0046] In one embodiment, the relative time consumption of the overall operation on the FPGA side is at least related to the actual number of clocks used by each module, the number of parallel modules, and the number of pipeline modules.

[0047] The FPGA side specifically counts the absolute and relative clock numbers used by each module; at the same time, the resource consumption of each module can be counted. The HLS high-level synthesis tool can be used for non-optimized synthesis, and the resource consumption report can be viewed after the IP is generated. The TCL script instruction can be used to generate IP cores for each module in the FPGA side algorithm (use TCL instructions to set each module as a top-level function in turn and perform synthesis design).

[0048] In one embodiment, the relative time consumption of the overall operation on the FPGA side is related to the relative clock number of the overall operation of each module on the FPGA side, and the relative clock number of the overall operation is: , The actual number of clocks for each module, is the number of parallel modules, is the number of pipelined modules.

[0049] After obtaining the time, perform time conversion. The time depends on the number of clocks and the clock frequency adopted in the actual project: , Frequency indicates the clock frequency, and CLK indicates the number of clocks.

[0050] In one embodiment, the time consumed for the interaction between the ARM side module and the FPGA side module is at least related to the actual transmission data length, thread usage, logic timing of the FPGA internal design, and interface protocol type.

[0051] In one embodiment, the time constraint threshold is used to constrain the sum of the running time of each module on the ARM side, the sum of the running time of each module on the FPGA side, and the sum of the time consumed by the interaction between each module and the ARM side module or the FPGA side module.

[0052] The specific constraint rules are: , In the formula, It means the total time spent; It means the time spent on the interaction of the jth module; It means the time spent by the nth module in Arm calculation; It means the time spent by the i-th module on the FPGA side; Preset for time constraints, which can be set based on experience.

[0053] In one embodiment, the resource upper limit is used to constrain the resource consumption of the system when the algorithm runs in the first deployment architecture, specifically: , In the formula, It means the resource consumption of each model deployment solution; It means the upper limit of each resource on the board.

[0054] In one embodiment, the design complexity of the deployment architecture may be calculated by the following formula, which includes: Complexity = w1*interaction logic complexity + w2*module complexity + w3*resource consumption + w4*computation time Wherein, w1, w2, w3 and w4 represent weighting coefficients, which can be set according to experience; the interaction logic complexity is related to the number of interactions between the ARM side memory and the FPGA side memory; the module complexity is related to the module setting position, which includes the ARM side and the FPGA side.

[0055] It should be noted that the time constraint threshold can be used to eliminate deployment architectures whose total consumption time is greater than the time constraint threshold, and the resource upper limit can be used to propose deployment architectures whose system resource consumption is greater than the resource upper limit. Finally, the final deployment architecture is selected by calculating the minimum complexity to reduce the amount of calculation.

[0056] Embodiment 2 Figure 8 This is a schematic diagram of the structure of an analysis device for a system-on-chip deployment numerical model provided in Embodiment 3 of the present invention. Figure 8 As shown, the device comprises: A design unit 801 is used to design at least one deployment architecture of the current algorithm, wherein the deployment architecture includes at least one parallel module and at least one pipeline module; A first acquisition unit 802 is used to respectively acquire the running time of each module on the ARM side of the algorithm running in the first deployment architecture, and the relative running time and absolute running time of each module on the FPGA side of the first deployment architecture; the first deployment architecture is any one of the at least one deployment architecture; The second acquisition unit 803 is used to acquire the time consumed by the interaction between the ARM side module and the FPGA side module in the first deployment architecture when the algorithm is running; The first constraint unit 804 is used to constrain the total consumption time with a time constraint threshold; the total consumption time at least includes the operation consumption time of each module on the ARM side, the operation consumption time of each module on the FPGA side, and the time consumed by the interaction between the ARM side module and the FPGA side module; the operation consumption time of each module on the FPGA side is related to the relative time consumption and the absolute time consumption of each module operation; A second constraint unit 805 is used to constrain the resource consumption of the system when the algorithm runs in the first deployment architecture with a resource upper limit; The complexity calculation unit 806 is used to calculate the design complexity of the first deployment architecture based on the number of interactions between the ARM side memory and the FPGA side memory of the first deployment architecture, the module setting position, the resource consumption of the system and the total consumption time, and select the first deployment architecture with the smallest design complexity as the final deployment architecture solution.

[0057] In one embodiment, the first acquisition unit 802 is further used to decompose the algorithm logic into multiple execution steps; each execution step corresponds to a parallel module or a pipeline module; the parallel module executes steps that can be performed simultaneously, and the pipeline module executes steps that are performed sequentially; At least one of the deployment architectures is formed based on the disassembled execution steps.

[0058] In one embodiment, the first constraint unit 804 is also used to ensure that the sum of the running time of each module on the ARM side, the sum of the running time of each module on the FPGA side, and the sum of the time consumed by the interaction between each module and the ARM side module or the FPGA side module is less than the time constraint threshold.

[0059] The message data processing resource scheduling device provided in the embodiment of the present invention can execute the message data processing resource scheduling device method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0060] Embodiment 3 Fig. 9 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0061] like Fig. 9 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. The input / output (I / O) interface 15 is also connected to the bus 14.

[0062] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0063] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as an analysis method for deploying a numerical model of a system on a chip.

[0064] In some embodiments, a method for analyzing a numerical model of a system-on-chip deployment may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the method for analyzing a numerical model of a system-on-chip deployment described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute a method for analyzing a numerical model of a system-on-chip deployment in any other appropriate manner (e.g., by means of firmware).

[0065] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0066] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0067] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0068] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0069] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0070] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0071] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0072] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for analyzing a numerical model of system-on-chip deployment, characterized in that: include: Designing at least one deployment architecture of the current algorithm, wherein the deployment architecture includes at least one parallel module and at least one pipeline module; Obtain respectively the running time of each module on the ARM side of the algorithm running in the first deployment architecture, and the relative running time and absolute running time of each module on the FPGA side; The first deployment architecture is any one of the at least one deployment architecture; Obtain the time consumed by the algorithm running in the first deployment architecture for the interaction between the ARM side module and the FPGA side module; The total consumption time is constrained by a time constraint threshold; The total consumption time at least includes the operation consumption time of each module on the ARM side, the operation consumption time of each module on the FPGA side, and the time consumed by the interaction between the ARM side module and the FPGA side module; the operation consumption time of each module on the FPGA side is related to the relative time consumption and the absolute time consumption of each module operation; Using a resource cap to constrain system resource consumption when the algorithm runs on the first deployment architecture; Calculate the design complexity of the first deployment architecture based on the number of interactions between the ARM side memory and the FPGA side memory of the first deployment architecture, the module setting position, the resource consumption of the system, and the total consumption time; The first deployment architecture with the smallest design complexity is selected as the final deployment architecture solution.

2. The method for analyzing the system-on-chip deployment numerical model according to claim 1, characterized in that: The design of at least one deployment architecture of the current algorithm includes: The algorithm logic is disassembled into multiple execution steps; each execution step corresponds to a parallel module or a pipeline module; the parallel module executes the steps that can be performed simultaneously, and the pipeline module executes the steps that are performed sequentially; At least one of the deployment architectures is formed based on the disassembled execution steps.

3. The method for analyzing the system-on-chip deployment numerical model according to claim 1, characterized in that: The relative time consumption of the overall operation on the FPGA side is at least related to the actual number of clocks used by each module, the number of parallel modules, and the number of pipelined modules.

4. The method for analyzing the system-on-chip deployment numerical model according to claim 3, characterized in that: The relative time consuming of the overall operation on the FPGA side is related to the relative clock number of the overall operation of each module on the FPGA side, and the relative clock number of the overall operation is: ， The actual number of clocks for each module, is the number of parallel modules, is the number of pipelined modules.

5. The method for analyzing the system-on-chip deployment numerical model according to claim 1, characterized in that: The time consumed for the interaction between the ARM side module and the FPGA side module is at least related to the actual transmission data length, thread usage, logic timing of the FPGA internal design, and interface protocol type.

6. The method for analyzing the numerical model of system-on-chip deployment according to claim 1, characterized in that: The constraining the total consumption time by the time constraint threshold comprises: The time constraint threshold is used to constrain the sum of the running time of each module on the ARM side, the sum of the running time of each module on the FPGA side, and the sum of the time consumed by the interaction between each module and the ARM side module or the FPGA side module.

7. The method for analyzing the system-on-chip deployment numerical model according to claim 1, characterized in that: The design complexity of the deployment architecture is calculated by the following formula, which includes: Complexity = w1*interaction logic complexity + w2*module complexity + w3*resource consumption + w4*computation time Wherein, w1, w2, w3 and w4 represent weighted coefficients; the interaction logic complexity is related to the number of interactions between the ARM side memory and the FPGA side memory; the module complexity is related to the module setting position, which includes the ARM side and the FPGA side.

8. An analysis device for a system-on-chip deployment numerical model, characterized in that: include: A design unit, configured to design at least one deployment architecture of the current algorithm, wherein the deployment architecture includes at least one parallel module and at least one pipeline module; A first acquisition unit is used to respectively acquire the running time of each module on the ARM side of the algorithm running in the first deployment architecture, and the relative running time and absolute running time of each module on the FPGA side of the first deployment architecture; The first deployment architecture is any one of the at least one deployment architecture; A second acquisition unit is used to acquire the time consumed by the interaction between the ARM side module and the FPGA side module in the first deployment architecture when the algorithm is running; A first constraint unit is used to constrain the total consumption time with a time constraint threshold; the total consumption time at least includes the operation consumption time of each module on the ARM side, the operation consumption time of each module on the FPGA side, and the time consumed by the interaction between the ARM side module and the FPGA side module; the operation consumption time of each module on the FPGA side is related to the relative time consumption and the absolute time consumption of each module operation; A second constraint unit, used to constrain the resource consumption of the system when the algorithm runs in the first deployment architecture with a resource upper limit; A complexity calculation unit is used to calculate the design complexity of the first deployment architecture based on the number of interactions between the ARM side memory and the FPGA side memory of the first deployment architecture, the module setting position, the resource consumption of the system and the total consumption time, and select the first deployment architecture with the smallest design complexity as the final deployment architecture solution.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the method for analyzing the system-on-chip deployment numerical model according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method for analyzing a numerical model of a system-on-chip deployment according to any one of claims 1 to 7 when the instructions are executed.

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