A GPU task execution method, device and medium

Abstract

The present application discloses a GPU task execution method, device and medium, which relates to the field of computing technology and is used to solve the problems of slow GPU task execution efficiency and complex data processing flow. The method includes: GDDR is divided into register area and general memory area according to high and low address segments. According to the source data volume and binary program volume of a single computing task, the source data, binary program and calculation result storage addresses are divided in the general memory area. The source data and binary program are copied to the corresponding storage addresses respectively by using the memory mapping mechanism, and the address writing operation is performed on the register area, and the above-mentioned storage addresses are searched accordingly. The computing core activation mask is written to the register area to activate the core. By partitioning the GDDR function, the precise control of the computing core and the data transmission management function are realized. By replacing the computing core of the original complex instruction set of the GPU with the computing core of the simple instruction set, the complexity of programming is reduced.

Description

Technical Field

[0001] The present application relates to the field of computing technology, and in particular to a GPU task execution method, device and medium. Background Art

[0002] With the continuous advancement of technology, especially in the fields of artificial intelligence, deep learning and high-performance computing, GPU accelerated computing has become a key force driving innovation in these fields.

[0003] At present, the complex language and tool software required for GPU programming have too slow computing efficiency for most simple tasks and complicated data processing procedures, posing a considerable challenge to those new to the industry. Summary of the invention

[0004] The embodiments of the present application provide a GPU task execution method, device and medium, which are used to solve the problems of slow GPU task execution efficiency and complex data processing flow.

[0005] The present application embodiment adopts the following technical solutions:

[0006] On the one hand, an embodiment of the present application provides a GPU task execution method, the method comprising: dividing a GDDR area into high and low address segments to obtain a register area and a general memory area; the address segment of the register area is lower than the address segment of the general memory area; dividing the general memory area according to the source data volume and binary program volume of a single task to obtain a source data storage address, a binary program storage address and a calculation result storage address; the binary program is obtained by compiling a kernel function required for task execution; copying the source data and binary program of the task to the source data storage address and the binary program storage address respectively through a memory mapping mechanism; performing an address write operation on the register area so that the source data storage address, the binary program storage address and the calculation result storage address can be searched through the register area; when writing the activation mask of the computing core to the register area, activating the computing core through the GPU; reading the register area through the GPU so that the computing core performs task calculation on the source data according to the binary program.

[0007] In one example, the register area includes multiple first registers and multiple second registers; each computing core of the GPU corresponds to a first register and a second register; an address write operation is performed on the register area to search for a source data storage address, a binary program storage address, and a calculation result storage address through the register area, specifically including: performing an address write operation on a target first register of the computing core to search for a binary program storage address in the target first register; performing an address write operation on a target second register of the computing core to search for a source data storage address and a calculation result storage address through the target second register.

[0008] In one example, an address write operation is performed on the target second register of the computing core so that the source data storage address and the calculation result storage address are found through the target second register, specifically including: an address write operation is performed on the target second register of the computing core to find the parameter structure storage address of the general memory area in the target second register, and the parameter structure storage address is obtained by encapsulating the source data storage address and the calculation result storage address.

[0009] In one example, the method also includes: dividing the general memory area according to the source data storage address and the calculation result storage address to obtain the parameter structure storage address; encapsulating the source data storage address, the calculation result storage address, the space of the source data storage address and the space of the calculation result storage address to obtain the parameter structure; and copying the parameter structure to the parameter structure storage address through the memory mapping mechanism.

[0010] In one example, the register area is read by the GPU so that the computing core performs task calculations on the source data according to the binary program, specifically including: reading the binary program storage address from the target first register by the AFU of the GPU, so that the AFU obtains the binary program from the general memory area, and copies the binary program storage address to the PC register of the computing core; reading the parameter structure storage address from the target second register by the computing core, so that the computing core obtains the source data and the calculation result storage address from the general memory area; when the computing core traverses the execution order of the binary program storage address, the computing core performs task calculations on the source data according to the binary program.

[0011] In one example, the register area also includes a third register; each bit of the third register corresponds to a computing core; when the activation mask of the computing core is written to the register area, the computing core is activated through the GPU, specifically including: writing the activation mask to the first target bit of the computing core in the third register, and activating the computing core when the GPU reads the activation mask.

[0012] In one example, the register area also includes a fourth register; each bit of the fourth register corresponds to a computing core; after reading the register area through the GPU so that the computing core performs task calculations on the source data according to the binary program, the method also includes: looking up the value of the second target bit of the computing core in the fourth register, and when the value of the second target bit is the same as the initial value, determining that the computing core has completed the task; when the value of the target bit is different from the initial value, determining that the computing core has not completed the task.

[0013] In one example, the method further includes: the computing core is a simple instruction set computing core, and the kernel function is written in the same way as the embedded C program.

[0014] On the other hand, an embodiment of the present application provides a GPU task execution device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute any one of the above-mentioned GPU task execution methods.

[0015] On the other hand, an embodiment of the present application provides a GPU task execution non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions can execute any one of the above-mentioned GPU task execution methods.

[0016] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects:

[0017] This application lays the foundation for data storage and management by dividing GDDR into a register area and a general memory area. The register area stores key control information, and the general memory area is used to store binary programs, source data, and calculation results, ensuring orderly data storage and efficient access, and improving data processing efficiency. By migrating the computing core of a simple instruction set to the GPU, the kernel function can be written in the same way as an embedded C program, simplifying the complexity of GPU programming and reducing the difficulty for ordinary programmers to design accelerated computing programs, which is crucial to promoting the healthy development of the industry. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solution of the present application, some embodiments of the present application will be described in detail below in conjunction with the accompanying drawings, in which:

[0019] Figure 1 A flowchart of a GPU task execution method provided in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of the structure of a GPU task execution device according to an embodiment of the present application;

[0021] Figure 3 A schematic diagram of a GPU task execution process according to an embodiment of the present application;

[0022] Figure 4 A schematic diagram of the structure of a GPU task execution device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0024] Some embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0025] Figure 1 A flowchart of a GPU task execution method provided in an embodiment of the present application. The method can be applied to different business fields. Certain input parameters or intermediate results in the process allow manual intervention and adjustment to help improve accuracy.

[0026] The analysis method involved in the embodiment of the present application can be implemented by a terminal device or a server, and the present application does not impose any special restrictions on this. For the convenience of understanding and description, the following embodiments are described in detail by taking the control host as an example.

[0027] It should be noted that, in some embodiments of the present application, the GPU includes an AFU (Acceleration Function Unit), a PCIe (Peripheral Component Interface Express) controller, a DMA (Direct Memory Access) controller and multiple computing cores.

[0028] AFU is an acceleration function unit that manages all computing cores and register areas. After writing to the register area, AFU sets the computing core according to the status of the register.

[0029] The PCIe controller is controlled by the DMA controller to perform bidirectional data transmission.

[0030] The computing core is a simple instruction set computing core. The kernel function is written in the same way as the embedded C program, which simplifies the complexity of GPU programming and reduces the difficulty for ordinary programmers to design accelerated computing programs.

[0031] S101: Divide the GDDR area into high and low address segments to obtain a register area and a general memory area; the address segment of the register area is lower than the address segment of the general memory area.

[0032] In some embodiments of the present application, GDDR is divided into two areas, the low address segment starting from address 0x00000000 is defined as the register area, and the high address segment starting from address 0x10000000 is defined as the general memory area.

[0033] It should be noted that the register area is placed at the low address end for the convenience of expansion. For example, if the register is placed after 1G in the memory, but a low-end model has a total memory of less than 1G, the task cannot be performed. If we place the register at address 0, the register may only take up a few KB in total. Even if our low-end model has a memory of only a few M, this architecture can still be used. That is, we place the register at a low address so that the registers of high, medium and low-end models have the same address, which is convenient for software writing and software porting.

[0034] Furthermore, the register area is divided into a plurality of first registers, a plurality of second registers, a third register, a fourth register and a fifth register.

[0035] Each computing core of the GPU corresponds to a first register, which is used to store the binary program storage address; each computing core of the GPU corresponds to a second register, which is used to store the parameter structure storage address; each bit of the third register corresponds to a computing core, and when the activation mask of the computing core is written to the third register, the computing core is activated by the AFU. Each bit of the fourth register corresponds to a computing core and is used to indicate the status of the computing core. Each bit of the fifth register corresponds to a computing core, allowing the AFU to restart any computing core. For example, the initial value of each bit after power-on is 0. After any computing core is activated, write 1 to the corresponding bit, and the AFU will reset the corresponding computing core.

[0036] By partitioning the GDDR functions, precise control of the computing core and data transmission management functions are achieved, improving the efficiency of the computing core in processing data.

[0037] S102: Divide the general memory area according to the source data volume and binary program volume of a single computing core to obtain source data storage addresses, binary program storage addresses and calculation result storage addresses; the binary program is obtained by compiling the kernel function required for task execution.

[0038] It should be noted that before dividing the general memory, it is necessary to read the source data for calculation and the size of the source data from the file in advance or use the formula, write the kernel function for the core calculation, call the compiler to compile the kernel function into a binary file program, and get the size of the binary program.

[0039] In some embodiments of the present application, in the general memory area, the memory management interface of the application program will calculate and determine the specific storage location according to the total size and allocation status of the general memory area of ​​GDDR, and obtain the source data storage address and the binary program storage address. For example, if the general memory area size is 1G in total and the source data size is 50MB, then the source data will be allocated to the general area of ​​memory larger than 50MB, and the address of this general area is the source data storage address.

[0040] By dividing the source data and binary programs in the general memory area with high addresses, it is convenient to isolate the functions of the register area, making memory management clearer and more orderly. For example, when performing multi-task computing, the binary programs and source data of different computing cores can be allocated and stored in the general memory area according to certain rules without interfering with the control information of the register area, which is conducive to improving the stability and maintainability of the system.

[0041] S103: Copying the source data and the binary program of the task to the source data storage address and the binary program storage address respectively through a memory mapping mechanism.

[0042] It should be noted that the DMA controller is controlled by the GPU, and the GPU can set it in detail, including the source address, destination address, data length, bit width, big and small endian parameters of data transmission. For example, when transferring the binary program and source data required by the computing core from the host memory to the GDDR general memory area of ​​the GPU, the GPU will accurately set the relevant parameters of the DMA controller according to the actual storage location of these data in the host memory and the predetermined storage location in the GPU memory, and then start the data transmission. This design enables data to be moved between different storage areas accurately and efficiently according to the requirements of the application, avoiding the CPU from being too involved in the tedious operation of data transmission, and improving the efficiency of data transmission and the overall performance of the system.

[0043] In the scenario of multi-tasking, different computing cores may require different binary programs and source data. The DMA controller can orderly transfer the data required by each task to the corresponding storage location according to the settings of the application. For example, when performing multiple different types of computing tasks (such as image processing tasks and mathematical computing tasks) at the same time, the DMA controller can accurately transfer the image data and related programs of the image processing tasks, as well as the numerical data and computing programs of the mathematical computing tasks to the corresponding addresses of the general memory area, providing data guarantee for the execution of subsequent computing cores and ensuring the smooth execution of multi-tasking.

[0044] In some embodiments of the present application, by setting a DMA controller in the GPU, data transfer is started, and the source data and binary program of the computing core task are copied to the source data storage address and the binary program storage address respectively.

[0045] S104: performing an address writing operation on the register area, so as to search for the source data storage address, the binary program storage address and the calculation result storage address through the register area.

[0046] In some embodiments of the present application, the source data storage address, the calculation result storage address, the space of the source data storage address and the space of the calculation result storage address are encapsulated to obtain a parameter structure, and the general memory area is divided according to the source data storage address and the calculation result storage address to obtain the parameter structure storage address.

[0047] Specifically: The memory management interface will take into account the total size of the general memory and the current allocation status for calculation. First, it will evaluate the occupied memory areas, which store the binary program, source data, and calculation results of the computing core. Then, according to the remaining available memory space, a suitable address range is determined according to the rules for storing the parameter structure. For example, if part of the general memory is already occupied by the binary program in the lower address segment, and the source data is stored in the middle address segment, the memory management interface will look for a continuous space in the higher unoccupied address area to allocate to the parameter structure, and determine the starting address of the space as the parameter structure storage address. This allocation method can ensure that the parameter structure has a reasonable storage location in the general memory, which does not conflict with other key data, and is convenient for the computing core to quickly access during execution.

[0048] Furthermore, by setting the DMA controller in the GPU, data transmission is started and the parameter structure is copied to the parameter structure storage address. Then the AFU performs an address write operation on the target first register of the computing core to find the binary program storage address in the target first register, and performs an address write operation on the target second register of the computing core to find the parameter structure storage address of the general memory area in the target second register. The parameter structure includes a source data storage address and a calculation result storage address, that is, the source data storage address and the calculation result storage address are found through the target second register.

[0049] S105: When the activation mask of the computing core is written into the register area, the computing core is activated through the GPU.

[0050] It should be noted that the activation mask is written to the first target bit of the computing core in the third register, and when the AFU reads the activation mask, the computing core is activated. For example, the initial value of each bit of the third register after power-on is 0. If 1 is written to any bit, the AFU will activate the corresponding computing core and clear the corresponding bit.

[0051] S106: The register area is read by the GPU so that the computing core performs task calculation on the source data according to the binary program.

[0052] In some embodiments of the present application, the binary program storage address is read from the target first register by the AFU of the GPU, so that the AFU obtains the binary program from the general memory area, and copies the binary program storage address to the PC register of the computing core, and then the parameter structure storage address is read from the target second register by the AFU, so that the AFU obtains the source data and the calculation result storage address from the general memory area; the computing core performs task calculation on the source data according to the binary program through the computing core in the execution order of the binary program storage address, and stores the calculation result to the calculation result storage address.

[0053] It should be noted that, since the kernel function of the computer may have errors, the accuracy of the kernel function may be verified until the test passes, and the kernel function of the calculation core begins to perform task calculations, that is, the above steps S103-S106.

[0054] For example, test data is selected from the source data, and the above-mentioned task execution process contents of S103-S106 are executed on the test data. That is, the source data is replaced with the test data. Then, after the computing core performs task calculation on the test data, according to the verification function pre-built by the host, by polling the fourth register, the value of the target bit of the computing core in the fourth register is checked to determine whether the task calculation is completed. If the calculation is completed, the application reads back the calculation result from the calculation result storage address and compares it with the result calculated by the verification function. If the results are consistent, the test passes. If the results are inconsistent, it is necessary to check the kernel function and the verification function, and test again after determining the cause of the problem. The reasons include logical errors in the kernel function or the verification function, data mismatch, and writing errors.

[0055] It should be noted that by querying the value of the second target bit of the computing core in the fourth register, when the value of the second target bit is the same as the initial value, it is determined that the computing core has completed the task; when the value of the target bit is different from the initial value, it is determined that the computing core has not completed the task.

[0056] Through testing with test data, based on mature test cases, users only need to modify the file path or formula for obtaining source data, kernel function and verification function to realize their own accelerated computing design. Moreover, the writing of kernel function is the same as that of ordinary embedded C program, and the writing of verification function is the same as that of ordinary host computer C++ program, which greatly simplifies the complexity of GPU programming and reduces the difficulty for ordinary programmers to design accelerated computing programs.

[0057] It should be noted that although the embodiments of the present application are based on Figure 1 Steps S101 to S106 are described in sequence, but this does not mean that steps S101 to S106 must be performed in a strict order. Figure 1 The order shown in the figure is to introduce and explain step S101 to step S106 in sequence, in order to facilitate those skilled in the art to understand the technical solution of the embodiment of the present application. In other words, in the embodiment of the present application, the order between step S101 to step S106 can be appropriately adjusted according to actual needs.

[0058] pass Figure 1The method divides GDDR into register area and general memory area, laying the foundation for data storage and management. The register area stores key control information, and the general memory area is used to store binary programs, source data and calculation results, ensuring orderly storage and efficient access of data, and improving data processing efficiency. By migrating the computing core of a simple instruction set to the GPU, the kernel function can be written in the way of embedded C program, simplifying the complexity of GPU programming and reducing the difficulty of ordinary programmers to design accelerated computing programs, which is crucial to promoting the healthy development of the industry.

[0059] Figure 2 A schematic diagram of the structure of a GPU task execution device according to an embodiment of the present application.

[0060] exist Figure 2 The GPU task execution device structure is shown in Figure 1, which includes two parts: GPU and GDDR. The GPU includes AFU, PCIe controller, DMA controller and multiple computing cores (Core0, Core1, Core2, Core3). GDDR includes register area (Registers) and general memory area (Memory).

[0061] Figure 3 A schematic diagram of a GPU task execution process according to an embodiment of the present application.

[0062] exist Figure 3 In the figure, the steps from top to bottom are: first, obtain the source data for calculation by reading files or using formulas, and write the kernel function for the calculation core calculation, then compile the kernel function to convert it into a binary program file, then write the host calculation verification function, call the memory management interface to obtain the binary program storage address, source data storage address, calculation result storage address and parameter structure storage address (addr_kernel, addr_src0, addr_src1, addr_src2, addr_dst and addr_arg); then copy the binary program, source data and parameter structure to the device (binary program storage address, source data storage address, parameter structure storage address), then write the binary program address and parameter structure address to the target first register (CTL_KERNEL_ADDR register) and the target second register (CTL_ARG_ADDR register) respectively; and write the third register (CTL_AP_START register) to activate the calculation core. It should be noted that when the data copied to the source data storage address is part of the test data of the source data, that is, when executing the test, it is necessary to query the fourth register (CTL_AP_IDLE register) to determine whether the calculation is completed. If the calculation is not completed, continue to poll the fourth register. If the calculation is completed, read the calculation result back from the calculation result storage address and execute the verification function.

[0063] Figure 4 A schematic diagram of the structure of a GPU task execution device provided in an embodiment of the present application includes:

[0064] at least one processor; and,

[0065] a memory communicatively connected to at least one processor; wherein,

[0066] The memory stores instructions that can be executed by at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute any one of the above-mentioned GPU task execution methods.

[0067] Some embodiments of the present application provide a GPU task execution non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions can execute any one of the above-mentioned GPU task execution methods.

[0068] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0069] The devices and media provided in the embodiments of the present application correspond one-to-one to the methods. Therefore, the devices and media also have similar beneficial technical effects as the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media will not be repeated here.

[0070] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0071] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0072] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0073] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0074] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0075] Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM), and non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0076] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0077] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0078] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the technical principle of the present application should fall within the protection scope of the present application.

Claims

1. A GPU task execution method, characterized in that: The method comprises: Dividing the GDDR area into high and low address segments to obtain a register area and a general memory area; the address segment of the register area is lower than the address segment of the general memory area; The general memory area is divided according to the source data volume and binary program volume of a single task to obtain source data storage addresses, binary program storage addresses and calculation result storage addresses; the binary program is obtained by compiling the kernel function required for task execution; Copying the source data and binary program of the task to the source data storage address and the binary program storage address respectively through a memory mapping mechanism; Performing an address writing operation on the register area, so as to search for the source data storage address, the binary program storage address and the calculation result storage address through the register area; When writing the activation mask of the computing core into the register area, activating the computing core through the GPU; The register area is read by the GPU so that the computing core performs task calculation on the source data according to the binary program.

2. The method according to claim 1, characterized in that The register area includes a plurality of first registers and a plurality of second registers; each computing core of the GPU corresponds to a first register and a second register; The performing of an address writing operation on the register area so as to search for a source data storage address, a binary program storage address and a calculation result storage address through the register area specifically includes: Performing an address write operation on a target first register of the computing core, so as to search for the binary program storage address in the target first register; An address writing operation is performed on the target second register of the computing core, so that the source data storage address and the calculation result storage address are searched through the target second register.

3. The method according to claim 2, characterized in that The performing an address writing operation on the target second register of the computing core so as to search the source data storage address and the computing result storage address through the target second register specifically includes: An address writing operation is performed on the target second register of the computing core to search for the parameter structure storage address of the general memory area in the target second register, wherein the parameter structure storage address is obtained by encapsulating the source data storage address and the calculation result storage address.

4. The method according to claim 3, characterized in that The method further comprises: According to the source data storage address and the calculation result storage address, the general memory area is divided to obtain a parameter structure storage address; Encapsulate the source data storage address, the calculation result storage address, the space of the source data storage address and the space of the calculation result storage address to obtain a parameter structure; The parameter structure is copied to the parameter structure storage address through the memory mapping mechanism.

5. The method according to claim 3, characterized in that: The reading of the register area by the GPU so that the computing core performs task calculation on the source data according to the binary program specifically includes: Reading the binary program storage address from the target first register through the AFU of the GPU, and copying the binary program storage address to the PC register of the computing core; Reading the parameter structure storage address from the target second register through the computing core, so that the computing core obtains the source data and the calculation result storage address from the general memory area; When the computing core traverses the execution order of the storage addresses of the binary program, the computing core performs task calculation on the source data according to the binary program.

6. The method according to claim 1, characterized in that The register area also includes a third register; each bit of the third register corresponds to a computing core; When the activation mask of the computing core is written into the register area, activating the computing core by the GPU specifically includes: An activation mask is written into the first target bit of the computing core in the third register, and when the GPU reads the activation mask, the computing core is activated.

7. The method according to claim 1, characterized in that The register area also includes a fourth register; each bit of the fourth register corresponds to a computing core; After the GPU reads the register area so that the computing core performs task calculation on the source data according to the binary program, the method further includes: searching for a value of a second target bit of the computing core in the fourth register, and determining that the computing core has completed executing the task when the value of the second target bit is the same as the initial value; When the value of the target bit is different from the initial value, it is determined that the execution task of the computing core is not completed.

8. The method according to claim 1, characterized in that The method further comprises: The computing core is a simple instruction set computing core, and the writing procedure of the kernel function is the same as the writing method of the embedded C program.

9. A GPU task execution device, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute a GPU task execution method as described in any one of claims 1-8.

10. A GPU task execution storage medium storing computer executable instructions, characterized in that: The computer executable instructions can execute a GPU task execution method as described in any one of claims 1 to 8.

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