Constant current driving method of LED display screen, constant current driving chip and LED display screen

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In the constant current driving method of the LED display screen, multiple groups of grayscale clock signals are received in turn, and row switching signals are received when receiving the read data clock, and the target row is determined, which solves the problem of limited brightness efficiency in the prior art. Achieve higher brightness efficiency and shorter scanning time.

CN119479533AActive Publication Date: 2025-02-18XIAN QINGSONG PHOTOELECTRIC TECH CO LTD

Patent Information

Application Number: CN202310942913.4
Authority / Receiving Office: CN · China
Patent Type: Applications(China)
Current Assignee / Owner
Filing Date: 2023-07-28
Publication Date: 2025-02-18
Estimated Expiration: 2043-07-28

AI Technical Summary

Technical Problem

In the prior art, the brightness efficiency is limited when driving LED display, resulting in insufficient display brightness of the LED.

Method used

By sequentially receiving multiple groups of grayscale clock signals inputted by external input, and the currently received grayscale clock signal is a grayscale clock, based on the first display data corresponding to the read data clock in the previous group of grayscale clock signals, the first display data is read according to the reading data clock in the previous group of grayscale clock signals. The LED lamp beads in the target row output the corresponding constant current driving signal to drive the LED lamp beads to emit light; when the currently received grayscale clock signal is a read data clock, the output of the constant current driving signal is stopped and the second display data is read. , the second display data is used for the scanning process corresponding to the next group of grayscale clock signals, and when receiving the read data clock, the row switching signal is received, and the grayscale clock correspondence in the next group of grayscale clock signals is determined according to the row switching signal. The target row driven by the constant current driving signal.

Benefits of technology

By receiving the row switching signal during the process of receiving the read data clock, the spare time period that occurs in a scan is shortened, thereby shortening the total time required for a scan, and increasing the duration of the grayscale clock in the total time This improves the brightness efficiency during LED display.

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Abstract

The embodiment of the invention discloses a constant-current driving method of an LED display screen, a constant-current driving chip and the LED display screen, and the method comprises the steps: sequentially receiving a plurality of groups of gray scale clock signals inputted from the outside, each group of gray scale clock signals being composed of a plurality of gray scale clocks and a plurality of read data clocks; when the gray scale clock is currently received, outputting a corresponding constant current driving signal to the LED lamp beads of the current target row based on first display data correspondingly read by a data reading clock in the previous group of gray scale clock signals, so as to drive the LED lamp beads to display; when a read data clock is currently received, the constant current driving signal is stopped from being output, second display data are read, and the second display data are used for next scanning; and in the process of receiving a plurality of continuous read data clocks, receiving a row switching signal, and determining a target row driven by the constant current driving signal corresponding to the next group of gray scale clock signals according to the row switching signal. By adopting the method, the technical problem that the brightness efficiency is limited when an LED is driven to display in the prior art can be solved.

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Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of LED display screens, and in particular to a constant current driving method of an LED display screen, a constant current driving chip, and an LED display screen. Background Art

[0002] Light-emitting diode (LED) is a commonly used light-emitting device that can efficiently convert electrical energy into light energy. Therefore, it is widely used in display, lighting and other fields. In the display field, small-pitch LED display screens composed of LEDs are widely used in high-definition display scenarios.

[0003] In small-pitch LED displays, constant current driver chips are usually used to precisely control the light-emitting diodes point-to-point. During control, a scan of the constant current driver chip can include three processes: 1. Output a constant current drive signal for driving the LEDs in the corresponding row for display; 2. Read the display data corresponding to the constant current drive signal output in the next scan; 3. Line break and blanking. After the three processes are executed in sequence, a scan of the constant current driver chip can be achieved.

[0004] During a scan, the LED emits light during the on-time, and the brightness of the LED light will be different when the on-time is different, that is, the brightness of the LED is related to the specific value of the on-time. In some technologies, the proportion of the maximum value of the LED's on-time during a scan to the total time required for a scan can be understood as the brightness efficiency when driving the LED display. However, the LED's on-time is related to the constant current drive signal, that is, the maximum value of the LED's on-time is related to the duration of the first process of outputting the constant current drive signal, and the duration of the first process accounts for a limited proportion of the total time required for a scan, which makes the brightness efficiency limited, that is, the display brightness of the LED is limited when driving the LED display. Summary of the invention

[0005] An embodiment of the present application provides a constant current driving method, a constant current driving chip and an LED display screen for solving the technical problem of limited brightness efficiency when driving LED displays in related technologies.

[0006] In a first aspect, an embodiment of the present application provides a constant current driving method for an LED display screen, comprising:

[0007] sequentially receiving a plurality of groups of grayscale clock signals inputted from the outside, each group of the grayscale clock signals being composed of a plurality of continuous grayscale clocks and a plurality of continuous read data clocks, and the grayscale clocks in a group of the grayscale clock signals being received before the read data clocks;

[0008] When the grayscale clock signal currently received is a grayscale clock, a corresponding constant current driving signal is output to the LED lamp beads of the current target row based on the first display data correspondingly read under the read data clock in the previous set of grayscale clock signals, so as to drive the LED lamp beads of the current target row to display;

[0009] When the grayscale clock signal currently received is a data reading clock, the constant current driving signal is stopped from being output, and the second display data is read, and the constant current driving signal corresponding to the second display data is used to be output under the grayscale clock in the next group of grayscale clock signals;

[0010] In the process of receiving a plurality of continuous data reading clocks, a row switching signal is received, and a target row driven by a constant current driving signal corresponding to a gray clock in a next group of gray clock signals is determined according to the row switching signal.

[0011] In a second aspect, an embodiment of the present application further provides a constant current driving chip for an LED display screen, and the constant current driving chip can execute the constant current driving method for an LED display screen as described in the first aspect.

[0012] In a third aspect, an embodiment of the present application further provides an LED display screen, comprising: a receiving card and an LED light board, wherein the receiving card comprises a logic chip, and the LED light board comprises a plurality of LED lamp beads, at least one constant current driver chip and at least one row driver chip.

[0013] The logic chip is used to sequentially send multiple groups of grayscale clock signals to the constant current driving chip, each group of the grayscale clock signals is composed of a plurality of continuous grayscale clocks and a plurality of continuous data reading clocks, and the grayscale clocks in a group of the grayscale clock signals are sent before the data reading clocks, and is also used to send a switching clock signal to the row driving chip, and the grayscale clock signal sent by the logic chip at the sending time corresponding to the switching clock signal is a data reading clock;

[0014] The row driver chip is used to send a row switching signal to the constant current driver chip according to the switching clock signal, and each switching clock signal corresponds to one row switching signal;

[0015] The constant current driving chip is used to sequentially receive multiple groups of grayscale clock signals input from the outside. When the grayscale clock signal currently received is a grayscale clock, the constant current driving signal is output to the LED lamp beads of the current target row based on the first display data corresponding to the read data clock in the previous group of grayscale clock signals, so as to drive the LED lamp beads of the current target row to display. When the grayscale clock signal currently received is a read data clock, the constant current driving signal is stopped from being output, and the second display data is read. The constant current driving signal corresponding to the second display data is used to be output under the grayscale clock in the next group of grayscale clock signals. In the process of receiving multiple consecutive read data clocks, the row switching signal is received, and the target row driven by the constant current driving signal corresponding to the grayscale clock in the next group of grayscale clock signals is determined according to the row switching signal.

[0016] In one embodiment of the present application, by sequentially receiving multiple groups of grayscale clock signals input from the outside, and when the grayscale clock signal currently received is a grayscale clock, a constant current drive signal is output to the LED lamp beads of the target row based on the first display data corresponding to the read data clock in the previous group of grayscale clock signals to drive the LED lamp beads to emit light. When the grayscale clock signal currently received is a read data clock, the constant current drive signal is stopped from being output, and the second display data is read. The second display data is used for the scanning process corresponding to the next group of grayscale clock signals. In addition, when receiving the read data clock, a row switching signal is also received, and the target row driven by the constant current drive signal corresponding to the grayscale clock in the next group of grayscale clock signals is determined according to the row switching signal, so as to output the corresponding constant current drive signal to the LED lamp beads of the target row when scanning based on the next group of grayscale clock signals. The technical means solves the technical problem of limited brightness efficiency when driving LED display in the related art. By receiving the row switching signal in the process of receiving the read data clock, the reading of display data can be processed in parallel with line feed and blanking to shorten the idle time period in one scan, thereby shortening the total time required for one scan. When the total time required for a scan is shortened, the duration corresponding to the grayscale clock will account for a higher proportion of the total time. Correspondingly, when the LED is driven to emit light by a constant current drive signal under the grayscale clock, the proportion of the LED on-time in the total time will also increase. At this time, when the on-time takes the maximum value, the proportion of the maximum value in the total time will also increase, that is, the brightness efficiency of the LED display is improved. In the process of receiving the read data clock, the row switching signal is received at the same time, and the integrity of the LED lamp bead display during this scan can be guaranteed as much as possible. In addition, dividing the grayscale clock signal into a grayscale clock and a read data clock can ensure that the constant current drive chip can more accurately execute the output of the constant current drive signal and read the display data. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1It is a connection diagram of an LED in the related art;

[0018] Figure 2 A schematic diagram of a row scanning time composition provided in the related art;

[0019] Figure 3 A schematic diagram of a signal transmission path when displaying on a small-pitch LED display screen provided by an embodiment of the present application;

[0020] Figure 4 A schematic diagram of the structure of a constant current driver chip provided by one embodiment of the present application;

[0021] Figure 5 A flowchart of a constant current driving method for an LED display screen provided by one embodiment of the present application;

[0022] Figure 6 A first schematic diagram of a grayscale clock signal provided by an embodiment of the present application;

[0023] Figure 7 A second schematic diagram of a grayscale clock signal provided by an embodiment of the present application;

[0024] Figure 8 A flowchart of another constant current driving method for an LED display screen provided by an embodiment of the present application;

[0025] Fig. 9 A third schematic diagram of a grayscale clock signal provided by an embodiment of the present application;

[0026] Fig.10 A schematic diagram of a first signal group provided for an embodiment of the present application;

[0027] Fig.11 A fourth schematic diagram of a grayscale clock signal provided by an embodiment of the present application;

[0028] Fig.12 A first schematic diagram of a clock driven count of a row switching signal provided by an embodiment of the present application;

[0029] Fig.13 A second schematic diagram of a clock driven count of a row switching signal provided by an embodiment of the present application;

[0030] Fig.14 A schematic diagram of the structure of an LED display screen provided in one embodiment of the present application. DETAILED DESCRIPTION

[0031] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only the parts related to the present application, rather than all structures, are shown in the accompanying drawings.

[0032] A fine pitch LED display can be understood as an LED display with a small LED pitch (e.g. less than 2.5mm). Currently, the LEDs in a fine pitch LED display are referred to as LED lamp beads. The red, green, and blue (optical primary colors) light-emitting diodes of each LED lamp bead are encapsulated in a lamp holder. The optical primary colors of the three types of light-emitting diodes are mixed to form the colors that the LED lamp bead can display. At this time, an LED lamp bead can be considered as a pixel of a fine pitch LED display.

[0033] LED lamp beads are driven by driver chips. Generally speaking, the driver chip includes at least a row driver chip and a constant current driver chip. For example, Figure 1 The figure is a connection diagram of an LED in the related art. Figure 1 Take an LED lamp bead as an example, and use the light-emitting diode VD1 to represent the LED lamp bead. Figure 1 It can be known that the LED lamp beads are controlled by the row driver chip 10 and the constant current driver chip 11 respectively. Among them, the row driver chip is used to realize row gating, and row gating can be understood as controlling the row channel where the LED lamp beads are located to be turned on (that is, controlling the row channel of a row of LED lamp beads to be turned on), so as to achieve the effect of selecting the row to be displayed in each row of LED lamp beads. The constant current driver chip is used to realize column gating, and column gating can be understood as generating a constant current drive signal according to the corresponding display data, and outputting the constant current drive signal to the LED lamp beads of the corresponding column. Among the LED lamp beads of the corresponding column, the LED lamp beads whose row channels are turned on can emit light based on the constant current drive signal. Therefore, the LED lamp beads can be turned on (i.e., emitting light) and turned off based on the constant current drive signal, and the corresponding display data can be displayed when the LED emits light. At this time, the LED lamp beads can be turned on row by row based on the row driver chip, and the LED lamp beads of the corresponding column in the conduction row can be lit based on the constant current driver chip, so as to realize the row-by-row light emission of the LED lamp beads, that is, point-to-point precise control of the LED lamp beads. The process of the constant current driver chip lighting up one or more rows of LED lamp beads based on the instruction of the row driver chip can also be considered as a row scan. Usually, a row scan can be a 1 / 2 scan, 1 / 4 scan, 1 / 8 scan or 1 / 16 scan (can also be recorded as 2 scans, 4 scans, 8 scans and 16 scans) and other scanning methods. Each scanning method is a technical means that has been realized and is not explained separately at present.

[0034] By quickly switching the rows of glowing LED beads (the human eye cannot distinguish the scanning process), the viewing effect of all LED beads of the small-pitch LED display screen glowing can be achieved, thereby realizing the display of the small-pitch LED display screen.

[0035] It is understandable that, due to the large number of LED lamp beads in the small-pitch LED display screen, multiple constant current driver chips can be set, and each constant current driver chip controls different parts of the LED lamp beads. Similarly, multiple row driver chips can also be set. With the cooperation of multiple row driver chips and multiple constant current driver chips, point-to-point precise control of each LED lamp bead can be achieved.

[0036] The constant current drive signal output by the constant current drive chip is usually a pulse width modulation (PWM) signal, which can also be recorded as a PWM wave. The PWM signal can control the on / off time of the LED lamp bead. Specifically, when the PWM signal is at a high level, the LED lamp bead is turned on, and at this time, the LED lamp bead is turned on (i.e., it emits light); when the PWM wave is at a low level, the LED lamp bead is turned off (i.e., it does not emit light). By using the short-term visual persistence effect, the duration of the high level can be adjusted to adjust the on-time of the LED lamp bead, thereby adjusting the brightness of the LED lamp bead. Generally speaking, the longer the duration of the high level, the brighter the actual brightness displayed by the LED lamp bead. It can be understood that the ratio of the high level time in the PWM signal to the PWM signal period is called the duty cycle. Based on the above description, it can be seen that the duty cycle determines the brightness of the LED lamp bead.

[0037] Generally speaking, the brightness of LED lamp beads can be expressed by grayscale, that is, the degree of precision when adjusting the brightness of LED lamp beads is the grayscale of LED display. At this time, when the constant current driver chip realizes column gating, it can be considered as controlling the conduction duty cycle of all channels when row gating (that is, the duty cycle of PWM signal), which determines the grayscale of LED lamp beads.

[0038] The constant current driver chip used in the small-pitch LED display screen not only has the function of outputting constant current drive signals, but also has self-decoding and data caching functions. When the data processing volume of the constant current driver chip is large, the display data can still be transmitted in advance in a serial manner and time-division control of the display process can be achieved.

[0039] Among them, the self-decoding function can be understood as decoding the received display data to determine the conduction duty cycle in the constant current drive signal when driving the LED lamp beads to display the display data. The data caching function refers to caching the data in the constant current drive chip, such as caching the display data that needs to be displayed by the LED lamp beads, so that the constant current drive chip can output the corresponding constant current drive signal.

[0040] Generally speaking, the constant current driver chip is driven by the grayscale clock (GCLK) signal to realize the control of the display of the LED lamp beads. One achievable method is that during the operation of the constant current driver chip, multiple groups of grayscale clock signals are continuously received, and each group of grayscale clock signals contains multiple grayscale clock signals. One group of grayscale clock signals corresponds to one line during scanning. The constant current driver chip obtains display data and outputs a constant current drive signal corresponding to the display data based on the control of the received grayscale clock signal. In addition, at the end of a line scan, line break and blanking are required. Among them, line break refers to determining the number of rows where the LED lamp beads are located when the next line scan is performed, which can generally be notified by the line driver chip to the constant current driver chip. Blanking can be simply understood as moving from the scan end point when scanning a line to the scan start point when scanning the next line. The scan end point and the scan start point both refer to the LED lamp beads at the corresponding position. Line break and blanking also take time. At this time, there is a spare time period after each group of grayscale clock signals, which is used to realize line feed and blanking. By setting the spare time period, the time required for line switching can be hidden, thereby avoiding the situation of wrong line display during scanning. At the same time, the spare time period can also provide waiting time for the constant current driver chip to read and decode the display data of the next scan (i.e., the next row scan), so that in the next scan, the corresponding constant current drive signal can be decoded based on the read display data and output. At this time, the time required to scan a line includes the duration of a group of grayscale clock signals and the spare time period.

[0041] For example, Figure 2 Schematic diagram of a row scanning time composition provided in the related art, wherein the first row of data is the waveform of the grayscale clock signal, Figure 2 exemplarily shows three groups of grayscale clock signals, where the number above each grayscale clock signal indicates the grayscale clock signal's number in the group. The second line of data indicates the number of scanned rows corresponding to each group of grayscale clock signals, and its duration can be understood as the duration required to scan a row. The third line of data indicates the time interval corresponding to the idle time period for line feed and blanking. Figure 2 In is recorded as the line blanking interval. Figure 2 It can be seen that there is a spare time period between adjacent groups of grayscale clock signals, and the spare time period is the line blanking interval. That is, the time length required to scan a line is composed of the duration of a group of grayscale clock signals and the spare time period, and there are spare time periods before and after a group of grayscale clock signals.

[0042] It can be understood that the LED lamp bead emits light based on the constant current driving signal. Figure 2In the time required to scan a line, the LED lamp beads will only emit light when the constant current drive signal is at a high level, and the LED lamp beads will not emit light during the rest of the time. However, the high level duration of the constant current drive signal (which can also be understood as the LED lamp bead conduction time) is limited and the time required to scan a line is also limited (the display line needs to be switched quickly). Therefore, when scanning a line, the proportion of the LED lamp bead conduction time in the time required to scan a line is also limited. Ideally (i.e., without considering the idle time period of line break and blanking), the duty cycle of the constant current drive signal that drives the LED lamp bead to display the maximum grayscale level (i.e., the highest brightness) that can be achieved at present is the largest, and the LED lamp bead conduction time is the longest. At this time, the proportion of the LED lamp bead conduction time in the duration of a set of grayscale clock signals can be understood as the brightness efficiency, which is generally between 50% and 70%, that is, the brightness efficiency is limited.

[0043] At this time, based on the limitation of brightness efficiency, when driving the LED lamp beads to emit light, the maximum brightness that the LED lamp beads can achieve is limited. In the related art, if you want higher brightness, you need to increase the current of the constant current drive signal. However, when the current of the constant current drive signal is increased, the power supply of the LED display needs to output a higher instantaneous output power, thereby increasing the heat generation and power consumption of the LED display, and the ripple fluctuation of the power supply becomes larger, making the stability of the LED display lower during display. When the display device (i.e., LED lamp bead) passes through a large current constant current drive signal, it will cause wear and tear. If it is subjected to a large current for a long time, the LED lamp bead will be seriously worn and aged, reducing the service life of the LED lamp bead. In addition, when the constant current drive chip outputs a constant current drive signal, there is also a maximum current limitation, which cannot meet all high-brightness display requirements.

[0044] Based on this, the embodiments of the present application provide a constant current driving method, a constant current driving chip and an LED display screen for solving the technical problem of limited display brightness of the LED when driving the LED display in the related technology. The brightness is improved by effectively improving the brightness, and the brightness of the LED lamp beads driven by the constant current driving signal is improved. In addition, the disadvantages of increasing the brightness of the LED lamp beads by increasing the current of the constant current driving signal in the related technology are avoided.

[0045] An embodiment of the present application provides a constant current driving method for an LED display screen, and the constant current driving method can be performed by a constant current driving device of the LED display screen. The constant current driving device can be implemented by software and / or hardware. The constant current driving device can be composed of two or more physical entities, or it can be composed of one physical entity. The constant current driving device has a data processing function. In one embodiment, the constant current driving device is described as a constant current driving chip in an LED display screen, wherein the LED display screen is a small-pitch LED display screen.

[0046] One or more constant current driving chips can be set for a small-pitch LED display screen. When multiple constant current driving chips are set, all of the multiple constant current driving chips execute the constant current driving method. Therefore, in the embodiment, one constant current driving chip is used as an example for description.

[0047] In order to facilitate understanding of the constant current driving method, the working process of the constant current driving chip is first exemplarily described in the embodiment. Figure 3 A schematic diagram of the signal transmission path when displaying on a small-pitch LED display screen provided by an embodiment of the present application. Figure 3 The small-pitch LED display screen includes a plurality of constant-current driving chips 20, each of which can drive a portion of LED lamp beads to emit light, and each portion of LED lamp beads constitutes all LED lamp beads of the small-pitch LED display screen.

[0048] It can be understood that the small pitch LED display screen can be composed of a receiving part and a display part. The display part can also be recorded as an LED light board. The LED light board is equipped with LED lamp beads, a row driver chip that drives the LED lamp beads to conduct, and a constant current driver chip that drives the LED lamp beads to emit light.

[0049] The small pitch LED display screen also includes FPGA30. FPGA is installed in the receiving part. The receiving part refers to the receiving card, which can also be recorded as a receiving card, a board or a control board. The receiving card is installed with multiple chips, and after the chips are matched, the functions of the small pitch LED display screen can be realized. At present, the receiving card is installed with at least a logic chip, and the logic chip is a field programmable gate array (Field Programmable Gate Array) as an example (i.e. Figure 3 The FPGA 30 shown is only an exemplary description). In actual applications, the logic chip can also use other chips with data processing functions. The FPGA can receive display data sent from the outside, and determine the RGB value and other parameters displayed by each LED lamp bead according to the display data, and control the LED lamp bead to display based on the RGB value and other parameters.

[0050] The small pitch LED display screen also includes a buffer driver 40, which can also be understood as a data transceiver memory, which can be installed in the receiving part to enhance (such as shaping the signal) and distribute (ie, multi-channel output) the output signal.

[0051] In one embodiment, when the FPGA controls the LED lamp bead to display, it sends at least display data, data clock signal, grayscale clock signal and latch signal to the constant current driver chip 20. Among them, the display data ( Figure 3 The data clock signal (DATA) refers to the RGB value and other parameters obtained after FPGA processing. Figure 3 DCLK) is the clock used to enable the constant current driver chip to receive display data. The latch signal ( Figure 3 The gray clock signal (referred to as LAT in FIG. 1 ) is an enable signal for latching the display data received by the constant current driver chip. The function of the gray clock signal (ie, GCLK) can refer to the related description of the above content.

[0052] based on Figure 3 It can be seen that the DATA, DCLK, LAT, and GCLK output by the FPGA 30 are first input to the buffer driver 40. Afterwards, the buffer driver 40 shapes the DATA, DCLK, LAT, and GCLK and sends the DATA, DCLK, LAT, and GCLK to each constant current driver chip 20 in a multi-group parallel manner. Figure 3 In the embodiment, the constant current driving chips in the same row can receive the same DCLK, LAT, and GCLK at the same time. Furthermore, the constant current driving chips 20 in the same row transmit the corresponding DATA in series. At this time, the buffer driver 40 only sends DATA to one constant current driving chip 20 in each row.

[0053] Need to explain, Figure 3 The relative position relationship between the constant current driver chips in the figure is not the relative position relationship when the constant current driver chips are actually installed. Figure 3 The relative positional relationship in the figure is only an exemplary expression for facilitating understanding of the signal transmission path.

[0054] The constant current driver chip works based on the received DATA, DCLK, LAT, and GCLK. Figure 4 A schematic diagram of the structure of a constant current driver chip provided by an embodiment of the present application. Figure 4 The constant current driving chip 20 includes a FIFO 21 , a control logic unit 22 , a static random access memory (SRAM) 23 , a configurable register 24 , a constant current source algorithm circuit 25 , a current generator 26 and a constant current source channel 27 .

[0055] Among them, FIFO (First Input First Output) 21 can also be recorded as FIFO memory, which adopts a first-in first-out method. FIFO21 has a serial data input terminal (i.e., SDI terminal) and a serial data output terminal (i.e., SDO terminal). At this time, the serially transmitted DATA is stored in FIFO through the serial data input terminal for use by the constant current driver chip, and the DATA in FIFO is also transmitted to the next constant current driver chip connected in the same row through the serial data output terminal.

[0056] The control logic unit 22 can control the constant current driver chip. The control logic unit has a data clock signal (i.e., DCLK) input terminal, through which DCLK is received, and then the control logic unit drives based on DCLK to store the display data in the FIFO. The control logic unit also has a latch signal input terminal (i.e., LE terminal), through which LAT is received, and then the control logic unit determines the DATA stored in the latch FIFO based on LAT.

[0057] The SRAM 23 is used to latch DATA. When the control logic unit determines to latch DATA based on LAT, it controls the SRAM to obtain DATA from the FIFO and latch DATA.

[0058] The configurable register 24 is used to temporarily store the instructions generated by the control logic unit 22. For example, the configurable register 24 stores the instructions generated by the control logic unit 22 for indicating the implementation of a certain function during the operation of the constant current source algorithm circuit 25, and then sends the instructions to the constant current source algorithm circuit 25. For another example, the configurable register 24 stores the instructions generated by the control logic unit 22 for indicating the implementation of a certain function during the operation of the current generator 26, and then sends the instructions to the current generator 26.

[0059] The constant current source algorithm circuit 25 can read and decode the display data, and generate a corresponding constant current drive signal. The constant current source algorithm circuit 25 has a grayscale clock signal (i.e., GCLK) input terminal. GCLK is received through the grayscale clock signal input terminal. After the constant current driver chip data is updated (such as receiving a new row of display data, etc.), the constant current algorithm circuit can read the latched DATA from the SRAM based on the drive of GCLK, and then, based on the latched DATA decoding, the conduction time ratio of the LED lamp bead is obtained and the corresponding constant current drive signal is output. In the embodiment, when the constant current driving method of the LED display is executed by the constant current driver chip, it can be mainly understood as being executed by the constant current source algorithm circuit 25.

[0060] The current generator 26 is used to generate a current signal, which is modulated based on the constant current drive signal output by the constant current source algorithm circuit 25 to output an electrical signal corresponding to the constant current drive signal. The circuit generator 26 has an external resistor input terminal (REXT), and the resistor connected to the external resistor input terminal (located outside the circuit generator 26) can set the magnitude of the current generated by the circuit generator 26.

[0061] The constant current source channel 27 refers to a channel for outputting a constant current drive signal. The constant current source channel 27 receives the constant current drive signal output by the constant current source algorithm circuit 25 and the current signal generated by the current generator 26, and then modulates the current signal based on the constant current drive signal to output an electrical signal corresponding to the constant current drive signal. It can be understood that Figure 4 In the example, the constant current source channel 27 has 16 channels, and the 16 channels correspond to the output terminals 0-15 (ie, OUT0-15). The 16 channels can light up 16 LED lamp beads at the same time.

[0062] Need to explain, Figure 4 The hardware structure of each circuit, component and unit inside the constant current driver chip is not limited at present. Figure 4 In addition to the structure shown, other circuits, elements and units may also be included, which are not currently limited.

[0063] It can be understood that the FPGA can also control the row driver chip to control the row driver chip to determine the number of rows of LED lamp beads that need to be turned on, and generate a row switching signal based on the number of rows and send it to the constant current driver chip, so that the constant current driver chip determines the number of rows of LED lamp beads that are turned on.

[0064] When the constant current driving chip is working, the constant current driving method of the LED display screen can be executed. Figure 5 A flowchart of a constant current driving method for an LED display screen provided by an embodiment of the present application. Figure 5 , the constant current driving method includes steps 110 to 140:

[0065] Step 110: sequentially receive multiple groups of grayscale clock signals input from the outside, each group of grayscale clock signals consists of multiple continuous grayscale clocks and multiple continuous read data clocks, and the grayscale clocks in a group of grayscale clock signals are received before the read data clocks.

[0066] For example, the constant current driver chip needs to receive a set of grayscale clock signals each time it performs a line scan, that is, a set of grayscale clock signals is used to drive the constant current display chip to perform a line scan. Multiple line scans are achieved by sequentially receiving multiple sets of grayscale clock signals.

[0067] In one embodiment, the grayscale clock signal includes two types: grayscale clock (which can be recorded as gray_clk) and read data clock (which can be recorded as data_clk), wherein the grayscale clock corresponds to the actual working time of the constant current source algorithm circuit, that is, the working time of decoding and outputting the constant current drive signal (i.e., PWM signal), and the read data clock corresponds to the working time of reading the latched display data (DATA) from the SRAM. Among them, decoding can be understood as the process of determining the proportion of LED lamp beads that need to be turned on when the LED lamp beads display the display data. Based on the proportion of conduction, the corresponding constant current drive signal can be obtained, and decoding and output can be performed synchronously.

[0068] A set of grayscale clock signals can be composed of a plurality of continuous grayscale clocks and a plurality of continuous read data clocks, and the number of grayscale clocks and the number of read data clocks can be set according to actual needs. For a set of grayscale clocks, the grayscale clocks are received before the read data clocks.

[0069] In one embodiment, a plurality of continuous read data clocks are composed of an even number of read clocks and an operating clock. That is, the read data clock includes two types: a read clock and an operating clock, wherein the read clock corresponds to the working time of reading latched display data from the SRAM, and the operating clock corresponds to the working time of transmitting the display data. Generally speaking, the number of read clocks is an even number, and the number of operating clocks is one. That is, when receiving a plurality of continuous read data clocks, an even number of read clocks are received first, and then an operating clock is received. Optionally, the number of read clocks is related to the number of constant current drive signals output by the constant current drive chip during one scan, and can reflect the depth of the internal cache of the constant current drive chip each time it is read, for example, with Figure 4 Taking the constant current driving chip shown as an example, the constant current driving chip outputs 16 constant current driving signals, and the 16 constant current driving signals correspond to 16 reading clocks, so that the display data corresponding to the corresponding constant current driving signal is read at each reading clock.

[0070] It can be understood that the grayscale clock signal is generated by the FPGA and sent to the constant current drive chip. At this time, the number of clocks contained in each group of grayscale clock signals is pre-set in the FPGA, and when a group of grayscale clock signals is sent at a pre-set frequency, the grayscale clock signals are counted synchronously. When the pre-set number of clocks is reached, it is determined that a group of grayscale clock signals has been sent, and the counting starts again. It can also be that the number of grayscale clocks and the number of read data clocks contained in a group of grayscale clock signals are pre-set in the FPGA, and when a group of grayscale clock signals is sent at a pre-set frequency, the counting starts synchronously.

[0071] For the constant current driver chip, when receiving a set of grayscale clock signals, the grayscale clock is first received, and after receiving multiple grayscale clocks continuously, the grayscale clock is no longer received and the read data clock is started to be received. After receiving multiple read data clocks continuously, when the read data clock is no longer received, it is determined that a set of grayscale clock signal reception ends. Optionally, the constant current driver chip pre-stores the number of grayscale clocks and the number of read data clocks in a set of grayscale clock signals, and then determines whether the grayscale clock or the read data clock is received based on the number of grayscale clock signals currently received. Alternatively, the FPGA notifies the constant current driver chip whether the grayscale clock or the read data clock is currently sent. It is understandable that the constant current driver chip can also determine whether the grayscale clock or the read data clock is currently received in other ways, and the embodiment does not limit this.

[0072] Step 120, when the currently received grayscale clock signal is a grayscale clock, a corresponding constant current drive signal is output to the LED lamp beads of the current target row based on the first display data correspondingly read under the read data clock in the previous group of grayscale clock signals to drive the LED lamp beads of the current target row to display.

[0073] When receiving a grayscale clock signal, if it is determined that the grayscale clock signal currently received is a grayscale clock, the constant current driver chip outputs a constant current drive signal. The constant current drive signal can control the LED lamp beads of the corresponding row to emit light, thereby realizing the display of the LED lamp beads. In one embodiment, the row where the LED lamp beads driven to emit light during a scan is recorded as the target row, and the LED lamp beads lit in the target row can be one or more, which is related to the number of constant current drive signals output by the constant current driver chip, and is not currently limited.

[0074] Exemplarily, the LED lamp bead conduction time ratio in the constant current drive signal output by the constant current drive chip during this scan is obtained based on the display data read during the previous scan, that is, the LED lamp bead conduction time ratio in the constant current drive signal output under the grayscale clock drive of the current group of grayscale clock signals is determined based on the display data read under the drive of the read data clock in the previous group of grayscale clock signals. Among them, the LED lamp bead conduction time ratio can also be understood as the duty cycle of the PWM signal. For the sake of distinction, the display data read under the drive of the read data clock in the previous group of grayscale clock signals is recorded as the first display data. That is, the constant current drive chip drives the LED lamp bead to display the display data read during the previous scan each time it scans. Specifically, when the constant current drive chip receives the grayscale clock, it obtains the first display data read during the previous scan, and obtains the LED lamp bead conduction time ratio required for this scan based on the first display data, and then outputs the corresponding constant current drive signal to drive the LED lamp bead in the target row opened by the current channel to emit light. Among them, the decoding process is not currently limited. Generally speaking, when decoding, the brightness of the LED lamp beads when driving the display can be determined based on parameters such as RGB values, and then the proportion of the LED lamp bead conduction time of the constant current drive signal can be determined based on the required brightness level and other contents.

[0075] It can be understood that the target row for the current channel opening can be determined based on the row driver chip.

[0076] It should be noted that the number of target rows that can be driven to emit light in each scan of the constant current driving signal is currently not limited, and the technical means for driving each row of LED lamp beads to emit light are the same. Therefore, the embodiment only describes the driving of one row of LED lamp beads to emit light as an example.

[0077] Step 130: When the currently received grayscale clock signal is a data reading clock, stop outputting the constant current drive signal and read the second display data. The constant current drive signal corresponding to the second display data is used to be output under the grayscale clock in the next set of grayscale clock signals.

[0078] When receiving a grayscale clock signal, if the grayscale clock signal currently received is a read data clock, the constant current driver chip no longer outputs a constant current drive signal, and reads display data based on multiple read data clocks received continuously. Optionally, when the grayscale clock signal currently received changes from a grayscale clock to a read data clock, the constant current driver chip can stop outputting the constant current drive signal, and when the read data clock continues to be received, the constant current driver chip will no longer output the constant current drive signal.

[0079] Specifically, when the constant current driver chip starts to receive the data reading clock, it reads the currently latched display data, which is a line of display data to be displayed in the next scan (when scanning multiple lines at a time, multiple lines of display data are read). The display data includes parameters such as the RGB value of each pixel during display. Among them, overall, the display data of the LED display screen is in frames, and one frame of display data can generate an image for the LED display screen to display. When the constant current driver chip scans a frame of display data line by line (generally from top to bottom), each scan reads a line of display data in a frame of display data.

[0080] It is understandable that latching display data and reading latched display data are both already implemented technical means and are not currently limited.

[0081] At present, for the convenience of distinction, the display data read under the driving of the data reading clock in the currently received set of grayscale clock signals is recorded as the second display data. It can be understood that the second display data and the first display data correspond to different rows of LED lamp beads.

[0082] Optionally, when the received read data clock is a read clock, the latched second display data is read, and when the received read data clock is an operation clock, the display data is transferred for subsequent use.

[0083] Optionally, after reading the second display data, the second display data is cached. Afterwards, when the next scan starts, that is, when a new set of grayscale clock signals is received, if the grayscale clock is received (that is, the grayscale clock is received again), the cached display data is decoded and the corresponding constant current drive signal is output, and the constant current drive signal can drive the LED lamp beads in the corresponding target row to emit light during the next scan. It can be understood that during the next scan, the latched display data will also be read according to the read data clock, and this process will be repeated to realize the display of the LED lamp beads.

[0084] Step 140 : receiving a row switching signal during the process of receiving a plurality of consecutive data reading clocks, and determining a target row driven by a constant current driving signal corresponding to a gray clock in a next set of gray clock signals according to the row switching signal.

[0085] Generally speaking, there is a spare time period between two adjacent groups of grayscale clock signals, which is used for line breaking and blanking. During line breaking and blanking, the constant current driver chip receives the line switching signal (i.e., row_cut) sent by the line driver chip. The line switching signal is used to enable the constant current driver chip to determine which line the constant current drive signal is output to during scanning, that is, to determine the target line for the next scan. The constant current drive signal is line-swapped according to the line switching signal, so as to output the constant current drive signal to the corresponding target line during the next scan.

[0086] For example, Figure 6 A first schematic diagram of a grayscale clock signal provided by an embodiment of the present application, Figure 6 In the figure, the first line is used to indicate the type of grayscale clock signal corresponding to the position of the second line, the second line is the specific waveform of the grayscale clock signal, and the third line indicates the row switching signal, wherein the row switching signal is high and effective, that is, when it is at a high level, the constant current driver chip determines that it has received the row switching signal. Figure 6 , a set of grayscale clock signals is composed of grayscale clock 51 ( Figure 6 The grayscale clock signal is composed of a grayscale clock 51 and a read data clock 52, wherein there are 17 read data clocks, the first 16 read data clocks can be considered as reading clocks, and the last read data clock can be considered as an operation clock. There are idle time periods in front and behind a set of grayscale clock signals, and the line feed signal is generally generated in the idle time period. Figure 6 In the embodiment, the constant current driving chip receives the row switching signal 54 during the idle time period 53. The row switching signal received during the idle time period after a group of grayscale clock signals is used for the next scan (ie, the next group of grayscale clock signals).

[0087] It can be understood that in a set of grayscale clock signals, the constant current driver chip can drive the LED lamp beads to light up only during the time corresponding to the grayscale clock, and the LED lamp beads can only light up when the constant current drive signal is at a high level. The LED lamp beads do not light up at other times (at least including the idle time period and the working time corresponding to the data reading clock). At this time, in the total time required for each scan, the effective time for controlling the LED lamp beads to light up is only related to the working time corresponding to the grayscale clock, and the degree of lightness is related to the proportion of the grayscale clock in the total time required for each scan. Therefore, in the embodiment, by increasing the proportion of the working time corresponding to the grayscale clock in the total time required for each scan, that is, increasing the proportion of the effective time of the LED lamp beads to light up, the brightness efficiency of the LED lamp beads is increased.

[0088] In one embodiment, during the process of receiving the grayscale clock signal, a row switching signal is received, that is, the row switching signal is received in advance, so as to hide the time of receiving the row switching signal and responding to the row switching signal (that is, line break and blanking) in the idle time period, thereby shortening the length of the idle time period, that is, realizing blanking indentation.

[0089] The row driver chip sends a row switching signal according to the instruction of the FPGA. Therefore, the row switching signal can be sent in advance by modifying the time when the row driver chip is instructed to send the row switching signal in the FPGA, so that the constant current driver chip receives the row switching signal in advance. In one embodiment, the row switching signal is received during the process of receiving multiple read data clocks. That is, the row switching signal generation time is located in the working time corresponding to the multiple read data clocks. Specifically, the FPGA sends a clock signal to the row driver chip, and the clock signal is used to drive the row driver chip to send the row switching signal outward. At present, the clock signal is recorded as a switching clock signal. That is, the FPGA sends a grayscale clock signal to the constant current driver chip and sends a row switching signal to the row driver chip in parallel. In one embodiment, the FPGA presets the frequency of the switching clock signal. The frequency of the switching clock signal can be determined according to the frequency of the grayscale clock signal to ensure that the constant current driver chip receives the row switching signal during the process of receiving the read data clock every time it scans. Among them, the FPGA starts to send the switching clock signal when sending the Nth grayscale clock signal in the first group of grayscale clock signals. The Nth grayscale clock signal is the read data clock, and the specific value of N can be set according to actual needs. At this time, at the time of sending the switching clock signal, the grayscale clock signal sent by the FPGA is the data reading clock, so as to ensure that the constant current driving chip receives the row switching signal when receiving the data reading clock.

[0090] After receiving the row switching signal, the constant current driver chip performs row switching and blanking based on the row switching signal, that is, determines the target row for the next scan and prepares to scan the LED lamp beads in the target row. At the same time, since the data reading clock is also received, the constant current driver chip also reads the display data for the next scan. That is, row switching and blanking are performed simultaneously with reading the display data, thereby shortening the length of the idle time period.

[0091] It should be noted that within the time range corresponding to the grayscale clock, the LED lamp beads of the target row may emit light due to the drive of the constant current drive signal. Within this time range, if a row switching signal is received, then after the constant current drive chip responds to the row switching signal to change lines and blank, the LED lamp beads that are emitting light will no longer emit light, that is, the row drive chip has closed the row channel of the LED lamp beads that are emitting light, and opened the row channel of the LED lamp beads of another target row. At this time, even if there is still display data that has not been displayed (for example, the constant current drive chip still outputs a constant current drive signal), the LED lamp beads that have closed the row channel will no longer emit light, that is, display data loss occurs. Therefore, setting the row switching signal to be received when receiving the read data clock can reduce the loss of display data.

[0092] In an optional manner, the receiving time of the row switching signal corresponding to a group of grayscale clock signals is later than the receiving time of the third read data clock. It can be understood that when the constant current driver chip drives the LED lamp bead to emit light, before receiving the third read data clock in a group of grayscale clock signals, the LED lamp bead may still emit light, that is, it is still displaying based on the received constant current drive signal, and after receiving the third read data clock, the LED lamp bead can display the display data corresponding to this scan. Therefore, the sending time of the switching clock signal sent by the FPGA to the row driver chip, the corresponding Nth grayscale clock signal can be the third read data clock, or, other read data clocks after the third read data clock (generally not the last few read data clocks). At this time, the receiving time of the row switching signal received by the constant current driver chip should be later than the receiving time of the third read data clock to ensure the display integrity of the display data during this scan. Optionally, the receiving time of the row switching signal is within the receiving time of the first half of the read data clock (such as when there are 17 read data clocks, the first half of the read data clock is the first 9 read data clocks), and is generally located after the receiving time of the third read data clock. It should be noted that, generally speaking, when the third data read clock is received, the LED lamp beads of the target row of this scan have already displayed the display data that needs to be displayed currently, and even if the row channel of the LED lamp beads is turned off, the display data will not be lost. Therefore, setting the row switching signal after receiving the third data read clock can ensure the display integrity of the LED lamp beads.

[0093] When receiving the read data clock, receiving the row switching signal can reduce the idle time period in a scanning process, thereby increasing the proportion of the grayscale clock. It can be understood that if the idle time period is reduced, then the total time required to scan a row will be reduced, while the working time of the grayscale clock remains unchanged. Therefore, the proportion of the grayscale clock working time in the total time will increase, and the constant current drive signal generated under the grayscale clock can have a higher proportion of the LED lamp bead conduction time, thereby increasing the grayscale level that can be achieved when the constant current drive signal drives the LED lamp bead to emit light. At this time, the frequency of the grayscale clock and the read data clock can also be appropriately reduced, and the proportion of the grayscale clock working time in the total time required to scan a row can also be increased.

[0094] Based on this approach, the idle time period can be very small (ie, there is no need to wait for line breaks and blanking for a long time), so the FPGA can send almost continuous groups of grayscale clock signals.

[0095] For example, Figure 7 A second schematic diagram of a grayscale clock signal provided by an embodiment of the present application, Figure 7 In the figure, the first line is used to indicate the type of grayscale clock signal at the corresponding position of the second line, the second line is the specific waveform of the grayscale clock signal, and the third line indicates the line switching signal. Figure 7 , when receiving the fifth read data clock 52, the row switching signal 54 is received, that is, the receiving time of the row switching signal 54 is advanced from the original T1 time to T2 time, so that the reading of display data and line feed and blanking are carried out simultaneously. At this time, the idle time period 53 between the two groups of grayscale clock signals is significantly reduced.

[0096] It can be understood that for the first group of grayscale clock signals, since there are no other groups of grayscale clock signals before it, then, under the grayscale clock in the grayscale clock signal, there is no display data read under the previous group of grayscale clock signals for use. At this time, in order to ensure that the constant current drive signal is output under the first group of grayscale clock signals, multiple additional data read clocks can be set before the first group of grayscale clock signals. Under the additional multiple data read clocks, the constant current drive chip reads the display data that needs to be displayed at the beginning. After that, under the grayscale clock in the first group of grayscale clock signals, the corresponding constant current drive signal can be output to the LED lamp beads of the target row based on the display data that needs to be displayed at the beginning. It should be noted that when initializing (i.e., preparing to start controlling the LED lamp beads for display), the first row is set as the target row by default, and the row channel of the LED lamp beads of the first row is controlled to be turned on. After that, under the additional multiple data read clocks, the constant current drive chip reads the display data corresponding to the first row. Therefore, under the grayscale clock in the first group of grayscale clock signals, the constant current drive chip outputs the corresponding constant current drive signal to the LED lamp beads of the first row by default. It can be understood that the additionally set multiple read data clocks can also be considered to belong to the first group of grayscale clock signals, that is, the first group of grayscale clock signals has more additionally set multiple read data clocks than other groups of grayscale clock signals. In this case, the first group of grayscale clock signals is composed of the additionally set multiple read data clocks, multiple grayscale clocks and multiple read data clocks in the order of receiving time. Moreover, under the additionally set multiple read data clocks, there is no need to receive the row switching signal.

[0097] In the above, by sequentially receiving multiple groups of grayscale clock signals input from the outside, and when the grayscale clock signal currently received is a grayscale clock, a constant current drive signal is output to the LED lamp beads of the target row based on the first display data corresponding to the read data clock in the previous group of grayscale clock signals to drive the LED lamp beads to emit light. When the grayscale clock signal currently received is a read data clock, the constant current drive signal is stopped from being output, and the second display data is read. The second display data is used for the scanning process corresponding to the next group of grayscale clock signals. In addition, when receiving the read data clock, a row switching signal is also received, and the target row driven by the constant current drive signal corresponding to the grayscale clock in the next group of grayscale clock signals is determined according to the row switching signal, so as to output the corresponding constant current drive signal to the LED lamp beads of the target row when scanning based on the next group of grayscale clock signals. The technical means solves the technical problem of limited brightness efficiency when driving LED display in the related art. By receiving the row switching signal in the process of receiving the read data clock, the read display data can be processed in parallel with the line feed and blanking to shorten the idle time period in one scan, thereby shortening the total time required for one scan. When the total time required for a scan is shortened, the duration corresponding to the grayscale clock will account for a higher proportion of the total time. Correspondingly, the proportion of the LED on-time in the total time when the LED is driven to emit light by the constant current drive signal under the grayscale clock will also increase. At this time, when the on-time takes the maximum value, the proportion of the maximum value in the total time will also increase, that is, the brightness efficiency of the LED display is improved. Dividing the grayscale clock signal into a grayscale clock and a read data clock can ensure that the constant current drive chip can more accurately execute the output of the constant current drive signal and read the display data. In addition, in the process of receiving the read data clock, the row switching signal is received at the same time, and the integrity of the LED lamp bead display during this scan can be guaranteed as much as possible. Setting the receiving time of the row switching signal to be after the receiving time of the third read data clock can further ensure the integrity of the display data when the LED lamp bead is driven to display.

[0098] Figure 8 A flowchart of another constant current driving method for an LED display screen provided by an embodiment of the present application. Figure 8 The constant current driving method shown is based on the above constant current driving method, by increasing the frequency of the data reading clock, shortening the working time corresponding to the data reading clock, and thus increasing the proportion of the grayscale clock.

[0099] refer to Figure 8 , the constant current driving method includes steps 210 to 240:

[0100] Step 210: sequentially receive multiple groups of grayscale clock signals input from the outside, each group of grayscale clock signals consists of multiple continuous grayscale clocks and multiple continuous read data clocks, and the grayscale clocks in a group of grayscale clock signals are received before the read data clocks.

[0101] Step 220, when the currently received grayscale clock signal is a grayscale clock, a corresponding constant current drive signal is output to the LED lamp beads of the current target row based on the first display data correspondingly read under the read data clock in the previous group of grayscale clock signals to drive the LED lamp beads of the current target row to display.

[0102] Step 230: when the currently received grayscale clock signal is a read data clock, a multiplied read data clock is obtained based on the currently received read data clock, and based on the multiplied read data clock, output of the constant current drive signal is stopped, and the second display data is read.

[0103] The multi-frequency read data clock is also a read data clock, but the frequency of the multi-frequency read data clock is higher than the frequency of the read data clock sent by the FPGA. In this way, the number of multi-frequency read data clocks is greater in the same time, and the constant current driver chip can execute more content. For example, taking the multi-frequency as double frequency, at this time, after the frequency of the 8 read data clocks sent by the FPGA is doubled, 16 read data clocks can be obtained, and the working time corresponding to the 8 read data clocks sent by the FPGA is consistent with the working time corresponding to the 16 double-frequency read data clocks under double frequency.

[0104] It can be understood that the constant current driver chip works based on the received clock. If a scanning process requires 17 data read clocks, then when using a double-frequency read data clock, only FPGA needs to send 8.5 read data clocks, so that the constant current driver chip can receive 17 double-frequency read data clocks, and then complete the work of reading display data corresponding to 17 read data clocks (i.e., required for one scan) within the working time corresponding to the original 8.5 read data clocks. This shortens the working time for reading display data and further increases the proportion of grayscale clocks in a set of grayscale clock signals, that is, improves the brightness efficiency.

[0105] Exemplarily, each grayscale clock signal generated by the FPGA has a uniform frequency, that is, the grayscale clock and the read data clock have the same frequency. In this case, the received read data clock can be processed by the constant current driver chip to obtain a multi-frequency read data clock. That is, the constant current driver chip receives the read data clock while performing multi-frequency processing.

[0106] At present, taking the double frequency read data clock as an example, how the constant current drive chip generates the double frequency read data clock is described. When generating the double frequency read data clock, the double edge trigger mode is used. That is, before step 210, it can also include: setting the double edge trigger mode.

[0107] It can be understood that a clock signal (such as a grayscale clock signal) has two edges in the waveform, which are a rising edge (i.e., an edge that becomes a high level) and a falling edge (i.e., an edge that becomes a low level). The constant current driver chip can identify each received clock signal by identifying the edges in the signal.

[0108] When the constant current driver chip receives the clock signal, the single edge trigger mode is often used. In the single edge trigger mode, the edge type at the start of the clock signal is specified. For example, when the edge type at the start of the clock signal is a rising edge, the constant current driver chip identifies that the waveform of the currently received signal is a rising edge, and determines a clock start. When the waveform of the currently received signal is identified as a falling edge, it determines a clock end. In this way, each clock signal is recognized. At this time, the clock signal is a high-level signal.

[0109] In one embodiment, the constant current driver chip is set to a dual-edge trigger mode. In the dual-edge trigger mode, the edge type of the clock start or clock end is not limited. For example, when the constant current driver chip receives a clock signal, when the first edge is identified, whether the edge is a rising edge or a falling edge, a clock start is determined. When the second edge is identified, whether the edge is a rising edge or a falling edge, a clock end is determined. When the third edge is identified, whether the edge is a rising edge or a falling edge, a clock start is determined, thereby realizing the recognition of each clock signal.

[0110] Optionally, the dual-edge trigger mode is set by the control logic unit, and then the control logic unit stores relevant data for setting the dual-edge trigger mode in a configurable register, and the constant current source algorithm circuit determines the current to be set to the dual-edge trigger mode through the configurable register.

[0111] After the dual-edge trigger mode is set, in this step, multiple consecutive data read clocks are converted into multi-frequency data read clocks, which may include steps 231 and 232:

[0112] Step 231, copy the currently received read data clock to obtain a copied read data clock, and when copying, control the edge signal of the read data clock and the edge signal of the copied read data clock to be arranged at intervals in timing, and the distance between any two adjacent edge signals is equal when arranged at intervals.

[0113] Exemplarily, the constant current driver chip divides the currently received read data clock into two paths, one of which is the originally received read data clock, and the other can be considered as the read data clock obtained by copying the received read data clock. Currently, the copied read data clock is recorded as the copied read data clock. The copied read data clock has the same waveform as the read data clock and the same number of clocks.

[0114] It can be understood that the reception and copying of the read data clock are performed simultaneously, that is, while receiving the read data clock, the currently received read data clock is copied. At this time, it can be considered that the constant current drive chip receives the read data clock and copies the read data clock at the same time.

[0115] Since the constant current driving chip can identify the grayscale clock signal by identifying the edge of the received signal, in order to obtain a double frequency read data clock, the edge signal of the read data clock and the edge signal of the copied read data clock can be arranged at intervals in timing. After the interval arrangement, when the constant current driving chip receives the read data clock and the copied read data clock at the same time, the received edge signals are: the edge signal of the read data clock (such as the upper edge signal), the edge signal of the copied read data clock (such as the upper edge signal), the edge signal of the read data clock (such as the lower edge signal), the edge signal of the copied read data clock (such as the lower edge signal), and the edge signal of the copied read data clock (such as the lower edge signal), and so on.

[0116] The technical means for achieving the staggered arrangement are not currently limited. For example, when the constant current driver chip obtains the copied read data clock, the copied read data clock is phase-shifted, and after the phase shift, the edge signals of the read data clock and the copied read data clock are staggered in timing.

[0117] In an optional manner, when the copied read data clock is phase-shifted by 90°, the position of the edge signal of the copied read data clock in the timing sequence can be located in the middle of the two positions of the two adjacent edge signals of the read data clock in the timing sequence, thereby achieving that when the edge signals of the read data clock and the copied read data clock are arranged at intervals, the distances between the adjacent edge signals are equal. After the distances are equal, a double frequency read data clock with a waveform specification can be obtained based on the edge signals arranged at intervals.

[0118] Optionally, the control logic unit in the constant current driving chip notifies the constant current source algorithm circuit through a configurable register to copy the received read data clock and arrange it at intervals.

[0119] Step 232: According to the dual-edge trigger mode, a double-frequency read data clock is obtained according to the edge signals arranged at intervals.

[0120] Exemplarily, when the dual-edge trigger mode is adopted, when the constant current driving chip identifies each edge signal arranged at intervals, each identified edge signal is used as the edge signal of the double-frequency read data clock, thereby obtaining the double-frequency read data clock.

[0121] For example, the edge signals arranged at intervals are: edge signal of the read data clock (such as rising edge signal), edge signal of the copy read data clock (such as rising edge signal), edge signal of the read data clock (such as falling edge signal), edge signal of the copy read data clock (such as falling edge signal)... At this time, when the constant current drive signal recognizes the first edge signal (edge signal of the read data clock), it is considered that the edge signal indicating the start of the clock in the first doubled frequency read data clock is recognized, when the constant current drive signal recognizes the second edge signal (edge signal of the copy read data clock), it is considered that the edge signal indicating the end of the clock in the first doubled frequency read data clock is recognized, when the constant current drive signal recognizes the third edge signal (edge signal of the read data clock), it is considered that the edge signal indicating the start of the clock in the second doubled frequency read data clock is recognized, and so on, all doubled frequency read data clocks can be recognized.

[0122] In one embodiment, when obtaining the double frequency read data clock, it is also necessary to determine whether the signal between adjacent edge signals is a high level or a low level. In an optional manner, the signals between the edge signals arranged at intervals are pre-set to be arranged alternately with high levels and low levels. That is, the first and second edge signals arranged at intervals are high level signals, the second and third edge signals are low level signals, the third and fourth edge signals are high level signals, and so on, thereby obtaining all the double frequency read data clocks. In another optional manner, an exclusive OR operation is used to determine whether the signal between adjacent edge signals is a high level or a low level.

[0123] Currently, taking the use of XOR operation to determine whether the signal between adjacent edge signals is a high level or a low level as an example, at this time, this step can be specifically as follows: according to the dual-edge trigger mode, based on the edge signals arranged at intervals, an XOR operation is performed on the read data clock and the copied read data clock to obtain a doubled frequency read data clock.

[0124] The continuous clock signal is realized by alternating high and low level signals. When performing an XOR operation on two sets of continuous clock signals, a low level signal is obtained based on two high (low) level signals, and a high level signal is obtained based on one high (low) level signal and one low (high) level signal.

[0125] On this basis, an XOR operation is performed on the read data clock and the copied read data clock, and based on the operation result, it is determined whether the edge signal of the doubled frequency read data clock is a high level signal or a low level signal.

[0126] For example, Fig. 9 A third schematic diagram of a grayscale clock signal provided by an embodiment of the present application, Fig. 9In the figure, the first row is used to indicate the type of grayscale clock signal at the corresponding position of the second row, the second and third rows are the specific waveforms of the grayscale clock signal, wherein the second row includes the specific waveform of the read data clock sent by the FPGA, the third row is the specific waveform of the copied read data clock, the fourth row is the specific waveform of the doubled read data clock (i.e. the specific waveform of the read data clock actually used by the constant current driver chip), and the fifth row indicates the row switching signal. Fig. 9 , the edge signals of the read data clock 521 and the copy read data clock 522 are arranged at intervals, and the edge signals arranged at intervals are used as the edge signals of the double frequency read data clock 523. When performing an XOR operation on the read data clock and the copy read data clock, there is only a high level signal of the read data clock between the first two edge signals arranged at intervals (corresponding to the rising edge signal of the read data clock and the rising edge signal of the copy read data clock) in timing, so the high level signal is retained, that is, the first two edge signals are high level signals. The second edge signal (corresponding to the rising edge signal of the copy read data clock) and the third edge signal (corresponding to the falling edge signal of the read data clock) arranged at intervals correspond to the high level signal of the read data clock and the high level signal of the copy read data clock in timing. After the XOR operation, it can be determined that the second edge signal and the third edge signal are low level signals. By analogy, after all the read data clocks and the copy read data clocks are XORed, the double frequency read data clock shown in the fourth row can be obtained.

[0127] In practical applications, other methods may also be used to determine whether the signal between adjacent edge signals is a high level or a low level.

[0128] It can be understood that when the constant current driver chip is driven based on a doubled frequency read data clock, it only needs to receive half of the original number of read data clocks from the FPGA. At this time, the FPGA can reset the number of grayscale clock signals in a set of grayscale clock signals (the number is obtained by adding half of the original number of grayscale clocks to the original number of read data clocks), and output a corresponding number of grayscale clock signals to the constant current driver chip based on the reset number. Optionally, the frequency of the grayscale clock signal generated by the FPGA can remain unchanged or be fine-tuned.

[0129] When the number of read data clocks is changed to half of the original number, the concept of half a clock appears. For example, a series of multiple read data clocks consists of an even number of read clocks and one operation clock. When the number is changed by half, 0.5 read data clocks will appear at the end. However, FPGA cannot transmit only half a clock signal, and needs to transmit a complete clock signal. On this basis, it is necessary to find a way to eliminate the situation where the FPGA transmits half a clock signal when doubling the frequency.

[0130] In one embodiment, the groups of grayscale clock signals required to display a frame of display data are taken as a whole to eliminate the concept of a logical half clock. At this time, the groups of grayscale clock signals corresponding to a frame of display data form a first signal group, and the groups of grayscale clock signals in the first signal group are continuous in timing.

[0131] Exemplarily, the FPGA regards each group of grayscale clock signals required for a frame of display data as a signal group, which is currently recorded as the first signal group. In addition, the total number of grayscale clock signals required in the first signal group is set in units of the first signal group. To eliminate the concept of half a clock, for example, there are four groups of grayscale clock signals in the first signal group, each group has 13.5 clocks, then the first signal group has a total of 13.5×4=54 grayscale clock signals. At this time, there is no concept of half a grayscale clock.

[0132] Exemplarily, each group of grayscale clock signals in the first signal group is continuous in timing, without idle time periods, to ensure that the constant current driver chip accurately identifies the grayscale clock and the read data clock. Afterwards, the constant current driver chip continues to receive each grayscale clock signal in the first signal group, and when the received grayscale clock signal is the read data clock, it becomes a double frequency read data clock. Since the current is a dual-edge trigger mode, the constant current driver chip only needs to identify the edge, which can avoid the occurrence of half a clock.

[0133] For example, Fig.10 A schematic diagram of a first signal group provided by an embodiment of the present application is shown in FIG. Fig.10 In the figure, the first signal group has four groups of grayscale clock signals, each group of grayscale clock signals has 5.5 grayscale clock signals, and the first signal group has a total of 22 grayscale clock signals. When the constant current driver chip scans once, it needs 2 grayscale clocks and 7 double-frequency reading data clocks. Fig.10 In the figure, the first row represents the waveform of the grayscale clock signal of the first signal group output by the FPGA (which can also be understood as the constant current driver chip receiving from the FPGA), the second row represents the waveform of the copied read data clock obtained by the constant current driver chip, and the third row represents the waveform of the grayscale clock signal actually used when the constant current driver chip scans during the working time corresponding to the first signal group, wherein the grayscale clock signal with a low frequency is the grayscale clock, and the grayscale clock signal with a high frequency is the read data clock (i.e., the double frequency read data clock). Based on Fig.10 It can be seen from the clock signal shown that the concept of half a clock signal no longer appears in the grayscale clock signal corresponding to a frame of display data.

[0134] Generally speaking, when a grayscale clock signal is determined as a whole based on a frame of display data, the occurrence of half a clock signal can be effectively avoided. In rare cases, there may be a half clock signal in the first signal group. In this case, half of the previous clock signal can be directly added to the end of the grayscale clock signal of the first signal group to obtain an integer number of grayscale clock signals.

[0135] Optionally, there may be a spare time period between adjacent first signal groups. It is understandable that the length of time required for a scanning process when the constant current driver chip drives the LED display screen to display is basically fixed, and accordingly, the length of time corresponding to displaying a frame of display data is also basically fixed. When the grayscale clock signal corresponding to a frame of display data is continuous, a spare time period may appear behind the first signal group, that is, the spare time period originally appearing between two adjacent groups of grayscale clock signals is concentrated behind the first signal group. When the spare time period appears, the constant current driver chip does not drive the display and does not read the display data. If the duration of the spare time period is long, a large black field may appear (the LED lamp beads do not display). At this time, the user will feel that the display content flickers when watching the LED display screen, and when the black field is large, it will also cause a large load on the power supply of the LED display screen.

[0136] Therefore, in one embodiment, in order to avoid a long idle time period after each first signal group, the number of rows corresponding to the continuous even-numbered scans can be taken as a whole, and the number of continuous even-numbered scans is less than the number of scans corresponding to one frame of display data, so that while eliminating half of the clock signal, the situation of a long idle time period can be avoided. At this time, the continuous even-numbered grayscale clock signal groups form a second signal group, and the grayscale clock signal groups in the second signal group are continuous in timing, and the number of grayscale clock signal groups in the second signal group is less than the number of grayscale clock signal groups corresponding to one frame of display data.

[0137] Exemplarily, the FPGA treats each group of grayscale clock signals required for continuous even-numbered scans as a signal group, which is currently recorded as the second signal group. In addition, the total number of grayscale clock signals required in the second signal group is set in units of the second signal group. It can be understood that the number of groups of grayscale clock signals included in the second signal group is an even number to eliminate the concept of half a clock.

[0138] Optionally, the number of groups of grayscale clock signals included in the second signal group is less than the number of groups of grayscale clock signals corresponding to one frame of display data (i.e., the number of groups of grayscale clock signals included in the first signal group). In this case, the idle time periods corresponding to the first signal group can be broken up and distributed between the second signal groups. This process can be implemented by FPGA, and reference can be made to the implementation methods of FPGA breaking up idle time periods in the relevant technology. In this case, the idle time periods between the second signal groups are small, which can avoid black fields on the LED display.

[0139] It can be understood that the processing method of the grayscale clock signal corresponding to the second signal group can refer to the processing method of the grayscale clock signal corresponding to the first signal group, which will not be described in detail at present.

[0140] In one embodiment, the second signal group consists of two consecutive groups of gray-scale clock signals to minimize the idle time periods.

[0141] In one embodiment of the present application, when eliminating the concept of half a clock signal, in addition to treating multiple groups of gray clock signals as a whole and setting the total number of gray clock signals contained therein, the idle time periods between each group of gray clock signals continuously output by the FPGA can also be set to alternate between high-level signals and low-level signals based on the characteristics of the double-edge trigger mode. That is, the idle time periods between each group of gray clock signals alternate between high-level signals and low-level signals in turn, and the level signal of the idle time period is determined according to the adjacent previous gray clock signal. At this time, the last gray clock signal (i.e., half of the read data clock) in a group of gray clock signals output by the FPGA has only one edge signal indicating the start, and then the level of the idle time period after the group of gray clock signals is consistent with the level of the half of the read data clock, until the next group of gray clock signals starts, and then another edge signal appears. At this time, the idle time periods between each group of gray clock signals will alternate between high-level signals and low-level signals in turn.

[0142] It can be understood that the process of obtaining a double frequency read data clock based on half of the read data clock and the corresponding half of the copied read data clock can refer to the aforementioned content and will not be described in detail at present.

[0143] For example, Fig.11 A fourth schematic diagram of a grayscale clock signal provided according to an embodiment of the present application. Fig.11 In the figure, the first line is used to indicate the type of grayscale clock signal at the corresponding position of the second line, the second line is the specific waveform of the grayscale clock signal, and the grayscale clock signal is the grayscale clock signal generated by the FPGA, and the third line indicates the row switching signal. Fig.11 , the first set of grayscale clock signals ( Fig.11 Only the last few read data clocks are shown in the figure. The last half of the read data clock of the next group of gray clock signals is a low-level signal. At this time, the following idle time period maintains a low-level signal. For FPGA, it can be considered that the level remains unchanged after outputting an integer number of gray clock signals, and then the next group of gray clock signals is output. At the beginning of the next group of gray clock signals, it becomes a high-level signal based on the edge signal that appears. The last half of the read data clock of the next group of gray clock signals is a high-level signal. At this time, the following idle time period maintains a high-level signal, thereby eliminating the half clock signal output by FGPA.

[0144] It should be noted that in the embodiments of the present application, in the schematic diagrams of each grayscale clock signal, the size of the idle time period is only used for exemplary description and cannot explain the size of the idle time period in actual application. If the sizes of the idle time periods in different schematic diagrams are inconsistent, it cannot explain that the idle time periods in actual application are inconsistent.

[0145] Step 240: In the process of receiving a plurality of continuous data read clocks, a row switching signal is received, and a target row driven by a constant current driving signal corresponding to a gray clock in a next set of gray clock signals is determined according to the row switching signal.

[0146] It is understandable that a double frequency read data clock is generated in the constant current driver chip. At this time, the reception time of the row switching signal should correspond to the working time corresponding to the double frequency read data clock. In one embodiment, it is also necessary to modify the frequency and sending time of the switching clock signal corresponding to the row switching signal in the FPGA to ensure that the constant current driver chip receives the row switching signal at the double frequency read data clock.

[0147] In one embodiment, when the first signal group or the second signal group is used to eliminate the concept of half a clock signal that appears when generating a double-frequency read data clock, the frequency of the clock drive count of the row switching signal in the FPGA should be doubled, that is, the frequency of the clock drive count corresponding to the row switching signal is set to twice the frequency. Among them, the clock drive count can be considered as a count of the switching clock signal. It should be noted that for the FPGA, only the frequency of the count is doubled, but the frequency of the switching clock signal is not increased, that is, the switching clock signal is still sent to the row driver chip at the current frequency. When the frequency of the count is doubled, the FPGA can be made to believe that the row switching signal is received within the working time corresponding to the half clock signal (the constant current driver chip does not actually receive the row switching signal). At this time, the FPGA can continue to work after the half clock signal. It can be understood that the FPGA generates a grayscale clock signal, and also needs to generate a data clock signal, a latch signal, and send corresponding display data, etc. The FPGA needs to work according to a complete clock cycle, and it is difficult to implement the working logic under the half grayscale clock signal. Therefore. This problem can be avoided by doubling the frequency of the row switching signal count, that is, by changing the count of the row switching signal at half the grayscale clock signal, the FPGA can still work according to the complete clock cycle.

[0148] For example, Fig.12The first schematic diagram of the clock drive count of the row switching signal provided by an embodiment of the present application. It is the clock drive count corresponding to the row switching signal in the FPGA when the first signal group is used, wherein the first row represents the vertical synchronization signal (which can also be understood as the frame synchronization signal), and the second row represents the first signal group, which includes multiple groups of grayscale clock signals, each group of grayscale clock signals includes a grayscale clock and a read data clock, and the blank part behind it can be regarded as an idle time period 53. The third row represents the clock drive count of the row switching signal by the FPGA, wherein at each arrow, the clock drive count is increased by 1, based on Fig.12 It can be seen that at the end of each data read clock (half clock signal), the clock drive count of the FPGA is increased by 1 to ensure that the FPGA counts normally when the first signal group is used.

[0149] For example, Fig.13 A second schematic diagram of the clock drive count of the row switching signal provided by an embodiment of the present application. It is the clock drive count corresponding to the row switching signal in the FPGA when the second signal group is used, wherein the first row VSYNC represents the vertical synchronization signal (which can also be understood as the frame synchronization signal), and the second row represents each second signal group corresponding to a frame of display data, wherein a second signal group includes two groups of grayscale clock signals, and each group of grayscale clock signals includes a grayscale clock 51 and a read data clock 52. The third row represents the clock drive count of the row switching signal by the FPGA, wherein at each arrow, the clock drive count is increased by 1, based on Fig.13 It can be seen that at the end of each data read clock (half clock signal), the clock drive count of the FPGA is increased by 1 to ensure that the FPGA counts normally when the second signal group is used.

[0150] As mentioned above, by setting the dual-edge trigger mode and increasing the frequency of the read data clock in the dual-edge trigger mode (i.e., using a multi-frequency read data clock), the working time of reading display data corresponding to the read data clock can be shortened, and the clock signal utilization rate in the non-display period is optimized, thereby shortening the time required to scan a line, so that in a set of grayscale clock signals, the proportion of grayscale clocks is further increased, and the brightness efficiency of LED lamp beads during display is improved. At this time, the brightness efficiency can be increased from 50%-70% to 79%-93%. For small-pitch LED display screens, lower power consumption can be used to display higher brightness (without significantly increasing the current of the constant current drive signal), ensuring the temperature rise redundancy during the operation of small-pitch LED display screens. In addition, the implementation process is simple and can be quickly implemented and popularized. In addition, when increasing the frequency of the read data clock, the total number of grayscale clock signals is set based on a frame of display data as a whole, or based on a continuous even-group grayscale clock signal as a whole, avoiding the occurrence of half a clock and ensuring the accurate operation of the constant current drive chip. By increasing the clock drive counting frequency of the row switching signal, the normal counting of the FPGA is also guaranteed, thereby ensuring the normal operation of the constant current drive chip.

[0151] In one embodiment of the present application, a constant current drive chip is also provided, which can be used to execute the constant current drive method provided in any of the above embodiments, and has corresponding functions and beneficial effects. Among them, the constant current drive chip executes the constant current drive method provided in any of the above embodiments, and the structure and implementation process involved can refer to the relevant description of the above embodiments.

[0152] In one embodiment of the present application, an LED display screen is also provided. The LED display screen can be an independent display, such as a billboard, etc., or can be integrated into an electronic device, such as a mobile phone, a television, an interactive tablet, etc., which is equipped with a display screen. Currently, the LED display screen is a small-pitch LED display screen.

[0153] Fig.14 A schematic diagram of the structure of an LED display screen provided in one embodiment of the present application, referring to Fig.14 The LED display screen 60 includes: a receiving card 61 and an LED light board 62, the receiving card 61 includes a logic chip 611, the LED light board 62 includes a plurality of LED lamp beads 621, at least one constant current driving chip 622 and at least one row driving chip 623, Fig.14 In the figure, four LED lamp beads 621, a constant current driving chip 622 and at least one row driving chip 623 are taken as an example, and the logic chip 611 is taken as an FPGA as an example.

[0154] The logic chip 611 is used to sequentially send multiple groups of grayscale clock signals to the constant current driving chip 622, each group of grayscale clock signals is composed of multiple continuous grayscale clocks and multiple continuous data reading clocks, and the grayscale clocks in a group of grayscale clock signals are sent before the data reading clocks, and is also used to send a switching clock signal to the row driving chip 623, and the grayscale clock signal sent by the logic chip 611 at the sending time corresponding to the switching clock signal is the data reading clock;

[0155] The row driving chip 623 is used to send a row switching signal to the constant current driving chip 622 according to the switching clock signal, and each switching clock signal corresponds to a row switching signal;

[0156] The constant current driving chip 622 is used to sequentially receive multiple groups of grayscale clock signals input from the outside. When the currently received grayscale clock signal is a grayscale clock, the corresponding constant current driving signal is output to the LED lamp beads 621 of the current target row based on the first display data corresponding to the read data clock in the previous group of grayscale clock signals, so as to drive the LED lamp beads 621 of the current target row to display. When the currently received grayscale clock signal is a read data clock, the output of the constant current driving signal is stopped, and the second display data is read. The constant current driving signal corresponding to the second display data is used to be output under the grayscale clock in the next group of grayscale clock signals. In the process of receiving multiple consecutive read data clocks, a row switching signal is received, and the target row driven by the constant current driving signal corresponding to the grayscale clock in the next group of grayscale clock signals is determined according to the row switching signal.

[0157] In one embodiment of the present application, the constant current driving chip 622 is used to stop outputting the constant current driving signal and read the second display data when the currently received grayscale clock signal is the read data clock. Specifically, when the currently received grayscale clock signal is the read data clock, a multiplied read data clock is obtained based on the currently received read data clock, and based on the multiplied read data clock, the constant current driving signal is stopped from being output and the second display data is read.

[0158] In one embodiment of the present application, the multi-frequency read data clock is a double-frequency read data clock, and the constant current drive chip 622 is also used to set a double-edge trigger mode before sequentially receiving multiple groups of grayscale clock signals input from the outside. The constant current drive chip 622 is used to obtain a multi-frequency read data clock based on the currently received read data clock, specifically for: copying the currently received read data clock to obtain a copied read data clock, and when copying, controlling the edge signal of the read data clock and the edge signal of the copied read data clock to be arranged at intervals in timing, and the distance between any two adjacent edge signals is equal when arranged at intervals; according to the double-edge trigger mode, a double-frequency read data clock is obtained based on each edge signal arranged at intervals.

[0159] In one embodiment of the present application, the constant current driving chip 622 is used to obtain a double-frequency read data clock based on each edge signal arranged at intervals according to a dual-edge trigger mode. Specifically, it is used to: perform an XOR operation on the read data clock and the copied read data clock based on each edge signal arranged at intervals according to the dual-edge trigger mode to obtain a double-frequency read data clock.

[0160] In one embodiment of the present application, the logic chip 611 is used to send multiple groups of grayscale clock signals to the constant current driving chip in sequence, and is also used to use each group of grayscale clock signals corresponding to a frame of display data as the first signal group, and set the total number of grayscale clock signals included in the first signal group and set each group of grayscale clock signals in the first signal group to be continuous in timing.

[0161] In one embodiment of the present application, the logic chip 611 is used to send multiple groups of grayscale clock signals to the constant current driving chip in sequence, and is also used to use a continuous even number of grayscale clock signals as the second signal group, and set the total number of grayscale clock signals included in the second signal group and set each group of grayscale clock signals in the second signal group to be continuous in timing, and the number of groups of grayscale clock signals in the second signal group is less than the number of groups of grayscale clock signals corresponding to one frame of display data.

[0162] In one embodiment of the present application, the second signal group consists of two consecutive groups of grayscale clock signals.

[0163] In one embodiment of the present application, when the logic chip 611 sends a switching clock signal to the row driver chip, it is also used to adjust the frequency of the clock drive count corresponding to the row switching signal to twice the frequency.

[0164] In one embodiment of the present application, the logic chip 611 is used to send multiple groups of grayscale clock signals to the constant current driving chip in sequence, and is also used to set the idle time periods between each group of grayscale clock signals to alternate between high-level signals and low-level signals in sequence, and the level signal of the idle time period is determined according to the adjacent previous grayscale clock signal.

[0165] In one embodiment of the present application, a row switching signal corresponding to a group of the grayscale clock signals is received in the constant current driving chip 622 later than a third read data clock is received in the constant current driving chip 622 .

[0166] In one embodiment of the present application, a plurality of consecutive read data clocks are composed of an even number of read clocks and one operation clock.

[0167] It is understandable that the LED display screen may also include components such as a buffer driver, which will not be described in detail in the embodiment.

[0168] Need to explain, Fig.14The components included in the LED display are only shown as examples, and the installation positions and relative position relationships of the components are not limited.

[0169] The LED display screen includes a constant current driving chip, which can be used to execute the constant current driving method provided in any of the above embodiments, and has corresponding functions and beneficial effects. The hardware and implementation process involved in the LED display screen can refer to the relevant description of the above embodiments.

[0170] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0171] Note that the above are only preferred embodiments of the present application and the technical principles used. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A constant current driving method for an LED display screen, characterized in that: include: Sequentially receiving a plurality of groups of grayscale clock signals input from the outside, each group of the grayscale clock signals being composed of a plurality of continuous grayscale clocks and a plurality of continuous read data clocks, and the grayscale clocks in a group of the grayscale clock signals being received before the read data clocks; When the grayscale clock signal currently received is a grayscale clock, a corresponding constant current driving signal is output to the LED lamp beads of the current target row based on the first display data correspondingly read under the read data clock in the previous set of grayscale clock signals, so as to drive the LED lamp beads of the current target row to display; When the grayscale clock signal currently received is a data reading clock, the constant current driving signal is stopped from being output, and the second display data is read, and the constant current driving signal corresponding to the second display data is used to be output under the grayscale clock in the next group of grayscale clock signals; In the process of receiving a plurality of continuous data reading clocks, a row switching signal is received, and a target row driven by a constant current driving signal corresponding to a gray clock in a next group of gray clock signals is determined according to the row switching signal.

2. The constant current driving method according to claim 1, characterized in that: When the grayscale clock signal currently received is a data reading clock, the constant current driving signal is stopped from being output, and the second display data is read, comprising: When the grayscale clock signal currently received is a read data clock, a multiplied read data clock is obtained based on the currently received read data clock, and based on the multiplied read data clock, output of the constant current drive signal is stopped and the second display data is read.

3. The constant current driving method according to claim 2, characterized in that: The multiplied frequency read data clock is a doubled frequency read data clock, Before sequentially receiving a plurality of groups of grayscale clock signals input from outside, the method includes: Set the dual edge trigger mode; The obtaining of a multiplied frequency read data clock based on the currently received read data clock comprises: The currently received read data clock is copied to obtain a copied read data clock, and when copying, the edge signal of the read data clock and the edge signal of the copied read data clock are controlled to be arranged at intervals in timing, and the distances between any two adjacent edge signals are equal during the interval arrangement; According to the dual-edge trigger mode, a read data clock with a double frequency is obtained based on the edge signals arranged at intervals.

4. The constant current driving method according to claim 3, characterized in that: The method of obtaining a double frequency reading data clock based on each edge signal arranged at intervals according to the dual edge trigger mode includes: According to the dual-edge trigger mode, an XOR operation is performed on the read data clock and the copied read data clock based on the edge signals arranged at intervals to obtain a read data clock with a double frequency.

5. The constant current driving method according to claim 3, characterized in that: The groups of grayscale clock signals corresponding to one frame of display data form a first signal group, and the groups of grayscale clock signals in the first signal group are continuous in timing.

6. The constant current driving method according to claim 3, characterized in that: Continuous even-group grayscale clock signals form a second signal group, each grayscale clock signal group in the second signal group is continuous in timing, and the number of grayscale clock signal groups in the second signal group is less than the number of grayscale clock signal groups corresponding to one frame of display data.

7. The constant current driving method according to claim 6, characterized in that: The second signal group consists of two consecutive groups of gray-scale clock signals.

8. The constant current driving method according to claim 5 or 6, characterized in that: The frequency of the clock driving count corresponding to the row switching signal is set to double the frequency.

9. The constant current driving method according to claim 3, characterized in that: The idle time periods between the grayscale clock signals of each group are alternately high-level signals and low-level signals, and the level signals of the idle time periods are determined according to the adjacent previous grayscale clock signal.

10. The constant current driving method according to claim 1, characterized in that: A receiving time of the row switching signal corresponding to a group of the grayscale clock signals is later than a receiving time of the third read data clock.

11. The constant current driving method according to claim 1, 5 or 6, characterized in that: The continuous plurality of read data clocks consists of an even number of read clocks and one operation clock.

12. A constant current driver chip for an LED display, characterized in that: The constant current driving chip is used to execute the constant current driving method of the LED display screen as described in any one of claims 1-11.

13. An LED display screen, characterized in that: The LED display screen includes: a receiving card and an LED light board, wherein the receiving card includes a logic chip, and the LED light board includes a plurality of LED lamp beads, at least one constant current driving chip and at least one row driving chip. The logic chip is used to sequentially send multiple groups of grayscale clock signals to the constant current driving chip, each group of the grayscale clock signals is composed of a plurality of continuous grayscale clocks and a plurality of continuous data reading clocks, and the grayscale clocks in a group of the grayscale clock signals are sent before the data reading clocks, and is also used to send a switching clock signal to the row driving chip, and the grayscale clock signal sent by the logic chip at the sending time corresponding to the switching clock signal is a data reading clock; The row driver chip is used to send a row switching signal to the constant current driver chip according to the switching clock signal, and each switching clock signal corresponds to one row switching signal; The constant current driving chip is used to sequentially receive multiple groups of grayscale clock signals input from the outside. When the grayscale clock signal currently received is a grayscale clock, the constant current driving signal is output to the LED lamp beads of the current target row based on the first display data corresponding to the read data clock in the previous group of grayscale clock signals, so as to drive the LED lamp beads of the current target row to display. When the grayscale clock signal currently received is a read data clock, the constant current driving signal is stopped from being output, and the second display data is read. The constant current driving signal corresponding to the second display data is used to be output under the grayscale clock in the next group of grayscale clock signals. In the process of receiving multiple consecutive read data clocks, the row switching signal is received, and the target row driven by the constant current driving signal corresponding to the grayscale clock in the next group of grayscale clock signals is determined according to the row switching signal.

Citation Information

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Patent Information

AI Technical Summary

Abstract

Description

Patent Citations

LED display screen driving chip and latch signal generation method and system

Multi-line scanning high-refresh-rate full-color LED driving chip and driving method

Clock synthesis circuitry and associated techniques for generating clock signals refreshing display screen content

Multi-row scanning and row changing display method and chip

Display driving method, display driving circuit, LED display panel and display device

Cited By

Liquid crystal display control method, driving chip and storage medium