Display panel and display device

Abstract

The invention relates to a display panel and a display device. The light-emitting stage of the display panel comprises a first light-emitting stage located in a data writing frame, and a non-light-emitting stage adjacent to the first light-emitting stage and located before the first light-emitting stage comprises a data writing stage; the light-emitting stage further comprises a second light-emitting stage, the second light-emitting stage is located in the data writing frame where the first light-emitting stage is located, and / or the second light-emitting stage is located in the holding frame adjacent to the data writing frame where the first light-emitting stage is located; wherein the light-emitting duration of the first light-emitting stage is different from the light-emitting duration of the second light-emitting stage. According to the display panel provided by the invention, the brightness fluctuation caused by writing the data signal into the pixel circuit is compensated by changing the light-emitting duration of the light-emitting element in the data writing frame or in the holding frames before and after the data writing frame, and the display effect is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In an organic light-emitting diode (OLED) display panel, each pixel includes a pixel circuit and a light-emitting element. The pixel circuit controls the current flowing through the light-emitting element, thereby driving the light-emitting element to emit light. By controlling the switching state of the transistor in the pixel circuit and the data signal written to the pixel circuit, the light-emitting duration of the light-emitting element and the current flowing through the light-emitting element can be adjusted, thereby adjusting the brightness of each pixel to form a display image. The design of the pixel circuit enables the display panel to achieve high-resolution, high-contrast and fast-response image display.

[0003] Signal fluctuations may occur in the pixel circuit during operation. When the signal fluctuations are transmitted to the light-emitting element, they will be reflected as brightness fluctuations of the light-emitting element, that is, the flickering phenomenon of the display panel in the human eye. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a display device.

[0005] The present disclosure provides a display panel, wherein the working phase of the display panel includes a plurality of non-luminous phases and a plurality of luminous phases; at least part of the non-luminous phases includes a data writing phase; the display panel includes a plurality of sub-pixels, wherein the sub-pixels include a pixel circuit and a luminous element electrically connected to the pixel circuit, wherein the luminous element emits light during the luminous phase; the pixel circuit includes a driving transistor and a data writing transistor, wherein the data writing transistor is used to provide a data signal to the driving transistor during the data writing phase; in the display panel, the display process of a frame of an image includes a plurality of sub-frames, wherein the plurality of sub-frames include a data writing frame and a holding frame; the luminous phase includes a first luminous phase, wherein the first luminous phase is located in the data writing frame; the non-luminous phase adjacent to the first luminous phase and located before the first luminous phase includes the data writing phase; the luminous phase also includes at least one second luminous phase, wherein the second luminous phase is located in the data writing frame where the first luminous phase is located, and / or the second luminous phase is located in the holding frame adjacent to the data writing frame where the first luminous phase is located; wherein the luminous duration of the first luminous phase is different from the luminous duration of the second luminous phase.

[0006] Based on the same inventive concept, the present disclosure also provides a display device, including the display panel.

[0007] The technical solution provided by the present invention has the following advantages over the prior art: the display panel provided by the present invention adjusts the brightness of the light-emitting element in the data writing frame by changing the light-emitting duration of the light-emitting element in the data writing frame; or, compensates for the brightness of the light-emitting element in the data writing frame by changing the light-emitting duration of the light-emitting element in the holding frame before and after the data writing frame, thereby compensating for the brightness fluctuation caused by the writing of the data signal into the pixel circuit, thereby improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0010] Figure 1 A schematic diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0011] Figure 2 A timing diagram of working stages of a display panel provided by an embodiment of the present disclosure;

[0012] Figure 3 A schematic diagram of a planar structure of a display panel provided in an embodiment of the present disclosure;

[0013] Figure 4 A timing diagram of another working phase of a display panel provided by an embodiment of the present disclosure;

[0014] Figure 5 A timing diagram of another working phase of a display panel provided by an embodiment of the present disclosure;

[0015] Figure 6 A timing diagram of another working phase of a display panel provided by an embodiment of the present disclosure;

[0016] Figure 7 A timing diagram of another working phase of a display panel provided by an embodiment of the present disclosure;

[0017] Figure 8 A timing diagram of another working phase of a display panel provided by an embodiment of the present disclosure;

[0018] Fig. 9 A timing diagram of another working phase of a display panel provided by an embodiment of the present disclosure;

[0019] Fig.10A timing diagram of another working phase of a display panel provided by an embodiment of the present disclosure;

[0020] Fig.11 A schematic diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0021] Fig.12 A timing diagram of another working phase of a display panel provided by an embodiment of the present disclosure;

[0022] Fig.13 A schematic diagram of the planar structure of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In order to more clearly understand the above-mentioned purposes, features and advantages of the embodiments of the present disclosure, the scheme of the embodiments of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other without conflict.

[0024] In the following description, many specific details are set forth to facilitate a full understanding of the embodiments of the present disclosure, but the embodiments of the present disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0025] The pixel circuit provided by the embodiment of the present disclosure is as follows: Figure 1 As shown, it includes a driving transistor M0, a gate reset transistor M1, a threshold compensation transistor M2, an anode reset transistor M3, a data writing transistor M4, a first light emission control transistor M5, a second light emission control transistor M6 and a storage capacitor Cst.

[0026] Among them, the gate reset transistor M1 is used to provide the reset signal Verf to the gate of the driving transistor M0, the threshold compensation transistor M2 is used to provide threshold compensation for the gate of the driving transistor M0, the anode reset transistor M3 is used to provide the reset signal Verf to the anode of the light-emitting element D, the data write transistor M4 is used to provide the data signal Data to the first electrode of the driving transistor M0, the first light-emitting control transistor M5 is used to provide the power signal PVDD to the first electrode of the driving transistor M0, the driving transistor M0 is used to provide a driving signal to the anode of the light-emitting element D according to the above-mentioned power signal PVDD and the data signal Data, and the second light-emitting control transistor M6 is used to provide a driving signal to the anode of the light-emitting element D.

[0027] Figure 2 It shows a Figure 1 The driving signal timing diagram of the pixel circuit shown in FIG. 1 is a timing diagram of the working phase of the display panel. Figure 2As shown, the working stages of the display panel include multiple non-luminous stages TB and multiple luminous stages TA. Specifically, in the luminous stage TA, the first luminous control transistor M5 is turned on and provides the power signal PVDD to the first electrode of the driving transistor M0. The driving transistor M0 provides a driving signal to the anode of the light-emitting element D according to the above-mentioned power signal PVDD and the data signal Data. The second luminous control transistor M6 is turned on and provides the driving signal to the anode of the light-emitting element D, and then the light-emitting element emits light in the luminous stage TA.

[0028] The display process of a frame of picture includes multiple sub-frames, and the multiple sub-frames include a data writing frame Active and a holding frame Keep. The data writing frame Active and the holding frame Keep both include a non-luminous stage TB and a luminous stage TA. The non-luminous stage TB in the data writing frame Active further includes a data writing stage Tdata. The above-mentioned data writing transistor M4 provides a data signal Data to the driving transistor M0 in the data writing stage Tdata.

[0029] Figure 3 A schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure is shown. As shown in the figure, the display panel includes a plurality of pixel circuits C and light-emitting elements D arranged in the display area AA. The light-emitting element D is electrically connected to the pixel circuit C. The specific circuit schematic diagram and driving timing of the pixel circuit C can be referred to Figure 1 and Figure 2 Among them, Figure 3 As shown, the display panel further includes a data signal line Data line, and a plurality of pixel circuits C are connected to the same data signal line Data line, and receive a data signal Data provided by the driving chip IC through the data signal line Data line.

[0030] When displaying a frame of picture, the brightness of each light-emitting element D in the display panel is different, and thus the data signal Data provided to each light-emitting element D is also different. For multiple light-emitting elements D whose pixel circuits C are connected to the same data signal line Data line, the data signal Data provided to one of the pixel circuits C will be coupled with the node of another pixel circuit C, causing the node potential to fluctuate or even jump, thereby causing the brightness of another light-emitting element D to deviate from expectations, resulting in brightness fluctuations. Since the data signal Data is written in the data writing frame Active, the above phenomenon causes the brightness of the light-emitting element D to fluctuate in the data writing frame Active, and the brightness of the data writing frame Active and the subsequent keeping frame Keep are unbalanced, causing the brightness of the display panel to flicker as seen by the human eye.

[0031] In view of this, the present disclosure provides a display panel having a planar structure as follows: Figure 3As shown, the circuit schematic diagram of the pixel circuit C can be referred to Figure 1 The display panel includes a plurality of sub-pixels, each of which includes a pixel circuit C and a light-emitting element D electrically connected to the pixel circuit C; the pixel circuit C includes a driving transistor M0 and a data writing transistor M4.

[0032] The working stages of the display panel provided by the embodiment of the present disclosure include multiple non-luminous stages TB and multiple luminous stages TA, and the light-emitting element D emits light in the luminous stage TA; at least part of the non-luminous stage TB includes a data writing stage Tdata, and the data writing transistor M4 is used to provide a data signal Data to the driving transistor M0 in the data writing stage Tdata.

[0033] Specifically, in the display panel, the display process of a frame includes multiple subframes, and the multiple subframes include a data writing frame Active and a holding frame Keep, and the data writing stage Tdata is located in the data writing frame Active. The display panel no longer writes data in the holding frame Keep, but uses the data signal written in the data writing frame Active to perform light display.

[0034] The light-emitting phase TA includes a first light-emitting phase T1, which is located in the data writing frame Active; and a non-light-emitting phase TB adjacent to and before the first light-emitting phase T1 includes a data writing phase Tdata. Figure 4 and Figure 5 As shown, each subframe includes only one non-luminous phase TB and one luminous phase TA. At this time, the data writing phase Tdata is located in the non-luminous phase TB of the refresh frame Active, and the first luminous phase T1 is the luminous phase TA of the refresh frame Active. In another embodiment, as Figures 6 to 8 As shown, each subframe includes at least two non-luminous phases TB and at least two luminous phases TA. At this time, the data writing phase Tdata is located in the first non-luminous phase TB of the refresh frame Active, and the first luminous phase T1 is the first luminous phase TA in the refresh frame Active.

[0035] Understandably, Figures 6 to 8 Taking the example that each subframe includes two non-light-emitting phases TB and two light-emitting phases TA, those skilled in the art can implement corresponding embodiments including more non-light-emitting phases TB and light-emitting phases TA based on the present disclosure, which will not be described in detail.

[0036] like Figures 4 to 8As shown, the light-emitting stage TA also includes at least one second light-emitting stage T2, the second light-emitting stage T2 is located in the data writing frame Active where the first light-emitting stage T1 is located, and / or the second light-emitting stage T2 is located in the keep frame Keep adjacent to the data writing frame Active where the first light-emitting stage T1 is located. The light-emitting duration of the first light-emitting stage T1 is different from the light-emitting duration of the second light-emitting stage T2.

[0037] Specifically, in Figure 4 and Figure 5 In the embodiment shown, each subframe includes only one non-light-emitting phase TB and one light-emitting phase TA. The second light-emitting phase T2 is located in a holding frame Keep adjacent to the data writing frame Active where the first light-emitting phase T1 is located. The holding frame Keep can be as follows: Figure 4 As shown, it is located after the data is written into the Active frame. Figure 5 The image is shown before the data is written into the Active frame (ie, the Keep frame corresponding to the previous refresh screen).

[0038] exist Figures 6 to 8 In the embodiment shown, each subframe includes at least two non-light-emitting phases TB and at least two light-emitting phases TA. The second light-emitting phase T2 can be as follows: Figure 6 The data writing frame Active is shown in the first light-emitting stage T1; the second light-emitting stage T2 may also be as shown in the Figure 7 As shown, the keep frame Keep is located adjacent to the data writing frame Active in the first light-emitting stage T1 and after the data writing frame Active; the second light-emitting stage T2 can also be as Figure 8 As shown, the hold frame Keep located adjacent to the data writing frame Active in the first light-emitting stage T1 and located before the data writing frame Active (ie, the hold frame Keep corresponding to the previous data writing frame Active).

[0039] Since the brightness of the light-emitting element D deviates from the expectation due to the writing of the data signal Data, the brightness fluctuation of the light-emitting element D mainly occurs in the data writing stage Tdata of the data writing frame Active. In the related art, the light-emitting durations of multiple light-emitting stages TA of the display panel are the same. Since the brightness perceived by the human eye can be accumulated over time, the above brightness fluctuations will be perceived by the human eye, thereby affecting the display effect. In the above embodiment of the present disclosure, the first light-emitting stage T1 is a light-emitting stage adjacent to the data writing stage Tdata, and the second light-emitting stage T2 is close to the first light-emitting stage T1. By adaptively adjusting the light-emitting durations of the first light-emitting stage T1 and the second light-emitting stage T2, the brightness of the light-emitting element D perceived by the human eye in the data writing stage Tdata can be adjusted, and finally reflected as the light-emitting duration of the first light-emitting stage T1 is different from the light-emitting duration of the second light-emitting stage T2.

[0040] The disclosed embodiments adjust the brightness of the light-emitting element in the data writing frame Active by changing the light-emitting duration of the light-emitting element in the data writing frame Active; or, compensate for the brightness of the light-emitting element in the data writing frame Active by changing the light-emitting duration of the light-emitting element in the hold frame Keep located before and after the data writing frame Active, thereby compensating for the brightness fluctuation caused by writing the data signal into the pixel circuit and improving the display effect.

[0041] Specifically, in Figures 6 to 8 In the illustrated embodiment, each subframe includes at least two non-light-emitting phases TB and at least two light-emitting phases TA. Figures 6 to 8 The pixel circuit C corresponding to the embodiment shown can be referred to Figure 1 , including a light emitting control transistor (which may be a first light emitting control transistor M5 and a second light emitting control transistor M6), the light emitting control transistor is electrically connected to the driving transistor M0 and the light emitting element D, and is used to control the driving current to flow through the light emitting element D in the light emitting stage TA. The light emitting control transistor is electrically connected to a light emitting control signal line, and a light emitting control signal Emit is transmitted on the light emitting control signal line; the change frequency of the light emitting control signal Emit is greater than the basic operating frequency of the display panel.

[0042] In some embodiments, the second light emitting stage T2 is the light emitting stage TA closest to the first light emitting stage T1 in the subframe where the second light emitting stage T2 is located, so as to specifically compensate for the brightness fluctuation of the data writing stage Tdata.

[0043] Specifically, in Figure 4 and Figure 5In the embodiment shown, each subframe includes only one non-luminous phase TB and one luminous phase TA. At this time, the luminous phase TA (i.e., the second luminous phase T2) of the hold frame Keep adjacent to the data writing frame Active can be regarded as the luminous phase TA closest to the first luminous phase T1.

[0044] exist Figure 6 In the embodiment shown, each subframe includes a plurality of non-light-emitting stages TB and a plurality of light-emitting stages TA, and the second light-emitting stage T2 and the first light-emitting stage T1 are both located in the data writing frame Active, the first light-emitting stage T1 is the first light-emitting stage of the data writing frame Active, and the second light-emitting stage T2 is the second light-emitting stage of the data writing frame Active. It can be understood that Figure 6 Taking the example that each subframe includes two non-luminous stages TB and two luminous stages TA, in other embodiments, for example, each subframe includes four non-luminous stages TB and four luminous stages TA, the first luminous stage T1 is still the first luminous stage of the data writing frame Active, and the second luminous stage T2 is still the second luminous stage of the data writing frame Active.

[0045] exist Figure 7 In the illustrated embodiment, each subframe includes a plurality of non-luminous phases TB and a plurality of luminous phases TA, and the second luminous phase T2 is located in a holding frame Keep after the data writing frame Active where the first luminous phase T1 is located, and the second luminous phase T2 is the first luminous phase in the holding frame Keep.

[0046] exist Figure 8 In the illustrated embodiment, each subframe includes a plurality of non-luminous phases TB and a plurality of luminous phases TA, and the second luminous phase T2 is located in a holding frame Keep before the data writing frame Active where the first luminous phase T1 is located, and the second luminous phase T2 is the last luminous phase in the holding frame Keep.

[0047] Since the brightness perceived by the human eye can be accumulated over time, the closer the distance between the second light-emitting stage T2 and the first light-emitting stage T1 is, the more directly the brightness change caused by adjusting the second light-emitting stage T2 can be compensated to the first light-emitting stage T1, and the better the compensation effect of brightness fluctuation is. In view of this, in some embodiments, such as Figures 4 to 6 as well as Figure 8 As shown, the second light-emitting stage T2 and the first light-emitting stage T1 are adjacent light-emitting stages TA, which further specifically compensate for the brightness fluctuation of the data writing stage Tdata.

[0048] For example, if there are other light-emitting stages TA between the second light-emitting stage T2 and the first light-emitting stage T1, the brightness change caused by adjusting the second light-emitting stage T2 will first compensate for the brightness of the middle light-emitting stage TA, and then the brightness change of the middle light-emitting stage TA will compensate for the brightness of the first light-emitting stage T1, ultimately resulting in a compensation effect that is worse than the compensation effect of the above embodiment.

[0049] In some embodiments, Figure 3 As shown, the display panel includes an edge pixel row P0 in the edge area of ​​the display area AA. The display panel will use an edge algorithm for the edge pixel row P0, that is, provide a black data voltage to the edge pixel row P0, so that the brightness transition from the display area AA to the non-display area of ​​the display panel is more natural. After applying the above edge algorithm, the data signal will jump to VGMP at the end of the data writing phase Tdata, and couple with the N1 node of the pixel circuit C connected to the same data signal line Data line, pulling up the potential of the N1 node; because the Keep frame does not write data, the coupling only occurs in the data writing frame Active, and the discontinuity of the coupling causes the brightness of the light-emitting element D to be lowered after the data writing phase Tdata, which is ultimately reflected in the high brightness of the light-emitting element D in the data writing frame Active, and the display panel has a flickering problem.

[0050] In view of this, in some embodiments, the luminous duration of the above-mentioned second luminous stage T2 is shorter than the luminous duration of the first luminous stage T1, thereby reducing the brightness of the data writing frame Active or the keep frame Keep adjacent to the data writing frame Active as perceived by the human eye, thereby compensating for the brightness fluctuation caused by the data signal writing into the pixel circuit and improving the display effect.

[0051] It should be noted that since the first light-emitting stage T1 is a light-emitting stage adjacent to the data writing stage Tdata, the final required light-emitting brightness of the light-emitting element D is mainly reflected by the light-emitting duration of the first light-emitting stage T1. Directly reducing the duration of the first light-emitting stage T1 may lead to over-compensation, making the light-emitting brightness of the light-emitting element D unable to reach the expected level. The same is true for the following embodiments and will not be repeated.

[0052] Specifically, in Figure 6 In the illustrated embodiment, the second light-emitting stage T2 and the first light-emitting stage T1 are located in the same data writing frame Active, the second light-emitting stage T2 is located after the first light-emitting stage T1, and the light-emitting duration of the second light-emitting stage T2 is shorter than the light-emitting duration of the first light-emitting stage T1, thereby reducing the light-emitting duration of the entire data writing frame Active, reducing the brightness of the data writing frame Active perceived by the human eye, compensating for the brightness fluctuation caused by the data signal writing into the pixel circuit, and improving the display effect.

[0053] exist Figure 5 and Figure 8 In the illustrated embodiment, the first light-emitting stage T1 is located in the data writing frame Active of the i-th frame, and the second light-emitting stage T2 is located in the holding frame Keep of the i-1-th frame, where i≥2 and i is a positive integer. The light-emitting duration of the second light-emitting stage T2 is shorter than the light-emitting duration of the first light-emitting stage T1, thereby reducing the light-emitting duration of the holding frame Keep adjacent to the data writing frame Active, reducing the brightness of the data writing frame Active perceived by the human eye, compensating for the brightness fluctuation caused by the data signal writing into the pixel circuit, and improving the display effect.

[0054] exist Figure 4 and Figure 7 In the embodiment shown, the second light-emitting stage T2 is located in the hold frame Keep adjacent to the data writing frame Active where the first light-emitting stage T1 is located, and the second light-emitting stage T2 is located after the first light-emitting stage T1. The light-emitting duration of the second light-emitting stage T2 is shorter than the light-emitting duration of the first light-emitting stage T1, thereby reducing the light-emitting duration of the hold frame Keep adjacent to the data writing frame Active, reducing the brightness of the data writing frame Active perceived by the human eye, compensating for the brightness fluctuation caused by the data signal writing into the pixel circuit, and improving the display effect. Specifically, in Figure 7 In the illustrated embodiment, one holding frame Keep includes at least two light emitting phases TA, and the second light emitting phase T2 is the first light emitting phase TA in the holding frame Keep.

[0055] Leakage current refers to the phenomenon that a small amount of current still passes through the source and drain of the transistor when the transistor should be in the off state. Although this current is very small, it will affect the display effect. For example, if the leakage current continues to exist, the brightness of the light-emitting element D will gradually decrease and cannot maintain the written brightness. Then, the brightness of the light-emitting element D will jump up when the next frame of data is written, and flickering will occur.

[0056] Moreover, in the LTPO (Low-Temperature Polycrystalline Oxide) display panel, although the low-temperature polycrystalline silicon (LTPS) transistor has the advantage of strong driving capability, its leakage problem is more serious, especially when the display panel displays at a low frequency, the brightness of the light-emitting element D caused by the leakage current gradually decreases more obviously.

[0057] In view of this, in some embodiments, Fig. 9 and Fig.10As shown, the first light-emitting stage T1 is located in the data writing frame Active2 of the i-th frame, and the second light-emitting stage T2 is located in the holding frame Keep of the i-1-th frame, specifically the holding frame Keep that is closest to the data writing frame Active2 of the first light-emitting stage T1, i≥2 and i is a positive integer.

[0058] Specifically, in Fig. 9 In the embodiment shown, one frame includes one data writing frame and three holding frames. At this time, the second light-emitting stage T2 is located at the last holding frame Keep3 of the i-1th frame closest to the first light-emitting stage T1; and Fig. 9 In the embodiment shown, one subframe includes only one light-emitting phase TA, and the second light-emitting phase T2 is the light-emitting phase TA of the third keep frame Keep3. Fig.10 In the embodiment shown, one frame includes one data writing frame and two holding frames, and the second light-emitting stage T2 is located at the last holding frame Keep2 of the i-1th frame closest to the first light-emitting stage T1; and Fig.10 In the illustrated embodiment, one subframe includes a plurality of light-emitting phases TA, and the second light-emitting phase T2 is the last light-emitting phase TA in the second keep frame Keep2.

[0059] Understandably, Fig. 9 and Fig.10 This is only an example. In other embodiments, a frame may include a larger number of retention frames. Those skilled in the art can derive a specific implementation method based on the above embodiments of the present disclosure, and will not be described in detail.

[0060] exist Fig. 9 and Fig.10 In the illustrated embodiment, the i-1th frame includes the Lth subframe FL, the Mth subframe FM and the Nth subframe FN, where L, M and N are all positive integers, L≥1, M>1 and N>1. The Lth subframe FL is located before the Mth subframe FM, which is located before the Nth subframe FN. The Lth subframe FL is a data writing frame Active or a holding frame Keep, and the Mth subframe FM and the Nth subframe FN are both holding frames Keep; the second light-emitting stage T2 is located at the Nth subframe FN.

[0061] Specifically, in Fig. 9In the illustrated embodiment, the Lth subframe FL may be the data writing frame Active1 of the i-1th frame, the Mth subframe FM may be the first hold frame Keep1 of the i-1th frame, and the Nth subframe FN may be the third and last hold frame Keep3 of the i-1th frame. In another specific embodiment, the Lth subframe FL may also be the first hold frame Keep1 of the i-1th frame, and the Mth subframe FM may also be the second hold frame Keep2 of the i-1th frame.

[0062] exist Fig.10 In the illustrated embodiment, the Lth subframe FL may be the data write frame Active1 of the i-1th frame, the Mth subframe FM may be the first keep frame Keep1 of the i-1th frame, and the Nth subframe FN may be the second and last keep frame Keep2 of the i-1th frame.

[0063] exist Fig. 9 and Fig.10 In the embodiment shown, the total lighting duration of the Lth subframe FL is T L , the total luminous duration of the Mth subframe FM is T M , the total luminous duration of the Nth subframe TN is T N , where T L <T M And T M ≥T N Specifically, when a subframe includes multiple light-emitting stages TA, the total light-emitting duration is the sum of the durations of all light-emitting stages TA of the subframe.

[0064] In order to solve the problem that the brightness of the light-emitting element D gradually decreases due to leakage current, the total light-emitting time of the Mth subframe FM is set to T M The total luminous duration greater than the Lth subframe FL is T L , that is, by increasing the luminous duration of the holding frame, the brightness of the light-emitting element D in the holding frame is compensated; at the same time, in order to avoid the brightness of the light-emitting element D in the data writing frame Active being too high, it is necessary to increase the luminous duration of the holding frame while relatively reducing the luminous duration of the last holding frame, that is, to make the total luminous duration T of the Nth subframe FN N The total luminous duration less than or equal to the Mth subframe FM is T M .

[0065] In other embodiments, the display panel includes multiple holding frames in one frame, and except for the last holding frame, the total luminous duration of the multiple holding frames increases successively, and the total luminous duration of the last holding frame is less than or equal to the total luminous duration of the second to last holding frame.

[0066] In some embodiments, Fig. 9 and Fig.10 As shown, the total luminous duration of the data written into the frame Active2 of the i-th frame is less than the total luminous duration of the N-th subframe FN. The luminous duration of the second luminous stage T2 is greater than the luminous duration of the first luminous stage T1.

[0067] When the display panel includes multiple hold frames in one frame, leakage current will cause the brightness of the light-emitting element to continue to decrease, and the impact brought is greater than the high brightness of the data writing frame. Therefore, at this time, the light-emitting duration of the second light-emitting stage T2 needs to be greater than the light-emitting duration of the first light-emitting stage T1 to balance the brightness of the light-emitting element during the entire display process.

[0068] In some embodiments, Fig. 9 As shown, one subframe includes only one light emitting phase TA, the Lth subframe FL includes the third light emitting phase T3, and the Mth subframe FM includes the fourth light emitting phase T4.

[0069] Specifically, in Fig. 9 In the embodiment shown, the third light-emitting stage T3 may be the light-emitting stage TA of writing data of the i-1 frame into the frame Active1; the fourth light-emitting stage T4 may be the light-emitting stage TA of the first hold frame Keep1 of the i-1 frame. In another specific embodiment, the third light-emitting stage T3 may also be the light-emitting stage TA of the first hold frame Keep1 of the i-1 frame; the fourth light-emitting stage T4 may also be the light-emitting stage TA of the second hold frame Keep2 of the i-1 frame.

[0070] The lighting duration of the second lighting stage T2 is less than or equal to the lighting duration of the fourth lighting stage T4, and the lighting duration of the fourth lighting stage T4 is greater than the lighting duration of the third lighting stage T3.

[0071] When a subframe of the display panel includes only one light-emitting stage TA, the light-emitting duration of the light-emitting stage TA is equivalent to the total light-emitting duration of the subframe. In order to solve the problem of the gradual decrease in the brightness of the light-emitting element D caused by leakage current, the light-emitting duration of the fourth light-emitting stage T4 is made longer than the light-emitting duration of the third light-emitting stage T3, that is, by increasing the light-emitting duration of the holding frame, the brightness of the light-emitting element D that decreases in the holding frame is compensated; at the same time, in order to avoid the brightness of the light-emitting element D being too high in the data writing frame Active, it is necessary to increase the light-emitting duration of the holding frame while relatively reducing the light-emitting duration of the last holding frame, that is, to make the light-emitting duration of the second light-emitting stage T2 less than or equal to the light-emitting duration of the fourth light-emitting stage T4.

[0072] In some embodiments, Fig.10 As shown, one subframe includes a plurality of light-emitting stages TA.

[0073] The Lth subframe FL includes a third light emitting stage T3 and a fifth light emitting stage T5; the Mth subframe FM includes a fourth light emitting stage T4 and a sixth light emitting stage T6; and the Nth subframe further includes a seventh light emitting stage T7.

[0074] Specifically, in Fig.10 In the illustrated embodiment, the Lth subframe FL can be the data writing frame Active1 of the i-1th frame picture, the third light-emitting stage T3 can be the first light-emitting stage TA of the data writing frame Active1, and the fifth light-emitting stage T5 can be the second light-emitting stage TA of the data writing frame Active1; the Mth subframe FM can be the first keeping frame Keep1 of the i-1th frame picture, the fourth light-emitting stage T4 can be the first light-emitting stage TA of the keeping frame Keep1, and the sixth light-emitting stage T6 can be the second light-emitting stage TA of the keeping frame Keep1; the Nth subframe can be the second and last keeping frame Keep2 of the i-1th frame picture, the seventh light-emitting stage T7 can be the first light-emitting stage TA of the keeping frame Keep2, and the seventh light-emitting stage T7 is located before the second light-emitting stage T2.

[0075] The total lighting duration of the third lighting stage T3 and the fifth lighting stage T5 is less than the total lighting duration of the fourth lighting stage T4 and the sixth lighting stage T6; the total lighting duration of the fourth lighting stage T4 and the sixth lighting stage T6 is greater than or equal to the total lighting duration of the second lighting stage T2 and the seventh lighting stage T7.

[0076] When a subframe of the display panel includes multiple light-emitting stages TA, the sum of the light-emitting durations of the multiple light-emitting stages TA is equivalent to the total light-emitting duration of the subframe. In order to solve the problem of the gradual decrease in the brightness of the light-emitting element D caused by leakage, the total light-emitting duration of the fourth light-emitting stage T4 and the sixth light-emitting stage T6 is made greater than the total light-emitting duration of the third light-emitting stage T3 and the fifth light-emitting stage T5, that is, by increasing the light-emitting duration of the holding frame, the brightness of the light-emitting element D that decreases in the holding frame is compensated; at the same time, in order to avoid the brightness of the light-emitting element D being too high in the data writing frame Active, it is necessary to increase the light-emitting duration of the holding frame while relatively reducing the light-emitting duration of the last holding frame, that is, to make the total light-emitting duration of the second light-emitting stage T2 and the seventh light-emitting stage T7 less than or equal to the total light-emitting duration of the fourth light-emitting stage T4 and the sixth light-emitting stage T6.

[0077] exist Fig.10 In the illustrated embodiment, the fifth light-emitting stage T5 is located after the third light-emitting stage T3 , the sixth light-emitting stage T6 is located after the fourth light-emitting stage T4 , and the second light-emitting stage T2 is located after the seventh light-emitting stage T7 .

[0078] The lighting duration of the fifth lighting stage T5 is greater than or equal to that of the third lighting stage T3, the lighting duration of the sixth lighting stage T6 is greater than or equal to that of the fourth lighting stage T4, and the lighting duration of the second lighting stage T2 is less than that of the seventh lighting stage T7.

[0079] When a subframe of the display panel includes multiple light-emitting stages TA, in order to further compensate for the brightness reduction caused by the leakage current, the light-emitting duration of the multiple light-emitting stages TA in a subframe can be gradually increased. At the same time, in order to avoid the brightness of the light-emitting element D being too high in the data writing frame Active, in the last holding frame of a frame, the light-emitting duration of the last light-emitting stage (i.e., the second light-emitting stage T2) needs to be shorter than the light-emitting duration of the previous light-emitting stage (i.e., the seventh light-emitting stage T7).

[0080] In some other embodiments, the Nth subframe includes a second light-emitting stage T2 and a seventh light-emitting stage, the second light-emitting stage T2 is located after the seventh light-emitting stage T7, and the light-emitting duration of the second light-emitting stage T2 is less than the light-emitting duration of the seventh light-emitting stage T7. At this time, the total light-emitting duration T of the Nth subframe is N It is possible that the total luminous duration of the Mth subframe is T M , that is, the total lighting duration of the fourth lighting stage T4 and the sixth lighting stage T6 is equal to the total lighting duration of the second lighting stage T2 and the seventh lighting stage T7.

[0081] In other embodiments, the leakage problem of the display panel is relatively small, and a plurality of holding frames (including the Lth subframe, the Mth subframe and the Nth subframe) are included in one frame, and one holding frame includes a plurality of light-emitting stages. At this time, the Nth subframe includes the second light-emitting stage T2 and the seventh light-emitting stage T7, the second light-emitting stage T2 is located after the seventh light-emitting stage T7, the light-emitting duration of the second light-emitting stage T2 is less than the light-emitting duration of the seventh light-emitting stage T7, and the total light-emitting duration of the Lth subframe is T2. L , the total luminous duration of the Mth subframe is T M , the total luminous duration of the Nth subframe is T N , where T L =T M =T N That is, the total lighting duration of the third light-emitting stage T3 and the fifth light-emitting stage T5 is equal to the total lighting duration of the fourth light-emitting stage T4 and the sixth light-emitting stage T6; the total lighting duration of the fourth light-emitting stage T4 and the sixth light-emitting stage T6 is equal to the total lighting duration of the second light-emitting stage T2 and the seventh light-emitting stage T7.

[0082] In the above-mentioned embodiment in which the luminous duration of the second luminous stage T2 is shorter than that of the first luminous stage T1, the luminous duration of the second luminous stage T2 is reduced by at least 2H compared with the luminous duration of the first luminous stage T1, and the luminous duration of the second luminous stage T2 is reduced by at most 16H compared with the luminous duration of the first luminous stage T1, where H is the time required for the display panel to scan a pixel row, also called line frequency or horizontal cycle.

[0083] The time required for the display panel to scan a pixel row refers to the time required for the display panel to update the display content row by row, also known as the row scanning time. During this time, the data signals of all pixels in a pixel row will be updated. The same applies to the following embodiments and will not be repeated here.

[0084] In the above-mentioned embodiment in which the luminous duration of the second luminous stage T2 is less than the luminous duration of the fourth luminous stage, the luminous duration of the second luminous stage T2 is reduced by at least 2H compared with the luminous duration of the fourth luminous stage, and the luminous duration of the second luminous stage T2 is reduced by at most 16H compared with the luminous duration of the fourth luminous stage, where H is the time required for the display panel to scan a pixel row.

[0085] A schematic diagram of a pixel circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the corresponding working phase timing diagram is as follows Figure 2 As shown in the figure, the pixel circuit further includes an anode reset transistor M3, the control electrode of the anode reset transistor M3 and the control electrode of the data writing transistor M4 are connected to the same signal line, and jointly receive the third scanning signal Scan3, and the anode reset transistor M3 is used to provide an anode reset signal Vref to the light emitting element D in the data writing stage Tdata.

[0086] Figure 2 Only the non-luminous period TB and the luminous period TA in the working stage of the display panel are marked. Those skilled in the art can Figures 4 to 10 In the embodiment shown in FIG. 1 , the light-emitting stages in other embodiments such as the first light-emitting stage T1 and the second light-emitting stage T2 are substituted into the Figure 2 The embodiments shown and the complete timing diagram of the display panel working stages are all within the protection scope of the present disclosure.

[0087] like Figure 2 As shown, at least part of the non-light-emitting phase TB also includes a bias phase Tp, the bias phase Tp is located in the hold frame Keep and before the light-emitting phase TA, and the data writing phase Tdata is only located in the data writing frame Active.

[0088] The anode reset transistor M3 is further used to provide an anode reset signal Vref to the light emitting element D in the bias phase Tp, and the data writing transistor M4 is further used to provide a bias signal to the driving transistor M0 in the bias phase Tp.

[0089] Specifically, the display panel does not write data in the hold frame Keep, although the data writing transistor M4 is turned on in the bias phase Tp, at this time the data writing transistor M4 is only used to perform bias adjustment for the N2 node in the circuit.

[0090] like Figure 1 and Figure 2 As shown, the pixel circuit further includes a gate reset transistor M1, a threshold compensation transistor M2, and a light emitting control transistor (specifically including a first light emitting control transistor M5 and a second light emitting control transistor M6).

[0091] At least part of the non-light-emitting phase TB of the data writing frame Active also includes a gate reset phase Tref and a threshold compensation phase Tth. Specifically, Figure 2 As shown, the threshold compensation phase Tth coincides with the data writing phase Tdata.

[0092] The control electrode of the gate reset transistor M1 receives the first scan signal Scan1 and is used to provide a gate reset signal Vref to the driving transistor M0 in the gate reset phase Tref.

[0093] The control electrode of the threshold compensation transistor M2 receives the second scan signal Scan2 and is used to compensate the threshold voltage of the driving transistor M0 in the threshold compensation stage Tth.

[0094] The control electrode of the light emitting control transistor receives the emission signal Emit and is used to control the light emitting current to flow through the light emitting element D in the light emitting stage TA.

[0095] When implementing it, Figure 1 As shown, the pixel circuit further includes a storage capacitor Cst, and the storage capacitor Cst is electrically connected between the power signal line PVDD and the gate of the driving transistor M0.

[0096] The schematic diagram of another pixel circuit provided by the embodiment of the present disclosure is as follows: Fig.11 As shown, the corresponding driving timing is as follows Fig.12 The pixel circuit further includes an anode reset transistor M3 and a bias transistor M8, the control electrode of the bias transistor M8 and the control electrode of the anode reset transistor M3 are connected to the same signal line and receive the third scan signal Scan3 together.

[0097] At least part of the non-light-emitting phase TB also includes an anode reset and bias phase Tpf, the bias transistor M8 is used to provide a bias signal DVH to the driving transistor M0 in the anode reset and bias phase Tpf, and the anode reset transistor M3 is used to provide an anode reset signal Vref to the light-emitting element D in the anode reset and bias phase Tpf. Specifically, the anode reset and bias phase Tpf is located after the data writing phase Tdata.

[0098] Fig.12 Only the non-luminous period TB and the luminous period TA in the working stage of the display panel are marked. Those skilled in the art can Figures 4 to 10 In the embodiment shown in FIG. 1 , the light-emitting stages in other embodiments such as the first light-emitting stage T1 and the second light-emitting stage T2 are substituted into the Fig.12 The embodiments shown and the complete timing diagram of the display panel working stages are all within the protection scope of the present disclosure.

[0099] In some embodiments, Fig.12 As shown, both the data writing frame Active and the holding frame Keep include an anode reset and bias phase Tpf, and are used to reset the anode of the light-emitting element D and to bias the N2 node in the circuit in the holding frame Keep. The data writing phase Tdata is only in the data writing frame Active.

[0100] like Fig.11 and Fig.12 As shown, the pixel circuit further includes a gate reset transistor M1, a threshold compensation transistor M2, and a light emitting control transistor (specifically including a first light emitting control transistor M5 and a second light emitting control transistor M6).

[0101] At least part of the non-light-emitting phase TB of the data writing frame Active also includes a gate resetting phase Tref. The gate resetting phase Tref is located before the data writing phase Tdata.

[0102] The control electrode of the gate reset transistor M1 receives the first scan signal Scan1 and is used to provide a gate reset signal Vref to the driving transistor M0 in the gate reset phase Tref.

[0103] The control electrode of the threshold compensation transistor M2 receives the second scan signal Scan2 and is used to compensate the threshold voltage of the driving transistor M0 in the data writing phase Tdata.

[0104] The control electrode of the light emitting control transistor receives the emission signal Emit and is used to control the light emitting current to flow through the light emitting element D in the light emitting stage TA.

[0105] Based on the same inventive concept, corresponding to the display panel of any of the above embodiments, the present application also provides a display device, such as Fig.13 As shown, the display device 1 includes a display panel 10 in any one of the above embodiments.

[0106] The display panel in the display device provided by the embodiment of the present disclosure adjusts the brightness of the light-emitting element in the data writing frame Active by changing the light-emitting duration of the light-emitting element in the data writing frame Active; or, compensates for the brightness of the light-emitting element in the data writing frame Active by changing the light-emitting duration of the light-emitting element in the keep frame Keep located before and after the data writing frame Active, thereby compensating for the brightness fluctuation caused by the writing of the data signal into the pixel circuit and improving the display effect.

[0107] Specifically, the display device can be a 3C electronic product such as a computer and its peripherals, communications and consumer electronics, for example, a smart phone, a laptop computer, a tablet computer, a smart wearable device, a home appliance, a gaming device, etc. In addition, the display device can also be applied to other types of electronic devices such as automotive electronics.

[0108] The device of the above embodiment includes the corresponding display panel in any of the above embodiments, and has the beneficial effects of the corresponding embodiments, which will not be described in detail here.

[0109] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including a..." do not exclude the existence of other identical elements in the process, method, article or device including the above elements.

[0110] The above are only specific embodiments of the present disclosure, which enable those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described above, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: The working phases of the display panel include a plurality of non-luminous phases and a plurality of luminous phases; at least part of the non-luminous phases include data writing phases; The display panel includes a plurality of sub-pixels, each of which includes a pixel circuit and a light-emitting element electrically connected to the pixel circuit, and the light-emitting element emits light in the light-emitting phase; The pixel circuit comprises a driving transistor and a data writing transistor, wherein the data writing transistor is used to provide a data signal to the driving transistor during the data writing phase; In the display panel, the display process of one frame includes a plurality of sub-frames, and the plurality of sub-frames include a data writing frame and a holding frame; The light emitting stage includes a first light emitting stage, and the first light emitting stage is located in the data writing frame; The non-light emitting phase adjacent to the first light emitting phase and located before the first light emitting phase includes the data writing phase; The light-emitting stage further includes at least one second light-emitting stage, the second light-emitting stage is located in the data writing frame where the first light-emitting stage is located, and / or the second light-emitting stage is located in the holding frame adjacent to the data writing frame where the first light-emitting stage is located; The lighting duration of the first lighting stage is different from the lighting duration of the second lighting stage.

2. The display panel according to claim 1, characterized in that: The second light-emitting phase is a light-emitting phase that is closest to the first light-emitting phase in the subframe where the second light-emitting phase is located.

3. The display panel according to claim 2, characterized in that: The second light emitting stage and the first light emitting stage are adjacent light emitting stages.

4. The display panel according to claim 3, characterized in that: The second light emitting stage and the first light emitting stage are in the same data writing frame, and the second light emitting stage is after the first light emitting stage; The lighting duration of the second lighting stage is shorter than the lighting duration of the first lighting stage.

5. The display panel according to claim 3, characterized in that: The first light-emitting stage is located in the data writing frame of the i-th frame, and the second light-emitting stage is located in the holding frame of the i-1-th frame, where i≥2 and i is a positive integer; The lighting duration of the second lighting stage is shorter than the lighting duration of the first lighting stage.

6. The display panel according to claim 3, characterized in that: The first light-emitting stage is located in the data writing frame of the i-th frame, and the second light-emitting stage is located in the holding frame of the i-1-th frame, where i≥2 and i is a positive integer; The i-1th frame includes the Lth subframe, the Mth subframe and the Nth subframe, L, M, N are all positive integers, L≥1, M>1, N>1; the Lth subframe is located before the Mth subframe, the Mth subframe is located before the Nth subframe, the Lth subframe is a data writing frame or a holding frame, the Mth subframe and the Nth subframe are both holding frames; the second light-emitting stage is located in the Nth subframe; The total luminous duration of the Lth subframe is T L , the total luminous duration of the Mth subframe is T M , the total luminous duration of the Nth subframe is T N ; Among them, T L <T M And T M ≥T N .

7. The display panel according to claim 6, characterized in that: The total luminous duration of the data writing frame of the i-th frame is less than the total luminous duration of the N-th subframe; The lighting duration of the second lighting stage is longer than the lighting duration of the first lighting stage.

8. The display panel according to claim 6, characterized in that: One of the subframes includes one of the light-emitting phases, the Lth subframe includes a third light-emitting phase, and the Mth subframe includes a fourth light-emitting phase; The lighting duration of the second lighting stage is less than or equal to the lighting duration of the fourth lighting stage, and the lighting duration of the fourth lighting stage is greater than the lighting duration of the third lighting stage.

9. The display panel according to claim 6, characterized in that: One subframe includes a plurality of light-emitting phases; The Lth subframe includes a third light-emitting stage and a fifth light-emitting stage; the Mth subframe includes a fourth light-emitting stage and a sixth light-emitting stage; The Nth subframe also includes a seventh light emitting stage; The total lighting duration of the third lighting stage and the fifth lighting stage is shorter than the total lighting duration of the fourth lighting stage and the sixth lighting stage; The total lighting duration of the fourth lighting stage and the sixth lighting stage is greater than or equal to the total lighting duration of the second lighting stage and the seventh lighting stage.

10. The display panel according to claim 9, characterized in that: The fifth light-emitting stage is located after the third light-emitting stage, the sixth light-emitting stage is located after the fourth light-emitting stage, and the second light-emitting stage is located after the seventh light-emitting stage; The lighting duration of the fifth lighting stage is greater than or equal to that of the third lighting stage, the lighting duration of the sixth lighting stage is greater than or equal to that of the fourth lighting stage, and the lighting duration of the second lighting stage is less than that of the seventh lighting stage.

11. The display panel according to claim 2, characterized in that: The second light emitting stage is located in the holding frame adjacent to the data writing frame where the first light emitting stage is located, and the second light emitting stage is located after the first light emitting stage; The lighting duration of the second lighting stage is shorter than the lighting duration of the first lighting stage.

12. The display panel according to claim 11, characterized in that: One holding frame includes at least two light-emitting stages, and the second light-emitting stage is the first light-emitting stage in the holding frame.

13. The display panel according to claim 4, 5 or 11, characterized in that: The luminous duration of the second luminous stage is reduced by at least 2H compared with the luminous duration of the first luminous stage, and the luminous duration of the second luminous stage is reduced by at most 16H compared with the luminous duration of the first luminous stage, where H is the time required for the display panel to scan a pixel row.

14. The display panel according to claim 8, characterized in that: The luminous duration of the second luminous stage is reduced by at least 2H compared with the luminous duration of the fourth luminous stage, and the luminous duration of the second luminous stage is reduced by at most 16H compared with the luminous duration of the fourth luminous stage, where H is the time required for the display panel to scan a pixel row.

15. The display panel according to claim 1, characterized in that: The pixel circuit further includes a light emitting control transistor, which is electrically connected to the driving transistor and the light emitting element and is used to control the driving current to flow through the light emitting element during the light emitting stage; The light-emitting control transistor is electrically connected to a light-emitting control signal line, and a light-emitting control signal is transmitted on the light-emitting control signal line; and a changing frequency of the light-emitting control signal is greater than a basic operating frequency of the display panel.

16. The display panel according to claim 1, characterized in that: The pixel circuit further includes an anode reset transistor, a control electrode of the anode reset transistor and a control electrode of the data writing transistor are connected to the same signal line, and the anode reset transistor is used to provide an anode reset signal to the light emitting element during the data writing stage.

17. The display panel according to claim 16, characterized in that: At least part of the non-light-emitting phase further includes a bias phase, and the holding frame includes the bias phase; The anode reset transistor is further used for providing the anode reset signal to the light emitting element during the bias phase, and the data writing transistor is further used for providing a bias signal to the driving transistor during the bias phase.

18. The display panel according to claim 16, characterized in that: The pixel circuit also includes a gate reset transistor, a threshold compensation transistor and a light emission control transistor; At least part of the non-light-emitting phase of the data writing frame further includes a gate resetting phase and a threshold compensation phase; The gate reset transistor is used to provide a gate reset signal to the driving transistor during the gate reset phase; The threshold compensation transistor is used to compensate the threshold voltage of the driving transistor in the threshold compensation stage; The light emission control transistor is used to control the light emission current to flow through the light emitting element during the light emission phase.

19. The display panel according to claim 1, characterized in that: The pixel circuit further includes an anode reset transistor and a bias transistor, wherein the control electrode of the bias transistor and the control electrode of the anode reset transistor are connected to the same signal line; At least part of the non-luminous phase also includes an anode reset and bias phase, the bias transistor is used to provide a bias signal to the driving transistor in the anode reset and bias phase, and the anode reset transistor is used to provide an anode reset signal to the light-emitting element in the anode reset and bias phase.

20. The display panel according to claim 19, characterized in that: The data writing frame and the holding frame both include the anode resetting and biasing phase.

21. The display panel according to claim 19, characterized in that: The pixel circuit also includes a gate reset transistor, a threshold compensation transistor and a light emission control transistor; At least part of the non-light-emitting phase of the data writing frame also includes a gate reset phase; The gate reset transistor is used to provide a gate reset signal to the driving transistor during the gate reset phase; The threshold compensation transistor is used to compensate the threshold voltage of the driving transistor during the data writing phase; The light emission control transistor is used to control the light emission current to flow through the light emitting element during the light emission phase.

22. A display device, characterized in that: A display panel comprising any one of claims 1 to 21.

Images