Sensitive amplifier and memory

Abstract

The embodiment of the invention provides a sensitive amplifier and a memory, and the sensitive amplifier comprises a cross coupling circuit which comprises a first node and a second node and is configured to perform signal amplification processing on the first node and the second node when the sensitive amplifier is in an amplification stage; the first node is connected with a bit line, and the second node is connected with a complementary bit line; the amplification control circuit is respectively connected with the first node and the second node and is configured to control the cross coupling circuit to perform signal amplification processing when the sensitive amplifier is in an amplification stage; when the sensitive amplifier is in the offset elimination stage, the cross coupling circuit is controlled not to carry out signal amplification processing; the offset elimination circuit is respectively connected with the first node and the second node and is configured to perform offset elimination processing on the sensitive amplifier when the sensitive amplifier is in an offset elimination stage; wherein at least a transistor included in the amplification control circuit is a thin oxygen device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a sensitive amplifier and a memory. Background Art

[0002] The sense amplifier (SA) is an important component of semiconductor memory. Its main function is to amplify the small signal on the bit line to perform read or write operations.

[0003] However, in the related art, due to the threshold loss problem when the transistor transmits a high level, the read voltage and write voltage of the sense amplifier may not reach the power supply voltage during the read and write operations. Furthermore, in order to reduce the threshold loss of the transistor, the gate voltage of the transistor needs to be increased, so the transistor is a thick oxide device, which increases the area of ​​the sense amplifier. Summary of the invention

[0004] Embodiments of the present disclosure provide a sense amplifier and a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides a sense amplifier, the sense amplifier comprising:

[0006] A cross-coupling circuit, comprising a first node and a second node, configured to perform signal amplification processing on the first node and the second node when the sense amplifier is in an amplification phase; the first node is connected to a bit line, and the second node is connected to a complementary bit line;

[0007] an amplification control circuit, connected to the first node and the second node respectively, and configured to control the cross-coupling circuit to perform signal amplification processing when the sense amplifier is in the amplification stage; and to control the cross-coupling circuit not to perform signal amplification processing when the sense amplifier is in the offset cancellation stage;

[0008] an offset cancellation circuit, connected to the first node and the second node respectively, and configured to perform an offset cancellation process on the sense amplifier when the sense amplifier is in the offset cancellation phase;

[0009] Wherein, at least the transistor included in the amplification control circuit is a thin-oxide device.

[0010] In some embodiments, the cross-coupled circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor;

[0011] The first end of the first transistor and the first end of the second transistor both receive a first power supply signal, and the first end of the third transistor and the first end of the fourth transistor both receive a second power supply signal; the second end of the first transistor, the control end of the second transistor and the control end of the fourth transistor are all connected to the first node, and the control end of the first transistor, the second end of the second transistor and the control end of the third transistor are all connected to the second node; the second end of the third transistor is connected to the third node, and the second end of the fourth transistor is connected to the fourth node; the control end of the third transistor is connected to the complementary bit line, and the control end of the fourth transistor is connected to the bit line.

[0012] In some embodiments, the amplification control circuit includes a fifth transistor and a sixth transistor;

[0013] The first end of the fifth transistor is connected to the third node, and the second end of the fifth transistor is connected to the first node; the first end of the sixth transistor is connected to the fourth node, and the second end of the sixth transistor is connected to the second node; the control end of the fifth transistor and the control end of the sixth transistor both receive an amplified control signal.

[0014] In some embodiments, the offset cancellation circuit includes a seventh transistor and an eighth transistor;

[0015] The first end of the seventh transistor is connected to the third node, and the second end of the seventh transistor is connected to the second node; the first end of the eighth transistor is connected to the fourth node, and the second end of the eighth transistor is connected to the first node; the control end of the seventh transistor and the control end of the eighth transistor both receive a debiasing control signal.

[0016] In some embodiments, the sense amplifier further comprises a pre-charge circuit;

[0017] The pre-charging circuit is connected to the third node and the fourth node respectively, and is configured to perform pre-charging processing on the sense amplifier based on a pre-charging source signal when the sense amplifier is in a pre-charging stage.

[0018] In some embodiments, the pre-charge circuit includes a first pre-charge transistor and a second pre-charge transistor;

[0019] The first end of the first pre-charge transistor and the first end of the second pre-charge transistor both receive the pre-charge source signal, the second end of the first pre-charge transistor is connected to the third node, the second end of the second pre-charge transistor is connected to the fourth node, and the control end of the first pre-charge transistor and the control end of the second pre-charge transistor both receive the pre-charge control signal.

[0020] In some embodiments, the pre-charging circuit includes a third pre-charging transistor;

[0021] The first end of the third pre-charge transistor receives the pre-charge source signal, the control end of the third pre-charge transistor receives a pre-charge control signal, and the second end of the third pre-charge transistor is connected to the third node or the fourth node.

[0022] In some embodiments, the sense amplifier further comprises a signal transmission circuit;

[0023] The signal transmission circuit is connected to the first node and the second node respectively, and is configured to transmit a signal between the first node and a target transmission node, and transmit a signal between the second node and a target complementary transmission node when the sensitive amplifier is in a signal transmission phase.

[0024] In some embodiments, the signal transmission circuit includes a first transmission transistor and a second transmission transistor;

[0025] The control end of the first transmission transistor and the control end of the second transmission transistor both receive transmission control signals, the first transmission transistor is connected in series between the first node and the target transmission node, and the second transmission transistor is connected in series between the second node and the target complementary transmission node.

[0026] In a second aspect, an embodiment of the present disclosure provides a memory, wherein the memory includes a sensitive amplifier as described in any one of the first aspects.

[0027] The disclosed embodiment provides a sense amplifier and a memory, the sense amplifier comprising: a cross-coupling circuit, comprising a first node and a second node, configured to perform signal amplification processing on the first node and the second node when the sense amplifier is in the amplification stage; the first node is connected to the bit line, and the second node is connected to the complementary bit line; an amplification control circuit, connected to the first node and the second node, respectively, configured to control the cross-coupling circuit to perform signal amplification processing when the sense amplifier is in the amplification stage; and when the sense amplifier is in the offset elimination stage, control the cross-coupling circuit not to perform signal amplification processing; an offset elimination circuit, connected to the first node and the second node, respectively, configured to perform offset elimination processing on the sense amplifier when the sense amplifier is in the offset elimination stage; wherein at least the transistor included in the amplification control circuit is a thin oxide device. In this way, by connecting the first node to the bit line and the second node to the complementary bit line, the transistor in the amplification control circuit can be avoided between the first node and the bit line and between the second node and the complementary bit line, so that the threshold loss problem when transmitting a high level can be avoided in the sense amplifier, and then the transistor in the sense amplifier can be a thin oxide device, saving area. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of the structure of a sensitive amplifier Figure 1 ;

[0029] Figure 2 A timing diagram of a write operation of a sensitive amplifier;

[0030] Figure 3 A schematic diagram of the structure of a sensitive amplifier Figure 2 ;

[0031] Figure 4 A schematic diagram of the structure of a sensitive amplifier Figure 3 ;

[0032] Figure 5 A schematic diagram of a read operation timing of a sensitive amplifier;

[0033] Figure 6 A schematic diagram of the structure of a sensitive amplifier Figure 4 ;

[0034] Figure 7 A schematic diagram of the structure of a sensitive amplifier Figure 5 ;

[0035] Figure 8 A schematic diagram of the structure of a sensitive amplifier provided in an embodiment of the present disclosure Figure 1 ;

[0036] Fig. 9 A schematic diagram of the structure of a sensitive amplifier provided in an embodiment of the present disclosure Figure 2 ;

[0037] Fig.10 A schematic diagram of the structure of a sensitive amplifier provided in an embodiment of the present disclosure Figure 3 ;

[0038] Fig.11 A schematic diagram of the structure of a sensitive amplifier provided in an embodiment of the present disclosure Figure 4 ;

[0039] Fig.12 A schematic diagram of the structure of a sensitive amplifier provided in an embodiment of the present disclosure Figure 5 ;

[0040] Fig.13 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant applications, rather than to limit the present disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant applications are shown in the drawings.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0043] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0044] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0045] There is a sense amplifier in the dynamic random access memory (DRAM) for signal amplification. However, in the related art, the read voltage and write voltage of the sense amplifier are limited by the N-type metal oxide semiconductor field effect transistor (NMOS) to transmit a high level signal ("1"), and thus cannot reach the power supply voltage VDD during fast reading and writing.

[0046] See also Figure 1 , which shows a schematic diagram of the structure of a sensitive amplifier Figure 1 .like Figure 1As shown, the sensitive amplifier 10 includes an amplifier circuit 11, an offset elimination circuit 12, a pre-charging circuit 13 and a signal transmission circuit 14 (the reference numerals 11, 12, 13, 14 are not shown in the figure). Among them, the amplifier circuit 11 includes a first transistor 111, a second transistor 112, a third transistor 113, a fourth transistor 114, a fifth transistor 115 and a sixth transistor 116, the first transistor 111, the second transistor 112, the third transistor 113 and the fourth transistor 114 form a cross-coupling circuit, and the fifth transistor 115 and the sixth transistor 116 form an amplifier control circuit; the offset elimination circuit 12 includes a seventh transistor 121 and an eighth transistor 122; the pre-charging circuit 13 includes a first pre-charging transistor 131 and a second pre-charging transistor 132; the signal transmission circuit 14 includes a first transmission transistor 141 and a second transmission transistor 142, and the specific connection relationship is as shown in FIG. Figure 1 As shown. Figure 1 In the figure, the first transistor 111 and the second transistor 112 are P-type metal oxide semiconductor field effect transistors (Positive channel Metal Oxide Semiconductor field effect transistor, PMOS tube), and the third transistor 113, the fourth transistor 114, the fifth transistor 115, the sixth transistor 116, the seventh transistor 121, the eighth transistor 122, the first pre-charge transistor 131, the second pre-charge transistor 132, the first transfer transistor 141 and the second transfer transistor 142 are NMOS tubes.

[0047] like Figure 1 As shown, blsb represents an amplification control signal, bleq represents a precharge control signal, vblp represents a precharge power signal, blsa represents a debiasing control signal, Isae represents a transmission control signal, Idl represents a target transmission node, Idl_n represents a target complementary transmission node, bl represents a bit line, bl_n represents a complementary bit line, sa1 represents a first coupling node, and sa2 represents a second coupling node. Here, the voltage value of the precharge power signal vblp is the precharge voltage; the signal to be processed is written from the target transmission node Idl and the target complementary transmission node Idl_n, or the amplified signal is transmitted to the target transmission node Idl and the target complementary transmission node Idl_n. In addition, SP1 and SN represent power signals, respectively, and the power signal SP1 and the power signal SN are connected to an external power control switch.

[0048] It should be noted that the gates of the fifth transistor 115 and the sixth transistor 116 receive the amplification control signal blsb. When the fifth transistor 115 and the sixth transistor 116 are turned on (or called turned on), the fifth transistor 115 and the sixth transistor 116 can be used as transmission gates. In this way, the cross-coupling circuit (the first transistor 111, the second transistor 112, the third transistor 113 and the fourth transistor 114), the fifth transistor 115 and the sixth transistor 116 form an inverter latch structure connected head to tail for amplifying the signal.

[0049] based on Figure 1 The sense amplifier 10 shown is shown in FIG. Figure 2 , which shows a timing diagram of a write operation of a sense amplifier. Figure 2 As shown, the S1 stage is the stage of writing a signal from the sense amplifier LSA (Write from LSA), and the S2 stage is the latching stage. The sense amplifier LSA refers to the subsequent amplifier circuit of the sense amplifier 10.

[0050] based on Figure 2 , taking the write operation (i.e., write operation) as an example, the states of each transistor in the S1 phase are as follows Figure 3 As shown, the states of each transistor in the S2 phase are as follows Figure 4 It should be noted that Figure 3 and Figure 4 In the figure, the paths formed after each transistor is turned on are indicated by solid lines, and the open circuits after each transistor is turned off (or closed) are indicated by dotted lines.

[0051] like Figure 3 As shown, the seventh transistor 121, the eighth transistor 122, the first pre-charge transistor 131 and the second pre-charge transistor 132 are in the off state, the fifth transistor 115, the sixth transistor 116, the first transmission transistor 141 and the second transmission transistor 142 are in the on state, the cross-coupling circuit is in the working state, and the signal to be processed is written through the first transmission transistor 141 and the second transmission transistor 142. Figure 4 As shown, the seventh transistor 121, the eighth transistor 122, the first pre-charge transistor 131, the second pre-charge transistor 132, the first transmission transistor 141 and the second transmission transistor 142 are in the off state, the fifth transistor 115 and the sixth transistor 116 are in the on state, and the cross-coupling circuit is in the working state.

[0052] It should be noted that, because the cross-coupling circuit is in operation, the first transistor 111 , the second transistor 112 , the third transistor 113 and the fourth transistor 114 included in the cross-coupling circuit are indicated by solid lines, but the four transistors are not turned on at the same time.

[0053] It should be noted that in the S1 phase of the write operation, V Idl =VDD, V bl =V Idl -V ds_NM1 ; In the S2 phase of the write operation, V sa1 =VDD, V bl =V sa1 -V ds_NM2 Among them, V Idl represents the voltage at the target transmission node Idl, VDD represents the power supply voltage, V bl represents the voltage of the bit line bl (ie, the gate of the fourth transistor 114), V ds_NM1 represents the source-drain voltage of the first transmission transistor 141, V sa1 represents the voltage at the first coupling node, V ds_NM2 represents the source-drain voltage of the fifth transistor 115. Therefore, the write voltage is limited by the NMOS tube transmitting "1" and cannot reach the VDD level during fast writing.

[0054] based on Figure 1 The sense amplifier 10 shown is shown in FIG. Figure 5 , which shows a timing diagram of a read operation of a sense amplifier. Figure 5 As shown, the S1 stage is the pre-charge stage (Pre-Charge, EQ), the S2 stage is the offset cancellation stage (Offset Cancellation, OC), the S3 stage is the charge sharing stage (Charge Sharing), the S4 stage is the amplification stage (Sensing), and the S5 stage is the stage of reading the amplified signal to the sensitive amplifier LSA (Send to LSA).

[0055] based on Figure 5 Taking the read operation (i.e., read-out operation) as an example, the states of the various transistors in the S4 stage are as follows: Figure 6 As shown, the states of each transistor in the S5 phase are as follows Figure 7 Similarly, Figure 6 and Figure 7 In the figure, the paths formed when each transistor is turned on are indicated by solid lines, and the disconnections formed when each transistor is turned off are indicated by dotted lines.

[0056] like Figure 6 As shown, the seventh transistor 121, the eighth transistor 122, the first pre-charge transistor 131, the second pre-charge transistor 132, the first transmission transistor 141 and the second transmission transistor 142 are in the off state, the fifth transistor 115 and the sixth transistor 116 are in the on state, and the cross-coupling circuit is in the working state. Figure 7As shown, the seventh transistor 121, the eighth transistor 122, the first pre-charge transistor 131 and the second pre-charge transistor 132 are in the off state, the fifth transistor 115, the sixth transistor 116, the first transfer transistor 141 and the second transfer transistor 142 are in the on state, and the cross-coupling circuit is in the working state; the amplified signal is sent to the sensitive amplifier LSA through the first transfer transistor 141 and the second transfer transistor 142.

[0057] It should be noted that in the S4 phase of the read operation, V sa1 =VDD, V bl =V sa1 -V ds_NM2 ; In the S5 phase of the read operation, V sa1 =VDD, V bl =V sa1 -V ds_NM2 Therefore, the read voltage is limited by the NMOS tube transmitting "1" and cannot reach the VDD level during fast readout.

[0058] It should also be noted that in the sense amplifier 10, the PMOS tube (the first transistor 111 and the second transistor 112) is connected to the bit line bl and the complementary bit line bl_n through the transmission gate (the fifth transistor 115 and the sixth transistor 116), and there is a threshold loss problem of voltage transmission (about the value of the source-drain voltage of the fifth transistor 115 or the source-drain voltage of the sixth transistor 116 is lost). The voltage value of the amplification control signal blsb received by the control end of the fifth transistor 115 and the sixth transistor 116 needs to be larger (for example, greater than 1.5 volts (Volt, V)) to reduce the threshold loss. Specifically, the fifth transistor 115 and the sixth transistor 116 are NMOS tubes. When transmitting a high-level signal ("1"), the source voltage is high and the gate-source voltage Vgs is small. The current of the NMOS tube is small. Because the time of the amplification stage is limited, the gate voltage of the NMOS tube needs to be higher to make the gate-source voltage Vgs large and improve the transmission speed. Therefore, the voltage value of the amplification control signal blsb needs to be larger, so that the fifth transistor 115 and the sixth transistor 116 need to be thick oxide devices.

[0059] In summary, in the related art, for the sense amplifier 10, both the write voltage and the read voltage are limited by the NMOS tube transmitting "1", and there is a threshold loss problem when the NMOS tube transmits "1", so that the VDD level cannot be reached during fast reading and writing. In addition, the voltage value of the amplification control signal blsb received by the gate of the fifth transistor 115 and the sixth transistor 116 is greater than 1.5V, and the fifth transistor 115 and the sixth transistor 116 are thick oxide devices, which increases the area of ​​the sense amplifier 10.

[0060] Based on this, the embodiment of the present disclosure provides a sense amplifier, a cross-coupling circuit, including a first node and a second node, configured to perform signal amplification processing on the first node and the second node when the sense amplifier is in the amplification stage; the first node is connected to the bit line, and the second node is connected to the complementary bit line; the amplification control circuit is connected to the first node and the second node respectively, configured to control the cross-coupling circuit to perform signal amplification processing when the sense amplifier is in the amplification stage; and when the sense amplifier is in the offset elimination stage, the cross-coupling circuit is controlled not to perform signal amplification processing; the offset elimination circuit is connected to the first node and the second node respectively, configured to perform offset elimination processing on the sense amplifier when the sense amplifier is in the offset elimination stage; wherein at least the transistor included in the amplification control circuit is a thin oxide device. In this way, by connecting the first node to the bit line and the second node to the complementary bit line, the transistor in the amplification control circuit can be avoided between the first node and the bit line and between the second node and the complementary bit line, so that the threshold loss problem when the sense amplifier is transmitted at a high level can be avoided, and then the transistor in the sense amplifier can be a thin oxide device, saving area.

[0061] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0062] In one embodiment of the present disclosure, see Figure 8 , which shows a schematic diagram of the composition structure of a sensitive amplifier provided by an embodiment of the present disclosure Figure 1 .like Figure 8 As shown, the sense amplifier 20 comprises:

[0063] The cross-coupling circuit 21 includes a first node and a second node, and is configured to perform signal amplification processing on the first node and the second node when the sense amplifier 20 is in the amplification stage; the first node is connected to the bit line, and the second node is connected to the complementary bit line;

[0064] an amplification control circuit 22, connected to the first node and the second node respectively, and configured to control the cross-coupling circuit 21 to perform signal amplification processing when the sense amplifier 20 is in the amplification stage; and to control the cross-coupling circuit 21 not to perform signal amplification processing when the sense amplifier 20 is in the offset cancellation stage;

[0065] An offset cancellation circuit 23 is connected to the first node and the second node respectively, and is configured to perform an offset cancellation process on the sense amplifier 20 when the sense amplifier 20 is in an offset cancellation phase;

[0066] Among them, at least the transistors included in the amplification control circuit 22 are thin-oxide devices.

[0067] In the embodiment of the present disclosure, the sense amplifier 20 can be applied in various signal amplification scenarios. Exemplarily, the sense amplifier 20 is a sense amplifier structure used for a dynamic random access memory.

[0068] It should be noted that the cross-coupling circuit 21 and the amplification control circuit 22 together constitute an amplification circuit. When the sense amplifier 20 is in the amplification stage, the cross-coupling circuit 21 performs signal amplification processing on the first node and the second node. In addition, when the sense amplifier 20 is in the offset cancellation stage, the sense amplifier 20 is not in the amplification state, and the cross-coupling circuit 21 does not perform signal amplification processing on the first node and the second node.

[0069] It should also be noted that transistors can be divided into thick oxide devices and thin oxide devices according to the thickness of the gate oxide layer. Among them, the gate oxide layer thickness of the thick oxide device is relatively large, which can withstand higher voltages and larger currents, but it will increase the area of ​​the transistor; the gate oxide layer thickness of the thin oxide device is relatively small, which can save the area of ​​the transistor. In the embodiment of the present disclosure, the first node is directly connected to the bit line, and the second node is directly connected to the complementary bit line. The transistors in the amplification control circuit 22 are not passed between the first node and the bit line, and between the second node and the complementary bit line. Therefore, the transistors included in the amplification control circuit 22 can be thin oxide devices, thereby saving the area of ​​the sensitive amplifier 20.

[0070] Specifically, in some embodiments, Fig. 9 As shown, the cross-coupling circuit 21 may include a first transistor 211, a second transistor 212, a third transistor 213 and a fourth transistor 214;

[0071] The first end of the first transistor 211 and the first end of the second transistor 212 both receive a first power supply signal, and the first end of the third transistor 213 and the first end of the fourth transistor 214 both receive a second power supply signal; the second end of the first transistor 211, the control end of the second transistor 212 and the control end of the fourth transistor 214 are all connected to the first node, and the control end of the first transistor 211, the second end of the second transistor 212 and the control end of the third transistor 213 are all connected to the second node; the second end of the third transistor 213 is connected to the third node, and the second end of the fourth transistor 214 is connected to the fourth node; the control end of the third transistor 213 is connected to the complementary bit line, and the control end of the fourth transistor 214 is connected to the bit line.

[0072] Here, the first node is represented by A, the second node is represented by B, the third node is represented by C, the fourth node is represented by D, the first power signal is represented by SP1, the second power signal is represented by SN, the bit line is represented by bl, and the complementary bit line is represented by bl_n. In addition, the first power signal SP1 and the second power signal SN are connected to an external power control switch.

[0073] In some embodiments, the first transistor 211 and the second transistor 212 are PMOS transistors, and the third transistor 213 and the fourth transistor 214 are NMOS transistors.

[0074] In this way, the first end of the first transistor 211 is a source electrode, receiving a first power supply signal; the second end of the first transistor 211 is a drain electrode, connected to the first node; the control end of the first transistor 211 is a gate electrode, connected to the second node. The first end of the second transistor 212 is a source electrode, receiving a first power supply signal; the second end of the second transistor 212 is a drain electrode, connected to the second node; the control end of the second transistor 212 is a gate electrode, connected to the first node. The first end of the third transistor 213 is a source electrode, receiving a second power supply signal; the second end of the third transistor 213 is a drain electrode, connected to the third node; the control end of the third transistor 213 is a gate electrode, connected to the complementary bit line and the second node. The first end of the fourth transistor 214 is a source electrode, receiving a second power supply signal; the second end of the fourth transistor 214 is a drain electrode, connected to the fourth node; the control end of the fourth transistor 214 is a gate electrode, connected to the bit line and the first node.

[0075] In some embodiments, Fig. 9 As shown, the amplification control circuit 22 may include a fifth transistor 221 and a sixth transistor 222;

[0076] The first end of the fifth transistor 221 is connected to the third node, and the second end of the fifth transistor 221 is connected to the first node; the first end of the sixth transistor 222 is connected to the fourth node, and the second end of the sixth transistor 222 is connected to the second node; the control end of the fifth transistor 221 and the control end of the sixth transistor 222 both receive the amplified control signal.

[0077] Here, the amplification control signal is represented by blsb.

[0078] It should be noted that when the fifth transistor 221 and the sixth transistor 222 are turned on, the fifth transistor 221 and the sixth transistor 222 can be used as transmission gates, so that the cross-coupling circuit 21 and the amplification control circuit 22 form a head-to-tail inverter latch structure for amplifying signals.

[0079] In some embodiments, the fifth transistor 221 and the sixth transistor 222 are NMOS transistors.

[0080] Thus, the first terminal of the fifth transistor 221 is a source connected to the third node; the second terminal of the fifth transistor 221 is a drain connected to the first node; the control terminal of the fifth transistor 221 is a gate, receiving the amplified control signal. The first terminal of the sixth transistor 222 is a source connected to the fourth node; the second terminal of the sixth transistor 222 is a drain connected to the second node; the control terminal of the sixth transistor 222 is a gate, receiving the amplified control signal.

[0081] It should be noted that in the relevant technology Figure 1 In the sense amplifier 10 shown, the first transistor 111 and the second transistor 112 need to be connected to the bit line and the complementary bit line through the fifth transistor 115 and the sixth transistor 116; specifically, the second end of the first transistor 111 and the control end of the second transistor 112 are connected to the bit line through the fifth transistor 115, and the control end of the first transistor 111 and the second end of the second transistor 112 are connected to the complementary bit line through the sixth transistor 116. However, the PMOS transistor (the first transistor 211 and the second transistor 212) in the sense amplifier 20 of the embodiment of the present disclosure is directly connected to the bit line and the complementary bit line; specifically, the second end of the first transistor 211 and the control end of the second transistor 212 are directly connected to the bit line, and the control end of the first transistor 211 and the second end of the second transistor 212 are directly connected to the complementary bit line. In this way, the sensitive amplifier 20 can avoid the threshold loss problem of transmitting a high-level signal ("1"); and because the threshold loss does not exist, the voltage value of the amplification control signal blsb received by the control end of the fifth transistor 221 and the sixth transistor 222 can be lower, so that the fifth transistor 221 and the sixth transistor 222 can use thin-film devices to save area.

[0082] In some embodiments, Fig. 9 As shown, the offset elimination circuit 23 may include a seventh transistor 231 and an eighth transistor 232;

[0083] The first end of the seventh transistor 231 is connected to the third node, and the second end of the seventh transistor 231 is connected to the second node; the first end of the eighth transistor 232 is connected to the fourth node, and the second end of the eighth transistor 232 is connected to the first node; the control end of the seventh transistor 231 and the control end of the eighth transistor 232 both receive a debiasing control signal.

[0084] Here, the depolarization control signal is represented by blsa.

[0085] It should be noted that when the sense amplifier 20 is in the offset elimination stage, the cross-coupling circuit 21 needs to be in a working state, the fifth transistor 221 and the sixth transistor 222 are turned off to ensure that the sense amplifier 20 is not in an amplification state, and the seventh transistor 231 and the eighth transistor 232 are turned on.

[0086] In some embodiments, the seventh transistor 231 and the eighth transistor 232 are NMOS transistors.

[0087] Thus, the first end of the seventh transistor 231 is a source connected to the third node; the second end of the seventh transistor 231 is a drain connected to the second node; the control end of the seventh transistor 231 is a gate, receiving a depolarization control signal. The first end of the eighth transistor 232 is a source connected to the fourth node; the second end of the eighth transistor 232 is a drain connected to the first node; the control end of the eighth transistor 232 is a gate, receiving a depolarization control signal.

[0088] In some embodiments, Fig. 9 As shown, the sense amplifier 20 may further include a pre-charging circuit 24 (the reference numeral is not shown in the figure);

[0089] The pre-charging circuit 24 is connected to the third node and the fourth node respectively, and is configured to perform a pre-charging process on the sense amplifier 20 based on the pre-charging source signal when the sense amplifier 20 is in the pre-charging stage.

[0090] Here, the precharge power supply signal is represented by vblp.

[0091] It should be noted that the voltage value of the pre-charge power signal is the pre-charge voltage. In the pre-charge stage, the pre-charge circuit 24 can charge the sense amplifier 20 to the pre-charge voltage. The voltage value of the pre-charge voltage can be VDD / 2 (i.e., half of the power supply voltage VDD) or other values, which are not specifically limited.

[0092] In some embodiments, Fig. 9 As shown, the pre-charging circuit 24 may include a first pre-charging transistor 241 and a second pre-charging transistor 242;

[0093] The first end of the first pre-charge transistor 241 and the first end of the second pre-charge transistor 242 both receive a pre-charge source signal, the second end of the first pre-charge transistor 241 is connected to the third node, the second end of the second pre-charge transistor 242 is connected to the fourth node, and the control end of the first pre-charge transistor 241 and the control end of the second pre-charge transistor 242 both receive a pre-charge control signal.

[0094] Here, the precharge control signal is represented by bleq.

[0095] In some embodiments, the first pre-charge transistor 241 and the second pre-charge transistor 242 are NMOS transistors.

[0096] In this way, the first end of the first pre-charge transistor 241 is a source electrode, receiving a pre-charge source signal; the second end of the first pre-charge transistor 241 is a drain electrode, connected to the third node; the control end of the first pre-charge transistor 241 is a gate electrode, receiving a pre-charge control signal. The first end of the second pre-charge transistor 242 is a source electrode, receiving a pre-charge source signal; the second end of the second pre-charge transistor 242 is a drain electrode, connected to the fourth node; the control end of the second pre-charge transistor 242 is a gate electrode, receiving a pre-charge control signal.

[0097] It should be noted that the pre-charging circuit 24 may include two pre-charging transistors or only one pre-charging transistor.

[0098] In some embodiments, Fig.10 As shown, the pre-charging circuit 24 may only include the third pre-charging transistor 243;

[0099] A first end of the third pre-charge transistor 243 receives a pre-charge source signal, a control end of the third pre-charge transistor 243 receives a pre-charge control signal, and a second end of the third pre-charge transistor 243 is connected to the third node or the fourth node.

[0100] For example, Fig.10 As shown, the second end of the third pre-charge transistor 243 is connected to the third node, but this is not specifically limited.

[0101] In some embodiments, Fig. 9 or Fig.10 As shown, the sense amplifier 20 may further include a signal transmission circuit 25 (the reference numeral is not shown in the figure);

[0102] The signal transmission circuit 25 is connected to the first node and the second node respectively, and is configured to transmit a signal between the first node and a target transmission node, and between the second node and a target complementary transmission node when the sense amplifier 20 is in a signal transmission phase.

[0103] Here, the target transmission node is represented by Id1, and the target complementary transmission node is represented by Idl_n.

[0104] It should be noted that when performing a write operation, the signal to be processed is written from the target transmission node and the target complementary transmission node, and amplified; when performing a read operation, the amplified signal is transmitted to the target transmission node and the target complementary transmission node.

[0105] In some embodiments, Fig. 9 or Fig.10 As shown, the signal transmission circuit 25 may include a first transmission transistor 251 and a second transmission transistor 252;

[0106] The control end of the first transmission transistor 251 and the control end of the second transmission transistor 252 both receive a transmission control signal. The first transmission transistor 251 is connected in series between the first node and the target transmission node, and the second transmission transistor 252 is connected in series between the second node and the target complementary transmission node.

[0107] Here, the transmission control signal is represented by Isae.

[0108] It should be noted that when performing a write operation, the signal to be processed is received by the first transfer transistor 251 and the second transfer transistor 252, and amplified; when performing a read operation, the signal to be processed on the bit line and the complementary bit line is amplified and sent to the target transmission node and the target complementary transmission node respectively through the first transfer transistor 251 and the second transfer transistor 252, and then sent to the next stage amplifier circuit (for example, the sensitive amplifier LSA).

[0109] In some embodiments, the first transfer transistor 251 and the second transfer transistor 252 are NMOS transistors.

[0110] In this way, the first end of the first transfer transistor 251 is the source, connected to the target transfer node; the second end of the first transfer transistor 251 is the drain, connected to the first node; the control end of the first transfer transistor 251 is the gate, receiving the transfer control signal. The first end of the second transfer transistor 252 is the source, connected to the target complementary transfer node; the second end of the second transfer transistor 252 is the drain, connected to the second node; the control end of the second transfer transistor 252 is the gate, receiving the transfer control signal.

[0111] It should be noted that Fig. 9 The sense amplifier 20 shown is a symmetrical structure. Fig.10 The sense amplifier 20 shown is of an asymmetric structure. That is, in the sense amplifier 20 of the asymmetric structure, the threshold loss problem when transmitting a high level can also be avoided, thereby saving area.

[0112] Further, Table 1 shows the voltage loss values ​​of transistors in the related art and the embodiments of the present disclosure using different devices (thin oxygen devices or thick oxygen devices).

[0113] It should be noted that, as shown in Table 1, the voltage value of the debiasing control signal blsa, the voltage value of the pre-charge control signal bleq, the voltage value of the amplification control signal blsb, the voltage value of the power supply voltage VDD, the voltage value of the first power supply signal SP1, and the voltage value of the transmission control signal Isae are all in units of V; the voltage loss value specifically refers to the voltage loss value between the power supply voltage VDD and the bit line, and the unit is millivolt (mV).

[0114] It should also be noted that "SSLT" stands for SS corner Low Temperature. Because the threshold voltage of the device increases at low temperatures, and the threshold voltage of the device at the SS corner is also larger than the threshold voltage of the device at other corners, the threshold loss is the most serious and the voltage loss value is the largest when the process is "SSLT".

[0115] Table 1

[0116]

[0117] It should also be noted that in the related art, the voltage value of the debiasing control signal blsa, the voltage value of the pre-charge control signal bleq and the voltage value of the amplification control signal blsb are greater than or equal to 1.5V, and the fifth transistor 115, the sixth transistor 116, the seventh transistor 121, the eighth transistor 122, the first pre-charge transistor 131 and the second pre-charge transistor 132 in the sensitive amplifier 10 are thick oxygen devices. When these 6 transistors are thick oxygen devices, the voltage loss value is 22mV; and when the related art all uses thin oxygen devices, the voltage loss value increases to 36mV.

[0118] The withstand voltage of thin oxide devices is generally about 1V. The more advanced the process node, the lower the withstand voltage of the device. The bit line in the DRAM is in a precharge state for a long time, and the voltage is about 0.5V. If Vgs≤1V, the voltage value of the amplified control signal blsb can be 1.5V. At this time, the fifth transistor 115 and the sixth transistor 116 are thick oxide devices.

[0119] It should also be noted that when the present disclosure uses thin oxygen devices throughout, the voltage loss value is 4mV, which is the loss value of the power supply voltage drop; while in the related art, the voltage loss value includes not only the loss value of the power supply voltage drop, but also the loss value of the threshold loss.

[0120] In the present disclosure, by directly connecting the PMOS tube (the first transistor 211 and the second transistor 212) to the bit line and the complementary bit line, the threshold loss problem of transmitting a high-level signal ("1") can be avoided, so that all transistors in the sensitive amplifier 20 can use thin-oxide devices, that is, the sensitive amplifier 20 can be a full thin-oxide structure to save area.

[0121] In the case where the timing in the related art is not changed, based on Figure 2 The write operation timing diagram shown in the figure is as follows: Fig. 9 The states of the various transistors in the sense amplifier 20 at various stages are shown in FIG. Fig.11 As shown. Fig.11 In the figure, the paths formed when each transistor is turned on are indicated by solid lines, and the disconnections formed when each transistor is turned off are indicated by dotted lines. Fig.11 (a) in FIG. 1 shows the states of the transistors in the phase S1 of writing the signal from the sense amplifier LSA. Fig.11 (b) in FIG. 1 shows the states of the transistors in the latching stage S2.

[0122] like Fig.11 As shown, in the signal writing stage S1 from the sense amplifier LSA, the seventh transistor 231, the eighth transistor 232, the first pre-filling transistor 241 and the second pre-filling transistor 242 are in the off state, the fifth transistor 221, the sixth transistor 222, the first transmission transistor 251 and the second transmission transistor 252 are in the on state, the cross-coupling circuit 21 is in the working state, and the signal to be processed is written through the first transmission transistor 251 and the second transmission transistor 252. In the latching stage S2, the seventh transistor 231, the eighth transistor 232, the first pre-filling transistor 241, the second pre-filling transistor 242, the first transmission transistor 251 and the second transmission transistor 252 are in the off state, the fifth transistor 221 and the sixth transistor 222 are in the on state, and the cross-coupling circuit 21 is in the working state.

[0123] It should be noted that, because the cross-coupling circuit 21 is in operation, the first transistor 211 , the second transistor 212 , the third transistor 213 and the fourth transistor 214 included in the cross-coupling circuit 21 are indicated by solid lines, but the four transistors are not turned on at the same time.

[0124] based on Figure 5 The read operation timing diagram shown in the figure is Fig. 9 The states of the various transistors in the sense amplifier 20 at various stages are shown in FIG. Fig.12 As shown. Fig.12 In the figure, the paths formed when each transistor is turned on are indicated by solid lines, and the disconnections formed when each transistor is turned off are indicated by dotted lines. Fig.12 (a) in FIG. 1 shows the state of each transistor in the pre-charge stage S1. Fig.12 (b) in FIG. 1 shows the state of each transistor in the offset cancellation stage S2. Fig.12 (c) in FIG. 1 shows the states of each transistor in the charge sharing stage S3. Fig.12 (d) in FIG. 4 shows the state of each transistor in the amplification stage S4. Fig.12 (e) in FIG. 5 represents the state of each transistor in the signal transmission stage S5.

[0125] It should be noted that in Figure 5In the figure, WL represents the word line and the signal at the word line, the signal Isa_eq is the complementary signal of the transmission control signal Isae; when the signal Isa_eq is in a high level state, the sense amplifier LSA performs a precharge operation; when the signal Isae is in a high level state, the sense amplifier LSA performs an amplification operation.

[0126] like Fig.12 As shown, in the pre-charge stage S1, the first pre-charge transistor 241, the second pre-charge transistor 242, the fifth transistor 221, the sixth transistor 222, the seventh transistor 231 and the eighth transistor 232 are in the on state, and the sense amplifier 20 is pre-charged until the bit line and the complementary bit line are charged to the pre-charge voltage. In the offset elimination stage S2, the seventh transistor 231 and the eighth transistor 232 are in the on state, the cross-coupling circuit 21 is in the working state, the second end of the third transistor 213 and the control end are short-circuited, and the second end of the fourth transistor 214 and the control end are short-circuited, so that the third transistor 213 and the fourth transistor 214 are offset eliminated. In the amplification stage S4, the fifth transistor 221 and the sixth transistor 222 are in the on state, the cross-coupling circuit 21 is in the working state, and there is a sufficient voltage difference between the voltage on the bit line and the voltage on the complementary bit line, and the sense amplifier 20 starts to amplify the signal. In the signal transmission stage S5, the fifth transistor 221, the sixth transistor 222, the first transmission transistor 251 and the second transmission transistor 252 are in the on state, the cross-coupling circuit 21 is in the working state, and the amplified signal is transmitted to the target transmission node and the target complementary transmission node.

[0127] It should be noted that there is a storage unit corresponding to the bit line. In the pre-charge stage S1 and the offset elimination stage S2, WL is in a low level state, the storage unit and the bit line are not conducting, and there is no data to be read on the bit line; in the charge sharing stage S3, WL is in a high level state, the storage unit and the bit line are conducting, the data stored in the storage unit is transmitted to the bit line, and the bit line and the storage unit complete charge sharing; in the amplification stage S4 and the signal transmission stage S5, WL is in a high level state, and the storage unit remains conducting.

[0128] In another embodiment of the present disclosure, see Fig.13 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Fig.13 As shown, the memory 30 may include the sense amplifier 20 described in any one of the aforementioned embodiments.

[0129] The memory 30 may be SRAM, DRAM, SDRAM, DDR SDRAM, etc., without any specific limitation.

[0130] Furthermore, in some embodiments, the memory 30 may include a DRAM chip. The DRAM chip may not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, DDR6, etc., but may also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, etc., which are not specifically limited here.

[0131] In the disclosed embodiment, the memory 30 includes the aforementioned sensitive amplifier 20 and has at least the same advantages as the sensitive amplifier 20, which can enable the sensitive amplifier 20 to avoid the threshold loss problem when transmitting a high level, so that the transistors in the sensitive amplifier 20 can be thin-oxide devices, thereby saving area.

[0132] Details not disclosed in the embodiments of the present disclosure may be understood by referring to the description of the aforementioned embodiments.

[0133] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0134] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0135] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0136] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0137] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0138] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0139] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A sensitive amplifier, characterized in that: The sense amplifier comprises: A cross-coupling circuit, comprising a first node and a second node, configured to perform signal amplification processing on the first node and the second node when the sense amplifier is in an amplification phase; the first node is connected to a bit line, and the second node is connected to a complementary bit line; an amplification control circuit, connected to the first node and the second node respectively, and configured to control the cross-coupling circuit to perform signal amplification processing when the sense amplifier is in the amplification stage; and to control the cross-coupling circuit not to perform signal amplification processing when the sense amplifier is in the offset cancellation stage; an offset cancellation circuit, connected to the first node and the second node respectively, and configured to perform an offset cancellation process on the sense amplifier when the sense amplifier is in the offset cancellation phase; Wherein, at least the transistor included in the amplification control circuit is a thin-oxide device.

2. The sense amplifier according to claim 1, characterized in that: The cross-coupled circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor; The first end of the first transistor and the first end of the second transistor both receive a first power supply signal, and the first end of the third transistor and the first end of the fourth transistor both receive a second power supply signal; the second end of the first transistor, the control end of the second transistor and the control end of the fourth transistor are all connected to the first node, and the control end of the first transistor, the second end of the second transistor and the control end of the third transistor are all connected to the second node; the second end of the third transistor is connected to the third node, and the second end of the fourth transistor is connected to the fourth node; the control end of the third transistor is connected to the complementary bit line, and the control end of the fourth transistor is connected to the bit line.

3. The sense amplifier according to claim 2, characterized in that: The amplification control circuit includes a fifth transistor and a sixth transistor; The first end of the fifth transistor is connected to the third node, and the second end of the fifth transistor is connected to the first node; the first end of the sixth transistor is connected to the fourth node, and the second end of the sixth transistor is connected to the second node; the control end of the fifth transistor and the control end of the sixth transistor both receive an amplified control signal.

4. The sensitive amplifier according to claim 3, characterized in that: The offset cancellation circuit includes a seventh transistor and an eighth transistor; The first end of the seventh transistor is connected to the third node, and the second end of the seventh transistor is connected to the second node; the first end of the eighth transistor is connected to the fourth node, and the second end of the eighth transistor is connected to the first node; the control end of the seventh transistor and the control end of the eighth transistor both receive a debiasing control signal.

5. The sense amplifier according to claim 4, characterized in that: The sense amplifier also includes a pre-charge circuit; The pre-charging circuit is connected to the third node and the fourth node respectively, and is configured to perform pre-charging processing on the sense amplifier based on a pre-charging source signal when the sense amplifier is in a pre-charging stage.

6. The sense amplifier according to claim 5, characterized in that: The pre-charging circuit includes a first pre-charging transistor and a second pre-charging transistor; The first end of the first pre-charge transistor and the first end of the second pre-charge transistor both receive the pre-charge source signal, the second end of the first pre-charge transistor is connected to the third node, the second end of the second pre-charge transistor is connected to the fourth node, and the control end of the first pre-charge transistor and the control end of the second pre-charge transistor both receive the pre-charge control signal.

7. The sense amplifier according to claim 5, characterized in that: The pre-charging circuit comprises a third pre-charging transistor; The first end of the third pre-charge transistor receives the pre-charge source signal, the control end of the third pre-charge transistor receives a pre-charge control signal, and the second end of the third pre-charge transistor is connected to the third node or the fourth node.

8. The sense amplifier according to claim 1, characterized in that: The sensitive amplifier also includes a signal transmission circuit; The signal transmission circuit is connected to the first node and the second node respectively, and is configured to transmit a signal between the first node and a target transmission node, and transmit a signal between the second node and a target complementary transmission node when the sensitive amplifier is in a signal transmission phase.

9. The sense amplifier according to claim 8, characterized in that: The signal transmission circuit includes a first transmission transistor and a second transmission transistor; The control end of the first transmission transistor and the control end of the second transmission transistor both receive transmission control signals, the first transmission transistor is connected in series between the first node and the target transmission node, and the second transmission transistor is connected in series between the second node and the target complementary transmission node.

10. A memory, characterized in that: The memory comprises a sense amplifier as claimed in any one of claims 1 to 9.

Images