Storage device, control method thereof and electronic equipment

Abstract

The invention provides a storage device, a control method thereof and electronic equipment, relates to the technical field of storage, and can further improve the storage density while increasing the current reading margin. The storage device comprises a first storage unit and a differential sensitive amplifier electrically connected with the first storage unit. The first storage unit comprises a first floating gate transistor and a second floating gate transistor. Wherein the first floating gate transistor and the second floating gate transistor are located in the subsequent working procedure, and metal oxide semiconductor ring channel type field effect transistors are adopted. The differential sensitive amplifier is located in the previous process and is connected with the source electrode of the first floating gate transistor and the source electrode of the second floating gate transistor at the same time.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a storage device and a control method thereof, and an electronic device. Background Art

[0002] The storage cells of current mainstream DRAM (dynamic random access memory) products are mainly based on the 1T1C (1transistor 1capacitor) structure, that is, one storage cell contains one transistor and one capacitor. With the evolution of process nodes, the storage density improvement based on the 1T1C structure has been limited.

[0003] In recent years, in order to improve storage density, researchers have provided a DRAM product using floating-gate transistors, such as Figure 1 As shown, in this storage product, the storage unit C uses a single floating gate transistor, and the floating gate transistor is manufactured in the front-end process. Figure 2 As shown, the memory cell C has a "0" state and a "1" state. Due to process fluctuations, the read current Ird in the two states is close to a normal distribution. Among them, the read current Ird in the "0" state is smaller, and the read current Ird in the "1" state is larger. When performing a read operation, the reference current Iref is set between the maximum read current in the "0" state and the minimum read current in the "1" state, the read current is amplified by the sense amplifier SA (sensing amplifier), and the read current is compared with the reference current Iref to read the stored data. In this case, the current read margin is small, which is equivalent to half of the current difference between the maximum read current in the "0" state and the minimum read current in the "1" state. This requires the sense amplifier SA to have a very precise sensitivity, which places high demands on the design of the storage device.

[0004] Based on this, the present application provides an improved storage device, which can further improve storage density while increasing current sense margin. Summary of the invention

[0005] The present application provides a storage device and a control method thereof, and an electronic device, which can increase the current sense margin while further improving the storage density.

[0006] The present application provides a storage device, which includes a first storage unit and a differential sensitive amplifier electrically connected to the first storage unit. The first storage unit includes a first floating gate transistor and a second floating gate transistor. The first floating gate transistor and the second floating gate transistor are located in the back-end process and use oxide semiconductor ring channel field effect transistors. The differential sensitive amplifier is located in the front-end process, and the differential sensitive amplifier is connected to the source of the first floating gate transistor and the second floating gate transistor at the same time.

[0007] On the one hand, in the storage device provided in the present application, the storage unit adopts a first floating gate transistor and a second floating gate transistor, and the two floating gate transistors are connected to the same differential sense amplifier, that is, the storage unit adopts a differential 2T structure. In this way, when performing a data reading operation, there is no need to set a reference current. By directly comparing the magnitudes of the read currents of the two floating gate transistors, the storage data in the storage unit can be obtained, thereby increasing the current reading margin, which can well meet the reliability and stability of the read operation.

[0008] On the other hand, in the storage device provided in the present application, the first floating gate transistor and the second floating gate transistor in the storage unit adopt OS CAA transistors (i.e., floating gate oxide semiconductor ring channel field effect transistors), and OS CAA transistors can meet the requirements of back end of line (BEOL) integration. On this basis, the differential sensitive amplifier is set in the front end of line (FEOL), thereby reducing the area overhead of the differential sensitive amplifier, thereby improving the storage density. Of course, the use of OS CAA transistors also has the advantages of low leakage, good retention characteristics, and low temperature preparation.

[0009] In some possible implementations, the above-mentioned storage device includes a first storage array; the first storage array includes: a plurality of floating gate transistors arranged in an array, a plurality of word lines, a plurality of plate lines, and a plurality of bit lines. In the first storage array, the gates of the floating gate transistors located in different rows are respectively connected to different word lines, the drains of the floating gate transistors located in different rows are respectively connected to different plate lines; the sources of the floating gate transistors located in different columns are respectively connected to different bit lines. Among the plurality of floating gate transistors arranged in an array, two adjacent floating gate transistors located in the same row serve as the first floating gate transistor and the second floating gate transistor in the first storage unit, respectively, and the two bit lines connected to the first floating gate transistor and the second floating gate transistor are connected to the same differential sense amplifier. The first storage units located in different columns are connected to different differential sense amplifiers through bit lines.

[0010] In some possible implementations, a storage device includes: a first storage array and a second storage array arranged in the same layer. The first storage array and the second storage array both include: a plurality of floating gate transistors, a plurality of word lines, a plurality of plate lines, and a plurality of bit lines arranged in an array. In the first storage array and the second storage array: the gates of the plurality of floating gate transistors located in different columns are connected to different word lines, the drains of the plurality of floating gate transistors located in different columns are connected to different plate lines; the sources of the plurality of floating gate transistors located in different rows are connected to different bit lines. The two floating gate transistors at corresponding positions in the first storage array and the second storage array serve as the first floating gate transistor and the second floating gate transistor in the first storage unit, respectively, and the two bit lines connected to the first floating gate transistor and the second floating gate transistor are connected to the same differential sense amplifier.

[0011] In some possible implementations, the first storage array and the second storage array are located in the same layer.

[0012] In some possible implementations, the first storage array and the second storage array are located in different layers.

[0013] Compared with the first storage array and the second storage array being integrated in the same layer, the storage density can be further improved by arranging the first storage array and the second storage array in different layers.

[0014] In some possible implementations, the first floating gate transistor includes: a stacked structure, a first trench, a gate, a floating gate, a gate insulating layer, and a channel layer. The stacked structure is arranged on a silicon substrate, and the stacked structure includes a source layer and a drain layer, and the source layer is closer to the silicon substrate relative to the drain layer. The first trench is arranged on the stacked structure, and the first trench at least extends into the source layer. The gate is arranged in the first trench and extends to the depth where the source layer is located. The floating gate is arranged in the first trench, and the floating gate is arranged around the gate. The gate insulating layer is located between the gate and the floating gate. The channel layer covers the inner wall of the first trench and connects the source layer and the drain layer.

[0015] The present application also provides a control method for a storage device provided in any of the above possible implementations, the control method comprising:

[0016] When performing a write operation: a high voltage is applied to the gate of the selected first floating-gate transistor, and a low voltage is applied to the source and drain; a high voltage is applied to the source and drain of the selected second floating-gate transistor, and a low voltage is applied to the gate. Alternatively, a high voltage is applied to the source and drain of the selected first floating-gate transistor, and a low voltage is applied to the gate; a high voltage is applied to the gate of the selected second floating-gate transistor, and a low voltage is applied to the source and drain.

[0017] When performing a read operation: a high voltage is applied to the gates of the selected first floating-gate transistor and the second floating-gate transistor, and a read voltage is applied to the drains of the selected first floating-gate transistor and the second floating-gate transistor; the source currents of the selected first floating-gate transistor and the second floating-gate transistor are amplified by a differential sensitive amplifier; based on the magnitude of the source currents of the selected first floating-gate transistor and the second floating-gate transistor, the storage data in the selected first storage unit is determined.

[0018] In some possible implementations, the above-mentioned applying a high voltage to the gate of the selected first floating gate transistor and a low voltage to the source and drain; and applying a high voltage to the source and drain of the selected second floating gate transistor and a low voltage to the gate, may include: applying a high voltage to the gate of the selected first floating gate transistor and a low voltage to the source and drain to write "1" in the selected first floating gate transistor; applying a high voltage to the source and drain of the selected second floating gate transistor and a low voltage to the gate to write "0" in the selected second floating gate transistor; in this case, the storage data "1" is written in the selected first storage unit.

[0019] In some possible implementations, the above-mentioned applying a high voltage to the source and drain of the selected first floating gate transistor and a low voltage to the gate; applying a high voltage to the gate of the selected second floating gate transistor and a low voltage to the source and drain may include: applying a high voltage to the source and drain of the selected first floating gate transistor and a low voltage to the gate to write "0" in the selected first floating gate transistor; applying a high voltage to the gate of the selected second floating gate transistor and a low voltage to the source and drain to write "1" in the selected second floating gate transistor; in this case, the storage data "0" is written in the selected first storage unit.

[0020] In some possible implementations, the above-mentioned determination of the storage data in the selected first storage unit based on the source current sizes of the selected first floating-gate transistor and the second floating-gate transistor may include: when the source current of the selected first floating-gate transistor is greater than the source current of the selected second floating-gate transistor, determining that the storage data in the selected first storage unit is "1"; when the source current of the selected first floating-gate transistor is less than the source current of the selected second floating-gate transistor, determining that the storage data in the selected first storage unit is "0".

[0021] The present application also provides an electronic device, which includes a circuit board and a storage device provided in any of the possible implementation methods described above, wherein the storage device is electrically connected to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the structure of a storage unit provided in the prior art;

[0023] Figure 2 A read current distribution curve and current read margin of a memory cell provided in the prior art;

[0024] Figure 3 A schematic diagram of the structure of a storage unit provided in an embodiment of the present application;

[0025] Figure 4 A read current distribution curve and current read margin of a memory cell provided in an embodiment of the present application;

[0026] Figure 5 A schematic diagram of the structure of a floating gate transistor in a memory cell provided in an embodiment of the present application;

[0027] Figure 6 A circuit diagram of a storage array provided in an embodiment of the present application;

[0028] Figure 7 A schematic diagram of the structure of a storage array provided in an embodiment of the present application;

[0029] Figure 8 A circuit diagram of a storage array provided in an embodiment of the present application;

[0030] Fig. 9 A schematic diagram of the structure of a storage array provided in an embodiment of the present application;

[0031] Fig.10 A schematic diagram of the structure of a storage array provided in an embodiment of the present application;

[0032] Fig.11 A schematic diagram of a write operation control of a storage unit provided in an embodiment of the present application;

[0033] Fig.12 A schematic diagram of a write operation control of a storage unit provided in an embodiment of the present application;

[0034] Fig.13 A schematic diagram of a read operation control of a storage unit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] The terms "first", "second", etc. in the specification embodiments, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or it can be indirect through an intermediate medium, or it can be the internal connection of two elements. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for description and clarification relative to the description, which may change accordingly according to the change of the orientation of the components in the drawings.

[0037] An embodiment of the present application provides an electronic device, which may be a mobile phone, a tablet computer, a personal computer (PC), a car computer, a smart watch, a smart bracelet, a server, or other electronic product. The present application does not limit the setting form of the electronic device.

[0038] The electronic device is provided with a circuit board and a storage device electrically connected to the circuit board. Of course, according to actual needs, the electronic device may also be provided with other devices, such as a processor, an input / output (I / O) device, a positioning module, a Bluetooth module, a sensor, a Wi-Fi module, etc.

[0039] In order to solve the problems of small current read margin (sense margin) and low storage density in existing storage devices, an embodiment of the present application provides a new type of storage device, in which a storage unit adopts a differential 2T structure based on a floating gate oxide semiconductor (oxide semiconductor, OS) ring channel (channel all around, CAA) field effect transistor (which can be referred to as a floating gate OS CAA transistor). The storage unit using the differential 2T structure can increase the current read margin (sense margin) while improving the storage density.

[0040] The storage device provided in the embodiment of the present application can be a device with storage function such as DRAM, cache, content addressable memory, etc. The present application does not limit the configuration form of the storage device. The following embodiments are all described by taking the storage device as DRAM as an example.

[0041] The specific structure of the storage device provided in the embodiment of the present application is described below.

[0042] As shown, an embodiment of the present application provides a storage device, in which a storage unit (also referred to as a first storage unit) of a new structure is used, such as Figure 3 As shown, the memory cell C1 includes a first floating gate transistor T1 and a second floating gate transistor T2, and the first floating gate transistor T1 and the second floating gate transistor T2 are both arranged in a back end of line (BEOL). The first floating gate transistor T1 and the second floating gate transistor T2 are both formed of an oxide semiconductor (OS) ring channel type (CAA) field effect transistor, which can be referred to as a floating gate OS CAA transistor.

[0043] It should be understood that during the manufacturing process of the existing memory device, the transistors in the memory cell are manufactured through the front end of line (FEOL), that is, a plurality of transistors are prepared on a substrate through the front end of line (FEOL).

[0044] In contrast, the transistors (T1, T2) in the memory cell C1 of the present application use floating gate OS CAA transistors, which can be integrated in the back-end process (BEOL). In addition, the use of floating gate OS CAA transistors also has the advantages of low leakage, good retention characteristics, and low temperature preparation. 2 It has great potential in DRAM applications. Where F is the feature size at the process node.

[0045] Indicative, such as Figure 3As shown, in the memory cell C1, the gates of the first floating gate transistor T1 and the second floating gate transistor T2 may be connected to the word line WL (word line), and the drains of the first floating gate transistor T1 and the second floating gate transistor T2 may be connected to the plate line PL (plate line). The source of the first floating gate transistor T1 and the source of the second floating gate transistor T2 are connected to the differential sensing amplifier 100 (differential sensing amplifier) ​​through different bit lines BL (bit lines).

[0046] In this way, when the storage data is written, the data in the storage cell C1 can be written by writing "0" and "1" in the two transistors (T1, T2) respectively, and the details can be referred to the following description. When the storage data is read, the read currents of the two transistors (T1, T2) can be compared through the differential sense amplifier 100, and the storage data in the storage cell C1 can be obtained according to the magnitude of the read currents of the two transistors (T1, T2).

[0047] refer to Figure 2 and Figure 4 As shown, compared to the existing current sense margin which is only equivalent to half of the current difference between the maximum read current of the transistor in the "0" state and the minimum read current in the "1" state, the present application is based on a differential 2T structure and does not need to set a reference current Iref. When reading the stored data, the storage data in the storage cell C1 can be obtained by directly comparing the sizes of the read currents of the two transistors (T1, T2).

[0048] That is to say, the current sense margin of the present application is approximately the difference between the maximum sense current of the "0" state and the minimum sense current of the "1" state of the transistor, which is equivalent to twice the existing current sense margin, which is a significant improvement, thereby greatly improving the reliability and stability of the read operation.

[0049] In the present application, for the write operation of the storage cell C1 using the differential 2T structure, the data written into the storage cell C1 can be defined by writing "1" and "0" into the first floating gate transistor T1 and the second floating gate transistor T2 respectively.

[0050] For example, in some possible implementations, when "1" is written in the first floating gate transistor T1 and "0" is written in the second floating gate transistor T2, the written data in the storage cell C1 is defined as "1"; and when "0" is written in the first floating gate transistor T1 and "1" is written in the second floating gate transistor T2, the written data in the storage cell C1 is defined as "0".

[0051] Schematically, the control process of writing "1" or "0" into the floating gate transistor is described by taking the first floating gate transistor T1 as an example. Figure 3 As shown, when writing "1" in the first floating gate transistor T1, a high voltage can be applied to the gate of the first floating gate transistor T1 through the word line WL, and a low voltage (such as grounding) can be applied to the drain and source of the first floating gate transistor T1 through the plate line PL and the bit line BL0. In this case, electron tunneling occurs between the floating gate and the channel, and a large number of electrons enter the channel. When the voltage is removed, the electrons still remain in the floating gate. At this time, the written state is 1; when writing "0" in the first floating gate transistor T1, a low voltage (such as grounding) can be applied to the gate of the first floating gate transistor T1 through the word line WL, and a high voltage can be applied to the drain and source of the first floating gate transistor T1 through the plate line PL and the bit line BL0. In this case, electrons tunnel from the floating gate through the oxide layer to the channel, and the floating gate loses electrons. At this time, the written state is 0.

[0052] Of course, in other possible implementations, "1" can be written in the first floating gate transistor T1 and "0" can be written in the second floating gate transistor T2, defining the write data in the storage cell C1 as "0"; while "0" can be written in the first floating gate transistor T1 and "1" can be written in the second floating gate transistor T2, defining the write data in the storage cell C1 as "1".

[0053] It should be understood that in the present application, although the threshold voltage (Vt) of the floating gate OS CAA transistor (T1, T2) is easily drifted due to the high temperature of the subsequent process, resulting in an increase in the process deviation of the threshold voltage (Vt), the differential 2T storage cell based on the present application can well meet the reliability and stability of the read operation by greatly improving the current read margin (sense margin).

[0054] In addition, in the present application, since the floating gate OS CAA transistors (T1, T2) are integrated in the back-end process (BEOL), the differential sense amplifier 100 can be integrated in the front-end process (FEOL). That is, the differential sense amplifier 100 is directly manufactured on the substrate through the front-end process (FEOL), and then the storage unit C1 is integrated above the differential sense amplifier 100 through the back-end process (BEOL). In this way, the area overhead of the differential sense amplifier 100 can be reduced, and the storage density can be improved.

[0055] The following is a brief description of the structure of the floating gate OS CAA transistors (T1, T2) integrated in the back-end process.

[0056] Schematically, the present application embodiment provides a floating gate OS CAA transistor, such as Figure 5 As shown, the floating gate OS CAA transistor may include a silicon substrate 10 and a stacked structure 20 disposed on the silicon substrate 10 .

[0057] like Figure 5 As shown, the stacked structure 20 includes a source layer S and a drain layer D, and the source layer S is closer to the silicon substrate 10 than the drain layer D. The source layer S serves as the source of the floating gate OS CAA transistor, and the drain layer D serves as the drain of the floating gate OS CAA transistor. Of course, other film layers such as a dielectric layer may be provided between the source layer S and the drain layer D.

[0058] like Figure 5 As shown, a first trench 200 is provided on the stacked structure 20, and the first trench 200 extends to the depth region where the source layer S is located. The gate G (gate), floating gate FG (floating gate), gate insulation layer 201, and channel layer 202 of the floating gate OS CAA transistor are provided in the first trench 200. The floating gate FG is provided around the gate G. The gate insulation layer 201 is filled between the gate G and the floating gate FG. The channel layer 202 covers the inner wall of the first trench 200 and connects the source layer S and the drain layer D. Of course, according to actual needs, some structures (such as the gate G) can be extended to the outside of the first trench 200 to connect with other wirings.

[0059] In addition, the storage unit of the differential 2T structure adopted in the present application can be differentiated in a single storage array or in two storage arrays. The following describes the two array integration methods through specific embodiments.

[0060] Embodiment 1

[0061] Schematically, this embodiment provides a storage device, such as Figure 6 As shown, the storage device includes a storage array A1 (also referred to as a first storage array), and the storage unit C1 implements differentiation within the storage array A1.

[0062] Indicative, such as Figure 6As shown, the memory array A1 (Array) includes: a plurality of floating gate transistors arranged in an array, a plurality of word lines (WL0, WL1, WL2, WL3), a plurality of plate lines (PL0, PL1, PL2, PL3), and a plurality of bit lines (BL0, BL1, BL2, BL3, BL4, BL5). Among the plurality of floating gate transistors arranged in an array, the plurality of floating gate transistors along the row direction may be first floating gate transistors T1 and second floating gate transistors T2 alternately arranged in sequence, and the first floating gate transistors T1 and the second floating gate transistors T2 arranged adjacently form a memory cell C1. The first floating gate transistors T1 or the second floating gate transistors T2 may all be arranged in the column direction. In this case, a plurality of memory cells C1 arranged in an array are formed in the memory array A1.

[0063] As shown in Reference 6, in the storage array A1:

[0064] The gates of the floating gate transistors (T1, T2) located in different rows are connected to different word lines (WL0, WL1, WL2, WL3). For example, the gates of the floating gate transistors (T1, T2) located in the first row are connected to the word line WL0, and the gates of the floating gate transistors (T1, T2) located in the second row are connected to the word line WL1.

[0065] The drains of the floating gate transistors (T1, T2) in different rows are connected to different plate lines (PL0, PL1, PL2, PL3). For example, the drains of the floating gate transistors (T1, T2) in the first row are connected to the plate line PL0, and the drains of the floating gate transistors (T1, T2) in the second row are connected to the plate line PL1.

[0066] The sources of the floating gate transistors (T1, T2) in different columns are connected to different bit lines (BL0, BL1, BL2, BL3, BL4, BL5). For example, the sources of the first floating gate transistors T1 in the first column are connected to the bit line BL0, and the drains of the second floating gate transistors T2 in the second column are connected to the bit line BL1.

[0067] like Figure 6 As shown, two bit lines (BL0 and BL1, BL2 and BL3, BL4 and BL5) connected to the same column of memory cells C1 are connected to the same differential sense amplifier 100, and bit lines connected to different memory cells C1 are connected to different differential sense amplifiers 100. For example, two bit lines (BL0, BL1) connected to the first column of memory cells C1 are connected to one differential sense amplifier 100, and two bit lines (BL2, BL3) connected to the second column of memory cells C1 are connected to another differential sense amplifier 100.

[0068] Figure 7This is a cross-sectional schematic diagram of a storage device provided in the first embodiment.

[0069] refer to Figure 7 As shown, in some possible implementations, for the storage device in the first embodiment, a plurality of differential sense amplifiers 100 can be first manufactured on a substrate through a front-end-of-line (FEOL) process, and then the above-mentioned storage array A1 and related signal lines (word lines WL, plate lines PL, bit lines BL), etc., can be formed in the direction of the plurality of differential sense amplifiers 100 through a back-end-of-line (BEOL) process.

[0070] Embodiment 2

[0071] Schematically, the second embodiment provides a storage device, which includes a first storage array A1 and a second storage array A2, and a storage unit C1 is differentially implemented in the two storage arrays (A1, A2).

[0072] The following describes the configuration of the first storage array A1 and the second storage array A2 respectively.

[0073] Indicative, such as Figure 8 As shown, the first memory array A1 includes a plurality of first floating gate transistors T1 arranged in an array, a plurality of word lines (WLL0, WLL1, WLL2, WLL3), a plurality of plate lines (PLL0, PLL1, PLL2, PLL3), and a plurality of bit lines (BLL0, BLL1, BLL2, BLL3, BLL4, BLL5).

[0074] In the first storage array A1:

[0075] The gates of the first floating-gate transistors T1 in different columns are connected to different word lines (WLL0, WLL1, WLL2, WLL3). For example, the gates of the first floating-gate transistors T1 in the first column are connected to the word line WLL0, and the gates of the first floating-gate transistors T1 in the second column are connected to the word line WLL1.

[0076] The drains of the first floating-gate transistors T1 located in different columns are connected to different plate lines (PLL0, PLL1, PLL2, PLL3). For example, the drains of the first floating-gate transistors T1 located in the first column are connected to the word line PLL0, and the drains of the first floating-gate transistors T1 located in the second column are connected to the word line PLL1.

[0077] The sources of the first floating-gate transistors T1 located in different rows are connected to different bit lines (BLL0, BLL1, BLL2, BLL3, BLL4, BLL5). For example, the sources of the first floating-gate transistors T1 located in the first row are connected to the bit line BLL0, and the drains of the first floating-gate transistors T1 located in the second row are connected to the bit line BLL1.

[0078] Indicative, such as Figure 8 As shown, the second storage array A2 includes a plurality of second floating gate transistors T2 arranged in an array, a plurality of word lines (WLR0, WLR1, WLR2, WLR3), a plurality of plate lines (PLR0, PLR1, PLR2, PLR3), and a plurality of bit lines (BLR0, BLR1, BLR2, BLR3, BLR4, BLR5).

[0079] In the first storage array A2:

[0080] The gates of the second floating-gate transistors T2 in different columns are connected to different word lines (WLR0, WLR1, WLR2, WLR3). For example, the gates of the second floating-gate transistors T2 in the first column are connected to the word line WLR0, and the gates of the second floating-gate transistors T2 in the second column are connected to the word line WLR1.

[0081] The drains of the second floating-gate transistors T2 located in different columns are connected to different plate lines (PLR0, PLR1, PLR2, PLR3). For example, the drains of the second floating-gate transistors T2 located in the first column are connected to the word line PLR0, and the drains of the second floating-gate transistors T2 located in the second column are connected to the word line PLR1.

[0082] The sources of the second floating-gate transistors T2 located in different rows are connected to different bit lines (BLR0, BLR1, BLR2, BLR3, BLR4, BLR5). For example, the sources of the second floating-gate transistors T2 located in the first row are connected to the bit line BLR0, and the drains of the second floating-gate transistors T2 located in the second row are connected to the bit line BLR1.

[0083] On this basis, if Figure 8 As shown, two floating gate transistors at corresponding positions in the first memory array A1 and the second memory array A2 can be used as the first floating gate transistor T1 and the second floating gate transistor T2 in the first memory cell C1, respectively. For example, the first floating gate transistor T1 located in the first row and first column of the first memory array A1 and the second floating gate transistor T2 located in the first row and first column of the second memory array A2 form a memory cell C1. The first floating gate transistor T1 located in the first row and second column of the first memory array A1 and the second floating gate transistor T2 located in the first row and second column of the second memory array A2 form a memory cell C1.

[0084] Of course, the two floating gate transistors (T1, T2) in the memory cell C1 may also be distributed in non-corresponding positions in the two memory arrays (A1, A2), and this application does not impose any limitation on this.

[0085] In this case, if Figure 8 As shown, two bit lines connected to two floating gate transistors (T1, T2) in the same memory cell C1 should be connected to the same differential sense amplifier 100. For example, the bit line BLL0 connected to the first floating gate transistor T1 in the first row and first column of the first memory array A1, and the bit line BLR0 connected to the second floating gate transistor T2 in the first row and first column of the second memory array A2 are connected to the same differential sense amplifier 100. The bit line BLL1 connected to the first floating gate transistor T1 in the second row and first column of the first memory array A1, and the bit line BLR1 connected to the second floating gate transistor T2 in the second row and first column of the second memory array A2 are connected to the same differential sense amplifier 100.

[0086] In addition, in the second embodiment, the first storage array A1 and the second storage array A2 can be integrated in the same layer or in different layers. The present application does not impose any limitation on this, and it can be set as needed in practice.

[0087] For example, Fig. 9 As shown, in some possible implementations, the first memory array A1 and the second memory array A2 may be integrated on the same layer. In this case, a plurality of differential sense amplifiers 100 ( Fig. 9 Only one is shown in the figure), and then above the multiple differential sense amplifiers 100, a first memory array A1 and a second memory array A2 arranged on the same layer and related signal lines (word lines WL, plate lines PL, bit lines BL) are formed through a back-end process (BEOL) .

[0088] For example, Fig.10 As shown, in some possible implementations, the first memory array A1 and the second memory array A2 may be integrated in different layers, and the second memory array A2 may be located between the first memory array A1 and the differential sense amplifier 100. In this case, a plurality of differential sense amplifiers 100 ( Fig.10 Only one is shown in the figure), and then the second memory array A2 is first manufactured on the plurality of differential sense amplifiers 100 through the back end of line (BEOL), and then the first memory array A1 is manufactured on the second memory array A2. Of course, the related signal lines (word lines WL, plate lines PL, bit lines BL) can be manufactured together in the back end of line (BEOL).

[0089] It can be understood here that, compared with the first storage array A1 and the second storage array A2 being integrated in the same layer, the storage density can be further improved by arranging the first storage array A1 and the second storage array A2 in different layers.

[0090] Indicatively, this embodiment 2 also provides a Figure 8 The control method for the read and write operation of the storage device shown in the figure may be specifically as follows: (the floating gate transistor marked with a dotted box represents the selected floating gate transistor)

[0091] When writing "1":

[0092] refer to Fig.11 As shown, in the first memory array A1, a high voltage (indicated as 1) is applied to the gate of the selected first floating-gate transistor T1 through the word line WLL0, and a low voltage (indicated as 0) is applied to the source and drain of the selected first floating-gate transistor T1 through the plate line PLL0 and the bit line BLL0, which may be grounded. Other unselected bit lines input a high voltage (1), and other unselected word lines and plate lines may input a low voltage (0). In this case, "1" is written into the selected first floating-gate transistor T1.

[0093] refer to Fig.11 As shown, in the second memory array A2, a low voltage (0) is applied to the gate of the selected second floating-gate transistor T2 through the word line WLR0, which may be grounded. A high voltage (1) is applied to the source and drain of the selected second floating-gate transistor T2 through the plate line PLR0 and the bit line BLR0. Other unselected word lines, plate lines, and bit lines may input a low voltage (0). In this case, "0" is written into the selected second floating-gate transistor T2.

[0094] The selected first floating gate transistor T1 and the selected second floating gate transistor T2 are two transistors in the selected memory cell C1. When "1" is written in the first floating gate transistor T1 and "0" is written in the second floating gate transistor T2, "1" is written in the selected memory cell C1.

[0095] When writing "1":

[0096] refer to Fig.12 As shown, in the first memory array A1, a low voltage (0) is applied to the gate of the selected first floating-gate transistor T1 through the word line WLL0, which may be grounded. A high voltage (1) is applied to the source and drain of the selected first floating-gate transistor T1 through the plate line PLL0 and the bit line BLL0. Other unselected word lines, plate lines, and bit lines may input a low voltage (0). In this case, "0" is written into the selected first floating-gate transistor T1.

[0097] refer to Fig.12As shown, in the second memory array A2, a high voltage (indicated as 1) is applied to the gate of the selected second floating-gate transistor T2 through the word line WLR0, and a low voltage (indicated as 0) is applied to the source and drain of the selected second floating-gate transistor T2 through the plate line PLR0 and the bit line BLR0, which may be grounded. Other unselected bit lines input a high voltage (1), and other unselected word lines and plate lines may input a low voltage (0). In this case, "1" is written into the selected second floating-gate transistor T2.

[0098] The selected first floating gate transistor T1 and the selected second floating gate transistor T2 are two transistors in the selected memory cell C1. When "0" is written in the first floating gate transistor T1 and "1" is written in the second floating gate transistor T2, "0" is written in the selected memory cell C1.

[0099] Of course, in other possible implementations, when "1" is written in the first floating gate transistor T1 and "0" is written in the second floating gate transistor T2 in the storage cell C1, the storage data written in the storage cell C1 is defined as "0"; and when "1" is written in the first floating gate transistor T1 and "0" is written in the second floating gate transistor T2, the storage data written in the selected storage cell C1 is defined as "1".

[0100] refer to Fig.13 As shown, during a read operation:

[0101] A high voltage is applied to the gates of the selected first and second floating gate transistors T1 and T2 through word lines WLL0 and WLR0 , respectively, and a read voltage is applied to the drains of the selected first and second floating gate transistors T1 and T2 through plate lines PLL0 and PLR0 , respectively.

[0102] The source currents of the selected first floating-gate transistor T1 and the second floating-gate transistor T2 are read and amplified by the differential sense amplifier 100 .

[0103] The storage data in the selected memory cell C1 is determined according to the magnitude of the source current of the selected first floating-gate transistor T1 and the second floating-gate transistor T2.

[0104] In some possible implementations, if the source current of the selected first floating-gate transistor T1 is greater than the source current of the selected second floating-gate transistor T2, it means that the first floating-gate transistor T1 is "1" and the second floating-gate transistor T2 is "0". In this case, it can be determined that the storage data in the selected storage cell C1 is "1". Correspondingly, if the source current of the selected first floating-gate transistor T1 is less than the source current of the selected second floating-gate transistor T2, it means that the first floating-gate transistor T1 is "0" and the second floating-gate transistor T2 is "1". In this case, it is determined that the storage data in the selected storage cell C1 is "0".

[0105] Of course, in other possible implementations, if the source current of the selected first floating-gate transistor T1 is greater than the source current of the selected second floating-gate transistor T2, it can be determined that the storage data in the selected storage cell C1 is "0"; if the source current of the selected first floating-gate transistor T1 is less than the source current of the selected second floating-gate transistor T2, it can be determined that the storage data in the selected storage cell C1 is "1". In practice, it can be designed according to needs.

[0106] For the storage device using a single storage array in the first embodiment, the control method of its read and write operations is similar to that in the second embodiment, and the only difference is that data can be written to the two floating gate transistors (T1, T2) in the selected storage cell C1 twice, for example, "1" is written to the first floating gate transistor T1 for the first time, and "0" is written to the second floating gate transistor T2 for the second time. For specific instructions, please refer to the corresponding part in the second embodiment, which will not be repeated here.

[0107] It should be noted that the connection method of the source and drain of the transistors (T1, T2) involved in the present application is only an example. In some cases, the source and drain of the transistors (T1, T2) involved in the present application may not be clearly distinguished, so the corresponding connection relationship can also be interchanged.

[0108] It should also be noted that the "row" and "column" involved in this application are only a set of relative directions, and this application does not impose any special restrictions on this. In some cases, the "row" direction is horizontal and the "column" direction is vertical; in some cases, the "row" direction is vertical and the "column" direction is horizontal.

[0109] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A storage device, characterized in that: It includes a first storage unit and a differential sensitive amplifier; The first storage unit includes a first floating gate transistor and a second floating gate transistor located in a back-end process; wherein the first floating gate transistor and the second floating gate transistor are oxide semiconductor ring channel field effect transistors; The source of the first floating gate transistor and the source of the second floating gate transistor are both connected to the differential sense amplifier, and the differential sense amplifier is located in the front-end process.

2. The storage device according to claim 1, characterized in that The storage device comprises a first storage array; The first memory array comprises: a plurality of floating gate transistors, a plurality of word lines, a plurality of plate lines, and a plurality of bit lines arranged in an array; In the first storage array, the gates of the floating gate transistors located in different rows are respectively connected to different word lines, the drains of the floating gate transistors located in different rows are respectively connected to different plate lines; the sources of the floating gate transistors located in different columns are respectively connected to different bit lines; Among the plurality of floating gate transistors arranged in the array, two adjacent floating gate transistors located in the same row serve as the first floating gate transistor and the second floating gate transistor in the first storage unit respectively, and the two bit lines connected to the first floating gate transistor and the second floating gate transistor are connected to the same differential sense amplifier; The first storage cells located in different columns are connected to different differential sense amplifiers through the bit lines.

3. The storage device according to claim 1, characterized in that: The storage device comprises: a first storage array and a second storage array arranged in the same layer; The first memory array and the second memory array both include: a plurality of floating gate transistors, a plurality of word lines, a plurality of plate lines, and a plurality of bit lines arranged in an array; In the first memory array and the second memory array: the gates of the plurality of floating gate transistors located in different columns are connected to different word lines, the drains of the plurality of floating gate transistors located in different columns are connected to different plate lines; the sources of the plurality of floating gate transistors located in different rows are connected to different bit lines; The two floating gate transistors at corresponding positions in the first storage array and the second storage array serve as the first floating gate transistor and the second floating gate transistor in the first storage unit respectively, and the two bit lines connected to the first floating gate transistor and the second floating gate transistor are connected to the same differential sense amplifier.

4. The storage device according to claim 3, characterized in that: The first storage array and the second storage array are located in the same layer.

5. The storage device according to claim 3, characterized in that: The first storage array and the second storage array are located in different layers.

6. The storage device according to any one of claims 1 to 5, characterized in that: The first floating gate transistor comprises: A stacked structure disposed on a silicon substrate, the stacked structure comprising a source layer and a drain layer, the source layer being closer to the silicon substrate than the drain layer; A first trench, wherein the first trench is disposed on the stacked structure and the first trench at least extends into the source layer; A gate, the gate being disposed in the first trench and extending to a depth where the source layer is located; A floating gate, wherein the floating gate is disposed in the first trench and surrounds the gate; a gate insulating layer, the gate insulating layer being located between the gate and the floating gate; A channel layer covers an inner wall of the first trench and connects the source layer and the drain layer.

7. A method for controlling a storage device according to any one of claims 1 to 6, characterized in that: include: When performing a write operation: Applying a high voltage to the gate of the selected first floating-gate transistor, and applying a low voltage to the source and drain; and applying a high voltage to the source and drain of the selected second floating-gate transistor, and applying a low voltage to the gate; Applying a high voltage to the source and drain of the selected first floating-gate transistor, and applying a low voltage to the gate; applying a high voltage to the gate of the selected second floating-gate transistor, and applying a low voltage to the source and drain; During a read operation: Applying a high voltage to gates of the selected first floating-gate transistor and the selected second floating-gate transistor, and applying a read voltage to drains of the selected first floating-gate transistor and the selected second floating-gate transistor; amplifying the source current of the selected first floating-gate transistor and the second floating-gate transistor by the differential sense amplifier; Storage data in the selected first storage unit is determined according to the magnitude of the source current of the selected first floating-gate transistor and the selected second floating-gate transistor.

8. The control method of the storage device according to claim 7, characterized in that: The step of applying a high voltage to the gate of the selected first floating-gate transistor and applying a low voltage to the source and drain; and applying a high voltage to the source and drain of the selected second floating-gate transistor and applying a low voltage to the gate comprises: Applying a high voltage to the gate of the selected first floating-gate transistor and applying a low voltage to the source and drain to write "1" in the selected first floating-gate transistor; Applying a high voltage to the source and drain of the selected second floating-gate transistor and a low voltage to the gate to write "0" in the selected second floating-gate transistor; The storage data "1" is written into the selected first storage unit.

9. The control method of the storage device according to claim 7 or 8, characterized in that: The step of applying a high voltage to the source and drain of the selected first floating-gate transistor and applying a low voltage to the gate; and applying a high voltage to the gate of the selected second floating-gate transistor and applying a low voltage to the source and drain comprises: Applying a high voltage to the source and drain of the selected first floating-gate transistor and a low voltage to the gate to write "0" in the selected first floating-gate transistor; Applying a high voltage to the gate of the selected second floating-gate transistor and applying a low voltage to the source and drain to write "1" in the selected second floating-gate transistor; The storage data "0" is written into the selected first storage unit.

10. The control method of a storage device according to any one of claims 7 to 9, characterized in that: The step of determining the storage data in the selected first storage unit according to the source current magnitudes of the selected first floating-gate transistor and the selected second floating-gate transistor comprises: When the source current of the selected first floating-gate transistor is greater than the source current of the selected second floating-gate transistor, it is determined that the storage data in the selected first storage unit is "1"; When the source current of the selected first floating-gate transistor is smaller than the source current of the selected second floating-gate transistor, it is determined that the storage data in the selected first storage unit is “0”.

11. An electronic device, characterized in that: It comprises a circuit board and a storage device as claimed in any one of claims 1 to 6, wherein the storage device is electrically connected to the circuit board.

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