Semiconductor packaging piece, manufacturing method thereof, semiconductor device and electronic equipment

Abstract

The invention discloses a semiconductor packaging piece, a manufacturing method thereof, a semiconductor device and electronic equipment. The semiconductor packaging piece comprises a semiconductor chip, a protection layer, a plastic packaging layer, a substrate and a conductive piece. The semiconductor chip includes a first surface and a second surface opposite to each other. The semiconductor chip further comprises a passivation layer, and the passivation layer covers the second surface and is provided with a conductive area. The protection layer is arranged on the side, away from the semiconductor chip, of the passivation layer and exposes the conductive area. The plastic packaging layer at least covers one side, deviating from the passivation layer, of the protection layer, and the hardness of the plastic packaging layer is greater than that of the protection layer. The semiconductor chip is disposed on the substrate, and the first surface is connected to the substrate. The conductive part comprises a first end and a second end which are opposite, the first end penetrates through the protective layer and then is electrically connected with the conductive area, and the second end is connected with the substrate.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor package, a semiconductor device, an electronic device, and a method for manufacturing a semiconductor package. Background Art

[0002] During the process of encapsulating the plastic layer of the semiconductor package, packaging stress will be generated. The stress generated by the packaging will be transmitted to the upper metal conductive layer of the semiconductor chip through the passivation layer, causing the filling layer (low-K material) between the metals to break, resulting in the reference voltage offset after the semiconductor package is packaged. Summary of the invention

[0003] The present application provides a semiconductor package, a semiconductor device, an electronic device and a method for manufacturing the semiconductor package.

[0004] The semiconductor package provided in the present application includes a semiconductor chip, a protective layer, a plastic encapsulation layer, a substrate and a conductive member. The semiconductor chip includes a first surface and a second surface opposite to each other. The semiconductor chip also includes a passivation layer, which covers the second surface and has a conductive area. The protective layer is arranged on the side of the passivation layer away from the semiconductor chip and exposes the conductive area. The plastic encapsulation layer at least covers the side of the protective layer away from the passivation layer, and the hardness of the plastic encapsulation layer is greater than the hardness of the protective layer. The semiconductor chip is arranged on the substrate, and the first surface is connected to the substrate. The conductive member includes a first end and a second end opposite to each other, the first end is electrically connected to the conductive area after passing through the protective layer, and the second end is connected to the substrate.

[0005] In some embodiments, the thickness of the protective layer is greater than or equal to 8 micrometers and less than or equal to 12 micrometers.

[0006] In certain embodiments, the protective layer is made of polyimide.

[0007] In certain embodiments, the molding layer includes a molding compound and a softener doped in the molding compound, and a weight ratio of the molding compound to the softener is 19:1.

[0008] In certain embodiments, the softener is made of insoluble silicone.

[0009] In some embodiments, the semiconductor chip further comprises a substrate, a device layer and a conductive layer. The substrate comprises the first surface. The device layer is disposed on a side of the substrate facing away from the first surface. The conductive layer is disposed on a side of the device layer facing away from the substrate, the conductive region is electrically connected to the conductive layer, and the conductive layer comprises a multi-layer metal structure, and the multi-layer metal structure is connected via a through hole of a low dielectric material.

[0010] The present application also provides a semiconductor device, which includes the semiconductor package described in any one of the above embodiments.

[0011] The present application also provides an electronic device, which includes the semiconductor device described in any one of the above embodiments.

[0012] The present application also provides a method for manufacturing a semiconductor package, the manufacturing method comprising: providing a wafer, the wafer comprising a first surface and a second surface opposite to each other, the wafer further comprising a passivation layer, the passivation layer covering the second surface and exposing a first hole having the conductive area; forming a protective layer meeting a preset thickness on the passivation layer, the protective layer having a second hole, the second hole being aligned with the first hole; dividing the wafer based on the scribe line of the wafer to obtain a semiconductor chip formed with the protective layer; forming a conductive member, so that the first end of the conductive member is electrically connected to the conductive area after passing through the second hole, and the second end of the conductive member is connected to a substrate, and forming a plastic encapsulation layer at least on the side of the protective layer away from the passivation layer to obtain the semiconductor package, the hardness of the plastic encapsulation layer being greater than the hardness of the protective layer.

[0013] In some embodiments, the protective layer is made of polyimide; the protective layer having a preset thickness is formed on the passivation layer, the protective layer having a second hole, and the second hole is aligned with the first hole, comprising: depositing polyimide on the side of the passivation layer away from the second surface; curing the polyimide to form the protective layer having a preset thickness; and opening the second hole and a scribe groove on the protective layer, the scribe groove being used to position and divide the wafer.

[0014] In some embodiments, depositing polyimide on the side of the passivation layer away from the second surface includes: introducing polyimide gas into a reaction chamber, and depositing the polyimide on the side of the passivation layer away from the second surface by chemical vapor deposition.

[0015] In some embodiments, the predetermined thickness is greater than or equal to 8 micrometers and less than or equal to 12 micrometers.

[0016] In certain embodiments, the reaction chamber includes an inert gas.

[0017] In certain embodiments, the atmospheric pressure in the reaction chamber is less than or equal to one atmosphere.

[0018] In some embodiments, curing the polyimide to form the protective layer includes: curing the polyimide for a first time at a first preset temperature and a first preset time; and curing the polyimide for a second time at a second preset temperature and a second preset time to form the protective layer.

[0019] In some embodiments, the first preset temperature is greater than or equal to 100°C and less than or equal to 250°C.

[0020] In some embodiments, the first preset duration is greater than or equal to 10 minutes and less than or equal to 30 minutes.

[0021] In some embodiments, the second preset temperature is greater than or equal to 300°C and less than or equal to 400°C.

[0022] In some embodiments, the second preset time period is greater than or equal to 10 hours and less than or equal to 20 hours.

[0023] In some embodiments, the second hole and the scribe groove are formed on the protective layer, including: coating a photoresist on the side of the protective layer away from the passivation layer, exposing and developing through a mask to form a developing layer on the side of the protective layer away from the passivation layer, a portion of the area not covered by the developing layer is aligned with the first hole, and a portion of the area is aligned with the scribe groove; and etching the area of ​​the protective layer not covered by the developing layer on the side of the protective layer away from the passivation layer to form the second hole and the scribe groove.

[0024] In some embodiments, a wafer is provided, including: inspecting, cleaning and drying the second side of the wafer to remove impurities located on the second side; thinning the first side to control the thickness of the wafer to a preset packaging thickness.

[0025] In certain embodiments, the molding layer includes a molding compound and a softener doped in the molding compound, and a weight ratio of the molding compound to the softener is 19:1.

[0026] In certain embodiments, the softener is made of insoluble silicone.

[0027] In the semiconductor package, semiconductor device, electronic device and method for manufacturing the semiconductor package of the present application, a protective layer is added to the passivation layer of the semiconductor package. Since the hardness of the protective layer is less than that of the plastic layer, the protective layer can buffer the packaging stress generated by the curing of the plastic layer during the packaging process, reduce the packaging stress transmitted to the semiconductor chip, and thus improve the reference voltage offset and functional abnormality problems of the semiconductor chip caused by the packaging stress.

[0028] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0030] Figure 1 is a schematic structural diagram of a semiconductor package according to some embodiments of the present application;

[0031] Figure 2 is a schematic diagram of the structure of an electronic device in some embodiments of the present application;

[0032] Figure 3 is a schematic structural diagram of a wafer in some embodiments of the present application;

[0033] Figure 4 yes Figure 1 An exemplary process diagram of a semiconductor package is shown;

[0034] Figure 5 yes Figure 1 An exemplary process diagram of a semiconductor package is shown;

[0035] Figure 6 yes Figure 1 An exemplary process diagram of a semiconductor package is shown;

[0036] Figure 7 yes Figure 1 An exemplary process diagram of a semiconductor package is shown;

[0037] Figure 8 yes Figure 1 An exemplary process diagram of a semiconductor package is shown;

[0038] Fig. 9 yes Figure 1 An exemplary process diagram of a semiconductor package is shown;

[0039] Fig.10 It is a normal distribution diagram of the reference voltage of the semiconductor package before and after packaging in the prior art;

[0040] Fig.11 It is a scatter plot of the reference voltage of the semiconductor package of the present application before and after packaging.

[0041] Description of main component numbers:

[0042] Electronic device 10000; semiconductor device 1000; semiconductor package 100;

[0043] Wafer 10, first surface 101; second surface 102, conductive area 1021;

[0044] Semiconductor chip 20;

[0045] Passivation layer 11, first hole 111; conductive layer 13, device layer 15, substrate 17;

[0046] Protective layer 30; second hole 31, scribe groove 33; plastic layer 50, conductive member 70; first end 71; second end 72; developing layer 80;

[0047] Substrate 90 ; Strip 91 . DETAILED DESCRIPTION

[0048] In the description of the present application, some of the disclosed contents have been shown in the accompanying drawings accordingly, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The contents described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0049] In the description of the present application, many different contents or examples are disclosed to realize different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application.

[0050] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0051] In the description of the present application, it should be understood that the terms used to indicate orientation or positional relationships (such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc.) are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and facilitating the understanding of the corresponding embodiments, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms used to indicate orientation or positional relationships cannot be understood as limitations on the present application.

[0052] In the description of the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes the first feature being directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0053] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection. It can be a mechanical connection or an electrical connection. It can be directly connected or indirectly connected through an intermediate medium. It can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0054] Voltage Reference (VR) usually refers to a high-stability voltage source used as a voltage reference in semiconductor chips. The stability of the reference voltage directly affects the performance and accuracy of semiconductor chips. Factors that determine the stability of the reference voltage include semiconductor chip design architecture, design technology, and manufacturing process. For applications that require high-precision voltage references, such as analog signal processing, sensor measurement, etc., the drift of the reference voltage may cause calculation errors, data loss, performance degradation, or cause unstable chip operation.

[0055] At present, the commonly used methods to solve the reference voltage drift of semiconductor chips are temperature compensation and self-calibration technology. Temperature compensation is achieved by integrating the temperature sensor with the reference voltage source of the semiconductor chip, and using the temperature sensor to measure the change in ambient temperature to compensate for the reference voltage. However, temperature compensation requires additional circuit complexity, and its compensation accuracy is affected by the accuracy of the temperature sensor itself. Internal calibration technology solves the problem of reference voltage drift by calibrating the circuit inside the semiconductor chip. Internal calibration technology can achieve higher accuracy and is not affected by the external environment. However, calibration technology requires additional circuit area and power consumption, and for some special application scenarios, such as high temperature and high voltage, calibration technology may fail.

[0056] See also Figure 1Based on the above problems, the semiconductor package 100 provided in the present application includes a semiconductor chip 20, a protective layer 30, a plastic encapsulation layer 50 and a conductive member 70. The semiconductor chip 20 includes a first surface 101 and a second surface 102 opposite to each other. The semiconductor chip 20 also includes a passivation layer 11, which covers the second surface 102 and has a conductive area 1021. The protective layer 30 is arranged on the side of the passivation layer 11 away from the semiconductor chip 20, and the conductive area 1021 is exposed. The semiconductor chip 20 is arranged on a substrate 90, the first surface 101 is connected to the substrate 90, the plastic encapsulation layer 50 at least covers the side of the protective layer 30 away from the passivation layer 11, and the hardness of the plastic encapsulation layer 50 is greater than the hardness of the protective layer 30. The conductive member 70 includes a first end 71 and a second end 72 opposite to each other. The first end 71 is electrically connected to the conductive area 1021 after passing through the protective layer 30, and the second end 72 is connected to the substrate 90.

[0057] The conductive area 1021 is used to electrically connect to an external element (such as the strip 91 on the substrate 90) through the conductive member 70 to transmit signals. The passivation layer 11 is used to isolate the semiconductor chip 20 from external electrical signals, avoid interference with electrical signals, and improve the working performance and stability of the chip. The passivation layer 11 can also reduce the resistance of the second side 102 of the semiconductor chip 20, improve the conductivity of the conductive area 1021, and reduce energy loss. In addition, the passivation layer 11 can prevent the semiconductor chip 20 and the conductive member 70 from reacting with oxygen, water and other substances in the external environment, play an anti-corrosion role, and thus extend the service life of the semiconductor package 100. The material of the passivation layer 11 can be a material with good insulation and chemical stability such as silicon nitride or silicon oxide. Preferably, the passivation layer 11 of the present application is Tetraethoxysilane and / or Silicon nitride, tetraethoxysilane and silicon nitride are a kind of rigid material with high hardness and wear resistance, which can provide sufficient protection for the semiconductor chip 20. The passivation layer 11 covers at least the second surface 102 and exposes the conductive area 1021. The conductive member 70 can be electrically connected to the conductive area 1021 after passing through the protective layer 30, so as to realize the electrical connection between the semiconductor chip 20 and the external components. The conductive member 70 includes but is not limited to conductive columns, metal leads (usually gold wires or copper wires) or metal bumps and other components that can realize electrical connection.

[0058] In an embodiment of the present application, when packaging to form a semiconductor package 100, the first end 71 of the conductive member 70 is connected to the conductive area 1021, and the second end 72 of the conductive member 70 is connected to the strip 91 on the substrate 90. Then, the plastic encapsulation layer 50 will wrap the entire semiconductor chip 20 and the metal wire and cover at least one side of the substrate 90 close to the semiconductor chip 20.

[0059] The plastic encapsulation layer 50 is used to seal and protect the semiconductor chip 20 and other components (such as conductive parts). However, stress will be generated during the curing process of the plastic encapsulation material of the plastic encapsulation layer 50. If the plastic encapsulation material directly contacts the passivation layer, the stress generated by the package will be transmitted to the conductive layer of the semiconductor chip through the passivation layer, causing deformation or fragmentation of the conductive layer, thereby affecting the electrical characteristics of the metal-oxide-semiconductor field effect transistor (MOS) and triode inside the semiconductor chip, thereby causing the reference voltage of the semiconductor package to drift and the semiconductor package to malfunction.

[0060] Therefore, the present application provides a protective layer 30 on the side of the passivation layer 11 facing away from the semiconductor chip 20. The hardness of the protective layer 30 is less than the hardness of the plastic sealing layer 50. In this way, the protective layer 30 can absorb the plastic sealing stress generated by the plastic sealing layer 50 during plastic sealing, and avoid the stress from being transferred to the conductive layer 13, thereby avoiding deformation and cracking of the conductive layer 13. Furthermore, the protective layer 30 of the present application can be a single layer or a multi-layer. In the implementation of the multi-layer protective layer 30, the materials of different layers can be different. The protective layer 30 exposes the conductive area 1021, which can protect the conductive layer 13 on the one hand, and ensure that the conductive member 70 can be electrically connected to the conductive layer 13 after passing through the protective layer 30 on the other hand.

[0061] The semiconductor package 100 of the present application adds a protective layer 30 on the passivation layer 11. Since the hardness of the protective layer 30 is less than that of the plastic layer 50, the protective layer 30 can buffer the packaging stress generated by the curing of the plastic layer 50 during the packaging process, reduce the packaging stress transmitted to the semiconductor chip 20, and thereby improve the reference voltage offset and functional abnormality problems of the semiconductor chip 20 caused by the packaging stress.

[0062] Please continue reading Figure 1 In some embodiments, the thickness of the protective layer 30 is greater than or equal to 8 micrometers and less than or equal to 12 micrometers.

[0063] Specifically, the thickness of the protective layer 30 can be 8 microns, 8.2 microns, 8.9 microns, 9.1 microns, 9.6 microns, 10.1 microns, 10.8 microns, 11.3 microns, 11.5 microns or 12 microns. If the thickness of the protective layer is less than 8 microns, the protective layer cannot provide physical protection for the semiconductor chip 20, resulting in the stress in the packaging process being transmitted from the protective layer to the semiconductor chip, increasing the risk of semiconductor damage, and easily causing the reference voltage of the semiconductor package to drift. If the thickness of the protective layer is greater than 12 microns, the protective layer is too thick, resulting in a waste of material. Therefore, the thickness of the protective layer 30 is greater than or equal to 8 microns and less than or equal to 12 microns. On the one hand, it can provide sufficient protection for the semiconductor chip 20 to avoid the stress in the packaging process from being transmitted from the protective layer 30 to the semiconductor chip 20, and on the other hand, it also avoids the waste of material.

[0064] Please continue reading Figure 1 In some embodiments, the protective layer 30 is made of polyimide.

[0065] Specifically, on the one hand, polyimide has high thermal stability, high temperature resistance of more than 400°C, and will not crack at -40°C. Second, polyimide has good resistance to a variety of chemical substances and can protect the semiconductor chip 20 from chemical corrosion. In addition, polyimide has good insulation performance and can effectively isolate current, prevent short circuits and electrical failures in the semiconductor chip 20, thereby improving the safety of the semiconductor package 100. In addition, polyimide is relatively lightweight, and the protective layer 30 made of polyimide helps to reduce the weight of the semiconductor package 100.

[0066] Please continue reading Figure 1 In some embodiments, the molding layer 50 includes a molding compound and a softener doped in the molding compound, and the weight ratio of the molding compound to the softener is 19:1.

[0067] Specifically, the molding compound can be selected from materials with certain mechanical strength and temperature resistance such as epoxy resin or polyurethane. The softener can improve the flexibility of the molding compound, increase the elasticity and softness of the molding compound, and reduce the stress after the molding compound is cured. The ratio of the molding compound to the softener is 19:1, which can not only ensure the strength of the molding layer 50, but also make it have good flexibility and adapt to the temperature and pressure changes in different working environments. If the proportion of the molding compound is too high, the molding layer may be too hard, resulting in brittle cracking of the semiconductor package 100; and if the proportion of the softener is too high, the strength of the molding layer may be insufficient, resulting in the inability to effectively protect the internal semiconductor chip 20. Therefore, the weight ratio of the molding compound to the softener is 19:1, which can enhance the toughness of the semiconductor package 100 on the basis of maintaining high strength, and ensure the long-term stability and reliability of the molding layer 50 in a variety of usage scenarios. In some embodiments, the softener is made of insoluble siloxane. Insoluble siloxane has good heat resistance and chemical resistance, and helps to maintain the heat resistance and good electrical insulation performance of the plastic packaging layer 50 .

[0068] Please continue reading Figure 1 In some embodiments, the semiconductor chip 20 further includes a substrate 17, a device layer 15, and a conductive layer 13. The substrate 17 includes a first surface 101. The device layer 15 is disposed on a side of the substrate 17 away from the first surface 101. The conductive layer 13 is disposed on a side of the device layer 15 away from the substrate 17, and the conductive region 121 is electrically connected to the conductive layer 13. The conductive layer 13 includes a multi-layer metal structure, and the multi-layer metal structure is connected through a through hole of a low dielectric material.

[0069] The substrate 17 is the base layer of the semiconductor chip 20, and is used to provide support and mechanical stability to other layer structures of the semiconductor chip 20. The substrate 17 may be, for example, silicon (Si), gallium nitride (GaN) or other high thermal conductivity materials. The substrate 17 of the present application is pure silicon. The pure silicon substrate 17 has sufficient strength and rigidity, and can also effectively dissipate heat to reduce the heat generated by the semiconductor chip 20 during operation. The device layer 15 is an active layer in the semiconductor chip 20, and is arranged on the side of the substrate 17 away from the first surface 101. The device layer 15 is used to integrate the functions of various electronic devices, including but not limited to transistors, diodes, or photodiodes. The material of the device layer 15 may be doped silicon, gallium arsenide (GaAs), etc., which is not limited in the present application.

[0070] The conductive layer 13 is arranged on the side of the device layer 15 away from the substrate 17, and is used to realize the electrical connection between the semiconductor chip 20 and the external components to transmit signals and currents. The conductive layer 13 includes a multi-layer metal structure, and low-dielectric materials (low-K materials) are filled between the multi-layer metal structures. The metal structures of different layers are connected through through holes of the low-dielectric materials. That is, the conductive layer 13 uses a multi-molecular material with a lower dielectric constant to replace the traditional silicon dioxide as a filler between the metal layers. In this way, the parasitic resistance, capacitance and inductance of the conductive layer 13 can be reduced, while ensuring that the conductive layer 13 has good insulation properties.

[0071] See also Figure 1 and Figure 2 The present application also provides a semiconductor device 1000 , and the semiconductor device 1000 includes the semiconductor package 100 of any one of the above-mentioned embodiments.

[0072] Specifically, the semiconductor device 1000 includes but is not limited to a circuit board, etc., and the semiconductor package 100 can be integrated into the semiconductor device 1000. The semiconductor package 100 of the semiconductor device 1000 of the present application adds a protective layer 30 between the passivation layer 11 and the plastic layer 50. Since the hardness of the protective layer 30 is less than the hardness of the plastic layer 50, the protective layer 30 can buffer the packaging stress generated by the curing of the plastic layer 50 during the packaging process, reduce the packaging stress transmitted to the semiconductor chip 20, and thus improve the reference voltage offset and functional abnormality problems of the chip caused by the packaging stress.

[0073] See also Figure 1 and Figure 2 The present application also provides an electronic device 10000, and the electronic device 10000 includes the semiconductor device 1000 of any one of the above-mentioned embodiments.

[0074] Among them, electronic device 10000 includes but is not limited to mobile phones, tablet computers, smart bracelets, smart watches, laptops, desktop computers, electric toothbrushes, or consumer electronic products such as drones. Electronic device 1000 also includes but is not limited to vehicles, ships, high-speed railways, trains, airplanes and other means of transportation.

[0075] The semiconductor package 100 of the electronic device 10000 of the present application adds a protective layer 30 between the passivation layer 11 and the plastic layer 50. Since the hardness of the protective layer 30 is less than the hardness of the plastic layer 50, the protective layer 30 can buffer the packaging stress generated by the curing of the plastic layer 50 during the packaging process, reduce the packaging stress transmitted to the semiconductor chip 20, and thereby improve the reference voltage offset and functional abnormality problems of the chip caused by the packaging stress.

[0076] The present application also provides a method for manufacturing a semiconductor package 100, the manufacturing method comprising:

[0077] 03: Please refer to Figure 3 , providing a wafer 10, the wafer 10 comprising a first surface 101 and a second surface 102 opposite to each other, the wafer 10 further comprising a passivation layer 11, the passivation layer 11 covers the second surface 102 and exposes a first hole 111 having a conductive area 1021;

[0078] 05: Please refer to Figure 4 and Figure 5 , forming a protection layer 30 having a preset thickness on the passivation layer 11, wherein the protection layer 30 has a second hole 31, and the second hole 31 is aligned with the first hole 111;

[0079] 07: Please refer to Figure 7 and Figure 8 , dividing the wafer 10 based on the scribe lines 33 of the wafer 10 to obtain semiconductor chips 20 formed with the protection layer 30;

[0080] 08: Please refer to Fig. 9 , forming a conductive member 70, so that the first end 71 of the conductive member 70 passes through the second hole 31 and is electrically connected to the conductive region 1021, and the second end 72 of the conductive member 70 is connected to the substrate 90; and

[0081] 09: Please refer to Figure 1 A plastic encapsulation layer 50 is formed at least on one side of the protection layer 30 away from the passivation layer 11 to obtain a semiconductor package 100 , and the hardness of the plastic encapsulation layer 50 is greater than that of the protection layer 30 .

[0082] After the following steps, the wafer 10 will be divided into semiconductor chips 20. In the method of 03, the wafer 10 already has a passivation layer 11, a substrate 17, a device layer 15 and a conductive layer 13. The structural characteristics of each layer are consistent with the above-mentioned semiconductor chip 20 and will not be repeated. Among them, the passivation layer 11 also has a first hole 111. The first hole 111 is filled with a conductive material as a conductive area 1021, and the conductive area 1021 is connected to the conductive layer 13. The first hole 111 can be one or more. The passivation layer 11 can be formed on the second surface 102 by methods such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), thereby effectively protecting the conductive area 1021.

[0083] In the semiconductor packaging method, a protective layer 30 with a preset thickness is first deposited on the passivation layer 11 of the wafer 10, and a second hole 31 connected to the conductive area 1021 on the passivation layer 11 is provided on the protective layer 30. The main function of the protective layer 30 is to provide additional physical protection for the semiconductor chip 20 to prevent the packaging stress from damaging the semiconductor chip 20. The thickness of the protective layer 30 needs to meet the preset thickness. Subsequently, the present application uses the scribe groove 33 on the wafer 10 as a guide to cut the wafer 10 into individual semiconductor chips 20 to ensure the integrity and size consistency of each semiconductor chip 20. Further, the conductive member 70 passes through the second hole 31 of the protective layer 30 to establish an electrical connection with the conductive area 1021 on the semiconductor chip 20. The conductive member 70 is usually made of a metal material such as aluminum or copper, and the connection between the conductive member 70 and the conductive area 1021 is ensured to be stable through processes such as metal evaporation, sputtering or welding. Finally, a plastic encapsulation layer 50 is formed on the outer side of the protective layer 30. More specifically, the first end 71 of the conductive member 70 is connected to the conductive area 1021, and the second end 72 of the conductive member 70 is connected to the strip 91 on the substrate 90. Then, the plastic encapsulation layer 50 will wrap the entire semiconductor chip 20 and the metal wire and cover at least one side of the substrate 90 close to the semiconductor chip 20. In the present application, the plastic encapsulation layer 50 covers all parts of the semiconductor chip 20 except the first side 101, and wraps the conductive member 70, so that the semiconductor chip 20 and the conductive member 70 are isolated from the external environment.

[0084] The molding of the plastic layer 50 can be completed by mold injection or hot pressing process to ensure the sealing and durability of the package, thereby protecting the semiconductor chip 20 from the influence of the external environment and ensuring its long-term stable operation.

[0085] The semiconductor package 100 of the semiconductor device 1000 adds a protective layer 30 between the passivation layer 11 and the plastic layer 50. Since the hardness of the protective layer 30 is less than that of the plastic layer 50, the protective layer 30 can buffer the packaging stress generated by the curing of the plastic layer 50 during the packaging process, reduce the packaging stress transmitted to the semiconductor chip 20, and thereby improve the reference voltage offset and functional abnormality problems of the chip caused by the packaging stress.

[0086] In some embodiments, the protective layer 30 is made of polyimide. 05: forming a protective layer 30 having a preset thickness on the passivation layer 11, the protective layer 30 having a second hole 31, and the second hole 31 is aligned with the first hole 111, comprising:

[0087] 051: depositing polyimide on the side of the passivation layer 11 facing away from the second surface 102;

[0088] 053: Curing the polyimide to form a protective layer 30 having a preset thickness;

[0089] 055: A second hole 31 and a scribe line 33 are opened on the protection layer 30 . The scribe line 33 is used for positioning and dividing the wafer 10 .

[0090] See also Figure 1 and Figure 4 In the method of 051, polyimide is formed on the side of the passivation layer 11 away from the second surface 102 by deposition, and the molecular chains of the polyimide can form a dense film layer, thereby providing better protection for the semiconductor chip 20.

[0091] See also Figure 4 In the method of 053, curing refers to the process of cross-linking the polymer chains of polyimide by heating or light to form a stable three-dimensional network structure to ensure the durability and stability of the protective layer 30 while ensuring its mechanical strength and chemical resistance. The curing conditions need to be controlled to avoid affecting the performance of the protective layer 30 due to insufficient curing. The curing conditions include but are not limited to reaction temperature and reaction time. The cured polyimide protective layer 30 can provide good physical protection for the conductive layer 13, and can also withstand higher temperatures and pressures, thereby improving the stability of the semiconductor seal.

[0092] See also Figure 1 , Figure 3 , Figure 5 and Figure 6 In the method of 055, a second hole 31 and a scribe groove 33 are opened on the protective layer 30, and the scribe groove 33 is used to locate and divide the wafer 10. The second hole 31 is opened to ensure that the conductive member 70 can pass through the protective layer 30 and connect with the first hole 111 of the passivation layer 11, thereby achieving good electrical connection. The scribe groove 33 is a mark for dividing the wafer 10, ensuring that the wafer 10 is cut into individual semiconductor chips 20 in the subsequent dicing process.

[0093] See also Figure 3 and Figure 4 In some embodiments, 051: depositing polyimide on a side of the passivation layer 11 away from the second surface 102, comprising:

[0094] 0511: Introduce polyimide gas into the reaction chamber, and deposit polyimide on the side of the passivation layer 11 facing away from the second surface 102 by chemical vapor deposition.

[0095] Specifically, in the method of 0511, the present application introduces polyimide gas into a reaction chamber for chemical vapor deposition, and chemical vapor deposition can achieve molecular-level deposition, ensuring that polyimide is uniformly deposited on the surface of the passivation layer 11 to form a protective layer 30 that meets a preset thickness. In addition, the reaction process of chemical vapor deposition can be precisely controlled, thereby effectively adjusting the deposition rate of polyimide and the thickness of the protective layer 30. The present application uses a thermal evaporator as a deposition tool, which can promote the reaction of polyimide gas by heating the substrate in the reaction chamber, so that the polyimide gas is deposited on the surface of the passivation layer 11.

[0096] See also Figure 3 and Figure 4 In some embodiments, the preset thickness is greater than or equal to 8 microns and less than or equal to 12 microns.

[0097] Specifically, the preset thickness of the protective layer 30 may be 8 microns, 8.2 microns, 8.9 microns, 9.1 microns, 9.6 microns, 10.1 microns, 10.8 microns, 11.3 microns, 11.5 microns or 12 microns. If the preset thickness of the protective layer 30 is less than 8 microns, the protective layer 30 cannot provide physical protection for the semiconductor chip 20, causing the stress in the packaging process to be transmitted from the protective layer 30 to the semiconductor chip 20, increasing the risk of semiconductor damage, and easily causing the reference voltage of the semiconductor package 100 to drift. If the preset thickness of the protective layer 30 is greater than 12 microns, the protective layer 30 is too thick, resulting in a waste of material.

[0098] The preset thickness of the protective layer 30 is greater than or equal to 8 microns and less than or equal to 12 microns. On the one hand, it can provide sufficient protection for the semiconductor chip 20 to prevent the stress in the packaging process from being transmitted from the protective layer 30 to the semiconductor chip 20, and on the other hand, it also avoids material waste.

[0099] See also Figure 3 and Figure 4 In some embodiments, the reaction chamber includes an inert gas as a protective gas to prevent oxidation of the wafer 10. The protective gas includes, but is not limited to, nitrogen or helium. During the deposition of polyimide, the inert gas can provide an oxygen-free environment, reduce the introduction of oxygen in the chemical reaction, thereby reducing the risk of oxidation of the wafer 10 in the reaction chamber, and ensure that the electrical performance of the semiconductor package 100 finally manufactured is not damaged.

[0100] See also Figure 3 and Figure 4In some embodiments, the atmospheric pressure in the reaction chamber is less than or equal to one atmosphere. The pressure reduction in the reaction chamber can reduce the collision frequency of polyimide gas molecules, thereby improving the deposition uniformity of polyimide, helping to obtain a more uniform thickness of the protective layer 30 and a better deposition effect, ensuring that the protective layer 30 finally formed has good compactness and uniformity.

[0101] See also Figure 3 and Figure 4 In some embodiments, 053: curing the polyimide to form a protective layer 30 comprises:

[0102] 0531: curing the polyimide for the first time at a first preset temperature and a first preset time; and

[0103] 0533: Curing the polyimide for the second time at a second preset temperature and a second preset time to form a protective layer 30.

[0104] Specifically, the method of 0531 and the method of 0533 are implemented using the resistance heating plate of the thermal evaporator. Other devices may be used in other embodiments of the present application. The resistance heating plate can provide a stable and uniform heat source to ensure that the polyimide can fully react during the curing process and form a highly cross-linked polyimide network structure. Thereby enhancing the mechanical strength and heat resistance of the protective layer 30 and improving the service life of the protective layer 30. The method of 0531 is used to preliminarily cure the polyimide to form a substrate, and the process of preliminary curing helps to control the thickness of the protective layer 30. The method of 0533 is a second curing to further increase the degree of cross-linking of the polyimide and ensure the mechanical strength and heat resistance of the protective layer 30.

[0105] See also Figure 3 and Figure 4 In some embodiments, the first preset temperature is greater than or equal to 100°C and less than or equal to 250°C.

[0106] Specifically, the first preset temperature may be 100°C, 110°C, 120°C, 140°C, 160°C, 180°C, 200°C, 220°C, 240°C or 250°C. If the first preset temperature is lower than 100°C, the curing temperature is too low, which may easily lead to insufficient mechanical strength of the protective layer 30; if the first preset temperature exceeds 250°C, it may cause thermal degradation or damage of the polyimide, thereby affecting the reliability of the semiconductor package 100. The first preset temperature is greater than or equal to 100°C and less than or equal to 250°C, which can cure the polyimide and form a uniform protective layer 30 with sufficient strength.

[0107] See also Figure 3 and Figure 4In some embodiments, the first preset duration is greater than or equal to 10 minutes and less than or equal to 30 minutes.

[0108] Specifically, the first preset time can be set to 10 minutes, 12 minutes, 14 minutes, 16 minutes, 18 minutes, 20 minutes, 22 minutes, 24 minutes, 26 minutes or 30 minutes. If the first preset time is less than 10 minutes, the protective layer 30 may not be completely cross-linked, affecting its mechanical properties and chemical resistance; if the first preset time is less than 10 minutes, the curing time is too long, which may increase energy consumption and cause excessive aging of the material. The first preset time is greater than or equal to 10 minutes and less than or equal to 30 minutes to ensure that the polyimide is fully cured at the set temperature to form an ideal protective layer 30.

[0109] See also Figure 3 and Figure 4 In some embodiments, the second preset temperature is greater than or equal to 300°C and less than or equal to 400°C.

[0110] Specifically, the second preset temperature may be 300° C., 310° C., 320° C., 340° C., 360° C., 370° C., 376° C., 380° C., 390° C. or 400° C. If the temperature is lower than 300° C., the desired curing effect may not be achieved, while a temperature exceeding 400° C. may cause thermal degradation of the polyimide material. The second preset temperature being greater than or equal to 300° C. and less than or equal to 400° C. helps to ensure the curing and chemical stability of the polyimide.

[0111] See also Figure 3 and Figure 4 In some embodiments, the second preset duration is greater than or equal to 10 hours and less than or equal to 20 hours.

[0112] Specifically, the second preset time can be set to 10 hours, 11 hours, 12 hours, 13 hours, 14 hours, 15 hours, 16 hours, 17 hours, 18 hours or 20 hours. If the second preset time is less than 10 hours, the polyimide may not meet the required performance standards; if the second preset time is greater than 20 hours, it will lead to reduced production efficiency and waste of resources. Therefore, the second preset time is greater than or equal to 10 hours and less than or equal to 20 hours, which helps to ensure that the polyimide is fully cured and ensure production efficiency.

[0113] See also Figure 1 , Figure 3 , Figures 4 to 5 In some embodiments, 055: opening a second hole 31 and a scribe groove 33 on the protective layer 30, including:

[0114] 0551: coating a photoresist on the side of the protective layer 30 away from the passivation layer 11, exposing and developing through a mask to form a developing layer 80 on the side of the protective layer 30 away from the passivation layer 11, wherein a portion of the area not covered with the developing layer 80 is aligned with the first hole 111, and a portion of the area is aligned with the scribe groove 33; and

[0115] 0553: On the side of the protection layer 30 facing away from the passivation layer 11 , the area of ​​the protection layer 30 not covered by the developing layer 80 is etched to form a second hole 31 and a scribe groove 33 .

[0116] See also Figure 5 and Figure 6 Specifically, in the 0551 method, photoresist is coated on the side of the protective layer 30 away from the passivation layer 11, wherein the area where the second hole 31 and the scribe groove 33 are to be formed is not coated with photoresist. When a contact photolithography machine is used for exposure, the light source is projected onto the photoresist through the mask plate, causing a chemical change in the photoresist area not blocked by the mask plate; then, the photoresist is removed by a developer to form the required development layer 80.

[0117] See also Figure 6 and Fig. 9 In the method of 0553, the etcher selectively etches the protective layer 30, and can remove the area not protected by the photoresist (i.e., the area not covered by the developing layer 80), thereby forming the first hole 111 and the scribe groove 33 on the protective layer 30 to meet the requirements of the subsequent installation of the conductive part 70 and the division of the wafer 10, thereby ensuring the connection of the conductive part 70 and the division and positioning of the wafer 10 in the subsequent process.

[0118] In some embodiments, 03: Provide a wafer 10, including:

[0119] 031: Inspect, clean and dry the second surface 102 of the wafer 10 to remove impurities on the second surface 102;

[0120] 032: Thinning the first surface 101 to control the thickness of the wafer 10 to a preset packaging thickness.

[0121] In the method of 031, before the protective layer 30 is formed on the wafer 10, the wafer 10 needs to be pretreated. First, the wafer 10 needs to be inspected by an electron microscope to identify impurities and defects on the surface of the wafer 10 to ensure that the surface quality of the second side 102 meets the requirements. Then, appropriate chemical solvents and detergents are used to clean the second side 102 using a wafer 10 cleaning machine to effectively remove dirt, grease and other impurities on the surface of the wafer 10 that may affect subsequent processing. Finally, the cleaning liquid remaining on the surface of the wafer 10 is removed through a drying process to ensure that the second side 102 is dry and clean. Pre-treating the wafer 10 can improve the quality of the second side 102 of the wafer 10, reduce defects that may occur in the subsequent packaging process, and ensure the performance and reliability of the wafer 10.

[0122] See also Figure 2 , Figure 6 and Figure 7 In the present application, after the protective layer 30 is formed on the wafer 10, the thickness is about 700um, while the preset package thickness of the semiconductor package 100 is 150-250um. Therefore, the thickness of the wafer 10 needs to be controlled within the preset package thickness. In the method of 032, mechanical grinding or chemical mechanical polishing technology can be used to uniformly thin the first surface 101 of the wafer 10 to control the thickness of the wafer 10 within the preset package thickness.

[0123] In some embodiments, the molding layer 50 includes a molding compound and a softener doped in the molding compound, and the weight ratio of the molding compound to the softener is 19:1.

[0124] Specifically, the molding compound can be selected from materials with certain mechanical strength and temperature resistance such as epoxy resin or polyurethane. The softener can improve the flexibility of the molding compound, increase the elasticity and softness of the molding compound, and reduce the stress of the molding compound after curing. The ratio of the molding compound to the softener is 19:1, which can not only ensure the strength of the molding layer 50, but also make it have good flexibility to adapt to the temperature and pressure changes in different working environments. If the proportion of the molding compound is too high, the molding layer 50 may be too hard, resulting in brittle cracking of the semiconductor package 100; and if the proportion of the softener is too high, the strength of the molding layer 50 may be insufficient, resulting in the inability to effectively protect the internal semiconductor chip 20. Therefore, the weight ratio of the molding compound to the softener is 19:1, which can enhance the toughness of the semiconductor package 100 on the basis of maintaining high strength, and ensure the long-term stability and reliability of the molding layer 50 in a variety of usage scenarios. In some embodiments, the softener is made of insoluble siloxane. Insoluble siloxane has good heat resistance and chemical resistance, and helps to maintain the heat resistance and good electrical insulation performance of the plastic packaging layer 50 .

[0125] After the manufacturing method of the semiconductor package 100 is completed, the present application performs CP tests on different semiconductor packages 100 . Fig.10 The normal distribution diagram of the reference voltage measured before and after packaging is shown for about 1000 semiconductor packages 100 without a protective layer 30, wherein the ordinate is the reference voltage of the semiconductor package 100 and the abscissa is the number of the semiconductor package 100. It can be seen that the reference voltage distribution of the semiconductor package 100 without a protective layer 30 after packaging is more divergent than that before packaging, wherein the chip with an offset exceeding + / -0.05V will also show functional abnormality.

[0126] Fig.11 The semiconductor package 100 provided with the protective layer 30 of the present application is a scatter plot of the reference voltage measured before and after packaging, the ordinate is the reference voltage of the semiconductor package 100, and the abscissa is the number of the semiconductor package 100. Among them, area I is the reference voltage measured after packaging of the semiconductor package 100 with a protective layer 30 thickness of 8um, area II is the reference voltage measured after packaging of the semiconductor package 100 with a protective layer 30 thickness of 10um, and area III is the reference voltage measured before packaging of the semiconductor package 100. It can be seen that the difference between the reference voltages of area I and area II is very small compared with area III. Therefore, it can be explained that the semiconductor package 100 of the present application, by adding a protective layer 30 between the passivation layer 11 and the plastic sealing layer 50, can buffer the packaging stress generated by the curing of the plastic sealing layer 50 and transmitted to the semiconductor chip 20 during the packaging process, thereby improving the reference voltage offset and functional abnormality problems caused by the packaging stress of the chip.

[0127] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments of the present application without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A semiconductor package, characterized in that: include: A semiconductor chip, comprising a first surface and a second surface opposite to each other, the semiconductor chip further comprising a passivation layer, the passivation layer covering the second surface and having a conductive region; A protective layer, disposed on a side of the passivation layer away from the semiconductor chip and exposing the conductive area; A plastic encapsulation layer, at least covering a side of the protective layer away from the passivation layer, wherein the hardness of the plastic encapsulation layer is greater than that of the protective layer; a substrate, the semiconductor chip being disposed on the substrate, the first surface being connected to the substrate; and The conductive member comprises a first end and a second end opposite to each other, wherein the first end is electrically connected to the conductive area after passing through the protective layer, and the second end is connected to the substrate.

2. The semiconductor package according to claim 1, wherein: The thickness of the protective layer is greater than or equal to 8 micrometers and less than or equal to 12 micrometers.

3. The semiconductor package according to claim 1, wherein: The protective layer is made of polyimide.

4. The semiconductor package according to claim 1, wherein: The molding layer includes a molding compound and a softener doped in the molding compound, and the weight ratio of the molding compound to the softener is 19:

1.

5. The semiconductor package according to claim 4, wherein: The softener is made of insoluble silicone.

6. The semiconductor package according to any one of claims 1 to 5, characterized in that: The semiconductor chip further comprises: a substrate, comprising the first surface; a device layer, disposed on a side of the substrate facing away from the first surface; and The conductive layer is arranged on the side of the device layer away from the substrate. The conductive region is electrically connected to the conductive layer. The conductive layer includes a multi-layer metal structure. The multi-layer metal structure is connected through a through hole of a low dielectric material.

7. A semiconductor device, characterized in that: A semiconductor package comprising any one of claims 1 to 6.

8. An electronic device, characterized in that: A semiconductor device comprising the semiconductor device according to claim 7.

9. A method for manufacturing a semiconductor package, characterized in that: include: A wafer is provided, the wafer comprising a first surface and a second surface opposite to each other, the wafer further comprising a passivation layer, the passivation layer covers the second surface and exposes a first hole having a conductive area; forming a protective layer having a preset thickness on the passivation layer, wherein the protective layer has a second hole, and the second hole is aligned with the first hole; Dividing the wafer based on the scribe lines of the wafer to obtain semiconductor chips with the protective layer formed thereon; forming a conductive member, so that a first end of the conductive member is electrically connected to the conductive region after passing through the second hole, and a second end of the conductive member is connected to the substrate; and A plastic encapsulation layer is formed at least on one side of the protective layer away from the passivation layer to obtain the semiconductor package, and the hardness of the plastic encapsulation layer is greater than the hardness of the protective layer.

10. The manufacturing method according to claim 9, characterized in that: The protective layer is made of polyimide; the protective layer having a preset thickness is formed on the passivation layer, the protective layer has a second hole, and the second hole is aligned with the first hole, comprising: Depositing polyimide on a side of the passivation layer facing away from the second surface; Curing the polyimide to form the protective layer having a predetermined thickness; and The second hole and the scribe groove are opened on the protection layer, and the scribe groove is used for positioning and dividing the wafer.

11. The manufacturing method according to claim 10, characterized in that: Depositing polyimide on a side of the passivation layer away from the second surface, comprising: A polyimide gas is introduced into the reaction chamber, and the polyimide is deposited on a side of the passivation layer away from the second surface by chemical vapor deposition.

12. The manufacturing method according to claim 11, characterized in that: The preset thickness is greater than or equal to 8 micrometers and less than or equal to 12 micrometers.

13. The manufacturing method according to claim 11, characterized in that: The reaction chamber contains an inert gas.

14. The manufacturing method according to claim 11, characterized in that: The atmospheric pressure in the reaction chamber is less than or equal to one atmosphere.

15. The manufacturing method according to claim 10, characterized in that: The step of curing the polyimide to form the protective layer comprises: Curing the polyimide for the first time at a first preset temperature and a first preset time; and The polyimide is cured for a second time at a second preset temperature and a second preset time to form the protective layer.

16. The manufacturing method according to claim 15, characterized in that: The first preset temperature is greater than or equal to 100° C. and less than or equal to 250° C.; and / or, The first preset duration is greater than or equal to 10 minutes and less than or equal to 30 minutes; and / or, The second preset temperature is greater than or equal to 300° C. and less than or equal to 400° C.; and / or, The second preset time length is greater than or equal to 10 hours and less than or equal to 20 hours.

17. The manufacturing method according to claim 10, characterized in that: The step of opening the second hole and the scribe groove on the protective layer comprises: Coating photoresist on the side of the protective layer away from the passivation layer, exposing and developing through a mask to form a developing layer on the side of the protective layer away from the passivation layer, wherein a portion of the area not covered with the developing layer is aligned with the first hole, and a portion of the area is aligned with the scribe groove; and On a side of the protection layer away from the passivation layer, an area of ​​the protection layer not covered by the developing layer is etched to form the second hole and the scribe line.

18. The manufacturing method according to claim 9, characterized in that: A wafer is provided, comprising: Inspecting, cleaning and drying the second side of the wafer to remove impurities on the second side; and The first surface is thinned to control the thickness of the wafer to a preset packaging thickness.

19. The manufacturing method according to claim 9, characterized in that: The molding layer includes a molding compound and a softener doped in the molding compound, and the weight ratio of the molding compound to the softener is 19:

1.

20. The manufacturing method according to claim 19, characterized in that: The softener is made of insoluble silicone.

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