Package structure

Abstract

The invention provides a packaging structure. A conductive substrate is disposed over a bracket. The plurality of bonding pads are disposed on the bracket and separated from the conductive substrate. A wafer is disposed over the conductive substrate. The wafer includes first and second laterally diffused metal oxide semiconductor transistors and first and second gate drivers. The first depletion type III-V transistor is disposed over the conductive substrate and separated from the wafer. The substrate is disposed over the conductive substrate and separated from the wafer and the first depletion type III-V transistor. A second depletion type III-V transistor is disposed over the substrate. The source of the first depletion type III-V transistor is electrically connected to the drain of the first laterally diffused metal oxide semiconductor transistor, and the drain of the first depletion type III-V transistor is electrically connected to the source of the second laterally diffused metal oxide semiconductor transistor.

Description

Technical Field

[0001] The present invention relates to a packaging structure, and more particularly to a packaging structure having a tandemly connected LDMOS transistor and a depletion-type III-V transistor. Background Art

[0002] III-V transistors, such as gallium nitride field effect transistors (GaN FETs), are often used in high-power and high-performance circuit applications due to their high efficiency characteristics and suitability for high-voltage operation. In addition, III-V transistors are often combined with other transistors (such as silicon field effect transistors) to produce high-performance switching devices, such as cascoded switches.

[0003] In general packaging design, multiple components can be placed on the same supporting surface, such as a direct bonding copper (DBC) or ceramic substrate placed on a lead frame. However, placing multiple components on a supporting surface often brings many unexpected non-ideal effects, so it is necessary to avoid unexpected non-ideal effects to improve the performance of the switching device. Summary of the invention

[0004] An embodiment of the present invention provides a packaging structure. The packaging structure includes a bracket, a plurality of bonding wires, a conductive substrate, a plurality of bonding pads, a chip, a first depletion type III-V transistor, a substrate, and a second depletion type III-V transistor. The conductive substrate is disposed on the bracket. The bonding pad is disposed on the bracket and separated from the conductive substrate. The chip is disposed on the conductive substrate. The chip includes a first lateral diffused metal oxide semiconductor transistor, a first gate driver, a second lateral diffused metal oxide semiconductor transistor, and a second gate driver. The first gate driver is coupled to the gate of the first lateral diffused metal oxide semiconductor transistor. The second gate driver is coupled to the gate of the second lateral diffused metal oxide semiconductor transistor. The first depletion type III-V transistor is disposed on the conductive substrate and separated from the chip. The substrate is disposed on the conductive substrate and separated from the chip and the first depletion type III-V transistor. The second depletion type III-V transistor is disposed on the substrate. The source of the first depletion type III-V transistor is electrically connected to the drain of the first LDMOS transistor, and the drain of the first depletion type III-V transistor is electrically connected to the source of the second LDMOS transistor.

[0005] The present invention can avoid unexpected non-ideal effects to improve the efficiency of the switch device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a circuit diagram showing a half-bridge driver according to some embodiments of the present invention.

[0007] Figure 2 FIG. 2 is a diagram showing a layout configuration of a chip with a half-bridge driver according to some embodiments of the present invention.

[0008] Figure 3 FIG. 2 shows a half-bridge driving circuit according to some embodiments of the present invention.

[0009] Figure 4 It is to show that according to some embodiments of the present invention Figure 3 A top view of the packaging structure of a half-bridge drive circuit.

[0010] Reference numerals:

[0011] 12-18,22-26,32-36: nodes

[0012] 100: Half-bridge driver

[0013] 110: Input filter

[0014] 120: Anti-break circuit

[0015] 130: High-side gate driver

[0016] 140: Low-side gate driver

[0017] 150: High-side Laterally Diffused Metal Oxide Semiconductor Transistor

[0018] 170: Low-side Laterally Diffused Metal Oxide Semiconductor Transistor

[0019] 200: Chip

[0020] 210,250: Smith trigger

[0021] 212,252: Undervoltage lockout circuit

[0022] 214,264:SR latch

[0023] 216,256:Drive

[0024] 222,262: Inverter

[0025] 224,226,230,262,266: AND gate

[0026] 232:Level Shifter

[0027] 300: Half-bridge drive circuit

[0028] 310: High-side depletion III-V transistor

[0029] 320: Low-side depletion III-V transistor

[0030] 350: substrate

[0031] 400: Bracket

[0032] 410: Conductive substrate

[0033] 420,420_1-420_9: Bonding pad

[0034] 450,450_1-450_9,450_a-450_d,450_2a-450_2c,450_3a,450_3b: Bonding wire

[0035] B1, B2: Matrix

[0036] COM,VB,VDD,VPP,VS,LD,HD: voltage

[0037] CH,CL: control signal

[0038] D1-D2: Drain

[0039] EN: Input signal

[0040] ENin: filtered signal

[0041] FW: floating well region

[0042] HIN: Input signal

[0043] HINin: filtered signal

[0044] LIN: Input signal

[0045] LINin: Filtered signal

[0046] G1-G2: Gate

[0047] R1, R2: resistors

[0048] S1-S2: Source

[0049] ST: Input signal

[0050] STin: filtered signal

[0051] VSS: Ground terminal DETAILED DESCRIPTION

[0052] In order to make the above and other purposes, features, and advantages of the present invention more clearly understood, preferred embodiments are given below and described in detail with reference to the accompanying drawings.

[0053] It is understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or parts. Therefore, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of some embodiments of the present invention.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

[0055] Some embodiments of the present invention may be understood in conjunction with the drawings, and the drawings of the embodiments of the present invention are also considered as part of the description of the embodiments of the present invention. It should be understood that the drawings of the embodiments of the present invention are not drawn in proportion to the actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present invention. In addition, the structures and devices in the drawings are drawn in a schematic manner to clearly show the features of the embodiments of the present invention.

[0056] In some embodiments of the present invention, relative terms such as "lower", "upper", "horizontal", "vertical", "below", "above", "top", "bottom", etc. should be understood as the orientations shown in the paragraph and related drawings. Such relative terms are only for the convenience of explanation and do not mean that the device described therein needs to be manufactured or operated in a specific orientation. Terms related to bonding and connection, such as "connection" and "interconnection", etc., unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein there is another structure disposed between the two structures. Moreover, such terms related to bonding and connection may also include situations where both structures are movable, or both structures are fixed.

[0057] Figure 11 is a circuit diagram showing a half-bridge driver 100 according to some embodiments of the present invention. The half-bridge driver 100 includes an input filter 110, an anti shoot-through circuit 120, a high side (HS) gate driver 130, a low side (LS) gate driver 140, a high side lateral diffused metal oxide semiconductor (LDMOS) transistor 150, and a LS LDMOS transistor 170. The high side gate driver 130 is used to drive the HS LDMOS transistor 150, and the low side gate driver 140 is used to drive the LS LDMOS transistor 170.

[0058] The input filter 110 is coupled to the input nodes 12, 14, 16 and 18 for filtering the input signals EN, ST, HIN and LIN to provide a filtered signal ENin to the low-side gate driver 140, and provide filtered signals STin, HINin and LINin to the anti-punch-through circuit 120. The anti-punch-through circuit 120 provides control signals CH and CL to the high-side gate driver 130 and the low-side gate driver 140 respectively according to the filtered signals STin, HINin and LINin.

[0059] The high-side gate driver 130 includes a schmitt trigger 210, an undervoltage lockout (UVLO) circuit 212, an SR latch 214, a driver 216, an inverter 222, AND gates 224, 226 and 230, a level shifter 232 and a resistor R1. The resistor R1 is coupled between the output of the driver 216 and the gate of the HS LDMOS transistor 150. The undervoltage lockout circuit 212 and the driver 216 are coupled to nodes 24 and 34, and the nodes 24 and 34 are used to receive a voltage VB and a voltage VS, respectively. The HS LDMOS transistor 150 is coupled between the node 32 and the node 34. In other words, the voltage HD at the node 32 represents the drain voltage of the HS LDMOS transistor 150, and the voltage VS at the node 34 represents the source voltage of the HS LDMOS transistor 150. In addition, the node 34 can be further coupled to a load (not shown). In this embodiment, the high-side gate driver 130 controls the switching of the HS LDMOS transistor 150 , such as turning it on (ON) or off (OFF), according to the control signal CH and the voltages VB and VS on the nodes 24 and 34 .

[0060] The low-side gate driver 140 includes a Smith trigger 250, an undervoltage lockout circuit 252, an SR latch 254, a driver 256, an inverter 262, and gates 264 and 266, and a resistor R2. The resistor R2 is coupled between the output of the driver 256 and the gate of the LS LDMOS transistor 170. The undervoltage lockout circuit 252 and the driver 256 are coupled to nodes 22 and 26, and nodes 24 and 34 are used to receive a voltage (or power supply) VDD and a voltage COM, respectively. In some embodiments, the voltage COM is a ground voltage VSS. The LS LDMOS transistor 170 is coupled between the node 36 and the node 26. In other words, the voltage LD of the node 36 represents the drain voltage of the LS LDMOS transistor 170, and the voltage COM of the node 26 represents the source voltage of the LS LDMOS transistor 170. Furthermore, the node 36 can be further coupled to a load (not shown). In this embodiment, the low-side gate driver 140 controls the switching of the LS LDMOS transistor 170 , such as turning on or off, according to the control signal CL, the filtered signal ENin, the voltage VDD at the node 22 and the voltage COM at the node 26 .

[0061] exist Figure 1 , the high-side gate driver 130 and the low-side gate driver 140 have similar circuit configurations. Compared to the low-side gate driver 140, the high-side gate driver 130 further includes a level shifter 232. It is worth noting that the circuits of the high-side gate driver 130 and the low-side gate driver 140 are only illustrative and are not intended to limit the present invention. Any gate driver suitable for LDMOS transistors can be applied to the present invention.

[0062] In the half-bridge driver 100 , the under-voltage lockout circuit 212 , the inverter 222 , the AND gate 224 , the SR latch 214 , the high voltage portion of the level shifter 232 , the AND gate 226 , the driver 216 , the resistor R1 , and the HSLDMOS transistor 150 of the high-side gate driver 130 are formed in a floating well region FW.

[0063] refer to Figure 2 , Figure 2 2 is a layout diagram of a chip 200 having a half-bridge driver 100 according to some embodiments of the present invention. In the chip 200, the HS LDMOS transistor 150 and the high-side gate driver 130 are formed on the floating well region FW. In this embodiment, the Smith trigger 210, the AND gate 230 and the low voltage portion of the level shifter 232 of the high-side gate driver 130 are formed outside the floating well region FW. It is worth noting that the substrate of the HS LDMOS transistor 150 is connected to the floating well region FW, while the substrate of the LS LDMOS transistor 170 is grounded.

[0064] Figure 3 FIG. 3 is a diagram showing a half-bridge driving circuit 300 according to some embodiments of the present invention. The half-bridge driving circuit 300 comprises a half-bridge driver 100 , a high-side depletion mode (D mode) III-V transistor 310 , and a low-side depletion mode III-V transistor 320 .

[0065] In the half-bridge driver circuit 300, the cascoded HS LDMOS transistor 150 and the high-side depletion III-V transistor 310 form a high-side power transistor, and the cascoded LS LDMOS transistor 170 and the low-side depletion III-V transistor 320 form a low-side power transistor. In this embodiment, the high-side depletion III-V transistor 310 and the low-side depletion III-V transistor 320 are gallium nitride (GaN) high electron mobility field effect transistors (HEMTs).

[0066] The high-side depletion III-V transistor 310 includes a gate G1, a source S1, a drain D1, and a bulk B1. The drain D1 of the high-side depletion III-V transistor 310 is coupled to the node 28 for receiving the voltage (or power supply) VPP. The source S1 of the high-side depletion III-V transistor 310 is coupled to the node 32 and the drain of the HS LDMOS transistor 150. The gate G1 and the bulk B1 of the high-side depletion III-V transistor 310 are coupled to the node 34. At the same time, the bulk and source of the HS LDMOS transistor 150 are also coupled to the node 34.

[0067] The low-side depletion III-V transistor 320 includes a gate G2, a source S2, a drain D2, and a body B2. The drain D2 of the low-side depletion III-V transistor 320 is coupled to the node 34. The source S2 of the low-side depletion III-V transistor 320 is coupled to the node 36 and the drain of the LS LDMOS transistor 170. The gate G2 and the body B2 of the low-side depletion III-V transistor 320 are coupled to the node 26. At the same time, the body and source of the LS LDMOS transistor 170 are also coupled to the node 26.

[0068] Figure 4 It is to show that according to some embodiments of the present invention Figure 3FIG. 2 is a top view of the package structure of the half-bridge driving circuit 300. The package structure of the half-bridge driving circuit 300 includes a frame 400 and a high-side depletion-type III-V transistor 310, a low-side depletion-type III-V transistor 320, and a chip 200 disposed above the frame 400. A conductive substrate 410 and a plurality of bonding pads 420 are formed on the upper surface of the frame 400. In addition, the bonding pads 420 are disposed around the conductive substrate 410, and each bonding pad 420 and the conductive substrate 410 are separated from each other. In some embodiments, the conductive substrate 410 is formed by a metal layer, for example, a metal material is plated on the upper surface of the frame 400. In some embodiments, each bonding pad 420 can be an electrode formed by a metal material. In some embodiments, the frame 400 can be a lead frame. In this embodiment, the number of bonding pads 420 is for illustration only and is not intended to limit the present invention.

[0069] exist Figure 4 , a high-side depletion-type III-V transistor 310 is disposed on a substrate 350. In some embodiments, the substrate 350 may be a direct bonding copper (DBC) or a ceramic substrate. In addition, the chip 200, the substrate 350, and the low-side depletion-type III-V transistor 320 are all placed and bonded to a conductive substrate 410, and the chip 200 is separated from the substrate 350 and the low-side depletion-type III-V transistor 320. In the chip 200, each node (e.g., nodes 12-18, 22-26, and 32-36) is formed by a separate bonding pad.

[0070] As described above, the high-side depletion III-V transistor 310 includes a gate G1, a source S1, a drain D1, and a body B1. For the high-side depletion III-V transistor 310, the high-side depletion III-V transistor 310 is separated from the conductive substrate 410 via the substrate 350. The drain D1 is electrically connected to the bonding pad 420_1 corresponding to the voltage VPP through a bonding wire 450_1. The source S1 is electrically connected to the node 32 of the chip 200 (i.e., the drain of the HS LDMOS transistor 150) through a bonding wire 450_a. The gate G1 is electrically connected to the bonding pad 420_2 corresponding to the voltage VS through a bonding wire 450_2a. The body B1 is coupled to the upper surface of the substrate 350 and is electrically connected to the node 34 of the chip 200 (i.e., the source of the HS LDMOS transistor 150) through a bonding wire 450_b.

[0071] As described above, the low-side depletion III-V transistor 320 includes a gate G2, a source S2, a drain D2, and a body B2. For the low-side depletion III-V transistor 320, the drain D2 is electrically connected to the bonding pad 420_2 corresponding to the voltage VS through the bonding wire 450_2c. Therefore, the drain D2 of the low-side depletion III-V transistor 320 can be connected to the gate of the high-side depletion III-V transistor 310 via the bonding wire 450_2c, the bonding pad 420_2, and the bonding wire 450_2a in sequence. In addition, the gate G2 is electrically connected to the bonding pad 420_3 corresponding to the voltage COM through the bonding wire 450_3a, and the source S2 is electrically connected to the node 36 (i.e., the drain of the LS LDMOS transistor 170) of the chip 200 through the bonding wire 450_d. The body B2 is electrically connected to the conductive substrate through the bonding wire 450_c.

[0072] In the chip 200, the source of the LS LDMOS transistor 170 is coupled to the node 26, and the node 26 is electrically connected to the bonding pad 420_3 corresponding to the voltage COM through the bonding wire 450_3b. Therefore, the source of the LS LDMOS transistor 170 can be connected to the gate G2 of the low-side depletion type III-V transistor 320 via the bonding wire 450_3b, the bonding pad 420_3 and the bonding wire 450_3a in sequence. The node 12 is electrically connected to the bonding pad 420_7 corresponding to the input signal EN through the bonding wire 450_7. The node 14 is electrically connected to the bonding pad 420_6 corresponding to the input signal ST through the bonding wire 450_6. The node 16 is electrically connected to the bonding pad 420_5 corresponding to the input signal HIN through the bonding wire 450_5. The node 18 is electrically connected to the bonding pad 420_4 corresponding to the input signal LIN through the bonding wire 450_4. Node 22 is electrically connected to bonding pad 420_8 corresponding to power source VDD through bonding wire 450_8. Node 24 is electrically connected to bonding pad 420_9 corresponding to voltage VB through bonding wire 450_9. In this embodiment, the input signal or control signal of chip 200 and the number of corresponding bonding pads are only for illustration and are not intended to limit the present invention.

[0073] As described above, the HS LDMOS transistor 150 and the high-side gate driver 130 are formed on the floating well region FW. By separating the substrate of the high voltage circuit from the substrate of the low voltage circuit, the chip and the heterogeneous material (eg, GaN / SiC) can be integrated into the same package structure.

[0074] exist Figure 4In the embodiment, the chip 200 and the low-side depletion-type III-V transistor 320 are disposed on a conductive substrate 410 and are grounded to the conductive substrate 410 (for example, the substrates of the chip 200 and the low-side depletion-type III-V transistor 320 are in direct contact with the conductive substrate 410), thereby reducing parasitic effects. In addition, the HS LDMOS transistor 150 and the HS LDMOS transistor 170 are integrated with related circuits (for example, a gate driver, a controller, etc.) in the chip 200, thereby increasing the integration of components and reducing the layout complexity of the package structure and the packaging cost.

[0075] Although the present invention has been described above with reference to the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the attached claims.

Claims

1. A packaging structure, characterized in that: include: A bracket; a plurality of bonding wires; A conductive substrate, disposed on the support; A plurality of bonding pads, disposed on the bracket and separated from the conductive substrate; A wafer, disposed on the conductive substrate, comprising: a first LDMOS transistor; a first gate driver coupled to the gate of the first LDMOS transistor; a second LDMOS transistor; and a second gate driver coupled to the gate of the second LDMOS transistor; a first depletion-type III-V transistor disposed on the conductive substrate and separated from the wafer; a substrate disposed on the conductive substrate and separated from the wafer and the first depletion-type III-V transistor; and a second depletion-type III-V transistor disposed on the substrate; The source of the first depletion type III-V transistor is electrically connected to the drain of the first lateral diffused metal oxide semiconductor transistor, and the drain of the first depletion type III-V transistor is electrically connected to the source of the second lateral diffused metal oxide semiconductor transistor.

2. The packaging structure according to claim 1, characterized in that: The source of the first depletion-type III-V transistor is connected to the drain of the first LDMOS transistor via the corresponding bonding wire.

3. The packaging structure according to claim 1, characterized in that: The drain of the first depletion type III-V transistor is connected to a first bonding pad of the bonding pads via the corresponding bonding wire, and the source of the second LDMOS transistor is connected to the first bonding pad via the corresponding bonding wire.

4. The packaging structure according to claim 3, characterized in that: The gate of the second depletion type III-V transistor is connected to the first bonding pad via the corresponding bonding wire.

5. The packaging structure according to claim 1, characterized in that: The sources of the first depletion-type III-V transistor and the first LDMOS transistor are respectively connected to a second bonding pad of the bonding pads via the corresponding bonding wires.

6. The packaging structure according to claim 1, characterized in that: The conductive substrate is formed by a metal layer, and the chip and the first depletion type III-V transistor are bonded to the metal layer.

7. The packaging structure according to claim 1, characterized in that: The chip and the first depletion type III-V transistor are connected to a common ground via the conductive substrate.

8. The packaging structure according to claim 1, characterized in that: The drain of the second depletion type III-V transistor is connected to a third bonding pad of the bonding pads via the corresponding bonding wire, and the source of the second depletion type III-V transistor is connected to the drain of the second lateral diffused metal oxide semiconductor transistor via the corresponding bonding wire.

9. The packaging structure according to claim 1, characterized in that: The first depletion type III-V transistor and the second depletion type III-V transistor are GaN high electron mobility field effect transistors.

10. The packaging structure according to claim 1, wherein: The above-mentioned substrate is a copper-clad ceramic substrate.

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