Semiconductor package and method for forming the same

Abstract

The invention discloses a semiconductor package. The semiconductor package includes: a package substrate; a first plurality of semiconductor dies disposed on the front surface of the package substrate; an embedded sub-package disposed on the back surface of the package substrate, the embedded sub-package comprising: a sub-package substrate, the front surface of which is attached to the back surface of the package substrate; an interconnection layer attached to the back surface of the sub-package substrate; comprising a second plurality of vertical interconnection parts and at least one horizontal interconnection part; a second plurality of semiconductor dies disposed on a back side of the sub-package substrate through an interconnect layer, each of the second plurality of semiconductor dies being electrically coupled to the sub-package substrate through at least one of a second plurality of vertical interconnects, at least two of the second plurality of semiconductor dies being electrically coupled to each other through at least one horizontal interconnect, electrically coupling the first plurality of semiconductor dies to each other through the embedded sub-package; a first plurality of vertical interconnects disposed on the back surface of the package substrate; and a solder bump attached to the first plurality of vertical interconnects.

Description

Technical Field

[0001] The present application relates generally to semiconductor devices and, more particularly, to semiconductor packages having embedded semiconductor packages. Background Art

[0002] The semiconductor industry has been facing complex integration challenges as consumers want their electronic devices to be smaller, faster, and higher performing, with more and more functions packed into a single device. In order to meet consumer demands, more and more electronic components are being integrated together at higher densities. However, the structure of semiconductor packaging is relatively complex, and its production process may have limited efficiency.

[0003] Therefore, there is a need for a method for forming a semiconductor package with improved production efficiency. Summary of the invention

[0004] An object of the present application is to provide a semiconductor package with improved production efficiency.

[0005] According to one aspect of the present application, a semiconductor package is provided. The semiconductor package includes: a package substrate, the package substrate having a front side and a back side; a first plurality of semiconductor bare chips, the first plurality of semiconductor bare chips are arranged on the front side of the package substrate and electrically coupled to the package substrate; an embedded sub-package, the embedded sub-package is arranged on the back side of the package substrate, the embedded sub-package includes: a sub-package substrate, the sub-package substrate has a front side and a back side, wherein the front side of the sub-package substrate is attached to the back side of the package substrate and electrically coupled to the package substrate; an interconnection layer, the interconnection layer is attached to the back side of the sub-package substrate and electrically coupled to the sub-package substrate; wherein the interconnection layer includes a second plurality of vertical interconnects and at least one horizontal interconnect; and a second plurality of semiconductor bare chips, the second plurality of semiconductor bare chips are connected to the package substrate by the The interconnect layer is arranged on the back side of the sub-package substrate, wherein each of the second plurality of semiconductor dies is electrically coupled to the sub-package substrate through at least one of the second plurality of vertical interconnects, and at least two of the second plurality of semiconductor dies are further electrically coupled to each other through the at least one horizontal interconnect, so that the first plurality of semiconductor dies are electrically coupled to each other through the embedded sub-package; and a first plurality of vertical interconnects, the first plurality of vertical interconnects are arranged on the back side of the package substrate, and the first plurality of vertical interconnects are parallel to the embedded sub-package, wherein each of the first plurality of semiconductor dies is electrically coupled to one of the first plurality of vertical interconnects; and a solder bump, the solder bump being attached to the first plurality of vertical interconnects.

[0006] According to another aspect of the present application, a method for forming a semiconductor package is provided. The method includes: providing a first plurality of semiconductor dies and a second plurality of semiconductor dies; forming an embedded sub-package, including: forming a second plurality of vertical interconnects on the second plurality of semiconductor dies, the second plurality of vertical interconnects being electrically coupled to the second plurality of semiconductor dies; attaching at least one horizontal interconnect to the second plurality of semiconductor dies, wherein at least two of the second plurality of semiconductor dies are electrically connected to each other via the at least one horizontal interconnect; molding the second plurality of semiconductor dies, the second plurality of vertical interconnects, and the at least one horizontal interconnect; forming a sub-package substrate on the second plurality of semiconductor dies, the second plurality of vertical interconnects, and the at least one horizontal interconnect, wherein the second plurality of vertical interconnects are electrically coupled to the sub-package substrate, wherein each of the second plurality of semiconductor dies is electrically coupled to the sub-package substrate via at least one of the second plurality of vertical interconnects. a packaging substrate; forming a first plurality of vertical interconnections; molding the embedded sub-package and the first plurality of vertical interconnections, wherein the first plurality of vertical interconnections are parallel to the embedded sub-package; attaching solder bumps so that the solder bumps are electrically coupled to the first plurality of vertical interconnections; forming a packaging substrate on the embedded sub-package and the first plurality of vertical interconnections, wherein the packaging substrate includes a front side and a back side, wherein the first plurality of vertical interconnections and the sub-package substrate of the embedded sub-package are attached to the back side of the packaging substrate and are electrically coupled to the back side of the packaging substrate; and arranging the first plurality of semiconductor dies on the front side of the packaging substrate, wherein the first plurality of semiconductor dies are electrically coupled to the packaging substrate, the first plurality of semiconductor dies are electrically coupled to each other through the embedded sub-package, and each of the first plurality of semiconductor dies is electrically coupled to one of the first plurality of vertical interconnections.

[0007] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative only, rather than limiting of the present invention. In addition, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings cited herein constitute a part of the specification. The features shown in the drawings illustrate only some embodiments of the present application, rather than all embodiments of the present application, unless otherwise explicitly stated in the detailed description, and readers of the specification should not make a contrary inference.

[0009] Figure 1 A cross-sectional view of a semiconductor package according to an embodiment of the present application is shown.

[0010] FIG. 2A to FIG. 2FA cross-sectional view of a method for forming an embedded sub-package according to an embodiment of the present application is shown.

[0011] FIG. 3A to FIG. 3E A cross-sectional view of a method for forming a vertical interconnection according to an embodiment of the present application is shown.

[0012] FIG. 4A to FIG. 4C A cross-sectional view of a portion of a method for forming a vertical interconnect according to another embodiment of the present application is shown.

[0013] FIG. 5A to FIG. 5G A cross-sectional view is shown of a method for forming a semiconductor package according to an embodiment of the present application.

[0014] Figure 6 to Figure 7 Cross-sectional views of semiconductor packages according to two embodiments of the present application are shown.

[0015] The same reference numbers will be used throughout the drawings to refer to the same or like parts. DETAILED DESCRIPTION

[0016] The following detailed description of exemplary embodiments of the present application refers to the accompanying drawings that form a part of the description. The accompanying drawings show specific exemplary embodiments in which the present application can be practiced. The detailed description, including the accompanying drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice the present application. Those skilled in the art may further utilize other embodiments of the present application and make logical, mechanical, etc. changes without departing from the spirit or scope of the present application. Therefore, readers of the following detailed description should not interpret the description in a restrictive manner, and only limit the scope of the embodiments of the present application with the appended claims.

[0017] In this application, the use of the singular includes the plural unless expressly stated otherwise. In this application, the use of "or" means "and / or" unless otherwise stated. In addition, the use of the term "including" and other forms such as "includes" and "included" are not limiting. In addition, unless specifically stated otherwise, terms such as "element" or "component" encompass elements and components that include one unit and elements and components that include more than one subunit. In addition, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0018] As used herein, for ease of description, spatially relative terms such as "under," "below," "above," "above," "up," "upper," "lower," "left," "right," "vertical," "horizontal," "side," etc. may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features), as illustrated in the drawings. In addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, the element may be directly connected or coupled to the other element, or there may be intermediate elements.

[0019] refer to Figure 1 , which shows a semiconductor package 100 according to one embodiment of the present application. The semiconductor package 100 includes a package substrate 110, and the package substrate 110 has a front side 111 and a back side 112. A first plurality of semiconductor dies 120 are disposed on the front side 111 of the package substrate 110 and are electrically coupled to the package substrate 110. Some other elements of the semiconductor package 100 may be disposed on the back side 112 of the package substrate 110, which will be described in detail below.

[0020] The package substrate 110 enables electrical connection between the first plurality of semiconductor dies 120 on its front side 111 and the elements on its back side 112. In some embodiments, the package substrate 110 includes one or more insulating layers interlaced with one or more conductive layers. In one embodiment, the insulating layer can be a core insulating board, wherein the conductive layer is patterned on the top and bottom surfaces, such as a copper clad laminate substrate. The conductive layer also includes conductive vias electrically coupled through the insulating layer. The package substrate 110 may include any number of conductive layers and insulating layers interlaced with each other.

[0021] Still refer to Figure 1 , an embedded sub-package 130 and a first plurality of vertical interconnects 140 are disposed on the back side 112 of the package substrate 110. Specifically, the embedded sub-package 130 includes a sub-package substrate 131, an interconnect layer 134, and a second plurality of semiconductor dies 137. Preferably, the sub-package substrate 131, the interconnect layer 134, and the second plurality of semiconductor dies 137 are arranged from top to bottom and electrically coupled together.

[0022] Specifically, the sub-package substrate 131 has a front side 132 and a back side 133, and the front side 132 of the sub-package substrate 131 is attached to the back side 112 of the package substrate 110 and is electrically coupled with the package substrate 110. In some embodiments, the sub-package substrate 131 may include an insulating layer and a conductive layer similar to the package substrate 110. In some embodiments, the sub-package substrate 131 includes a dielectric layer and a conductive layer. The sub-package substrate 131 realizes redistribution from the package substrate 110 above to the interconnection layer 134, especially to the second plurality of vertical interconnections 135 below.

[0023] The interconnect layer 134 is attached to the back side 133 of the sub-package substrate 131 and is electrically coupled to the sub-package substrate 131. The interconnect layer 134 includes a second plurality of vertical interconnects 135 and at least one horizontal interconnect 136. In some embodiments, the second plurality of vertical interconnects 135 include a conductive layer 135 electrically coupled to a second plurality of semiconductor dies 137 below. In some embodiments, at least one horizontal interconnect 136 is a silicon bridge with a terminal or a pad. The terminal or pad may include solder, copper or gold interconnects. In some embodiments, the terminal may have a fine interconnect pitch between 0.1um and 1um. At least one horizontal interconnect 136 may electrically couple at least two of the second plurality of semiconductor dies 137 below together. Preferably, the second plurality of vertical interconnects 135 may surround at least one horizontal interconnect 136 in the interconnect layer 134.

[0024] Still refer to Figure 1 The second plurality of semiconductor dies 137 are disposed on the back side 133 of the sub-package substrate 131 through the interconnect layer 134 . Specifically, each of the second plurality of semiconductor dies 137 is electrically coupled to the sub-package substrate 131 through at least one of the second plurality of vertical interconnects 135 .

[0025] It can be seen that the embedded sub-package 130 implements integrated electrical connections therein. Components outside the embedded sub-package 130 can be electrically connected through the embedded sub-package 130 itself without the need for other electrical wiring. Electrical connections between the first plurality of semiconductor dies 120 and the second plurality of semiconductor dies 137 of the embedded sub-package 130 are implemented. Specifically, the first plurality of semiconductor dies 120 are electrically coupled to each other through the embedded sub-package 130.

[0026] Still refer to Figure 1As described above, the semiconductor package 100 also includes a first plurality of vertical interconnects 140 on the back side 112 of the package substrate 110. Generally speaking, the first plurality of vertical interconnects 140 are parallel to the embedded sub-package 130. Through the package substrate 110, each of the first plurality of semiconductor dies 120 is electrically coupled to one of the first plurality of vertical interconnects 140. Therefore, each of the first plurality of vertical interconnects 140 achieves a redistribution of at least a portion of the corresponding semiconductor die. It is understood that the first plurality of vertical interconnects 140 may further include a redistribution structure 141 for electrically connecting them to other elements below. In some embodiments, the first plurality of vertical interconnects 140 may also serve to provide mechanical support for the semiconductor package 100.

[0027] In some embodiments, each of the first plurality of vertical interconnects 140 may include at least one conductive via or at least one conductive pillar. The first plurality of vertical interconnects 140 may be molded with a polymer composite material such as epoxy, epoxy acrylate, or any suitable polymer with or without fillers, wherein the conductive vias or conductive pillars pass through the polymer composite material.

[0028] Furthermore, solder bumps 150 are attached to the first plurality of vertical interconnections 140 so that the semiconductor package 100 described above may be further attached to another circuit board or substrate to be integrated with other elements.

[0029] As described above, electrical interconnection is achieved through the embedded sub-package 130. Specifically, at least one horizontal interconnect 136 can be used as the center of the electrical interconnect. Therefore, a large amount of heat may be generated and accumulated in the semiconductor package 100, and the heat needs to be dissipated to obtain optimal performance. In some embodiments, an interconnect heat sink (not shown) may be provided for at least one horizontal interconnect 136. Specifically, the interconnect heat sink may be in thermal contact with at least one horizontal interconnect 136. It will be understood that in some embodiments, the interconnect heat sink may include thermally conductive vias embedded in the sub-package substrate 131 and the package substrate 110. The interconnect heat sink may also extend above the package substrate 110 to further dissipate heat.

[0030] As described above, the embedded sub-package 130 includes components that can be pre-integrated, that is, they can be pre-formed modularly before being assembled with other components. Similarly, the first plurality of vertical interconnects 140 can also be pre-formed modularly. The semiconductor package 100 achieves a high degree of integration of multiple semiconductor dies, uses at least one horizontal interconnect as a bridge to achieve rapid electrical connection between multiple semiconductor dies, and also achieves modularization of package components, which is conducive to customized specifications and sizes. Therefore, the manufacturing efficiency of the semiconductor package 100 can be improved, and the semiconductor package structure is easy to adjust and adapt.

[0031] FIG. 2A to FIG. 2F A cross-sectional view of a method for forming an embedded sub-package according to an embodiment of the present application is shown.

[0032] refer to Figure 2A , a plurality of semiconductor dies 237 are provided. In addition, a plurality of vertical interconnects 235 are formed on the plurality of semiconductor dies 237. In some embodiments, the plurality of vertical interconnects 235 may include a conductive layer.

[0033] refer to Figure 2B , a plurality of semiconductor dies 237 are attached to a carrier 260. In some embodiments, the carrier 260 comprises a substrate, such as silicon, a polymer, a polymer composite, a metal foil, a ceramic, a glass, an epoxy glass, beryllium oxide, a tape, or other suitable low-cost rigid material for structural support. The carrier 260 may be a wafer or a circle, for example, having a diameter of 15-30 centimeters (cm). An adhesive film or adhesive layer may be formed on the carrier 260. The adhesive layer may be a flexible plastic base film, such as polyvinyl chloride (PVC) or a polyolefin, with a synthetic acrylic adhesive or an ultraviolet (UV) sensitive adhesive for installation and removal of the device. The adhesive layer may be removed by light, heat, laser, or mechanical pressure. Alternatively, an adhesive material such as a thermal epoxy, a polymer composite, or an inorganic adhesive compound may also be applied to the carrier 260.

[0034] refer to Figure 2C , at least one horizontal interconnect 236 is attached to the plurality of semiconductor dies 237. As shown in the above figure, at least two of the plurality of semiconductor dies 237 are electrically connected to each other through at least one horizontal interconnect 236. For example, the horizontal interconnect 236 can be attached to the semiconductor die 237 using a bonding process or a surface mounting process.

[0035] refer to Figure 2D, multiple semiconductor dies 237, multiple vertical interconnects 235, and at least one horizontal interconnect 236 are molded. In some embodiments, a molding compound can be deposited using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable processes to cover multiple semiconductor dies 237, multiple vertical interconnects 235, and at least one horizontal interconnect 236. The molding compound can be a polymer composite material, such as epoxy resin, epoxy acrylate, or any suitable polymer, with or without filler. The molding compound is non-conductive and can provide structural support for other components. It is understood that, preferably, the molding compound is formed around the edges of the semiconductor die 237 to provide isolation from their respective sides.

[0036] refer to Figure 2E , a sub-package substrate 231 is formed on a plurality of semiconductor dies 237, a plurality of vertical interconnects 235, and at least one horizontal interconnect 236. In some embodiments, the sub-package substrate 231 includes a dielectric layer 238 and a conductive layer 239. Figure 2E As shown, a plurality of vertical interconnects 235 are electrically coupled to the sub-package substrate 231 , wherein each of the plurality of semiconductor dies 237 is electrically coupled to the sub-package substrate 231 through at least one of the plurality of vertical interconnects 235 .

[0037] Next, refer to Figure 2F , the carrier is removed, and thus, an embedded sub-package 230 is formed, which can be used in subsequent processes to integrate it with other components of the semiconductor package.

[0038] FIG. 3A to FIG. 3E A cross-sectional view of a method for forming a vertical interconnection according to an embodiment of the present application is shown.

[0039] refer to Figure 3A , a plurality of conductive pillars 343 are disposed on the carrier 342. Preferably, the plurality of conductive pillars 343 may include Cu, Al, Sn, Ni, Au, Ag, Pb, Bi, etc. or a combination thereof. In some embodiments, the plurality of conductive pillars 343 may be implemented as stacked bumps or stud bumps. It is understood that the number of the plurality of conductive pillars 343 should be sufficient to form a plurality of vertical interconnects.

[0040] refer to Figure 3B, a plurality of conductive pillars 343 are molded using a molding material 344. To achieve further electrical connection, the conductive pillars 343 may be exposed to the molding material 344. For example, grinding may be performed after the molding process to expose the conductive pillars 343. The molding material may be a polymer composite material or any other suitable material.

[0041] Next, refer to Figure 3C , a redistribution layer 341 is formed on the molded conductive pillars 343. Specifically, the redistribution layer 341 may include a conductive layer 345 and a dielectric layer 346. In this way, the plurality of conductive pillars 343 are electrically connected to the redistribution layer 341.

[0042] refer to Figure 3D , multiple conductive pillars 343 are cut to obtain Figure 3E Each vertical interconnect 340 of the plurality of vertical interconnects shown. For example, singulation can be performed by cutting at a predetermined cutting channel with a saw or laser cutting tool. These vertical interconnects can have the same shape, size or layout, or can have different shapes, sizes or layouts, depending on the components they connect.

[0043] In some other embodiments, multiple vertical interconnects may refer to FIG. 4A to FIG. 4C Another way of forming is shown.

[0044] refer to Figure 4A , a dielectric layer 443 is formed on the carrier 442. Figure 4B , a plurality of through holes 444 are formed in the dielectric layer 443. In some embodiments, a laser or etching may be used to form the plurality of through holes 444. Figure 4C , filling the plurality of through holes with conductive material to form a plurality of conductive through holes where the through holes are located.

[0045] exist Figures 4A to 4C After following the steps shown, you can then perform FIG. 3C to FIG. 3E The steps shown are used to obtain a plurality of vertical interconnections. The following steps will not be described in detail here.

[0046] FIG. 5A to FIG. 5G A cross-sectional view illustrating a method for forming a semiconductor package according to an embodiment of the present application is shown.

[0047] refer to Figure 5A , the preformed embedded sub-package 530 is attached to the carrier 542 , wherein the front side 532 of the sub-package substrate 531 is attached to the carrier 542 .

[0048] refer to Figure 5B, a plurality of vertical interconnects 540 are also attached to the carrier 542 . In some embodiments, the plurality of vertical interconnects 540 include a redistribution layer 541 oriented in a direction away from the carrier 542 .

[0049] refer to Figure 5C , the embedded sub-package 530 and the plurality of vertical interconnects 540 are molded together using a molding process, wherein the first plurality of vertical interconnects 540 are parallel to the embedded sub-package 530. In other words, the vertical interconnects 540 and the embedded sub-package 530 do not overlap each other. In some embodiments, after the molding process, the conductive structure of the redistribution layer 541 can be exposed to the molding material to further form electrical connections, such as solder bumps.

[0050] refer to Figure 5D , solder bumps 550 are attached using, for example, a surface mounting process such that solder bumps 550 are electrically coupled to the plurality of vertical interconnects 540. In some embodiments, solder bumps 550 are electrically coupled to redistribution layer 541 to electrically couple to the plurality of vertical interconnects 540. It is understood that solder bumps 550 may also be attached at other times, such as at Figure 5G The chip shown is attached afterward, as described in the following paragraphs.

[0051] Next, refer to Figure 5E , remove the carrier 542. In some embodiments, the entire package structure may be flipped over so as to further attach the package substrate to the plurality of vertical interconnects 540 and the embedded sub-package 530 after the molding process.

[0052] refer to Fig. 5F , a package substrate 510 is formed on an embedded sub-package 530 and a plurality of vertical interconnects 540. The package substrate 510 includes a front side 511 and a back side 512. The plurality of vertical interconnects 540 and the sub-package substrate 531 of the embedded sub-package 530 are attached to and electrically coupled with the back side 512 of the package substrate 510.

[0053] refer to Figure 5G , a plurality of semiconductor dies 520 are disposed on a front side 511 of a package substrate 510, wherein the plurality of semiconductor dies 520 are electrically coupled to the package substrate 510. In this way, the plurality of semiconductor dies 520 are electrically coupled to each other through the embedded sub-package 530. In addition, each of the plurality of semiconductor dies 520 is electrically coupled to one of the plurality of vertical interconnects 540. It is understood that in some embodiments, the solder bumps 550 may be attached after the attachment of the plurality of semiconductor dies 520.

[0054] As described above, at least one horizontal interconnect 536 may serve as the center of electrical interconnection and may generate heat that needs to be dissipated for optimal performance. In some embodiments, an interconnect heat sink (not shown) may be formed that is in thermal contact with at least one horizontal interconnect 536. In some embodiments, thermally conductive vias may be formed that are embedded in the sub-package substrate 531 and the package substrate 510. The interconnect heat sink may also extend above the package substrate 510 to further dissipate heat.

[0055] Figure 6 to Figure 7 Cross-sectional views of semiconductor packages according to two embodiments of the present application are respectively shown.

[0056] refer to Figure 6 , the semiconductor package 600 may include a device for further heat dissipation. In particular, the semiconductor package 600 further includes a substrate 601, on which a solder bump 650 is attached. In addition, a basic thermal interface material layer 602 is formed below the embedded sub-package 630. In some embodiments, after the solder bump 650 is mounted on the substrate 601, the basic thermal interface material layer 602 is in thermal contact with the plurality of semiconductor dies 637 of the embedded sub-package 630 and the substrate 601. Therefore, the heat generated by the plurality of semiconductor dies 637 can be effectively transferred to the outside of the substrate 601.

[0057] Reference Figure 7 ,and Figure 6 In contrast, the semiconductor package 700 further includes a top thermal interface material layer 703 located on the plurality of semiconductor dies 720. In addition, the semiconductor package 700 further includes a top heat sink 704, which can be disposed on the top thermal interface material layer 703 for direct heat dissipation of the plurality of semiconductor dies 720.

[0058] The discussion herein includes a number of illustrative drawings that show various parts of semiconductor packages and methods of manufacturing semiconductor packages. For clarity of illustration, these figures do not show all aspects of each example component. Any example component and / or method provided herein may share any or all features with any or all other components and / or methods provided herein.

[0059] Various embodiments have been described herein with reference to the accompanying drawings. However, it is apparent that various modifications and changes may be made thereto, and additional embodiments may be implemented without departing from the broader scope of the invention as set forth in the appended claims. In addition, other embodiments will be apparent to those skilled in the art by considering the specification and practice of one or more embodiments of the invention disclosed herein. Therefore, the present application and the embodiments herein are intended to be considered merely exemplary, with the true scope and spirit of the invention being indicated by the list of the appended exemplary claims.

Claims

1. A semiconductor package, characterized in that: The semiconductor package comprises: A packaging substrate having a front side and a back side; a first plurality of semiconductor dies disposed on a front surface of the packaging substrate and electrically coupled to the packaging substrate; An embedded sub-package, wherein the embedded sub-package is arranged on the back side of the package substrate, and the embedded sub-package comprises: a sub-package substrate having a front side and a back side, wherein the front side of the sub-package substrate is attached to and electrically coupled to the back side of the package substrate; an interconnect layer attached to a back side of the subpackage substrate and electrically coupled to the subpackage substrate; wherein the interconnect layer includes a second plurality of vertical interconnects and at least one horizontal interconnect; and a second plurality of semiconductor dies disposed on a back side of the subpackage substrate through the interconnect layer, wherein each of the second plurality of semiconductor dies is electrically coupled to the subpackage substrate through at least one of the second plurality of vertical interconnects, and at least two of the second plurality of semiconductor dies are further electrically coupled to each other through the at least one horizontal interconnect, such that the first plurality of semiconductor dies are electrically coupled to each other through the embedded subpackage; and a first plurality of vertical interconnects disposed on a back side of the package substrate and parallel to the embedded sub-package, wherein each of the first plurality of semiconductor dies is electrically coupled to one of the first plurality of vertical interconnects; and Solder bumps are attached to the first plurality of vertical interconnects.

2. The semiconductor package according to claim 1, wherein: Each of the first plurality of vertical interconnects includes at least one conductive via or at least one conductive pillar.

3. The semiconductor package according to claim 1, wherein: The semiconductor package further includes an interconnect heat sink in thermal contact with the at least one horizontal interconnect.

4. The semiconductor package according to claim 3, wherein: The interconnect heat sink includes thermally conductive vias embedded in the subpackage substrate and the package substrate.

5. The semiconductor package according to claim 1, wherein: Both the embedded sub-package and the first plurality of vertical interconnects are modularly pre-formed.

6. The semiconductor package according to claim 1, wherein: The semiconductor package further includes: a substrate, wherein the solder bump is mounted on the substrate; and A base thermal interface material layer is located between the substrate and the embedded sub-package, wherein the base thermal interface material layer is in thermal contact with the second plurality of semiconductor dies.

7. The semiconductor package according to claim 6, wherein: The semiconductor package further comprises: a top thermal interface material layer on the first plurality of semiconductor dies; and A top heat sink is disposed on the top thermal interface material layer.

8. A method for forming a semiconductor package, characterized in that: The method comprises: providing a first plurality of semiconductor dies and a second plurality of semiconductor dies; Forming an embedded sub-package, including: forming a second plurality of vertical interconnects on the second plurality of semiconductor dies, the second plurality of vertical interconnects being electrically coupled to the second plurality of semiconductor dies; attaching at least one horizontal interconnect to the second plurality of semiconductor dies, wherein at least two of the second plurality of semiconductor dies are electrically connected to each other via the at least one horizontal interconnect; molding the second plurality of semiconductor dies, the second plurality of vertical interconnects, and the at least one horizontal interconnect; forming a subpackage substrate on the second plurality of semiconductor dies, the second plurality of vertical interconnects, and the at least one horizontal interconnect, wherein the second plurality of vertical interconnects are electrically coupled to the subpackage substrate, wherein each of the second plurality of semiconductor dies is electrically coupled to the subpackage substrate through at least one of the second plurality of vertical interconnects; forming a first plurality of vertical interconnects; molding the embedded subpackage and the first plurality of vertical interconnects, wherein the first plurality of vertical interconnects are parallel to the embedded subpackage; attaching solder bumps such that the solder bumps are electrically coupled to the first plurality of vertical interconnects; forming a package substrate on the embedded sub-package and the first plurality of vertical interconnects, wherein the package substrate comprises a front side and a back side, wherein the first plurality of vertical interconnects and the sub-package substrate of the embedded sub-package are attached to and electrically coupled with the back side of the package substrate; and The first plurality of semiconductor dies are arranged on a front surface of the package substrate, wherein the first plurality of semiconductor dies are electrically coupled to the package substrate, the first plurality of semiconductor dies are electrically coupled to each other through the embedded sub-package, and each of the first plurality of semiconductor dies is electrically coupled to one of the first plurality of vertical interconnects.

9. The method according to claim 8, characterized in that Forming a first plurality of vertical interconnects includes: molding a plurality of conductive pillars; forming a redistribution layer on the plurality of conductive pillars, wherein the plurality of conductive pillars are electrically connected to the redistribution layer; The plurality of conductive pillars are cut to obtain a first plurality of vertical interconnects.

10. The method according to claim 8, characterized in that Forming a first plurality of vertical interconnects includes: forming a plurality of vias in the dielectric layer; filling the plurality of through holes with a conductive material to form a plurality of conductive through holes; forming a redistribution layer on the plurality of conductive vias, wherein the plurality of conductive vias are electrically connected to the redistribution layer; The plurality of conductive vias are cut to obtain a first plurality of vertical interconnects.

11. The method according to claim 8, characterized in that The method further includes forming an interconnect heat sink in thermal contact with the at least one horizontal interconnect.

12. The method according to claim 11, characterized in that Forming an interconnect heat sink includes forming thermally conductive vias embedded in the sub-package substrate and the package substrate.

13. The method according to claim 8, characterized in that The method further comprises: providing a substrate; forming a base thermal interface material layer below the embedded sub-package; The solder bumps are mounted on the substrate, wherein the base thermal interface material layer is in thermal contact with the second plurality of semiconductor dies.

14. The method according to claim 13, characterized in that The method further comprises: forming a top thermal interface material layer on the first plurality of semiconductor dies; and The top heat sink is disposed on the top thermal interface material layer.

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