Chip stacking structure and preparation method thereof, packaging structure and electronic equipment

Abstract

The invention provides a chip stacking structure, a preparation method thereof, a packaging structure and electronic equipment, relates to the technical field of semiconductor packaging, and aims to solve the problem that a traditional semiconductor packaging mode is large in occupied area. The chip stacking structure comprises a first device, a second device and a flexible interposer, wherein the first device and the second device are arranged in a stacked mode. Wherein the first surface of the first device and the first surface of the second device are oppositely arranged and connected, and the second surface of the first device and the second surface of the second device are oppositely arranged. The flexible interposer comprises a first sub-part, a first connecting sub-part and a second sub-part, the first connecting sub-part is connected between the first sub-part and the second sub-part, the first sub-part is located on the side, away from the second device, of the first device, and the second sub-part is located on the side, away from the first device, of the second device. Through the arrangement, the area occupied by the first device and the second device on the packaging substrate is reduced, so that the area of the packaging structure is reduced, and miniaturization development of electronic equipment is facilitated.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and in particular to a chip stacking structure and a preparation method thereof, a packaging structure, and an electronic device. Background Art

[0002] With the rapid growth of the electronics industry and the increase in user demand, electronic devices are developing in a smaller and smaller direction. Therefore, small and light semiconductor packages are required in electronic devices. The development trend of semiconductor chips related to semiconductor packages is to reduce the size of semiconductor chips. In the field of packaging technology, with the rapid growth of demand for small-sized semiconductor chips, it is necessary to realize a chip stacking structure with a compact size. Summary of the invention

[0003] The embodiments of the present disclosure provide a chip stacking structure and a preparation method thereof, a packaging structure, and an electronic device, aiming to improve the problem that a traditional chip structure occupies a large area on a packaging substrate.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] On the one hand, a chip stacking structure is provided. The chip stacking structure includes a first device and a second device arranged in a stacked manner and a flexible interposer. The first surface of the first device and the first surface of the second device are arranged opposite to each other and connected, and the second surface of the first device and the second surface of the second device are arranged opposite to each other. The flexible interposer includes a first sub-portion, a first connecting sub-portion and a second sub-portion, the first connecting sub-portion is connected between the first sub-portion and the second sub-portion, the first sub-portion is located on a side of the first device away from the second device, and the second sub-portion is located on a side of the second device away from the first device.

[0006] In this solution, the flexible interposer connects the first sub-part and the second sub-part through the first connecting sub-part, so that the first sub-part and the second sub-part of the flexible interposer can be arranged relative to each other. Furthermore, the first sub-part is located on the side of the first device away from the second device, which is convenient for the first sub-part to be connected to the first device, and the second sub-part is located on the side of the second device away from the first device, which is convenient for the second sub-part to be connected to the second device. Furthermore, the first device and the second device are stacked to form a 3D (three-dimensional) package. In this way, it is beneficial to reduce the area occupied by the first device and the second device on the package substrate, thereby reducing the area of ​​the package structure, which is beneficial to the miniaturization of electronic devices.

[0007] In some embodiments, the flexible interposer includes a flexible substrate and a first electrical connection layer that are stacked, wherein the first electrical connection layer is located on one side of the flexible substrate, and the first electrical connection layer is connected to the first device and the second device.

[0008] In some embodiments, the flexible substrate is further comprised of a material comprising at least one of polyimide and polyester resin.

[0009] In some embodiments, in a direction perpendicular to the first surface of the first device, the first sub-portion partially overlaps with the first device, and the second sub-portion partially overlaps with the second device.

[0010] In some embodiments, the first device includes a first interposer and a plurality of chips, the plurality of chips are spaced apart on the first interposer and connected to the first interposer, and a surface of the first interposer away from the plurality of chips is a second surface of the first device; and / or, the second device includes a second interposer and a plurality of chips, the plurality of chips are spaced apart on the second interposer and connected to the second interposer, and a surface of the second interposer away from the plurality of chips is a second surface of the second device.

[0011] In some embodiments, a chip of the first device and a chip of the second device are stacked and connected.

[0012] In some embodiments, the first device and / or the second device is a chip.

[0013] In some embodiments, a third device is also included, and the third device is located on a side of the first sub-portion facing away from the first device; the flexible intermediary layer also includes a third sub-portion, a second connecting sub-portion, and a fourth sub-portion located on a side of the first device facing away from the second device, the second connecting sub-portion is connected between the third sub-portion and the fourth sub-portion, the fourth sub-portion is located between the third sub-portion and the first device, the third sub-portion is connected to the third device, and the fourth sub-portion is connected to the second surface of the first device.

[0014] In some embodiments, the flexible intermediary layer also includes a second electrical connection layer and a conductive through hole, the conductive through hole passes through the flexible substrate, and the second electrical connection layer is located on the side of the flexible substrate away from the first electrical connection layer; the third sub-portion is located on the side of the third device away from the first device and is connected to the second surface of the third device, the second surface of the third device is arranged opposite to the first surface of the first device, and the first surface of the third device is arranged opposite to the second surface of the first device.

[0015] In some embodiments, the fourth sub-portion is spaced apart from the first sub-portion.

[0016] In some embodiments, a plurality of fourth devices are stacked and arranged, and the fourth devices are located on the side of the third device away from the first device; the flexible interposer also includes a plurality of connecting parts, and the connecting parts include a fifth sub-part, a third connecting sub-part and a sixth sub-part, and the third connecting sub-part is connected between the fifth sub-part and the sixth sub-part, and the fifth sub-part is away from the third device relative to the sixth sub-part; for one of the connecting parts: the fifth sub-part and the sixth sub-part are located on both sides of one of the fourth devices, and the fifth sub-part is connected to the second surface of one of the fourth devices, and the sixth sub-part is connected to the second surface of another device, and the other device and one of the fourth devices are two adjacent devices, and the second surface of the fourth device is arranged opposite to the first surface of the third device.

[0017] In some embodiments, the third sub-portion is located on a side of the third device close to the first device and connected to a first surface of the third device, and the first surface of the third device is arranged opposite to the second surface of the first device.

[0018] In some embodiments, a fourth device is further included, wherein the fourth device is located on a side of the third device facing away from the first device, a first surface of the fourth device is arranged opposite to the first surface of the third device, and a second surface of the fourth device is arranged opposite to and connected to the second surface of the third device; the flexible interposer also includes a fifth sub-portion, a third connecting sub-portion and a sixth sub-portion, the third connecting sub-portion is connected between the fifth sub-portion and the sixth sub-portion, the fifth sub-portion is located on a side of the fourth device facing away from the third device and is connected to the first surface of the fourth device, and the sixth sub-portion is located on a side of the third device facing away from the fourth device and is connected to the first surface of the third device.

[0019] On the other hand, a method for preparing a chip stacking structure is provided, comprising: providing a flexible intermediary layer, a first device and a second device; connecting the second surface of the first device to the flexible intermediary layer, and connecting the second surface of the second device to the flexible intermediary layer; bending the flexible intermediary layer to form a first connecting sub-portion, and stacking the first device and the second device.

[0020] In some embodiments, the first sub-portion of the flexible intermediary layer is located on one side of the second surface of the first device, and the second sub-portion of the flexible intermediary layer is located on one side of the second surface of the second device; bending the flexible intermediary layer includes: bending the flexible intermediary layer between the first sub-portion and the second sub-portion, and making the first surface of the first device and the first surface of the second device relatively arranged and connected, the second surface of the first device and the second surface of the second device are arranged back to back, and the first connecting sub-portion is located on one side of the first device and the second device.

[0021] In some embodiments, the preparation method includes: connecting the second surfaces of multiple first devices to a first intermediary layer, connecting the second surfaces of multiple second devices to a second intermediary layer; connecting the surface of the first intermediary layer facing away from the first device to the first sub-unit, and connecting the surface of the second intermediary layer facing away from the second device to the second sub-unit.

[0022] In some embodiments, the preparation method includes: providing a flexible intermediary layer, a first device and a second device, and also includes: providing a third device, the flexible intermediary layer also includes a third sub-section and a fourth sub-section, and the fourth sub-section is spaced apart from the first sub-section; connecting the second surface of the first device to the flexible intermediary layer, and also includes: connecting the second surface of the first device to the fourth sub-section, and connecting the third device to the third sub-section; bending the flexible intermediary layer, and also includes: bending the flexible intermediary layer between the third sub-section and the fourth sub-section to form a second connecting sub-section, and making the second surface of the third device opposite to the first surface of the first device, and the first surface of the third device facing the second surface of the first device.

[0023] In some embodiments, the preparation method includes: providing a flexible intermediary layer, a first device and a second device, and also includes: providing a fourth device, the flexible intermediary layer also includes a fifth sub-section and a sixth sub-section, and the sixth sub-section is spaced apart from the third sub-section; connecting the second surface of the first device to the flexible intermediary layer, and also includes: connecting the second surface of the third device to the third sub-section and the sixth sub-section, and connecting the second surface of the fourth device to the fifth sub-section; bending the flexible intermediary layer, and also includes: bending the flexible intermediary layer between the fifth sub-section and the sixth sub-section to form a third connecting sub-section, and making the second surface of the fourth device opposite to the first surface of the first device, and the first surface of the fourth device facing the second surface of the first device.

[0024] In some embodiments, the preparation method includes: providing a flexible intermediary layer, a first device and a second device, and also includes: providing a fourth device, the flexible intermediary layer also includes a fifth sub-section and a sixth sub-section, and the sixth sub-section is spaced apart from the third sub-section; connecting the second surface of the first device to the flexible intermediary layer, and also includes: connecting the first surface of the third device to the third sub-section, connecting the first surface of the third device to the sixth sub-section, and connecting the second surface of the fourth device to the fifth sub-section; bending the flexible intermediary layer, and also includes: bending the flexible intermediary layer between the fifth sub-section and the sixth sub-section to form a third connecting sub-section, and making the second surface of the fourth device opposite to the first surface of the first device, and the first surface of the fourth device facing the second surface of the first device.

[0025] In another aspect, a packaging structure is provided, comprising: a chip stacking structure and a packaging substrate, wherein the chip stacking structure is the chip stacking structure as described in the above embodiment, or the chip stacking structure is prepared by the chip stacking structure preparation method of the above embodiment. The packaging substrate is electrically connected to the chip stacking structure.

[0026] On the other hand, an electronic device is provided, comprising a circuit board and the packaging structure as described in the above embodiment, wherein the circuit board is electrically connected to the packaging structure.

[0027] It can be understood that the beneficial effects that can be achieved by the chip stacking structure preparation method, packaging structure, and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the chip stacking structure described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0029] Figure 1 is a block diagram of an electronic device according to some embodiments;

[0030] Figure 2 is a schematic structural diagram of an electronic device according to some embodiments;

[0031] Figure 3 is a schematic diagram of a packaging structure according to some current embodiments;

[0032] Figure 4 is a schematic structural diagram of a packaging structure according to some embodiments;

[0033] Figure 5 is a schematic diagram of the structure of a flexible interposer according to some embodiments;

[0034] Figure 6 is a schematic structural diagram of a packaging structure according to some embodiments;

[0035] Figure 7 is a schematic structural diagram of a packaging structure according to some embodiments;

[0036] Figure 8 is a schematic structural diagram of a packaging structure according to some embodiments;

[0037] Fig. 9 is a schematic diagram of the structure of a flexible interposer according to some embodiments;

[0038] Fig.10 is a schematic structural diagram of a chip stacking structure according to some embodiments;

[0039] Fig.11 is a schematic structural diagram of a chip stacking structure according to some embodiments;

[0040] Fig.12 is a flow chart of a method for preparing a chip stacking structure according to some embodiments;

[0041] Fig.13 A schematic diagram of the structure of a chip stacking structure before bending according to some embodiments;

[0042] Fig.14 for Fig.13 A schematic diagram of the structure of the chip stacking structure after bending;

[0043] Fig.15 is a schematic structural diagram of a chip stacking structure before bending according to some embodiments;

[0044] Fig.16 for Fig.15 A schematic diagram of the structure of the chip stacking structure after bending;

[0045] Fig.17 is a schematic structural diagram of a chip stacking structure before bending according to some embodiments;

[0046] Fig.18 for Fig.17 A schematic diagram of the structure of the chip stacking structure after bending;

[0047] Fig.19is a schematic structural diagram of a chip stacking structure before bending according to some embodiments;

[0048] Fig. 20 for Fig.19 Schematic diagram of the chip stacking structure after bending. DETAILED DESCRIPTION

[0049] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0050] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0051] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0052] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0053] When describing some embodiments, the term "connected" and its derivative expressions may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0054] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0055] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0056] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0057] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0058] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0059] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0060] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0061] The electronic device may include image sensors, NAND flash memory, high bandwidth memory, mobile phones, tablet computers, televisions, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and other electronic products. The embodiments of the present disclosure do not impose any special restrictions on the specific forms of the above electronic devices.

[0062] Figure 1 A block diagram of an electronic device provided for some embodiments of the present disclosure. Figure 2 This is a schematic diagram of the structure of an electronic device provided by some embodiments of the present disclosure. Figure 1 and Figure 2 As shown, the electronic device 1000 may include a circuit board 200, a package structure 100, and a connector 5 disposed between the circuit board 200 and the package structure 100, and the package structure 100 is electrically connected to the circuit board 200 through the connector 5. The connector 5 may be, for example, a ball grid array (BGA). In addition, the electronic device may further include at least one of a central processing unit (CPU) and a cache.

[0063] Typically, multiple microelectronic circuits are integrated in a semiconductor chip. The semiconductor chip itself cannot be used as a finished product and may be damaged by external physical or chemical impact. The semiconductor chip can be packaged to form a package structure 100. The package structure 100 includes a chip structure and a package substrate.

[0064] Figure 3 Schematic diagram of a packaging structure provided by some current embodiments. Figure 3 As shown, the package structure 100' includes a chip structure 10' and a package substrate 20. The chip structure 10' includes: a first device 11' and a second device 12'. The package structure 10' in this embodiment uses an embedded multi-die interconnect bridge (EMIB) technology to package the chip structure 10'. Figure 3As shown, the embedded multi-die interconnection bridge A' can be embedded in the packaging substrate 20 and electrically coupled to the packaging substrate 20. At the same time, the first device 11' and the second device 12' are arranged on the packaging substrate 20 at intervals. Among them, the first device 11' is electrically connected to the packaging substrate 20 and the embedded multi-die interconnection bridge A'. The second device 12' is electrically connected to the packaging substrate 20 and the embedded multi-die interconnection bridge A'. The embedded multi-die interconnection bridge A' can realize communication and interconnection between the first device 11' and the second device 12'. However, the packaging structure 100' of the above embodiment makes the chip structure 10' occupy a large area on the packaging substrate 20, and the more chip structures 10' are packaged, the larger the area occupied on the packaging substrate 20, which is not conducive to packaging more chip structures 10', nor is it conducive to the miniaturization of electronic devices.

[0065] Since the chip structure in the above embodiments occupies a large area on the packaging substrate, resulting in a large area of ​​the packaging structure, some embodiments of the present disclosure provide a packaging structure. Figure 4 Schematic diagram of the packaging structure provided by some embodiments of the present disclosure. The following explanation is given by taking the direction perpendicular to the packaging substrate 20 as the first direction X and the direction parallel to the packaging substrate 20 as the second direction Y as an example. Figure 4 As shown, the package structure 100 includes a chip stacking structure 10 and a package substrate 20. The chip stacking structure 10 includes: a device assembly 1 and a flexible interposer 2. The device assembly 1 includes a first device 11 and a second device 12 stacked along a first square X, a first surface 111 of the first device 11 and a first surface 121 of the second device 12 are arranged opposite to each other and connected, and a second surface 112 of the first device 11 and a second surface 122 of the second device 12 are arranged opposite to each other. Exemplarily, the first surface 111 of the first device 11 and the first surface 121 of the second device 12 can be bonded together. The first device 11 can include a chip. The second device 12 can include a chip.

[0066] The flexible interposer 2 includes a first sub-portion 201, a first connecting sub-portion 203, and a second sub-portion 202, wherein the first connecting sub-portion 203 is connected between the first sub-portion 201 and the second sub-portion 202. The first sub-portion 201 is located on the side of the first device 11 away from the second device 12, that is, the first sub-portion 201 is located on the side where the second surface 112 of the first device 11 is located, so that the first sub-portion 201 is electrically connected to the second surface 112 of the first device 11. The second sub-portion 202 is located on the side of the second device 12 away from the first device 11, that is, the second sub-portion 202 is located on the side where the second surface 122 of the second device 12 is located, so that the second sub-portion 202 is electrically connected to the second surface 122 of the second device 12. In addition, the second surface 122 of the second device 12 can be partially electrically connected to the flexible interposer 2 and partially electrically connected to the package substrate 20. The flexible interposer 2 can realize communication and interconnection between the first device 11 and the second device 12.

[0067] Exemplarily, the first sub-section 201, the first connecting sub-section 203 and the second sub-section 202 can be integrally arranged. The material of the flexible intermediary layer 2 can include ultra-thin flexible materials such as polyimide and polyester resin, which is conducive to saving the production cost of the flexible intermediary layer 2. Through the above arrangement, the flexible intermediary layer 2 has a certain flexibility. Therefore, the first connecting sub-section 203 of the flexible intermediary layer 2 can be bent, so that the first sub-section 201 and the second sub-section 202 of the flexible intermediary layer 2 are arranged relatively along the first direction X, and further, the first device 11 and the second device 12 are stacked along the first direction X, thereby forming a 3D (three-dimensional) package. In this way, it is conducive to reducing the area occupied by the first device 11 and the second device 12 on the packaging substrate 20, thereby reducing the area of ​​the packaging structure, which is conducive to the miniaturization of electronic equipment.

[0068] Figure 5 A schematic diagram of the structure of a flexible interposer provided in some embodiments of the present disclosure.

[0069] In some embodiments, Figure 5 As shown, the flexible interposer 2 includes a flexible substrate 21 and a first electrical connection layer 22 which are stacked, and the first electrical connection layer 22 is located on one side of the flexible substrate 21. Figure 4 and Figure 5 The first electrical connection layer 22 may be located on a side of the flexible substrate 21 close to the device assembly 1 , so that the first electrical connection layer 22 is electrically connected to the first device 11 and the second device 12 .

[0070] In some examples, such as Figure 4 and Figure 5 As shown, the first electrical connection layer 22 may include metal lines, and the metal lines are used to electrically connect the first device 11 , the second device 12 and the package substrate 20 together.

[0071] In other examples, such as Figure 4 and Figure 5 As shown, the first electrical connection layer 22 may include a connector 5. Exemplarily, the connector 5 may include a bump, such as a solder ball. The material of the connector 5 may include metals such as tin.

[0072] Through the above arrangement, the first electrical connection layer 22 can be electrically connected to both the first device 11 and the second device 12 to achieve communication and interconnection between the first device 11 and the second device 12 .

[0073] In some embodiments, the material of the flexible substrate 21 includes at least one of polyimide and polyester resin. For example, the flexible substrate 21 may be a film made of polyimide, or the flexible substrate 21 may be a film made of polyester resin. It can be understood that the flexible substrate 21 is composed of a material of polyimide or polyester resin, and the flexible substrate 21 can be made into a thin film structure, so that the thickness of the flexible substrate 21 is thinner. Preferably, the thickness of the flexible substrate 21 can range from 20μm to 200μm. For example, the thickness of the flexible interposer 2 can be 20μm, 90μm or 200μm, and when the thickness of the flexible interposer 2 is closer to 20μm, it is more conducive to reducing the overall thickness of the chip stacking structure 10.

[0074] Through the above arrangement, the thickness of the chip stacking structure 10 after packaging will not be too large, which is conducive to controlling the thickness of the packaging structure, and further, is conducive to the miniaturization of electronic devices. In addition, the flexible substrate 21 made of at least one of polyimide and polyester resin can have a certain degree of flexibility, which is conducive to forming the first connecting sub-portion 203 of the flexible interposer 2.

[0075] In some embodiments, continue to refer to Figure 4 , in the first direction X, the first sub-portion 201 partially overlaps with the first device 11, and the second sub-portion 202 partially overlaps with the second device 12. It should be noted that “the first sub-portion 201 partially overlaps with the first device 11” means that a part of the orthographic projection of the first sub-portion 201 on the packaging substrate 20 is located within the orthographic projection of the first device 11 on the packaging substrate 20, and a part is located outside the orthographic projection of the first device 11 on the packaging substrate 20. “The second sub-portion 202 partially overlaps with the second device 12” means that a part of the orthographic projection of the second sub-portion 202 on the packaging substrate 20 is located within the orthographic projection of the second device 12 on the packaging substrate 20, and a part is located outside the orthographic projection of the second device 12 on the packaging substrate 20.

[0076] It can be seen from the above embodiment that the first sub-portion 201 is used to be electrically connected to the first device 11, and the second sub-portion 202 is used to be electrically connected to the second device 12. Therefore, when the first sub-portion 201 partially overlaps with the first device 11, the overlapping portion can be electrically connected to the first device 11; similarly, when the second sub-portion 202 partially overlaps with the second device 12, the overlapping portion can be electrically connected to the second device 12, which is beneficial to saving the manufacturing materials of the flexible interposer 2 and saving costs.

[0077] Figure 6 Schematic diagram of a packaging structure provided by other embodiments of the present disclosure. Figure 6 As shown, the first device 11 may include a first interposer 3 and a plurality of chips, the plurality of chips are arranged on the first interposer 3 along the second direction Y at intervals and connected to the first interposer 3, and the surface of the first interposer 3 away from the plurality of chips is the second surface 112 of the first device 11. The first sub-portion 201 of the flexible interposer 2 is electrically connected to the surface of the first interposer 3 away from the plurality of chips. With such an arrangement, the plurality of chips can communicate and interconnect through the first interposer 3.

[0078] Exemplarily, the first interposer 3 may include a plurality of conductive vias (not shown in the figure), and the conductive vias penetrate the first interposer 3 along the first direction X. One end of the conductive via is electrically connected to each of the plurality of chips, and the other end of the conductive via is electrically connected to the first sub-portion 201 of the flexible interposer 2. Through the above arrangement, the plurality of chips can be electrically connected to the first sub-portion 201 through the first interposer 3.

[0079] For example, Figure 6 As shown, the second device 12 may include a second interposer 4 and a plurality of chips, the plurality of chips are arranged at intervals along the second direction Y on the second interposer 4 and connected to the second interposer 4, and the surface of the second interposer 4 away from the plurality of chips is the second surface 122 of the second device 12. The flexible interposer 2 is electrically connected to the surface of the second interposer 4 away from the plurality of chips. In this way, the plurality of chips can communicate and interconnect with the second interposer 4.

[0080] Exemplarily, the second interposer 4 may include a plurality of conductive vias, which penetrate the second interposer 4 along the first direction X. One end of the conductive via 24 is electrically connected to the plurality of chips, and the other end of the conductive via is electrically connected to the second sub-portion 202 of the flexible interposer 2 .

[0081] In this embodiment, the conductive through-hole may be a through-silicon via or a through-hole made of other materials, and a conductive material may be filled in the through-hole to ensure its conductive function.

[0082] When more chips need to be packaged, the first interposer 3 in this embodiment is used to realize communication and interconnection between multiple chips to form a first device 11; the second interposer 4 in this embodiment is used to realize communication and interconnection between multiple chips to form a second device 12. Subsequently, the first device 11 and the second device 12 are stacked along the first direction X, which can reduce the area occupied by the device assembly 1 on the packaging substrate 20, thereby packaging more chips and facilitating the miniaturization of electronic devices.

[0083] In some embodiments, Figure 6 As shown, when the first device 11 and the second device 12 both have multiple chips, illustratively, a chip of the first device 11 is stacked with a chip of the second device 12 and connected. Specifically, in this embodiment, the first device 11 includes chip A1, chip A2, chip A3 and chip A4; the second device 12 includes chip B1, chip B2, chip B3 and chip B4. Among them, a chip of the first device 11 is stacked with a chip of the second device 12, for example, chip A1 is stacked with chip B1, chip A2 is stacked with chip B2, chip A3 is stacked with chip B3, and chip A4 is stacked with chip B4. Exemplarily, a chip of the first device 11 can be bonded with a chip of the second device 12, which is beneficial to improve the overall stability of the chip stacking structure 10.

[0084] In some embodiments, Figure 4 As shown, the first device 11 is a chip, or the second device 12 is a chip, or the first device 11 and the second device 12 are both chips. Exemplarily, the first device 11 may include a memory chip, a logic chip, a communication chip, a processing chip, etc. Exemplarily, the second device 12 may include a memory chip, a logic chip, a communication chip, a processing chip, etc. The present disclosure does not limit the type and function of the chip. Through the above arrangement, when packaging the chip, the flexible interposer 2 can realize the communication and interconnection between the first device 11 and the second device 12. At the same time, since the flexible interposer 2 has a certain flexibility, the first connecting sub-portion 203 of the flexible interposer 2 can be bent, so that the first sub-portion 201 and the second sub-portion 202 of the flexible interposer 2 are arranged relative to each other along the first direction X, and further, the first device 11 and the second device 12 are stacked along the first direction X, thereby forming a 3D (three-dimensional) package. In this way, it is beneficial to reduce the area occupied by the chip on the packaging substrate 20, thereby reducing the area of ​​the packaging structure, which is beneficial to the miniaturization of electronic devices.

[0085] Figure 7 A schematic diagram of the packaging structure provided for some embodiments of the present disclosure. Figure 8A schematic diagram of a packaging structure provided in some embodiments of the present disclosure. Figure 7 and Figure 8 As shown, the device assembly 1 further includes a third device 13, and the third device 13 is located on a side of the first sub-portion 201 away from the first device 11. Figure 7 and Figure 8 , the third device 13 is located above the first sub-portion 201. The third device 13 has a first surface 131 and a second surface 132 opposite to each other, wherein the first surface 131 of the third device 13 is arranged opposite to the second surface 112 of the first device 11, and the second surface 132 of the third device 13 is arranged opposite to the first surface 111 of the first device 11.

[0086] The flexible interposer 2 further includes a third sub-portion 204, a second connecting sub-portion 205, and a fourth sub-portion 206 located on a side of the first device 11 away from the second device 12. The second connecting sub-portion 205 is connected between the third sub-portion 204 and the fourth sub-portion 206. By way of example, the third sub-portion 204, the second connecting sub-portion 205, and the fourth sub-portion 206 can be integrally arranged. The fourth sub-portion 206 is located between the third sub-portion 204 and the first device 11, wherein the third sub-portion 204 is electrically connected to the third device 13, and the fourth sub-portion 206 is electrically connected to the second surface 112 of the first device 11.

[0087] In one example, if Figure 7 As shown, the third sub-portion 204 is electrically connected to the first surface 131 of the third device 13, and the fourth sub-portion 206 is electrically connected to the second surface 112 of the first device 11. The second connecting sub-portion 205 connects the third sub-portion 204 and the fourth sub-portion 206, and Figure 7 The second connecting sub-portion 205 is located at a side of the third device 13 close to the first device.

[0088] In another example, Figure 8 As shown, the third sub-portion 204 is electrically connected to the second surface 132 of the third device 13, the fourth sub-portion 206 is electrically connected to the second surface 112 of the first device 11, and the fourth sub-portion 206 is connected to the first surface 131 of the third device 13. The second connecting sub-portion 205 connects the third sub-portion 204 and the fourth sub-portion 206, and the second connecting sub-portion 205 is located on the side of the third device 13. It should be noted that the "side of the third device 13" refers to: the side of the third device 13 when the third device 13 is placed horizontally on the horizontal plane with the first surface 131 of the third device 13 as the horizontal plane.

[0089] Through the above arrangement, the flexible interposer 2 enables the third device 13 to communicate and interconnect with the first device 11, and further enables the first device 11, the second device 12 and the third device 13 to communicate and interconnect. At the same time, the third device 13 is stacked with the first device 11 and the second device 12 along the first direction X, which is conducive to reducing the area occupied by the device assembly 1 on the packaging substrate 20, thereby reducing the area of ​​the packaging structure, which is conducive to the miniaturization of electronic devices.

[0090] Fig. 9 FIG. 2 is a schematic diagram of another flexible intermediary layer 2 provided in some embodiments of the present disclosure. Fig. 9 As shown, the flexible interposer 2 further includes a second electrical connection layer 23 and a conductive through hole 24. The conductive through hole 24 can penetrate the flexible substrate 21 along the first direction X, and the second electrical connection layer 23 is located on the side of the flexible substrate 21 away from the first electrical connection layer 22. One end of the conductive through hole 24 is electrically connected to the first electrical connection layer 22, and the other end of the conductive through hole 24 is electrically connected to the second electrical connection layer 23. Among them, the conductive through hole 24 can be a through silicon via (TSV) or a through hole of other materials. In addition, a conductive material can be filled in the conductive through hole 24 to ensure its conductive function.

[0091] Exemplarily, the second electrical connection layer 23 may include a metal line. Exemplarily, the second electrical connection layer 23 may also include a connector, and the connector may include a bump, such as a solder ball. The material of the connector may include metal such as tin.

[0092] The flexible intermediary layer 2 provided in this embodiment can be applied to Figure 8 In the packaging structure. Combined Figure 8 and Fig. 9 The first electrical connection layer 22 of the flexible interposer 2 can be electrically connected to the second surface 132 of the third device 13; the second electrical connection layer 23 can be electrically connected to the second surface 112 of the first device 11. The first electrical connection layer 22 is electrically connected to the second electrical connection layer 23 through the conductive via 24, further realizing communication and interconnection between the third device 13 and the first device 11.

[0093] In some embodiments, Figure 8As shown, the first sub-section 201, the second sub-section 202 and the first connecting sub-section 203 can be integrally arranged to form a first component 230, and the third sub-section 204, the fourth sub-section 206 and the second connecting sub-section 205 can be integrally arranged to form a second component 220. The fourth sub-section 206 is spaced apart from the first sub-section 201, that is, the first component and the second component are spaced apart. Exemplarily, the first sub-section 201 and the fourth sub-section 206 can be connected to the two ends of the third device 13 respectively. Both ends of the third device 13 are connected to the flexible interposer 2, which is conducive to improving the stability of the third device 13 package.

[0094] Fig.10 A schematic diagram of a chip stacking structure provided in some embodiments of the present disclosure. Fig.10 As shown, the chip stacking structure 10 further includes a plurality of fourth devices 14 which are stacked and arranged in layers. The fourth devices 14 are located on a side of the third device 13 which is away from the first device 11 .

[0095] The flexible interposer 2 further includes a plurality of connecting portions 210 , including a fifth sub-portion 207 , a third connecting sub-portion 208 and a sixth sub-portion 209 . The third connecting sub-portion 208 is connected between the fifth sub-portion 207 and the sixth sub-portion 209 . The fifth sub-portion 207 is farther away from the third device 13 than the sixth sub-portion 209 .

[0096] For a connecting portion 210, the fifth sub-portion 207 and the sixth sub-portion 209 are located on both sides of a fourth device 14, and the fifth sub-portion 207 is connected to the second surface 142 of a fourth device 14, and the sixth sub-portion 209 is connected to the second surface of another device, the other device and the fourth device 14 are two adjacent devices, and the second surface 142 of the fourth device 14 is arranged back to back with the first surface 131 of the third device 13.

[0097] It should be noted that “another device and a fourth device 14 are two adjacent devices” means that for the fourth device 14 adjacent to the third device 13 (i.e. Fig.10 For the fourth device 14 at the bottom, the other device may be the third device 13 ; except for the above case, the other device may be the fourth device 14 .

[0098] In this embodiment, one fourth device 14 is arranged in one-to-one correspondence with one connection portion 210. That is to say, the second surface 142 of each fourth device 14 is connected to the fifth sub-portion 207 of one connection portion 210. When multiple devices need to be packaged, through the above arrangement, the first device 11, the second device 12, the third device 13 and the plurality of fourth devices 14 can be stacked along the first direction X, and the communication and interconnection between the devices can be realized through the flexible interposer 2, which is conducive to reducing the area occupied by the first device 11, the second device 12, the third device 13 and the plurality of fourth devices 14 on the packaging substrate 20, thereby reducing the area of ​​the packaging structure, which is conducive to the miniaturization of electronic devices.

[0099] Fig.11 A schematic diagram of a chip stacking structure provided in some embodiments of the present disclosure. Fig.11 As shown, the third sub-portion 204 is located on a side of the third device 13 close to the first device 11, and is electrically connected to the first surface 131 of the third device 13, and the first surface 131 of the third device 13 is arranged opposite to the second surface 112 of the first device 11. In addition, the fourth sub-portion 206 is electrically connected to the second surface 112 of the first device 11, and the second connecting sub-portion 205 connects the third sub-portion 204 and the fourth sub-portion 206.

[0100] Through the above arrangement, communication and interconnection between the third device 13 and the first device 11 can be achieved, and the third device 13 and the first device 11 are stacked, which reduces the area of ​​the packaging structure and is conducive to the miniaturization of electronic equipment.

[0101] In some embodiments, Fig.11 As shown, the chip stacking structure 10 also includes a fourth device 14, which is located on the side of the third device 13 away from the first device 11, the first surface 141 of the fourth device 14 is arranged opposite to the first surface 131 of the third device 13, and the second surface 142 of the fourth device 14 is arranged opposite to and connected to the second surface 132 of the third device 13.

[0102] The flexible interposer 2 further includes a plurality of connecting portions 210, and the connecting portion 210 includes a fifth sub-portion 207, a third connecting sub-portion 208, and a sixth sub-portion 209. The third connecting sub-portion 208 is connected between the fifth sub-portion 207 and the sixth sub-portion 209. The fifth sub-portion 207 is located on a side of the fourth device 14 away from the third device 13, and is electrically connected to the first surface 141 of the fourth device 14, and the sixth sub-portion 209 is located on a side of the third device 13 away from the fourth device 14, and is electrically connected to the first surface 131 of the third device 13.

[0103] When multiple devices need to be packaged, illustratively, the chip stacking structure 10 may include multiple third devices 13, multiple fourth devices 14, and multiple connecting portions 210. illustratively, one third device 13, one fourth device 14, and one connecting portion 210 may be stacked along the first direction X. One third device 13, one fourth device 14, and one connecting portion 210 form a third component 240. Adjacent third components 240 are connected by a second component 220, and the second component 220 is located at one end of the third component 240 away from the connecting portion 210.

[0104] The third sub-portion 204 is electrically connected to the first surface 131 of the third device 13, and the fourth sub-portion 206 is electrically connected to the device surface opposite to the first surface 131 of the third device 13. Fig.11 As shown, the device opposite to the first surface 131 of the third device 13 may be the fourth device 14, or may be the first device 11. For example, the third device 13 closest to the package substrate 20 (eg Fig.11 The device opposite to the first surface 131 of the third device 13 at the bottom is the first device 11. In addition, the device opposite to the first surface of the third device 13 that continues to be stacked along the first direction X is the fourth device 14. The second connecting sub-section 205 connects the third sub-section 204 and the fourth sub-section 206. Through the above-mentioned arrangement, the devices can communicate and interconnect through the flexible intermediate layer 2, and the stacking arrangement of multiple devices is conducive to reducing the area occupied by the device on the packaging substrate 20, which is conducive to the miniaturization of electronic devices. Furthermore, packaging multiple devices can improve the performance of electronic equipment, and at the same time, it will not increase the area occupied by the device on the packaging substrate 20. For example, when multiple devices are memory chips, it is beneficial to improve the storage capacity of electronic equipment, and at the same time, it does not occupy a large area.

[0105] Fig.12 It is a flow chart of a method for preparing a chip stacking structure provided in some embodiments of the present disclosure. Fig.13 It is a schematic structural diagram of the chip stacking structure before bending provided in some embodiments of the present disclosure. Fig.14 yes Fig.13 Schematic diagram of the structure of the chip stacking structure after bending. In some embodiments, the method for preparing the chip stacking structure 10 includes:

[0106] S1. Provide a flexible intermediate layer, a first device, and a second device.

[0107] Combination Figure 4 and Figure 5The flexible intermediary layer 2 may include a flexible substrate 21 and a first electrical connection layer 22 which are stacked, and the first electrical connection layer 22 is located on one side of the flexible substrate 21. The material of the flexible intermediary layer 2 may include ultra-thin flexible materials such as polyimide and polyester resin. Preferably, the thickness of the flexible intermediary layer 2 is in the range of 20 μm-200 μm. The first device 11 may include a chip. The second device 12 may include a chip.

[0108] S2. Connect the second surface of the first device to the flexible intermediate layer, and connect the second surface of the second device to the flexible intermediate layer.

[0109] like Fig.13 As shown, exemplarily, the second surface 112 of the first device 11 is electrically connected to the first electrical connection layer 22 of the flexible interposer 2 , and the second surface 122 of the second device 12 is electrically connected to the first electrical connection layer 22 of the flexible interposer 2 .

[0110] S3, bending the flexible intermediate layer to form a first connecting sub-portion, and stacking the first device and the second device.

[0111] like Fig.13 and Fig.14 As shown, bending Fig.13 The flexible interposer 2 at position A in the middle is formed Fig.14 A first device 11 and a second device 12 are stacked along the first direction X. Compared with the first device 11 and the second device 12 being arranged at intervals, the stacked arrangement of the first device 11 and the second device 12 is conducive to reducing the area occupied on the packaging substrate 20, which is conducive to the miniaturization of electronic devices.

[0112] Exemplarily, the flexible interposer 2 may completely cover the second surface 112 of the first device 11 and the second surface 122 of the second device 12, or the flexible interposer 2 may partially cover the second surface 112 of the first device 11 and the second surface 122 of the second device 12. And the flexible interposer 2 can realize the communication and interconnection between the first device 11 and the second device 12. Further, the second device 12 may be electrically connected to the package substrate 20. Thus, the first device 11 is electrically connected to the package substrate 20.

[0113] In some embodiments, Fig.13 and Fig.14 As shown, the first sub-portion 201 of the flexible intermediary layer 2 is located on one side of the second surface 112 of the first device 11, and the second sub-portion 202 of the flexible intermediary layer 2 is located on one side of the second surface 122 of the second device 12. Bending the flexible intermediary layer 2 includes: bending the flexible intermediary layer 2 between the first sub-portion 201 and the second sub-portion 202, that is, bending Fig.13The flexible intermediate layer 2 is located at the middle A position, and the first surface 111 of the first device 11 and the first surface 121 of the second device 12 are arranged opposite to each other and connected, the second surface 112 of the first device 11 and the second surface 122 of the second device 12 are arranged back to back, and the first connecting sub-portion 203 is located on one side of the first device 11 and the second device 12.

[0114] It should be noted that “the first connecting sub-portion 203 is located on one side of the first device 11 and the second device 12” means that the first connecting sub-portion 203 is located on the side of the first device 11 and the second device 12, that is, taking the packaging substrate 20 as a horizontal plane, when the first device 11 and the second device 12 are placed horizontally on the packaging substrate 20, the side of the first device 11 and the second device 12.

[0115] Through the above-mentioned arrangement, the first connecting sub-section 203 can connect the first sub-section 201 and the second sub-section 202 to realize communication and interconnection between the first device 11 and the second device 12, and is located on one side of the first device 11 and the second device 12, occupying a smaller area on the packaging substrate 20, which is beneficial to reducing the area of ​​the chip stacking structure 10 on the packaging substrate 20 and is beneficial to the miniaturization of electronic devices.

[0116] In some embodiments, reference Figure 6 After providing the flexible interposer 2, the first device 11 and the second device 12, the preparation method further includes: connecting a plurality of chips to the first interposer 3 to form the first device 11; connecting a plurality of chips to the second interposer 4 to form the second device 12. The surface of the first interposer 3 facing away from the chip is connected to the first sub-portion 201, and the surface of the second interposer 4 facing away from the chip is connected to the second sub-portion 202.

[0117] It can be understood that the surface of the first interposer 3 facing away from the chip is the second surface 112 of the first device 11; the surface of the second interposer 4 facing away from the chip is the second surface 122 of the second device 12. Based on the above steps, the flexible interposer 2 between the first interposer 3 and the second interposer 4 is bent, so that the first surface 111 of a first device 11 is connected to the first surface 121 of a second device 12, and the second surface 122 of the second device 12 is electrically connected to the packaging substrate 20. Such a configuration is conducive to reducing the area of ​​the chip stacking structure 10 on the packaging substrate 20, which is conducive to the miniaturization of electronic devices.

[0118] Fig.15 1 is a schematic structural diagram of the chip stacking structure 10 before bending provided in some embodiments of the present disclosure. Fig.16 yes Fig.15In some embodiments, while providing the flexible interposer 2, the first device 11 and the second device 12, it also includes: providing a third device 13, the flexible interposer 2 also includes a third sub-section 204 and a fourth sub-section 206, and the fourth sub-section 206 is spaced apart from the first sub-section 201.

[0119] While connecting the second surface 112 of the first device 11 with the flexible intermediate layer 2 , the method also includes: connecting the second surface 112 of the first device 11 with the fourth sub-portion 206 , and connecting the third device 13 with the third sub-portion 204 .

[0120] Bending the flexible intermediate layer 2 also includes: bending the flexible intermediate layer 2 between the third sub-section 204 and the fourth sub-section 206 to form a second connecting sub-section 205. Fig.15 The flexible interposer 2 at position B in the middle is formed after bending Fig.16 After the second connecting sub-portion 205 is formed, the second surface 132 of the third device 13 is disposed opposite to the first surface 111 of the first device 11, and the first surface 131 of the third device 13 is disposed opposite to the second surface 112 of the first device 11.

[0121] In the chip stacking structure 10 formed by the above steps, the first device 11, the second device 12 and the third device 13 are stacked along the first direction X, which is beneficial to reducing the area occupied by the chip stacking structure 10 on the packaging substrate 20 and is beneficial to the miniaturization of electronic devices.

[0122] Fig.17 1 is a schematic structural diagram of the chip stacking structure 10 before bending provided in some embodiments of the present disclosure. Fig.18 yes Fig.17 FIG. 1 is a schematic structural diagram of the chip stacking structure 10 after being bent.

[0123] In some embodiments, Fig.17 and Fig.18 As shown, while providing the flexible intermediate layer 2, the first device 11 and the second device 12, it also includes: providing a fourth device 14, and the flexible intermediate layer 2 also includes a fifth sub-section 207 and a sixth sub-section 209, and the sixth sub-section 209 is spaced apart from the third sub-section 204 along the second direction Y.

[0124] While connecting the second surface 112 of the first device 11 with the flexible intermediate layer 2 , the second surface 132 of the third device 13 is connected with the third sub-section 204 and the sixth sub-section 209 , and the second surface 142 of the fourth device 14 is connected with the fifth sub-section 207 .

[0125] For example, the second surface 132 of the third device 13 may be electrically connected to the third sub-portion 204 and the sixth sub-portion 209 through the connection portion 210 . The second surface 142 of the fourth device 14 may be electrically connected to the fifth sub-portion 207 through the connection portion 210 .

[0126] After providing the fourth device 14, the flexible intermediary layer 2 further includes the fifth sub-portion 207 and the sixth sub-portion 209, bending the flexible intermediary layer 2 further includes: bending the flexible intermediary layer 2 between the fifth sub-portion 207 and the sixth sub-portion 209 to form the third connecting sub-portion 208. Fig.17 The flexible interposer 2 at the middle C position forms Fig.18 The third connecting sub-portion 208 is disposed in the fourth device 14. The second surface 142 of the fourth device 14 is disposed opposite to the first surface 111 of the first device 11, and the first surface 141 of the fourth device 14 is disposed opposite to the second surface 112 of the first device 11.

[0127] When multiple fourth devices 14 need to be packaged, multiple third sub-units 204, multiple fourth sub-units 206, multiple fifth sub-units 207, and multiple sixth sub-units 209 can be provided. In two adjacent fourth devices 14, the second surface 142 of one fourth device 14 is connected to the third sub-unit 204 and the sixth sub-unit 209, and the first surface 141 of the other fourth device 14 is connected to the fifth sub-unit 207 and the fourth sub-unit 206. In this way, the first device 11, the second device 12, the third device 13, and the fourth device 14 can be stacked along the first direction X, which is beneficial to reducing the area occupied by the chip stacking structure 10 on the packaging substrate 20, and is beneficial to the miniaturization of electronic devices.

[0128] Fig.19 1 is a schematic structural diagram of the chip stacking structure 10 before bending provided in some embodiments of the present disclosure. Fig. 20 yes Fig.19 FIG. 1 is a schematic structural diagram of the chip stacking structure 10 after being bent.

[0129] In some embodiments, Fig.19 and Fig. 20 As shown, while providing the flexible intermediate layer 2 , the first device 11 and the second device 12 , it also includes: providing a fourth device 14 , and the flexible intermediate layer 2 also includes a fifth sub-section 207 and a sixth sub-section 209 , and the sixth sub-section 209 is spaced apart from the third sub-section 204 .

[0130] While connecting the second surface 112 of the first device 11 to the flexible intermediate layer 2 , it also includes: connecting the first surface 131 of the third device 13 to the third sub-section 204 , connecting the first surface 131 of the third device 13 to the sixth sub-section 209 , and connecting the second surface 142 of the fourth device 14 to the fifth sub-section 207 .

[0131] For example, the first surface 131 of the third device 13 may be electrically connected to the third sub-portion 204 through the connector 5. The first surface 131 of the third device 13 may be electrically connected to the sixth sub-portion 209 through the connector 5. The second surface 142 of the fourth device 14 may be electrically connected to the fifth sub-portion 207 through the connector 5.

[0132] Bending the flexible intermediate layer 2 also includes: bending the flexible intermediate layer 2 between the fifth sub-section 207 and the sixth sub-section 209 to form a third connecting sub-section 208. Fig.19 The flexible interposer 2 at position D in the middle forms Fig. 20 The third connecting sub-portion 208 is disposed in the fourth device 14. The second surface 142 of the fourth device 14 is disposed opposite to the first surface 111 of the first device 11, and the first surface 141 of the fourth device 14 is disposed opposite to the second surface 112 of the first device 11.

[0133] When multiple fourth devices 14 need to be packaged, multiple fourth devices 14, third sub-units 204, fourth sub-units 206, fifth sub-units 207 and sixth sub-units 209 can be provided. On the basis of the above embodiment, two adjacent fourth devices 14 can be stacked along the first direction X, the first surface 141 of one fourth device 14 is electrically connected to the fifth sub-unit 207 and the fourth sub-unit 206, and the second surface 142 of one fourth device 14 is connected to the first surface 141 of another fourth device 14, and the second surface 142 of another fourth device 14 is electrically connected to the third sub-unit 204 and the sixth sub-unit 209. In this way, the first device 11, the second device 12, the third device 13 and the fourth device 14 can be stacked along the first direction X, which is beneficial to reducing the area occupied by the chip stacking structure 10 on the packaging substrate 20, and is beneficial to the miniaturization of electronic devices.

[0134] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A chip stacking structure, characterized in that: include: A first device and a second device are stacked, wherein a first surface of the first device and a first surface of the second device are arranged opposite to each other and connected, and a second surface of the first device and a second surface of the second device are arranged opposite to each other; A flexible intermediary layer includes a first sub-section, a first connecting sub-section, and a second sub-section, wherein the first connecting sub-section is connected between the first sub-section and the second sub-section, the first sub-section is located on a side of the first device facing away from the second device, and the second sub-section is located on a side of the second device facing away from the first device.

2. The chip stacking structure according to claim 1, characterized in that: The flexible intermediate layer includes a flexible substrate and a first electrical connection layer which are stacked. The first electrical connection layer is located on one side of the flexible substrate and is connected to the first device and the second device.

3. The chip stacking structure according to claim 2, characterized in that: Also includes: The material of the flexible substrate includes at least one of polyimide and polyester resin.

4. The chip stacking structure according to claim 2 or 3, characterized in that: In a direction perpendicular to the first surface of the first device, the first sub-portion partially overlaps with the first device, and the second sub-portion partially overlaps with the second device.

5. The chip stacking structure according to claim 4, characterized in that: The first device includes a first interposer and a plurality of chips, wherein the plurality of chips are spaced apart on the first interposer and connected to the first interposer, and a surface of the first interposer away from the plurality of chips is a second surface of the first device; And / or, the second device includes a second interposer and a plurality of chips, the plurality of chips are spaced apart on the second interposer and connected to the second interposer, and a surface of the second interposer facing away from the plurality of chips is a second surface of the second device.

6. The chip stacking structure according to claim 5, characterized in that: A chip of the first device and a chip of the second device are stacked and connected.

7. The chip stacking structure according to claim 4, characterized in that: The first device and / or the second device is a chip.

8. The chip stacking structure according to claim 4, characterized in that: Also comprising a third component, the third component is located on a side of the first sub-section away from the first component; The flexible interposer also includes a third sub-portion, a second connecting sub-portion, and a fourth sub-portion located on a side of the first device facing away from the second device, the second connecting sub-portion being connected between the third sub-portion and the fourth sub-portion, the fourth sub-portion being located between the third sub-portion and the first device, the third sub-portion being connected to the third device, and the fourth sub-portion being connected to the second surface of the first device.

9. The chip stacking structure according to claim 8, characterized in that: The flexible intermediary layer further comprises a second electrical connection layer and a conductive through hole, wherein the conductive through hole penetrates the flexible substrate, and the second electrical connection layer is located on a side of the flexible substrate away from the first electrical connection layer; The third sub-section is located on a side of the third device away from the first device and is connected to the second surface of the third device. The second surface of the third device is arranged opposite to the first surface of the first device, and the first surface of the third device is arranged opposite to the second surface of the first device.

10. The chip stacking structure according to claim 8 or 9, characterized in that: The fourth sub-portion is spaced apart from the first sub-portion.

11. The chip stacking structure according to claim 9, characterized in that: Also comprising a plurality of fourth devices arranged in a stacked manner, wherein the fourth devices are located on a side of the third device away from the first device; The flexible interposer further comprises a plurality of connection parts, wherein the connection parts comprise a fifth sub-part, a third connection sub-part and a sixth sub-part, wherein the third connection sub-part is connected between the fifth sub-part and the sixth sub-part, and the fifth sub-part is farther away from the third device than the sixth sub-part; For one of the connecting parts: the fifth sub-part and the sixth sub-part are located on both sides of one of the fourth devices, and the fifth sub-part is connected to the second surface of one of the fourth devices, the sixth sub-part is connected to the second surface of another device, the other device and the fourth device are two adjacent devices, and the second surface of the fourth device is arranged back to back with the first surface of the third device.

12. The chip stacking structure according to claim 8, characterized in that: The third sub-section is located on a side of the third device close to the first device and is connected to a first surface of the third device. The first surface of the third device is arranged opposite to the second surface of the first device.

13. The chip stacking structure according to claim 12, characterized in that: Also included is a fourth device, the fourth device is located on a side of the third device away from the first device, a first surface of the fourth device is disposed opposite to the first surface of the third device, and a second surface of the fourth device is disposed opposite to and connected to the second surface of the third device; The flexible intermediary layer also includes a fifth sub-section, a third connecting sub-section and a sixth sub-section, the third connecting sub-section is connected between the fifth sub-section and the sixth sub-section, the fifth sub-section is located on a side of the fourth device facing away from the third device and is connected to the first surface of the fourth device, and the sixth sub-section is located on a side of the third device facing away from the fourth device and is connected to the first surface of the third device.

14. A method for preparing a chip stacking structure, characterized in that: include: Providing a flexible interposer, a first device, and a second device; Connecting the second surface of the first device to the flexible intermediary layer, and connecting the second surface of the second device to the flexible intermediary layer; The flexible intermediate layer is bent to form a first connecting sub-portion, and the first device and the second device are stacked.

15. The method for preparing a chip stacking structure according to claim 14, characterized in that: The first sub-portion of the flexible intermediary layer is located on one side of the second surface of the first device, and the second sub-portion of the flexible intermediary layer is located on one side of the second surface of the second device; and the bending of the flexible intermediary layer comprises: The flexible intermediary layer between the first sub-section and the second sub-section is bent, and the first surface of the first device and the first surface of the second device are arranged opposite to each other and connected, the second surface of the first device and the second surface of the second device are arranged opposite to each other, and the first connecting sub-section is located on one side of the first device and the second device.

16. The method for preparing a chip stacking structure according to claim 15, characterized in that: The preparation method comprises: Connecting a plurality of chips to a first interposer to form the first device; connecting a plurality of chips to a second interposer to form the second device; A surface of the first interposer facing away from the chip is connected to the first sub-portion, and a surface of the second interposer facing away from the chip is connected to the second sub-portion.

17. The method for preparing a chip stacking structure according to claim 15, characterized in that: The preparation method includes: while providing the flexible interposer, the first device and the second device, also includes: Providing a third device, wherein the flexible interposer further comprises a third sub-portion and a fourth sub-portion, and the fourth sub-portion is spaced apart from the first sub-portion; While connecting the second surface of the first device to the flexible intermediate layer, the method further includes: connecting the second surface of the first device to the fourth sub-section, and connecting the third device to the third sub-section; The bending of the flexible intermediary layer also includes: bending the flexible intermediary layer between the third sub-section and the fourth sub-section to form a second connecting sub-section, and making the second surface of the third device opposite to the first surface of the first device, and the first surface of the third device facing the second surface of the first device.

18. The method for preparing a chip stacking structure according to claim 17, characterized in that: The preparation method includes: while providing the flexible interposer, the first device and the second device, also includes: Providing a fourth device, wherein the flexible interposer further comprises a fifth sub-portion and a sixth sub-portion, and the sixth sub-portion is spaced apart from the third sub-portion; While connecting the second surface of the first device to the flexible intermediate layer, the method further includes: connecting the second surface of the third device to the third sub-section and the sixth sub-section, and connecting the second surface of the fourth device to the fifth sub-section; The bending of the flexible intermediary layer also includes: bending the flexible intermediary layer between the fifth sub-section and the sixth sub-section to form a third connecting sub-section, and making the second surface of the fourth device opposite to the first surface of the first device, and the first surface of the fourth device facing the second surface of the first device.

19. The method for preparing a chip stacking structure according to claim 17, characterized in that: The preparation method includes: while providing the flexible interposer, the first device and the second device, also includes: Providing a fourth device, wherein the flexible interposer further comprises a fifth sub-portion and a sixth sub-portion, and the sixth sub-portion is spaced apart from the third sub-portion; While connecting the second surface of the first device to the flexible intermediate layer, the method further includes: connecting the first surface of the third device to the third sub-section, connecting the first surface of the third device to the sixth sub-section, and connecting the second surface of the fourth device to the fifth sub-section; The bending of the flexible intermediary layer also includes: bending the flexible intermediary layer between the fifth sub-section and the sixth sub-section to form a third connecting sub-section, and making the second surface of the fourth device opposite to the first surface of the first device, and the first surface of the fourth device facing the second surface of the first device.

20. A packaging structure, characterized in that: include: A chip stacking structure, wherein the chip stacking structure is the chip stacking structure according to any one of claims 1 to 13, or the chip stacking structure is prepared by the chip stacking structure preparation method according to any one of claims 14 to 19; A packaging substrate is electrically connected to the chip stacking structure.

21. An electronic device, characterized in that: It comprises a circuit board and the packaging structure as claimed in claim 20, wherein the circuit board is electrically connected to the packaging structure.

Images