Hybrid discrete device for photovoltaic energy storage

Abstract

The invention relates to the technical field of photovoltaic energy storage, in particular to a hybrid discrete device for photovoltaic energy storage, which comprises a plurality of hybrid discrete devices, each hybrid discrete device comprises at least one insulated gate bipolar transistor (IGBT) and at least one metal oxide semiconductor (MOS) tube connected with the IGBT, the hybrid discrete devices are connected to form an inverter circuit, and the inverter circuit is connected with the hybrid discrete devices. The MOS tube is controllably conducted based on the first illumination intensity signal and the third current signal, and the IGBT tube is controllably conducted based on the second illumination intensity signal and the third illumination intensity signal. A mixed single tube structure is adopted, different characteristics of the IGBT tube and the MOS tube are utilized, more flexible power conversion is achieved, a circuit structure of an inversion loop is freely combined based on actual current, different powers are compatible, and the device can well adapt to the situation that current continuously changes in a photovoltaic energy storage system.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic energy storage, and in particular to a hybrid discrete device for photovoltaic energy storage. Background Art

[0002] At present, the industry has hybrid insulated gate bipolar transistor (IGBT) and silicon carbide semiconductor field effect transistor (SiC MOSFET) modules. The advantage is that the degree of integration is high, but the disadvantage is that the design of the whole machine is relatively simple and the cost is relatively high. Since the module is integrated, its internal circuit structure and connection method are fixed, and there are great restrictions in different power segments. If you want to unify the high-power and low-power compatible packaging, the module will be larger and cause unnecessary waste in the low-power segment. Summary of the invention

[0003] The purpose of the present invention is to provide a hybrid discrete device for photovoltaic energy storage to solve the above technical problems;

[0004] The technical problem solved by the present invention can be achieved by adopting the following technical solutions:

[0005] A hybrid discrete device device for photovoltaic energy storage includes a plurality of hybrid discrete devices, each of which includes at least one IGBT tube and at least one MOS tube connected to the IGBT tube, the hybrid discrete devices are connected to form an inverter circuit, the MOS tube is controllably turned on based on a first light intensity signal and a third current signal, and the IGBT tube is controllably turned on based on a second light intensity signal and the third light intensity signal.

[0006] Preferably, the IGBT tubes in the hybrid discrete device are connected in series in the same direction, the MOS tubes in the hybrid discrete device are connected in series in the same direction, the anode end of the anti-parallel diode of the IGBT tube located at the first end of the hybrid discrete device is connected to the anode end of the body diode of the MOS tube, and the cathode end of the anti-parallel diode of the IGBT tube located at the second end of the hybrid discrete device is connected to the cathode end of the body diode of the MOS tube;

[0007] The current output value corresponding to the first light intensity signal is smaller than the current output value corresponding to the second light intensity signal, and the current output value corresponding to the second light intensity signal is smaller than the current output value corresponding to the third light intensity signal.

[0008] Preferably, the inverter circuit includes:

[0009] A first level connection branch, wherein the first level connection branch is provided with a first hybrid discrete part, a first end of the first hybrid discrete part is connected to a connection node, and a second end of the first hybrid discrete part is connected to a first level signal;

[0010] a second level connection branch, wherein the second level connection branch is provided with a third hybrid discrete part and a second hybrid discrete part, a first end of the third hybrid discrete part is connected to a second level signal, a second end of the second hybrid discrete part is connected to a second end of the third hybrid discrete part, and a first end of the second hybrid discrete part is connected to the connection node;

[0011] The third level connection branch includes a fourth hybrid discrete part, a first end of the fourth hybrid discrete part is connected to a third level signal, and a second end of the fourth hybrid discrete part is connected to the connection node.

[0012] Preferably, the first hybrid discrete part includes at least one first hybrid discrete device connected in series in the same direction, the second hybrid discrete part includes at least one second hybrid discrete device connected in series in the same direction, the third hybrid discrete part includes at least one third hybrid discrete device connected in series in the same direction, and the fourth hybrid discrete part includes at least one fourth hybrid discrete device connected in series in the same direction;

[0013] The hybrid discrete devices include the first hybrid discrete device, the second hybrid discrete device, the third hybrid discrete device, and the fourth hybrid discrete device.

[0014] Preferably,

[0015] The first hybrid discrete part and the third hybrid discrete part are controllably conductive in a direction from the first level signal to the second level signal based on a first loop conductive signal;

[0016] The second hybrid discrete part and the fourth hybrid discrete part are controllably conductive in a direction from the second level signal to the third level signal based on a second loop conductive signal;

[0017] The first hybrid discrete portion and the fourth hybrid discrete portion are controllably conductive in a direction from the first level signal to the third level signal based on a third loop conductive signal.

[0018] Preferably, a groove for connecting a mounting card is provided on the packaging shell of the hybrid discrete device, the hybrid discrete device is evenly distributed on a heat sink, the first end of the mounting card is connected to the groove, and the second end of the mounting card is connected to the upper surface of the heat sink.

[0019] Preferably, a heat dissipation substrate is provided on the back of the packaging shell, the heat dissipation substrate is embedded in the packaging shell, and the heat dissipation surface of the heat dissipation substrate is exposed from the back of the packaging shell and connected to the radiator.

[0020] Preferably, the heat dissipation substrate is a ceramic substrate clad with copper on both sides, and the thickness of the exposed copper layer of the heat dissipation substrate is less than or equal to the thickness of the internal copper layer of the heat dissipation substrate.

[0021] Preferably, a pin terminal is provided on a single side of the packaging shell, the pin terminal includes a power pin and a signal pin, the power pin and the signal pin of each hybrid discrete device are located on the same side, the size of the power pin is larger than the size of the signal pin, and the pin terminal is connected to the heat dissipation substrate.

[0022] Preferably, the pin terminals are all special-shaped structures bent multiple times, and the pin terminals include a connecting portion extending from a side of the packaging shell, a pin tip pointing vertically upward, and a plurality of bending portions located between the connecting portion and the pin tip.

[0023] Beneficial effects of the present invention: Due to the adoption of the above technical scheme, the present invention adopts a hybrid single-tube structure, utilizes the different characteristics of the IGBT tube and the MOS tube, realizes more flexible power conversion, and is compatible with different powers based on the circuit structure of the actual current free combination inverter circuit, which can better adapt to the situation of constantly changing current in the photovoltaic energy storage system. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of the front structure of the hybrid discrete device in an embodiment of the present invention;

[0025] Figure 2 It is a schematic diagram of the side structure of a hybrid discrete device in an embodiment of the present invention;

[0026] Figure 3 It is a schematic diagram of the back structure of the hybrid discrete device in an embodiment of the present invention;

[0027] Figure 4 A top view of a hybrid discrete device for photovoltaic energy storage according to an embodiment of the present invention;

[0028] Figure 5 It is a structural diagram of a hybrid discrete device for photovoltaic energy storage in an embodiment of the present invention;

[0029] Figure 6 It is a circuit diagram of a hybrid discrete device for photovoltaic energy storage in an embodiment of the present invention;

[0030] Figure 7 Schematic diagram of a small current loop in which the first loop conduction signal is effective in an embodiment of the present invention;

[0031] Figure 8 Schematic diagram of a medium current loop in which the first loop conduction signal is effective in an embodiment of the present invention;

[0032] Fig. 9 Schematic diagram of a large current loop in which the first loop conduction signal is effective in an embodiment of the present invention;

[0033] Fig.10 Schematic diagram of a small current loop in which the second loop conduction signal is effective in an embodiment of the present invention;

[0034] Fig.11 Schematic diagram of a small current loop in which the third loop conduction signal is effective in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0037] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0038] A hybrid discrete device for photovoltaic energy storage, such as Figures 1 to 5 As shown, it includes several hybrid discrete devices, each of which includes at least one IGBT tube and at least one MOS tube connected to the IGBT tube. The hybrid discrete devices are connected to form an inverter circuit. The MOS tube can be turned on controllably based on the first light intensity signal and the third light intensity signal, and the IGBT tube can be turned on controllably based on the second light intensity signal and the third light intensity signal.

[0039] Specifically, the present invention adopts a hybrid single-tube structure, the inverter circuit structure can be freely combined at the whole machine end, and a single or dual transistor can be used in the low-power segment, and the medium and high-power ends can be solved by increasing the number of series and parallel connections.

[0040] In a preferred embodiment, the IGBT tubes in the hybrid discrete device are connected in series in the same direction, the MOS tubes in the hybrid discrete device are connected in series in the same direction, the anode end of the anti-parallel diode of the IGBT tube located at the first end of the hybrid discrete device is connected to the anode end of the body diode of the MOS tube, and the cathode end of the anti-parallel diode of the IGBT tube located at the second end of the hybrid discrete device is connected to the cathode end of the body diode of the MOS tube;

[0041] The current output value corresponding to the first light intensity signal is smaller than the current output value corresponding to the second light intensity signal, and the current output value corresponding to the second light intensity signal is smaller than the current output value corresponding to the third light intensity signal.

[0042] Specifically, the internal chip of the hybrid discrete device of the present invention must include at least one IGBT and at least one MOS tube, the IGBT tube has a corresponding anti-parallel diode, and the Mosfet has a corresponding body diode; further specifically, the internal chip of the hybrid discrete device of the present invention includes 1-2 IGBTs, 1-2 diodes and 1-2 silicon carbide Mosfets.

[0043] Multiple chips can be connected into an inverter circuit using aluminum bonding wires, aluminum ribbons, copper bonding wires, copper busbars, etc. according to different power requirements.

[0044] The signal circuits of IGBT and MOS are independent of each other and are distributed on both sides. The high and low potentials of the external circuit are used to control the on and off of the device. The power circuits are connected to each other. Both IGBT and MOS can use anti-parallel diodes when freewheeling, and the connected power circuits can better reduce the loop inductance.

[0045] In a preferred embodiment, the inverter circuit includes:

[0046] A first level connection branch, the first level connection branch is provided with a first hybrid discrete part, a first end of the first hybrid discrete part is connected to a connection node N, and a second end of the first hybrid discrete part is connected to a first level signal;

[0047] a second level connection branch, the second level connection branch is provided with a second hybrid discrete part and a third hybrid discrete part, a first end of the third hybrid discrete part is connected to the second level signal, a second end of the second hybrid discrete part is connected to the second end of the third hybrid discrete part, and a first end of the second hybrid discrete part is connected to the connection node N;

[0048] The third level connecting branch includes a fourth hybrid discrete part, a first end of the fourth hybrid discrete part is connected to the third level signal, and a second end of the fourth hybrid discrete part is connected to the connecting node N.

[0049] Specifically, the hybrid discrete devices are connected to form an inverter circuit, the inverter circuit is used for AC-DC conversion, the MOS tube is controllably turned on based on the first light intensity signal and the third light intensity signal, and the IGBT tube is controllably turned on based on the second light intensity signal and the third light intensity signal. According to the unstable switching of the solar illumination intensity in the photovoltaic energy storage system, the present invention realizes the effective switching of the IGBT tube and the MOS tube based on the current corresponding to the solar illumination intensity to adapt to the illumination conditions of different intensities.

[0050] The IGBT tubes and MOS tubes in the hybrid discrete device are connected in series in the same direction, and the IGBT tube anti-parallel diodes and the MOS tube body diodes at both ends of the device are specifically connected. The present invention can increase or decrease the number of IGBT tubes and MOS tubes based on actual needs, which helps to share the voltage, reduce the voltage stress borne by a single device, and improve the voltage resistance.

[0051] Specifically, the inverter circuit includes a first level connection branch, a second level connection branch and a third level connection branch. Each branch has a corresponding hybrid discrete part, which is formed by connecting hybrid discrete devices in series and connected to each other through a connection node N. Each hybrid discrete part controls the conduction direction based on different circuit conduction signals to achieve precise control of level conversion and realize three-level inversion.

[0052] The present invention makes full use of the characteristics of IGBT and MOS in hybrid discrete devices. IGBT has the ability to control high voltage and large current, and MOS has the advantages of high input impedance and fast switching speed. The present invention uses MOS under low current, IGBT under medium current, and both at full current, so that the hybrid discrete devices can play their respective advantages under different working conditions and improve the overall performance.

[0053] In a preferred embodiment, the first hybrid discrete part includes at least one first hybrid discrete device 11 connected in series in the same direction, the second hybrid discrete part includes at least one second hybrid discrete device 12 connected in series in the same direction, the third hybrid discrete part includes at least one third hybrid discrete device 13 connected in series in the same direction, and the fourth hybrid discrete part includes at least one first hybrid discrete device 11 connected in series in the same direction;

[0054] The hybrid discrete devices include a first hybrid discrete device 11 , a second hybrid discrete device 12 , a third hybrid discrete device 13 and a fourth hybrid discrete device 14 .

[0055] Specifically, the inverter circuit includes a first hybrid discrete device 11, a second hybrid discrete device 12, a third hybrid discrete device 13 and a fourth hybrid discrete device 14;

[0056] The first hybrid discrete device 11 is a plurality of hybrid discrete devices, the second hybrid discrete device 12 is a plurality of hybrid discrete devices, the third hybrid discrete device 13 is a plurality of hybrid discrete devices, and the fourth hybrid discrete device 14 is a plurality of hybrid discrete devices;

[0057] Each hybrid discrete device includes a number of IGBT tubes and MOS tubes; the present invention takes the first hybrid discrete device 11 as a hybrid discrete device, the second hybrid discrete device 12 as a hybrid discrete device, the third hybrid discrete device 13 as a hybrid discrete device, and the fourth hybrid discrete device 14 as a hybrid discrete device, and each hybrid discrete device includes an IGBT tube and a MOS tube as an example.

[0058] The circuit diagram of this transmitter is as follows Figure 6 As shown, in other embodiments, if the number of hybrid discrete devices or the number of IGBT tubes and MOS tubes in the hybrid discrete devices is to be increased, they can be increased in the same direction in series. For example, D1 can be represented by several IGBT tubes connected in series in the same direction, M1 can be represented by several MOS tubes connected in series in the same direction, and so on.

[0059] The first hybrid discrete device 11 includes a first IGBT tube Q1, a first MOS tube M1 and a first anti-parallel diode D1. The anode end of the first anti-parallel diode D1 of the first IGBT tube Q1 is connected to the anode end of the body diode of the first MOS tube M1 as the first end of the first hybrid discrete device 11 connected to the connection node N. The cathode end of the first anti-parallel diode D1 of the first IGBT tube Q1 is connected to the cathode end of the body diode of the first MOS tube M1 as the second end of the first hybrid discrete device 11 connected to the first level signal.

[0060] The second hybrid discrete device 12 includes a second IGBT tube Q2, a second MOS tube M2, and a second anti-parallel diode D2. The anode end of the second anti-parallel diode D2 of the second IGBT tube Q2 is connected to the anode end of the body diode of the second MOS tube M2 as the first end of the second hybrid discrete device 12 connected to the connection node N, and the cathode end of the second anti-parallel diode D2 of the second IGBT tube Q2 is connected to the cathode end of the body diode of the second MOS tube M2 as the second end of the second hybrid discrete device 12.

[0061] The third hybrid discrete device 13 includes a third IGBT tube Q3, a third MOS tube M3 and a third anti-parallel diode D3. The anode end of the third anti-parallel diode D3 of the third IGBT tube Q3 is connected to the anode end of the body diode of the third MOS tube M3 as the first end of the third hybrid discrete device 13 connected to the second level signal. The cathode end of the third anti-parallel diode D3 of the third IGBT tube Q3 is connected to the cathode end of the body diode of the third MOS tube M3 as the second end of the third hybrid discrete device 13 connected to the second end of the second hybrid discrete device 12.

[0062] The fourth hybrid discrete device 14 includes a fourth IGBT tube Q4, a fourth MOS tube M4 and a fourth anti-parallel diode D4. The anode end of the fourth anti-parallel diode D4 of the fourth IGBT tube Q4 is connected to the anode end of the body diode of the fourth MOS tube M4 as the first end of the fourth hybrid discrete device 14 connected to the third level signal, and the cathode end of the fourth anti-parallel diode D4 of the fourth IGBT tube Q4 is connected to the cathode end of the body diode of the fourth MOS tube M4 as the second end of the fourth hybrid discrete device 14 connected to the connection node N.

[0063] Therefore, the present invention requires at least four hybrid discrete devices to form a circuit.

[0064] In photovoltaic applications, the current size is controlled by the light intensity and changes all the time. It cannot have a fixed working mode. When the light is strong, the current output is large, and when the light is weak, the current output is small.

[0065] In this application example, when the current output is small, the MOS tube switches and the IGBT tubes are all turned off, that is, only the first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 are working;

[0066] Since the internal resistance of SiC mosfet is very small at low current, it is more efficient to use MOS tubes at low current. The parasitic body diode of MOS tube generally has poor characteristics. In this application example, the anti-parallel diodes attached to IGBT can be used: the first anti-parallel diode D1, the second anti-parallel diode D2, the third anti-parallel diode D3 and the fourth anti-parallel diode D4 for commutation to improve working efficiency.

[0067] As the intensity of sunlight increases, the current increases. At this time, the IGBT tube is switched on and the MOS tubes remain closed, that is, only the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3, and the fourth IGBT tube Q4 are switched on to work. The internal resistance of the SiC mosfet will increase rapidly with the increase of current, while the IGBT has a small change rate with the current conversion. Therefore, when the current increases, it is more efficient to use the IGBT tube, and the anti-parallel diodes attached to the IGBT are used for commutation: the first anti-parallel diode D1, the second anti-parallel diode D2, the third anti-parallel diode D3 and the fourth anti-parallel diode D4.

[0068] As the sunlight intensity reaches its peak, the current increases to the peak value. At this time, the IGBT tube switches, and the MOS tube also switches, that is, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, the fourth MOS tube M4, the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3, and the fourth IGBT tube Q4 all work, and the working efficiency reaches the maximum value.

[0069] More specifically, the first light intensity signal, the second light intensity signal, and the third light intensity signal in the present invention all correspond to current values ​​under different light intensities. In this embodiment,

[0070] A current less than 30% of the preset current value is a small current, corresponding to the first light intensity signal. At this time, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, and the fourth MOS tube M4 are switched on, the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3, and the fourth IGBT tube Q4 are turned off, and the first anti-parallel diode D1, the second anti-parallel diode D2, the third anti-parallel diode D3, and the fourth anti-parallel diode D4 are commutated.

[0071] The current between 30% and 70% of the preset current value is the medium current, which corresponds to the second light intensity signal. At this time, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, and the fourth MOS tube M4 are turned off, the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3, and the fourth IGBT tube Q4 are switched, and the first anti-parallel diode D1, the second anti-parallel diode D2, the third anti-parallel diode D3, and the fourth anti-parallel diode D4 are commutated.

[0072] A current greater than 70% of the preset current value is a large current, corresponding to the third light intensity signal. At this time, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, the fourth MOS tube M4, the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3, and the fourth IGBT tube Q4 all work, and the working efficiency reaches the maximum value.

[0073] In this application example, four hybrid discrete devices are connected in series to form a working circuit. If a higher output power is required, multiple devices can be connected in parallel. They are fixed on the heat sink by snap-fitting, and the contact surface is coated with thermal conductive material to enhance heat dissipation.

[0074] In a preferred embodiment,

[0075] The first hybrid discrete part and the third hybrid discrete part are controllably conductive in a direction from a first level signal to a second level signal based on a first loop conductive signal;

[0076] The second hybrid discrete part and the fourth hybrid discrete part are controllably conductive in a direction from the second level signal to the third level signal based on the second loop conductive signal;

[0077] The first hybrid discrete portion and the fourth hybrid discrete portion are controllably conductive in a direction from a first level signal to a third level signal based on a third loop conductive signal.

[0078] More specifically, if Figure 7 As shown,

[0079] In this embodiment, the inverter circuit is used to perform AC-DC conversion. The inverter circuit of the present invention connects a first level signal, a second level signal and a third level signal, wherein the first level signal is a high potential signal, the second level signal is a 0 potential signal, and the third level signal is a low potential signal. The inverter circuit is turned on by sequentially switching the first circuit conduction signal, the second circuit conduction signal, and the third circuit conduction signal.

[0080] Take the first circuit where the first circuit conduction signal is turned on as an example:

[0081] In the low current state corresponding to the first light intensity signal, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, and the fourth MOS tube M4 are switched on, the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3, and the fourth IGBT tube Q4 are turned off, and the first anti-parallel diode D1, the second anti-parallel diode D2, the third anti-parallel diode D3, and the fourth anti-parallel diode D4 are commutated;

[0082] When the first loop conduction signal is valid, the first MOS tube M1 and the third MOS tube M3 are turned on, the second MOS tube M2 and the fourth MOS tube M4 are turned off, and the current passes through the first MOS tube M1, the second anti-parallel diode D2 and the body diode of the second MOS tube M2, and the third MOS tube M3 to form a loop.

[0083] like Figure 8 As shown,

[0084] In the medium current state corresponding to the second light intensity signal, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, and the fourth MOS tube M4 are turned off, the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3, and the fourth IGBT tube Q4 are switched on, and the first anti-parallel diode D1, the second anti-parallel diode D2, the third anti-parallel diode D3, and the fourth anti-parallel diode D4 are commutated.

[0085] When the first loop conduction signal is valid, the first IGBT tube Q1 and the third IGBT tube Q3 are turned on, the second IGBT tube Q2 and the fourth IGBT tube Q4 are turned off, and the current passes through the first IGBT tube Q1, the second anti-parallel diode D2 and the body diode of the second MOS tube M2, and forms a loop through the third IGBT tube Q3.

[0086] like Fig. 9 As shown,

[0087] In the high current state corresponding to the third light intensity signal, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, the fourth MOS tube M4, the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3, and the fourth IGBT tube Q4 all work.

[0088] When the first loop conduction signal is valid, the first MOS tube M1, the third MOS tube M3, the first IGBT tube Q1, and the third IGBT tube Q3 are turned on, and the current passes through the first MOS tube M1 and the first IGBT tube Q1, passes through the second anti-parallel diode D2 and the body diode of the second MOS tube M2 to form a loop, and flows out from the third MOS tube M3 and the third IGBT tube Q3.

[0089] like Fig.10 As shown,

[0090] Continuing to take the low current state corresponding to the first light intensity signal as an example, at this time, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, and the fourth MOS tube M4 are switched on, the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3, and the fourth IGBT tube Q4 are turned off, and the first anti-parallel diode D1, the second anti-parallel diode D2, the third anti-parallel diode D3, and the fourth anti-parallel diode D4 are commutated;

[0091] When the second loop conduction signal is valid, the second MOS tube M2 and the fourth MOS tube M4 are turned on, the first MOS tube M1 and the third MOS tube M3 are turned off, and the current forms a loop through the third anti-parallel diode D3 and the body diode of the third MOS tube M3, and flows out after passing through the second MOS tube M2 and the fourth MOS tube M4;

[0092] The deformation of medium current and large current under the second loop conduction signal can refer to the above embodiment, which will not be described in detail here.

[0093] like Fig.11 As shown,

[0094] Continuing to take the low current state corresponding to the first light intensity signal as an example, at this time, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, and the fourth MOS tube M4 are switched on, the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3, and the fourth IGBT tube Q4 are turned off, and the first anti-parallel diode D1, the second anti-parallel diode D2, the third anti-parallel diode D3, and the fourth anti-parallel diode D4 are commutated;

[0095] When the third loop conduction signal is valid, the first MOS tube M1 and the fourth MOS tube M4 are turned on, the second MOS tube M2 and the third MOS tube M3 are turned off, and the current forms a loop through the first MOS tube M1 and the fourth MOS tube M4.

[0096] In a preferred embodiment, further Figures 1 to 5 As shown, a packaging shell 1 of a hybrid discrete device is provided with a groove 2 for connecting a mounting card 6. The hybrid discrete device is evenly distributed on a heat sink. The first end of the mounting card 6 is connected to the groove 2, and the second end of the mounting card 6 is connected to the upper surface of the heat sink.

[0097] Specifically, the packaging shell 1 of the present invention is integrally formed by epoxy injection molding to wrap all other structural components. The shell has functions such as insulation, chip protection, and installation stress.

[0098] At the same time, the one-piece molded shell has good insulation properties, which can effectively prevent electrical short circuits between internal chips and circuits and the external environment, thereby improving the safety of the device. It is especially suitable for high-voltage and high-current environments such as photovoltaic energy storage systems.

[0099] The housing has two grooves 2 for fixing the mounting card 6, and the size of the mounting card 6 is compatible with the existing common discrete device mounting card 6. The advantage of the groove 2 is that the photovoltaic energy storage machine has a higher creepage distance requirement, and the installation groove 2 can increase the creepage distance, eliminating the need to add an external safety insulation protective shell.

[0100] Specifically, when the photovoltaic energy storage device has high requirements for creepage distance, the installation groove 2 can increase the creepage distance. The increase in creepage distance can effectively prevent the surface discharge of the insulating medium caused by excessive electric field strength, thereby improving the safety of the equipment. In addition, this design eliminates the step of adding an external safety insulation protective shell, simplifies the overall structure, and reduces the cost and complexity of the equipment.

[0101] In a preferred embodiment, a heat dissipation substrate 4 is provided on the back of the packaging shell 1 . The heat dissipation substrate 4 is embedded in the packaging shell 1 . The heat dissipation surface of the heat dissipation substrate 4 is exposed from the back of the packaging shell 1 and connected to the radiator 5 .

[0102] Specifically, the insulating heat dissipation substrate 4 generally adopts a ceramic substrate. In order to pursue good performance, a high thermal conductivity ceramic Si3N4 material can be used. The ceramic substrate is covered with copper on both sides. Generally, the thickness of the copper layer on the exposed surface needs to be less than or equal to the copper layer on the inner surface. The purpose is to ensure that the exposed surface is not concave due to process or structural stress, resulting in poor contact with the radiator 5 and heat dissipation problems.

[0103] The insulating heat dissipation substrate 4 can adopt a general heat dissipation method and be installed with the radiator 5 after being coated with thermal grease. In a scenario with high power, in order to ensure good heat dissipation, multiple weldings can be used with the heat dissipation substrate 4. The number of weldings is not limited. In this application example, four weldings are used.

[0104] In a preferred embodiment, the heat dissipation substrate 4 is a ceramic substrate with copper cladding on both sides, and the thickness of the exposed copper layer of the heat dissipation substrate 4 is less than or equal to the thickness of the internal copper layer of the heat dissipation substrate 4 .

[0105] Specifically, a heat dissipation substrate 4 is provided on the back of the package shell 1, and the heat dissipation substrate 4 is embedded in the package shell 1, and its heat dissipation surface is exposed from the back and connected to the heat sink 5. The heat dissipation substrate 4 adopts a ceramic substrate with copper cladding on both sides, and this material has good thermal conductivity. Moreover, the thickness of the copper layer on the exposed surface is less than or equal to the thickness of the copper layer on the inner surface, so that the exposed surface can be prevented from being concave due to process or stress problems, ensuring good contact with the heat sink 5, thereby ensuring the stability of the heat dissipation effect.

[0106] In a preferred embodiment, a pin terminal 3 is provided on a single side of the packaging shell 1, and the pin terminal 3 includes a power pin 32 and a signal pin 31. The power pin 32 and the signal pin 31 of each hybrid discrete device are located on the same side, the size of the power pin 32 is larger than the size of the signal pin 31, and the pin terminal 3 is connected to the heat dissipation substrate 4.

[0107] Specifically, the pin terminal 3 in the present invention adopts a multiple-bending design, which is different from the single-bending design of existing discrete devices, and can be quickly installed on the PCB board through welding. The installation height can be controlled by shortening the length of the pin tip.

[0108] The spacing between the pin terminals 3 is consistent with that of existing discrete devices, which has the advantage of being able to be quickly compatible with the overall design of existing discrete devices.

[0109] The width of a single power pin 32 is between 2mm and 3mm, and the width of a single signal pin 31 is between 1mm and 2mm. Compared with the situation that the pins of traditional discrete devices have the same width, the power pins are enlarged and optimized to increase the current output capacity.

[0110] The pin terminal 3 is connected to the bottom insulated heat dissipation substrate 4 by welding. Traditional discrete devices are connected by binding wires, and the binding wires and the pins cannot dissipate heat, which affects the overcurrent capacity. By welding, the binding wires are placed on the insulated heat dissipation substrate 4, which can effectively dissipate heat. The pins are welded on the insulated heat dissipation substrate 4, which can also ensure heat dissipation.

[0111] The pin terminals 3 are kept on a single side of the package housing 1 and are evenly arranged. Compared with the traditional module, the PCB layout of the whole machine is simpler.

[0112] In a preferred embodiment, the functional pin terminals 3 are all of a multi-bent special-shaped structure, and the pin terminals 3 include a connecting portion extending from the side of the packaging shell 1, a vertically upward pin tip, and a plurality of bent portions between the connecting portion and the pin tip.

[0113] Specifically, a single side of the package housing 1 is provided with a power pin 32 and a signal pin 31 , and pins of all hybrid discrete devices are on the same side, which facilitates the layout and connection of the circuit.

[0114] The size of the power pin 32 is larger than that of the signal pin 31 . This design can meet the large current requirement of power transmission while avoiding signal interference.

[0115] The power pin 32 and the signal pin 31 are special-shaped structures with multiple bends, including a connecting part, a pin tip and a bend part, which can be easily installed and welded. The multiple bend design is different from the single bend of existing discrete devices. It can be quickly installed on the PCB board by welding, and the installation height can be controlled by shortening the length of the pin tip.

[0116] The above description is only a preferred embodiment of the present invention, and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A hybrid discrete device for photovoltaic energy storage, characterized in that: It comprises a plurality of hybrid discrete devices, each of which comprises at least one IGBT tube and at least one MOS tube connected to the IGBT tube, the hybrid discrete devices are connected to form an inverter circuit, the MOS tube is controllably turned on based on a first light intensity signal and a third current signal, and the IGBT tube is controllably turned on based on a second light intensity signal and the third light intensity signal.

2. The hybrid discrete device for photovoltaic energy storage according to claim 1, characterized in that: The IGBT tubes in the hybrid discrete device are connected in series in the same direction, and the MOS tubes in the hybrid discrete device are connected in series in the same direction. The anode end of the anti-parallel diode of the IGBT tube located at the first end of the hybrid discrete device is connected to the anode end of the body diode of the MOS tube, and the cathode end of the anti-parallel diode of the IGBT tube located at the second end of the hybrid discrete device is connected to the cathode end of the body diode of the MOS tube. The current output value corresponding to the first light intensity signal is smaller than the current output value corresponding to the second light intensity signal, and the current output value corresponding to the second light intensity signal is smaller than the current output value corresponding to the third light intensity signal.

3. The hybrid discrete device for photovoltaic energy storage according to claim 1, characterized in that: The inverter circuit comprises: a first level connection branch, wherein the first level connection branch is provided with a first hybrid discrete part, a first end of the first hybrid discrete part is connected to a connection node (N), and a second end of the first hybrid discrete part is connected to a first level signal; a second level connection branch, wherein the second level connection branch is provided with a third hybrid discrete part and a second hybrid discrete part, a first end of the third hybrid discrete part is connected to a second level signal, a second end of the second hybrid discrete part is connected to a second end of the third hybrid discrete part, and a first end of the second hybrid discrete part is connected to the connection node (N); The third level connection branch comprises a fourth hybrid discrete part, a first end of the fourth hybrid discrete part is connected to the third level signal, and a second end of the fourth hybrid discrete part is connected to the connection node (N).

4. The hybrid discrete device for photovoltaic energy storage according to claim 3, characterized in that: The first hybrid discrete part comprises at least one first hybrid discrete device (11) connected in series in the same direction, the second hybrid discrete part comprises at least one second hybrid discrete device (12) connected in series in the same direction, the third hybrid discrete part comprises at least one third hybrid discrete device (13) connected in series in the same direction, and the fourth hybrid discrete part comprises at least one fourth hybrid discrete device (14) connected in series in the same direction; The hybrid discrete device comprises the first hybrid discrete device (11), the second hybrid discrete device (12), the third hybrid discrete device (13) and the fourth hybrid discrete device (14).

5. The hybrid discrete device for photovoltaic energy storage according to claim 3, characterized in that: The first hybrid discrete part and the third hybrid discrete part are controllably conductive in a direction from the first level signal to the second level signal based on a first loop conductive signal; The second hybrid discrete part and the fourth hybrid discrete part are controllably conductive in a direction from the second level signal to the third level signal based on a second loop conductive signal; The first hybrid discrete portion and the fourth hybrid discrete portion are controllably conductive in a direction from the first level signal to the third level signal based on a third loop conductive signal.

6. The hybrid discrete device for photovoltaic energy storage according to claim 1, characterized in that: The packaging shell (1) of the hybrid discrete device is provided with a groove (2) for connecting a mounting card (6); the hybrid discrete device is evenly distributed on a heat sink (5); a first end of the mounting card (6) is connected to the groove (2); and a second end of the mounting card (6) is connected to the upper surface of the heat sink (5).

7. The hybrid discrete device for photovoltaic energy storage according to claim 6, characterized in that: A heat dissipation substrate (4) is provided on the back of the packaging shell (1); the heat dissipation substrate (4) is embedded in the packaging shell (1); the heat dissipation surface of the heat dissipation substrate (4) is exposed from the back of the packaging shell (1) and is connected to the radiator (5).

8. The hybrid discrete device for photovoltaic energy storage according to claim 7, characterized in that: The heat dissipation substrate (4) is a ceramic substrate with copper cladding on both sides, and the thickness of the exposed copper layer of the heat dissipation substrate (4) is less than or equal to the thickness of the built-in copper layer of the heat dissipation substrate (4).

9. The hybrid discrete device for photovoltaic energy storage according to claim 7, characterized in that: A pin terminal (3) is provided on one side of the packaging shell (1), the pin terminal (3) comprising a power pin (32) and a signal pin (31), the power pin (32) and the signal pin (31) of each hybrid discrete device are located on the same side, the size of the power pin (32) is larger than the size of the signal pin (31), and the pin terminal (3) is connected to the heat dissipation substrate (4).

10. The hybrid discrete device for photovoltaic energy storage according to claim 9, characterized in that: The pin terminals (3) are all of a multi-bent special-shaped structure, and the pin terminals (3) comprise a connecting portion extending from the side of the packaging shell (1), a pin tip extending vertically upward, and a plurality of bent portions located between the connecting portion and the pin tip.

Images