A Commutation Failure Suppression Strategy Considering Commutation Bus Voltage Phase Jump

Abstract

The present invention discloses a commutation failure suppression strategy that takes into account the voltage phase jump of the commutation bus, which relates to the field of power engineering and control automation technology, including: constructing a phase-locked loop tracking error prediction model based on the voltage phase jump; constructing a commutation failure suppression strategy that occurs during the fault recovery process based on the voltage phase jump according to the phase-locked loop tracking error prediction model; adjusting the parameters of the commutation failure suppression strategy that occurs during the fault recovery process based on the voltage phase jump, and outputting the final commutation failure suppression strategy. The present invention determines that the essential inducing factor of CFFR is the voltage phase jump; designs a control strategy to prevent commutation failure in the LCC-HVDC system, ensuring the stable transmission of the LCC-HVDC and the safe operation of the power system. Accurately compensate for the voltage phase jump caused by the AC fault, so that the thyristors of the LCC-HVDC have sufficient angle compensation to achieve successful commutation.

Description

Technical Field

[0001] The present invention relates to the field of power engineering and control automation technology, and more particularly to a commutation failure suppression strategy taking into account a commutation bus voltage phase jump. Background Art

[0002] Line converter-based high-voltage direct current (LCC-HVDC) technology has been widely adopted due to its advantages in large-capacity, long-distance power transmission. It is expected to play a more important role in modern power systems, especially in the transmission of large-scale renewable energy (tens of gigawatts) to load centers. However, the existence of commutation failure (CF) significantly affects the security of power transmission. In particular, commutation failure during fault recovery (CFFR) is the most critical, as it can cause the LCC-HVDC to lock up, resulting in long-term active power transmission interruption.

[0003] To address the above issues, a large number of studies have been conducted on the mechanism of CFFR. Studies have found that factors such as AC voltage fluctuations, interactions between controllers, DC current fluctuations, and insufficient reactive power may all lead to the occurrence of CFFR. To this end, a variety of CFFR suppression strategies have been proposed, including methods based on additional equipment or controllers. However, these methods have obvious disadvantages: 1) Equipment-based methods increase construction costs and system complexity; 2) Controller-based methods only consider specific types of CFFR caused by faults in the sending or receiving system; 3) Most importantly, the impact of phase jumps has been ignored in most studies, while studies have found that phase jumps are the main factor leading to CFFR.

[0004] Therefore, how to propose a commutation failure suppression strategy that takes into account the voltage phase jump of the commutation bus, clarify the relationship between the network structure, voltage phase jump, phase-locked loop tracking error and commutation failure during fault recovery, based on the essential inducing effect of voltage phase jump on CFFR, ensure the stable transmission of LCC-HVDC and the safe operation of the power system, and effectively prevent commutation failure in the LCC-HVDC system are issues that technicians in this field urgently need to solve. Summary of the Invention

[0005] In view of this, the present invention provides a commutation failure suppression strategy that takes into account the voltage phase jump of the commutation bus. It clarifies the interrelationships among the network structure, voltage phase jump, phase-locked loop tracking error, and commutation failure during fault recovery. Based on the essential induction effect of voltage phase jump on CFFR, the present invention ensures the stable transmission of LCC-HVDC and the safe operation of the power system, and effectively prevents commutation failure in the LCC-HVDC system. To achieve the above objectives, the present invention adopts the following technical solutions:

[0006] A commutation failure suppression strategy considering the phase jump of the commutation bus voltage includes:

[0007] Construct a phase-locked loop tracking error prediction model based on voltage phase jump;

[0008] Based on the phase-locked loop tracking error prediction model, a commutation failure suppression strategy that occurs during fault recovery based on voltage phase jump is constructed;

[0009] Parameters of the commutation failure suppression strategy occurring during the fault recovery process based on the voltage phase jump are adjusted, and a final commutation failure suppression strategy is output.

[0010] Optionally, the construction of the phase-locked loop tracking error prediction model based on voltage phase jump includes: at the moment of fault occurrence and fault clearing, the voltage phase jump is regarded as having an amplitude of θ PAJ The fault occurs at t = 0s and lasts for T f The Laplace domain expression of the phase-locked loop tracking error is obtained when . The inverse Laplace transform is applied to the Laplace domain expression to obtain the maximum phase-locked loop tracking error faced by the DC system after the fault occurs.

[0011] Optionally, the strategy for suppressing commutation failure occurring during fault recovery based on voltage phase jump includes: constructing a controller for suppressing commutation failure occurring during fault recovery based on voltage phase jump; simulating an improved CIGRE LCC-HVDC reference system for the controller for suppressing commutation failure occurring during fault recovery based on voltage phase jump, analyzing the decisive influence of voltage phase jump on commutation failure occurring during fault recovery, and conducting a rationality analysis of preventing commutation failure occurring during fault recovery based on voltage phase jump.

[0012] Optionally, the rationality analysis includes: single-phase fault analysis at the sending end and three-phase fault analysis at the receiving end.

[0013] Optionally, the controller for suppressing commutation failure that occurs during fault recovery based on voltage phase jump includes: controller 1, controller 2 and controller 3, controller 1 and controller 2 respectively compensate for the phase-locked loop tracking error caused by transient changes in network structure and transient changes in DC power, and controller 3 is used to prevent the fixed arc extinction angle controller from saturating due to a sending-end power grid fault; all controllers are set with dead zones to prevent the controller from being incorrectly started during steady state, and controller 3 uses the sending-end fault signal transmitted from the sending-end power grid as a trigger signal. When there is no fault in the sending-end power grid, the fault signal is 0 and controller 3 will not be activated.

[0014] Optionally, the improved CIGRE LCC-HVDC benchmark system includes: Model 1 and Model 2, wherein Model 1 replaces the equivalent Thevenin system with a transmission line, and other system parameters in Model 1 are the same as those of the original system; in Model 2, in addition to applying the modifications made to Model 1, a load L1 is added to bus 1, and capacitors are connected to the receiving-end grid commutation bus and bus 1, respectively, to maintain their rated voltages.

[0015] Optionally, adjusting the parameters of the commutation failure suppression strategy occurring during the fault recovery process based on the voltage phase jump includes adjusting the parameters of the controller 1 , the controller 2 , and the controller 3 respectively.

[0016] Optionally, tuning the parameters of the controller 1 includes:

[0017] Controller 1 is designed to compensate for the voltage phase jump caused by transient changes in the network structure to suppress the phase-locked loop tracking error caused by the voltage phase jump;

[0018] Simulations show that under the same Rf conditions, faults at the receiving grid's commutation busbar cause the largest voltage phase jump. Since the inverter station is directly connected to the receiving grid's commutation busbar, AC faults at the receiving grid's commutation busbar have the most direct impact on the commutation voltage.

[0019] The AC fault of the receiving-end power grid commutation bus is used to compensate for the voltage phase jump caused by transient changes in the network structure.

[0020] It can be seen from the above technical solution that, compared with the prior art, the present invention discloses a commutation failure suppression strategy that takes into account the phase jump of the commutation bus voltage, which has the following beneficial effects:

[0021] This invention proposes a commutation failure suppression strategy that takes into account commutation bus voltage phase jumps. The strategy includes: constructing a phase-locked loop (PLL) tracking error prediction model based on voltage phase jumps; constructing a commutation failure suppression strategy that occurs during fault recovery based on voltage phase jumps based on the PLL tracking error prediction model; tuning the parameters of the commutation failure suppression strategy that occurs during fault recovery based on voltage phase jumps, and outputting a final commutation failure suppression strategy. In terms of mechanism analysis, the invention clarifies the interrelationships between network structure, voltage phase jumps, PLL tracking error, and commutation failure during fault recovery, determining that the fundamental inducing factor for CFFR is voltage phase jumps, rather than voltage disturbances, control interactions, or DC fluctuations. In terms of control methods, based on the essential inducing effect of voltage phase jumps on CFFR, a control strategy is designed to effectively prevent commutation failures in LCC-HVDC systems, ensuring stable power transmission and safe operation of the LCC-HVDC system. The strategy accurately compensates for voltage phase jumps caused by AC faults, ensuring sufficient angle compensation for successful commutation in the LCC-HVDC thyristors. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0023] Figure 1 Schematic diagram of the linearization model of the SRF-PLL provided by the present invention.

[0024] Figure 2 The voltage phase θ before and after the fault and the corresponding PLL-TE result diagram provided by the present invention.

[0025] Figure 3 This is a schematic diagram of the CFFR suppression controller based on voltage phase jump provided by the present invention.

[0026] Figure 4 Schematic diagram of the improved CIGRE LCC-HVDC benchmark system provided by the present invention.

[0027] Figure 5 The simulation results of Example 1 and Example 2 provided by the present invention are shown in FIG.

[0028] Figure 6 This is a schematic diagram of the power system model provided by the present invention for simulating AC faults at RCBs.

[0029] Figure 7After the RCB provided by the present invention fails, the voltage phase jump (PAJ) of the RCB and the residual voltage E' eq relationship curve diagram.

[0030] Figure 8 The commutation bus voltage U provided by the present invention LCC and the equivalent voltage E of the AC system eq The phasor diagram between .

[0031] Figure 9 The β output by the constant current controller and the fixed arc extinction angle controller of the DC system when the sending end fails provided by the present invention ord Schematic diagram of the principle.

[0032] Figure 10 The different T ini 、T f 、R f 、D f and simulation results under type faults.

[0033] Figure 11 Schematic diagram of the LCC-HVDC system for asynchronous interconnection provided by the present invention.

[0034] Figure 12 The simulation results of Example 3 and Example 4 provided by the present invention are shown in FIG. DETAILED DESCRIPTION

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0036] The embodiment of the present invention discloses a commutation failure suppression strategy considering the phase jump of the commutation bus voltage, including:

[0037] Construct a phase-locked loop tracking error prediction model based on voltage phase jump;

[0038] Based on the phase-locked loop tracking error prediction model, a commutation failure suppression strategy that occurs during fault recovery based on voltage phase jump is constructed;

[0039] Parameters of the commutation failure suppression strategy occurring during the fault recovery process based on the voltage phase jump are adjusted, and a final commutation failure suppression strategy is output.

[0040] In a specific embodiment, a commutation failure suppression strategy considering the commutation bus voltage phase jump includes: a phase-locked loop tracking error prediction method based on voltage phase jump, a CFFR suppression strategy based on voltage phase jump and its parameter setting method. The specific steps are as follows:

[0041] Step 1: Phase-locked loop tracking error prediction method based on voltage phase jump

[0042] The linearization model of the synchronous reference frame-PLL of the LCC-HVDC system is as follows: Figure 1 As shown, where θ represents the actual phase of the voltage, is the phase output of the phase-locked loop. In order to consider the most extreme voltage phase jump that the DC system may encounter, the voltage phase jump should be considered to have an amplitude of θ at the moment of fault occurrence and fault clearing. PAJ Therefore, formula (1) can express that the fault occurs at t = 0s and lasts for T f The Laplace domain expression of the phase-locked loop tracking error (PLL-TE) when . Applying the inverse Laplace transform to formula (1) yields the maximum PLL-TE that the DC system may face after a fault occurs, as shown in formula (2). The schematic diagram is shown in Figure 2 shown.

[0043]

[0044] Where s is the complex variable of Laplace transform, K p is the proportional coefficient of the phase-locked loop, K i is the integral coefficient of the phase-locked loop, θ(s) is the voltage phase after Laplace transform, and P1 and P2 are the coefficients for calculating the maximum tracking error of the phase-locked loop after inverse Laplace transform.

[0045] Step 2: CFFR suppression strategy based on voltage phase jump

[0046] (1) CFFR suppression controller based on voltage phase jump

[0047] Figure 3The proposed CFFR suppression controller is demonstrated. Controllers 1 and 2 compensate for PLL-TE caused by transient changes in network structure and DC power, respectively. Both transient changes in network structure and DC power are caused by AC faults, and the generation of PLL-TE is specifically reflected in the voltage phase jump of the converter bus at the converter station. Controller 3 is used to prevent saturation of the constant arc extinction angle controller (CEA controller) due to faults in the sending-end grid (SE). All controllers are set with dead zones to prevent incorrect activation of the controllers during steady-state. It should be emphasized that controller 3 uses the sending-end fault signal transmitted from the SE system as its trigger signal. When there is no fault in the SE system, the fault signal is 0 and controller 3 is not activated.

[0048] The present invention effectively suppresses CFFR through three additional controllers. Controllers 1 and 2 are used to compensate for the phase-shift-induced thyristor (SCR)-induced commutation (PLL-TE) caused by voltage phase jumps on the inverter station's commutation busbar. The magnitude of the voltage phase jump is used to determine the thyristor triggering deviation caused by PLL-TE, thereby compensating for the thyristor's triggering error and ensuring sufficient angle for successful commutation.

[0049] (2) Rationality analysis of CFFR prevention based on voltage phase jump

[0050] Based on the simulation results of the improved CIGRE LCC-HVDC benchmark system in PSCAD, the decisive influence of voltage phase jump on CFFR is analyzed. Figure 4 As shown in Figure 1, the CIGRE LCC-HVDC benchmark system was modified to accommodate changes in the receiving grid (RE) network structure and adjust the fault location. Model 1 replaces the equivalent Thevenin system with a transmission line with an impedance of 0.0529 + j0.529 (Ω / km). The other system parameters in Model 1 are identical to the original system. In Model 2, in addition to the modifications made in Model 1, a load with a capacity of L1 = 2000 MW is added to Bus 1. Two sets of capacitors, C1 = 15.45 μF and C2 = 18.05 μF, are connected to the receiving grid converter bus (RCB) and Bus 1 to maintain their rated voltage. The receiving grid capacity ratio (SCR) for Models 1 and 2 is 2.42 and 2.69, respectively, indicating that the strength of the two systems is very similar.

[0051] In the specific implementation, the following two examples are established based on Model 1 and Model 2. Since non-permanent AC faults account for approximately 70%-90% of all AC faults in actual systems and exhibit resistive transition impedance, the analysis and example studies in the embodiments of the present invention are based on resistive AC faults to better reflect the actual situation.

[0052] Case 1: A single-phase ground fault (SLG) occurs on the sending-end commutation bus (SCB) of Model 1 and Model 2, and the fault starts at T ini = 2.0 seconds, the fault duration is T f = 0.1 seconds, fault resistance R f =30Ω. This example simulates a relatively minor fault.

[0053] Case 2: A three-phase ground fault (TLG) occurs on the RCBs of Model 1 and Model 2, and the fault starts at T ini = 2.0 seconds, the fault duration is T f = 0.1 seconds, fault resistance R f =1Ω. This example simulates a more serious fault.

[0054] The simulation results of Example 1 and Example 2 are as follows: Figure 5 As shown in the figure, the βmin value is calculated by formula (3), where β min and γ min They represent the critical triggering advance angle and arc extinction angle of the thyristor to avoid CFFR. d 、X B and U LL They represent the RMS values ​​of DC current, leakage reactance of converter transformer and commutation voltage respectively.

[0055]

[0056] According to the simulation results, the single-phase fault analysis at the sending end is carried out: From (a4), it can be seen that CFFR occurs at t = 2.154 seconds in model 1. According to (a3), the trigger advance angle command value β of the controller is ord =47.3°, greater than β min =37.3°, theoretically CFFR should not occur. However, since the PLL-TE in (a1) is 10.3°, the actual trigger advance angle β act is 37°, lower than β min , leading to the occurrence of CFFR. In contrast, at t = 2.154 seconds, the PLL-TE of Model 2 is only 1.6°, successfully avoiding the occurrence of CFFR. As shown in (a2), the difference between Model 1 and Model 2 is mainly attributed to the different network structures. Under fault conditions, the different network structures lead to different degrees of voltage phase jump. The voltage phase jump of Model 2 is -5.5°, which is significantly smaller than the -10.6° of Model 1, ultimately resulting in different PLL-TE. The larger PLL-TE is the direct cause of the CFFR caused by the single-phase fault at the transmitting end, while the larger voltage phase jump is the essential inducing factor.

[0057] According to the simulation results, the receiving end three-phase fault analysis is carried out: From (b4), it can be seen that CFFR occurs at t = 2.174 seconds in model 1. According to (b3), the trigger lead angle command value β ord =90.0°, greater than β min =37.8°, theoretically CFFR should not occur. However, since the PLL-TE in (b1) is 52.7°, the actual thyristor trigger lead angle β act is 37.3°, lower than β min =37.8°, leading to CFFR. In contrast, when CFFR occurred in Model 1, the PLL-TE in Model 2 was only 32.5°, resulting in no CFFR. Similar to Example 1, this difference is primarily due to differences in network structure. Under the RE fault condition, the voltage phase jump in Model 2 was -59.0°, significantly smaller than the -87.6° in Model 1. This difference in voltage phase jump resulted in a larger PLL-TE in Model 1, directly triggering the occurrence of CFFR. Therefore, voltage phase jump also plays a fundamental role in inducing CFFR at the receiving end.

[0058] In summary, during the fault recovery process, the size of PLL-TE directly determines whether CFFR occurs, and PLL-TE is directly caused by the voltage phase jump. Therefore, whether it is a single-phase grounding fault or a three-phase grounding fault, when the voltage phase jump exceeds a certain critical value, the thyristor trigger advance angle (β act ) will drop below the critical value (β min ), thereby triggering CFFR. The occurrence of voltage phase jumps is the essential factor in the occurrence of CFFR. Therefore, CFFR suppression based on voltage phase jumps can most directly achieve linear and margin-based compensation of the thyristor trigger angle, effectively preventing the occurrence of CFFR.

[0059] Step 3: Parameter Setting Method for CFFR Suppression Strategy Based on Voltage Phase Jump

[0060] (1) Parameter tuning of controller 1

[0061] Controller 1 is designed to compensate for the voltage phase jump caused by transient changes in the network structure to suppress the PLL-TE caused by the voltage phase jump. Since the inverter station is directly connected to the RCB, the AC fault occurring at the RCB has the most direct impact on the commutation voltage. The simulation results also show that under the same R f Under these conditions, the RCB fault causes the largest voltage phase jump. Therefore, the AC fault of the RCB can be used to compensate for the voltage phase jump caused by the transient change of the network structure.

[0062] Although the location and severity of faults vary, some areas are more susceptible to faults due to geographical and climatic factors, and these areas have long been known to system operators. Therefore, in practice, the parameters of controller 1 can be adjusted based on the voltage phase jump prediction based on data from these areas.

[0063] when Figure 6 When an AC fault occurs at the RCB of the power system shown in FIG, the relationship described in formula (4) holds. Combined with the phase angle relationship, it can be inferred that R f The smaller the AC system equivalent voltage E' eq The smaller it is, the more serious the AC fault is. Correspondingly, θ PAJ The bigger. Figure 7 Visually demonstrates E' eq and θ PAJ There is an approximate linear relationship between them, which is consistent with the results obtained from fault data extraction in related literature.

[0064]

[0065] Therefore, by solving formula (2), we can obtain the PLL-TE corresponding to the maximum voltage phase jump required to compensate for transient changes in the network structure, that is, α 1,max , as shown in formula (5). According to actual engineering data, the fault resistance R measured in the high-voltage transmission network f are all within the range of 0-10Ω. Therefore, R f Setting it to 0.001Ω is small enough in practical applications. In addition, although the fault duration is not fixed, it is not without range. Therefore, T f The expected maximum fault duration can be selected based on historical data, relevant operating regulations or equipment specifications to ensure adequate compensation.

[0066]

[0067] in, is the equivalent impedance of the AC system before the fault.

[0068] (2) Parameter tuning of controller 2

[0069] When SE and RE faults occur, the DC active power P d Rapid decline, leading to PAJ. Figure 8 As shown, it is the commutation bus voltage U LCC and the equivalent voltage E of the AC system eq The phasor diagram between , ignoring the network loss, the voltage phasor satisfies formulas (6) and (7). Considering that in the actual transmission system, the line reactance X eq Much larger than the resistance Req , and P d Much larger than reactive power Q d , so formula (6) and Q can be ignored d ·R eq The influence of , thus formula (8) is obtained.

[0070]

[0071] Among them, δ is the voltage phase change caused by power change, δU LCC , ΔU LCC They are the transverse and longitudinal components of the voltage between the commutation bus voltage and the equivalent system voltage.

[0072] Considering the monotonicity of the tangent function on the interval [0°, 90°], θ LCC -θ eq Can be regarded as P d Combining formula (2), we get formula (9), where α 2，max Indicates the PLL-TE corresponding to the maximum voltage phase jump required to compensate for the transient change of DC power. In formula (9), select T f The method is consistent with that used in controller 1.

[0073]

[0074] (3) Parameter tuning of controller 3

[0075] In the DC current I d In the case of small, especially when the measured arc extinction angle γ mea When the value is relatively large, the fixed arc extinction angle controller (CEA) of the LCC-HVDC may enter saturation during the SE fault. After the fault is cleared, the integral link of the fixed arc extinction angle controller will slow down the response due to the cumulative effect, such as Figure 9 Although controllers 1 and 2 compensate for PLL-TE, when the fixed arc extinction angle controller outputs β ord When it is insufficient, CFFR may still occur.

[0076] To prevent CEA from entering saturation during SE faults, we only need to ensure that (10) holds true, where γ ref It is the reference value of arc extinguishing angle.

[0077] γ ref =γ mea (10)

[0078] Assuming that the RCB AC voltage is at the rated value, the inverter DC voltage U dsatisfies formula (11), and γ satisfies formula (12), where the subscript N represents the reference value of the corresponding variable. Therefore, the γ of the CEA controller ref According to formula (14), the increment Δγ ref Make corrections.

[0079]

[0080]

[0081] In a specific embodiment, the present invention can accurately compensate for the voltage phase jump caused by the AC fault, so that the thyristors of the LCC-HVDC have sufficient angle compensation to achieve successful commutation. The specific steps are as follows:

[0082] (1) Effectiveness of CFFR suppression strategy based on voltage phase jump

[0083] In order to verify the effectiveness of the proposed CFFR suppression strategy under various fault conditions, different starting times T are set in the SCB and RCB of Model 1. ini Duration T f , Fault resistance R f 、Position D f and type of failure. T ini varies between 0 and 0.02 seconds, T f The options are 0.1 seconds and 0.05 seconds. f From 0 to R f,max , where R f,max It refers to the maximum fault resistance that may cause CFFR under the traditional CIGRELCC-HVDC controller. f It represents the electrical distance from the fault point to the inverter, expressed as a percentage of the total length of the transmission line, and the values ​​of 0%, 30% and 60% are selected. Figure 10 As shown, different T ini 、T f 、R f 、D f The simulation results under the and types of faults are displayed in the form of a three-dimensional scatter plot, and the conclusions are as follows:

[0084] 1) In some RE-SLG and RE-TLG fault scenarios, the traditional CIGRE LCC-HVDC controller alone does not cause CFFR to occur. As shown in (c) and (d), adding the proposed controller does not increase the number of CFFR occurrences, indicating that adding the proposed controller has no negative impact on CFFR suppression.

[0085] 2) The proposed controller is only Figure 10The proposed method is ineffective in two of the scenarios described above because the AC voltage drop and DC current oscillation occur simultaneously during the recovery process. However, this phenomenon is not common, and CFFR is effectively suppressed in all other scenarios with an efficiency of 99.88%, fully demonstrating the robustness and feasibility of the proposed strategy. Therefore, the proposed method can effectively suppress CFFR caused by SE and RE AC faults under various fault conditions by compensating for voltage phase jumps.

[0086] (2) Comparison with other methods

[0087] Build model 3, using Figure 11 The IEEE 39-bus system shown in FIG2 is used as the receiving grid. The LCC-HVDC system that realizes asynchronous interconnection of the system is as follows: Figure 7 The LCC-HVDC system is based on the CIGRE LCC-HVDC benchmark system. The model replaces the equivalent Thevenin system with a transmission line with an impedance of 0.0529+j0.529 (Ω / km). Other system parameters are the same as the original system. Figure 10 The receiving-end grid shown has the inverter station connected to node 38, and the transformer between nodes 29 and 38 replaced with a 10-kilometer transmission line.

[0088] like Figure 10 and Figure 11 As shown in Figure 1, LCC-HVDC is used as a transmission line to connect the power grids at the sending and receiving ends. The current LCC-HVDC is based on the traditional CIGRE LCC-HVDC benchmark control strategy. When an AC fault occurs at the sending end or the receiving end, Figure 10 and Figure 11 The power system shown will experience multiple commutation failures. By adding the control strategy proposed in this invention to the inverter station and corresponding fault detection devices to the rectifier station to generate a sending-end fault signal, the inverter station thyristors can be guaranteed to have sufficient triggering angles during the fault recovery process, effectively ensuring that CFFR is suppressed.

[0089] Specifically, to demonstrate the effectiveness of the proposed method, a comparison is made between the traditional CIGRE LCC-HVDC benchmark model control method, a typical strategy that ignores PLL-TE and involves complex control logic, a typical control method that directly compensates for PLL-TE, and the control strategy proposed in this paper. The specific steps are as follows:

[0090] Example 3: Set a SE single-phase ground fault at t = 4.0 seconds in the SCB of Model 3, and the fault resistance R f =1Ω, fault duration T f = 0.1 seconds;

[0091] Example 4: In model 3, bus 26 is at t = 4.0 seconds and a three-phase ground fault RE is set. The fault resistance R f =15Ω, fault duration T f =0.1 seconds.

[0092] The simulation results are as follows Figure 12 As shown, the analysis is as follows:

[0093] Example 3: In Figure 12 In the example, as shown in (a4), Methods 1-3 experience commutation failure between t = 4.14-4.20 seconds, indicating that Methods 1-3 are ineffective in suppressing CFFR caused by SE fault in Model 3. Method 2 directly feeds PLL-TE back to the DC controller, but cannot suppress CFFR because it cannot prevent saturation of the CEA controller. Method 3 presets a fixed recovery path to ensure that the DC system avoids CFFR. However, β CEA and β CC The rapid change of Δγ leads to erroneous control actions, resulting in ref ≠0, the system cannot resume normal operation, such as Figure 12 Method 4 quickly increases Δγ after a fault. ref , which has a similar value to that of Method 3. However, in contrast to Method 3, Method 4 does not exhibit Δγ after fault clearing at t = 4.1 seconds. ref The rapid decline of , thus preventing the deterioration of DC system recovery caused by rapid changes in controller parameters, such as Figure 12 In addition, although other methods experience CFFR, in method 4, PLL-TE is compensated by α1+α2, leaving a certain margin, as shown in (a1). Figure 12 Therefore, with the target compensation of the thyristor firing angle and without the need for complex control mode switching, the DC system can quickly and smoothly transition from fault to steady-state operation, effectively avoiding CFFR, as shown in (a2) in the figure. Figure 12 As shown in (a4) in .

[0094] Example 4: If Figure 12 As shown in (b4) in Figure 1, Methods 1 and 3 experienced commutation failure between t = 4.15 and 4.25 seconds. Method 1 experienced periodic CF after t = 4.3 seconds, indicating that the system cannot operate under such a weak system. Method 3 maintained Δγ after the system recovered. ref ≠0, which is consistent with the results in Example 3, indicating that the false triggering of the predefined recovery path is their common defect. Although Method 2 does not experience CFFR, the angle compensation caused by the dead zone and filter is insufficient and delayed, resulting in a secondary CF during the fault period of t = 4.09 seconds, as shown in Figure 12As shown in (b4) in , this continuous commutation failure has the same hazard as CFFR. Figure 12 According to (b1) in , the controller 3 in method 4 is not activated under RE fault, which shows the superior performance of the proposed controller 3 under SE fault. Figure 12 In (b2), the PLL-TE caused by the RE fault is compensated with a margin by α1+α2 after the fault is cleared, where the maximum value of α1+α2 is 42.107°. In addition, when the PLL-TE reaches its maximum, the margin is approximately 8.64°. Ultimately, through targeted thyristor trigger angle compensation without complex control mode switching, Method 4 effectively suppresses CFFR and ensures a fast and smooth transition of the DC system from fault to steady-state operation, as shown in Figure 4. Figure 12 As shown in (b4).

[0095] In summary, compared with methods 1-3, method 4 of the present invention can effectively prevent CFFR without affecting the steady-state operation of the system even in a very weak AC system.

[0096] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0097] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A commutation failure suppression strategy considering the phase jump of the commutation bus voltage, characterized in that: include: Construct a phase-locked loop tracking error prediction model based on voltage phase jump; Based on the phase-locked loop tracking error prediction model, a commutation failure suppression strategy that occurs during fault recovery based on voltage phase jump is constructed; The strategy for suppressing commutation failures during fault recovery based on voltage phase jumps includes: constructing a controller for suppressing commutation failures during fault recovery based on voltage phase jumps; simulating an improved CIGRE LCC-HVDC reference system for the controller for suppressing commutation failures during fault recovery based on voltage phase jumps, analyzing the decisive impact of voltage phase jumps on commutation failures during fault recovery, and conducting a rationale analysis of preventing commutation failures during fault recovery based on voltage phase jumps; The improved CIGRE LCC-HVDC benchmark system includes: Model 1 and Model 2. In Model 1, the equivalent Thevenin system is replaced by a transmission line. The other system parameters in Model 1 are the same as those of the original system. In Model 2, in addition to the modifications made in Model 1, a load L1 is added to bus 1, and capacitors are connected to the receiving grid commutation bus and bus 1, respectively, to maintain their rated voltages. Setting parameters of the commutation failure suppression strategy that occurs during the fault recovery process based on the voltage phase jump, and outputting a final commutation failure suppression strategy; Adjusting the parameters of the commutation failure suppression strategy occurring during the fault recovery process based on the voltage phase jump includes: adjusting the parameters of the controller 1, the controller 2, and the controller 3 respectively; Tuning the parameters of controller 1 includes: Controller 1 is designed to compensate for the voltage phase jump caused by transient changes in the network structure to suppress the phase-locked loop tracking error caused by the voltage phase jump; The simulation results show that under the same Rf conditions, the fault of the receiving grid commutation bus causes the largest voltage phase jump; the inverter station is directly connected to the receiving grid commutation bus, and the AC fault of the receiving grid commutation bus is used to compensate for the voltage phase jump caused by transient changes in the network structure.

2. A commutation failure suppression strategy considering commutation bus voltage phase jump according to claim 1, characterized in that: The construction of the phase-locked loop tracking error prediction model based on voltage phase jump includes: at the moment of fault occurrence and fault clearing, the voltage phase jump is regarded as having an amplitude of θ PAJ The fault occurs at t = 0s and lasts for T f The Laplace domain expression of the phase-locked loop tracking error is obtained when . The inverse Laplace transform is applied to the Laplace domain expression to obtain the maximum phase-locked loop tracking error faced by the DC system after the fault occurs.

3. A commutation failure suppression strategy considering commutation bus voltage phase jump according to claim 1, characterized in that: The rationality analysis includes: single-phase fault analysis at the sending end and three-phase fault analysis at the receiving end.

4. A commutation failure suppression strategy considering commutation bus voltage phase jump according to claim 1, characterized in that: The controller for suppressing commutation failure that occurs during fault recovery based on voltage phase jump includes: controller 1, controller 2 and controller 3. Controller 1 and controller 2 compensate for phase-locked loop tracking errors caused by transient changes in network structure and DC power, respectively. Controller 3 is used to prevent saturation of the fixed arc-extinction angle controller due to a sending-end grid fault. All controllers are set with dead zones to prevent erroneous startup of the controller during steady state. Controller 3 uses a sending-end fault signal transmitted from the sending-end grid as a trigger signal. When there is no fault in the sending-end grid, the fault signal is 0 and controller 3 will not be activated.

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