Screening method for parallel current sharing of power semiconductor chips and electronic device

Abstract

The application provides a screening method and electronic equipment for parallel current sharing of power semiconductor chips, and the method comprises the following steps: acquiring chip parameters corresponding to each power semiconductor chip, and sorting a plurality of power semiconductor chips according to a plurality of chip parameters to obtain a chip combination, wherein the chip parameter is a parameter representing the characteristics of the power semiconductor chip; acquiring circuit parameters corresponding to each branch in the power module, and sorting a plurality of branches according to a plurality of circuit parameters to obtain a branch combination, wherein the circuit parameter is a parameter representing the characteristics of the branch; and connecting the power semiconductor chips in the chip combination into the branches in the branch combination in sequence to obtain a target power module. The application solves the problem that the chip utilization rate is low due to the consistency of the threshold voltage of the chip in the prior art chip screening method based on the threshold voltage consistency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic chip, in particular to a screening method for parallel current sharing of power semiconductor chips, a computer readable storage medium, a computer program product and an electronic device. BACKGROUND

[0002] With the rapid development of electronic technology and power systems, the demand for high-performance power devices is increasing. Traditional silicon-based power semiconductor devices have been widely used in many industrial fields, especially in power systems, and have shown great vitality. However, as the application demand continues to increase, the performance limitations of traditional silicon-based materials under high voltage and high temperature conditions gradually appear, making it difficult to meet the requirements of modern industry for higher voltage and higher reliability. Silicon carbide (SiC) as a wide bandgap semiconductor material, with its characteristics significantly better than silicon (Si) material, has gradually become an ideal choice for high-power and high-temperature applications. SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) has a higher breakdown field and a wider bandgap, allowing it to operate stably at higher voltages and temperatures. Specifically, the critical breakdown field of SiC is about ten times that of silicon, allowing SiC devices to withstand higher voltages while having lower on-resistance. In addition, the thermal conductivity of SiC is more than three times that of silicon, which means that SiC devices can dissipate heat more effectively under high power and high temperature conditions, thereby improving the reliability and efficiency of the system. SiC devices also have higher electron saturation velocity and lower switching loss, making them perform well in high-frequency applications.

[0003] However, in practical applications, there is a problem of uneven current distribution in the parallel use of SiC MOSFET, which is mainly caused by differences in parasitic parameters and manufacturing processes. Uneven current distribution can cause reliability problems and even lead to module failure. Specifically, the mismatch of circuit parasitic inductance caused by asymmetric circuit layout is an important factor leading to uneven current distribution.

[0004] The prior art scheme is based on threshold voltage consistency for chip screening. By screening chips with similar threshold voltages, parallel connection of the chips can achieve good results in dynamic current sharing under symmetric layout, and is only applicable to power modules with symmetric layout. However, for asymmetric layout circuit parameters that do not match, the dynamic current distribution of the parallel connected chips is still unbalanced, and cannot be associated with the circuit layout parameters. Moreover, this method cannot achieve static current sharing of the parallel connected chips. Based on threshold voltage consistency for chip screening, it is difficult to operate in practice. Due to the difference in manufacturing process, even if the devices produced in the same batch, the threshold voltage also has a certain distribution range. Therefore, it is a very challenging task to find devices with completely consistent threshold voltages. The screening process requires a lot of time and labor cost, and the qualified rate after screening is low, resulting in a decrease in production efficiency. Secondly, this method does not consider the influence of the inconsistent parasitic inductance of each branch caused by asymmetric circuit layout, and there is still a large dynamic unbalanced current between the parallel connected chips, which has poor effect in actual application. SUMMARY

[0005] The main purpose of the present application is to provide a screening method for parallel current sharing of power semiconductor chips, a computer readable storage medium, a computer program product and an electronic device, so as to at least solve the problem of low chip utilization caused by the need for consistent threshold voltage of chips in the prior art method of chip screening based on threshold voltage consistency.

[0006] In order to achieve the above purpose, according to one aspect of the present application, a screening method for parallel current sharing of power semiconductor chips is provided. The power semiconductor chips are multiple, and the power module includes multiple parallel branches. The power semiconductor chips are used to be connected into the branches one by one. The method comprises: acquiring chip parameters corresponding to each power semiconductor chip, and sorting multiple power semiconductor chips according to multiple chip parameters to obtain a chip combination. The chip parameter is a parameter representing the characteristics of the power semiconductor chip. Acquiring circuit parameters corresponding to each branch in the power module, and sorting multiple branches according to multiple circuit parameters to obtain a branch combination. The circuit parameter is a parameter representing the characteristics of the branch. The power semiconductor chips in the chip combination are connected into the branches in the branch combination in turn to obtain a target power module.

[0007] Optionally, the chip parameters corresponding to each of the power semiconductor chips are obtained, and the power semiconductor chips are sorted according to the chip parameters to obtain a chip combination, including: obtaining the threshold voltage corresponding to each of the power semiconductor chips, and sorting and numbering the power semiconductor chips in order according to the size of the threshold voltage corresponding to each of the power semiconductor chips to obtain the chip combination, wherein the threshold voltage of the power semiconductor chip with a smaller serial number in the chip combination is smaller.

[0008] Optionally, the circuit parameters corresponding to each of the branches in the power module are obtained, and the branches are sorted according to the circuit parameters to obtain a branch combination, including: obtaining the branch current corresponding to each of the branches, and sorting and numbering the branches in order according to the size of the branch current corresponding to each of the branches to obtain the branch combination, wherein the branch current of the branch with a smaller serial number in the branch combination is smaller.

[0009] Optionally, the branch current corresponding to each of the branches is obtained, including: modeling the circuit topology of the power module, and obtaining the branch current corresponding to each of the branches according to the modeled circuit topology.

[0010] Optionally, the power module has k, the power module includes m branches, the power semiconductor chip has N, k = N / m, the power semiconductor chip in the chip combination is connected into the branch in the branch combination in order, including: grouping the chip combination according to the serial number of the power semiconductor chip in the chip combination to obtain m first combinations arranged in order, each first combination includes k power semiconductor chips, wherein the serial number of all power semiconductor chips in the first first combination is 1-k, the serial number of all power semiconductor chips in the second first combination is k+1-2k, and the serial number of all power semiconductor chips in the mth first combination is N-k-N; k power modules are sorted and numbered in order to obtain a module combination; according to the serial number of the power module in the module combination, the power semiconductor chips in the i-th first combination are connected into the i-th branch of each power module in order.

[0011] Optionally, the power modules are k in number, the power modules include m branches, the power semiconductor chips are N in number, and mk < N < m(k + 1). The power semiconductor chips in the chip combination are sequentially connected into the branches in the branch combination, including: removing all the power semiconductor chips after the nth power semiconductor chip in the chip combination to obtain a target chip combination, wherein n = mk, and the serial numbers of all the power semiconductor chips in the target chip combination are 1-n; grouping the target chip combination according to the serial numbers of the power semiconductor chips in the target chip combination to obtain m first combinations arranged in sequence, each of the first combinations including k power semiconductor chips, wherein the serial numbers of all the power semiconductor chips in the first first combination are 1-k, the serial numbers of all the power semiconductor chips in the second first combination are k+1-2k, and the serial numbers of all the power semiconductor chips in the mth first combination are n-k-n; sequentially sorting and numbering the k power modules to obtain a module combination; and sequentially connecting the power semiconductor chips in the ith first combination into the ith branch of each power module according to the serial numbers of the power modules in the module combination.

[0012] Optionally, after obtaining the target power module, the method further includes packaging the target power module.

[0013] According to another aspect of the present application, a computer readable storage medium is provided, which includes a stored program, wherein the computer readable storage medium controls a device where the computer readable storage medium is located to perform any of the screening methods for parallel current sharing of power semiconductor chips when the program is executed.

[0014] According to still another aspect of the present application, a computer program product is provided, which includes computer instructions, and the computer instructions are executed by a processor to implement any of the screening methods for parallel current sharing of power semiconductor chips.

[0015] According to yet another aspect of the present application, an electronic device is provided, which includes one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include a program for performing any of the screening methods for parallel current sharing of power semiconductor chips.

[0016] According to the technical solution of the application, first, chip parameters corresponding to each power semiconductor chip are acquired, and the plurality of power semiconductor chips are sorted according to the plurality of chip parameters to obtain a chip combination, then circuit parameters corresponding to each branch in the power module are acquired, and the plurality of branches are sorted according to the plurality of circuit parameters to obtain a branch combination, and finally, the power semiconductor chips in the chip combination are sequentially connected into the branches in the branch combination to obtain the target power module. Compared with the prior art method of selecting chips based on threshold voltage consistency, which requires the threshold voltage of the chips to be consistent and thus leads to low chip utilization, the application selects chips according to chip parameters and circuit parameters, so that the chip selection index can be associated with the circuit parameters, ensuring that even if the circuit layout of the power module is asymmetric, parallel current sharing can be realized based on the chip parameters and the circuit parameters at the same time, without the need for the threshold voltage of the chips to be consistent, and for chips with dispersion, good current sharing effect can also be achieved, ensuring high chip utilization. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings constituting a part of the specification illustrate the application and the exemplary embodiments thereof, and are used to explain the application, and do not constitute an improper limitation on the application. In the drawings:

[0018] Figure 1 Fig. 1 is a hardware structure block diagram of a mobile terminal for executing a selection method of parallel current sharing of power semiconductor chips according to an embodiment of the application;

[0019] Figure 2 Fig. 2 is a flow chart of a selection method of parallel current sharing of power semiconductor chips according to an embodiment of the application;

[0020] Figure 3 Fig. 3 is a schematic diagram of an output characteristic curve of a power semiconductor chip according to an embodiment of the application.

[0021] In the above drawings, the following reference signs are used:

[0022] 102, processor; 104, memory; 106, transmission device; 108, input / output device. DETAILED DESCRIPTION

[0023] It should be noted that the embodiments in the application and the features in the embodiments can be combined with each other without conflict. The application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0024] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0025] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0026] As described in the background section, the existing chip screening method based on consistent threshold voltage has an asymmetrical circuit layout, resulting in a mismatch in parasitic inductance and an inability to achieve static current sharing of parallel chips. This makes screening difficult and inefficient. To solve the above problems, embodiments of this application provide a screening method for parallel current sharing of power semiconductor chips, a computer-readable storage medium, a computer program product, and an electronic device.

[0027] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0028] The methods and embodiments provided in this application can be executed on a mobile terminal, a computer terminal, or a similar computing device. Taking running on a mobile terminal as an example, Figure 1 This is a hardware structure block diagram of a mobile terminal for a power semiconductor chip parallel current sharing screening method according to an embodiment of the present invention. Figure 1 As shown, a mobile terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The mobile terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the mobile terminal described above. For example, the mobile terminal may also include components that are more...Figure 1 more or less components than those shown in the figures, or configured differently from those shown in the figures. Figure 1

[0029] The memory 104 is used to store computer programs, such as software programs of application software and modules, for example, the computer program corresponding to the screening method for parallel current sharing of power semiconductor chips in the embodiments of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implements the above method. The memory 104 can include a high-speed random access memory, and can also include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some examples, the memory 104 can further include a memory remotely arranged with respect to the processor 102, and the remote memory can be connected to the mobile terminal through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The transmission device 106 is used to receive or send data via a network. The specific examples of the above network can include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet in a wireless manner.

[0030] In the present embodiment, a screening method for parallel current sharing of power semiconductor chips running on a mobile terminal, a computer terminal or a similar computing device is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described herein can be executed in an order different from that shown.

[0031] Figure 2 is a flowchart of the screening method for parallel current sharing of power semiconductor chips according to the embodiments of the present application. As shown in Figure 2 the method comprises the following steps:

[0032] In step S201, chip parameters corresponding to each power semiconductor chip are obtained, and a plurality of power semiconductor chips are sorted according to a plurality of chip parameters to obtain a chip combination. The chip parameter is a parameter representing the characteristics of the power semiconductor chip.

[0033] ​In step S202, circuit parameters corresponding to each branch in the power module are obtained, and the plurality of branches are sorted according to the plurality of circuit parameters to obtain a branch combination, the circuit parameter being a parameter representing the characteristics of the branch.

[0034] In step S203, the power semiconductor chips in the chip combination are sequentially connected into the branches in the branch combination to obtain a target power module.

[0035] According to the above embodiment, first, chip parameters corresponding to each power semiconductor chip are obtained, and the plurality of power semiconductor chips are sorted according to the plurality of chip parameters to obtain a chip combination, then circuit parameters corresponding to each branch in the power module are obtained, and the plurality of branches are sorted according to the plurality of circuit parameters to obtain a branch combination, and finally, the power semiconductor chips in the chip combination are sequentially connected into the branches in the branch combination to obtain a target power module. Compared with the prior art method of selecting chips based on threshold voltage consistency, which requires the threshold voltage of the chips to be consistent, the present application selects chips according to chip parameters and circuit parameters, so that the chip selection index can be associated with the circuit parameters, ensuring that even if the circuit layout of the power module is not symmetrical, parallel current sharing can be achieved based on chip parameters and circuit parameters, without the need for the threshold voltage of the chips to be consistent. For chips with dispersion, good current sharing effect can also be achieved, ensuring high chip utilization.

[0036] It should be noted that the chip parameter refers to the characteristics of the chip itself, such as threshold voltage, transfer curve, and circuit parameter refers to the parasitic parameter on each branch in the power module.

[0037] Specifically, the above-mentioned chip parameters can include but are not limited to maximum power, operating frequency, threshold voltage, and on-resistance, etc.

[0038] According to some example embodiments of the present application, obtaining chip parameters corresponding to each power semiconductor chip and sorting the plurality of power semiconductor chips according to the plurality of chip parameters to obtain a chip combination includes: obtaining threshold voltages corresponding to each power semiconductor chip, and sequentially sorting and numbering the plurality of power semiconductor chips according to the size of their corresponding threshold voltages to obtain a chip combination, wherein the threshold voltage of the power semiconductor chip with a smaller serial number in the chip combination is smaller.

[0039] In this embodiment, the chip combination sorted and numbered according to the size of the threshold voltage can be used to select and configure according to the characteristics of the power semiconductor chip in parallel current sharing, and by sorting according to the size of the threshold voltage, it can ensure that the current distribution of each power semiconductor chip in parallel current sharing is more uniform, and it can also be used to locate and replace the problem chip more easily when a fault occurs, improving the efficiency of maintenance and management.

[0040] Figure 3 is a schematic diagram of an output characteristic curve of a power semiconductor chip, as Figure 3 The threshold voltage of the power semiconductor chip is tested by using a power analyzer or other test platform to test the threshold voltage of each power semiconductor chip. The threshold voltage is selected as the sorting parameter. Assuming that there are N chips, all the chips are sorted according to the threshold voltage from small to large, and are respectively numbered as 1 to N. th The threshold voltage of the power semiconductor chip is tested by using a power analyzer or other test platform to test the threshold voltage of each power semiconductor chip. The threshold voltage is selected as the sorting parameter. Assuming that there are N chips, all the chips are sorted according to the threshold voltage from small to large, and are respectively numbered as 1 to N.

[0041] According to some example embodiments of the present application, the circuit parameters corresponding to each branch in the power module are obtained, and the plurality of branches are sorted according to the plurality of circuit parameters to obtain a branch combination, including: obtaining the branch current corresponding to each branch, and sequentially sorting and numbering the plurality of branches according to the size of the branch current corresponding to each branch to obtain the branch combination, wherein the branch current of the branch with a smaller serial number in the branch combination is smaller.

[0042] In this embodiment, by means of sorting and numbering according to the size of the branch current, the current size of each branch can be determined, so that each branch can bear a relatively uniform current load, and the failure or failure caused by overloading of the branch can be effectively avoided.

[0043] Specifically, the branches are sorted and named according to the size of the current distribution of each branch. The branch with the smallest branch current is numbered as No. 1, and then the branches are sorted in ascending order according to the size of the branch current. Assuming that there are m branches, the branch with the largest branch current is named as m branch.

[0044] According to some example embodiments of the present application, the branch current corresponding to each branch is obtained, including: modeling the circuit topology of the power module, and obtaining the branch current corresponding to each branch according to the modeled circuit topology.

[0045] In this embodiment, the circuit topology of the power module is modeled, which is helpful to understand the connection mode and mutual relationship of each part in the circuit, so as to better analyze the performance and working state of the circuit. According to the modeled circuit topology, the branch current corresponding to each branch can be calculated, so as to understand the current distribution of each branch.

[0046] Specifically, the current distribution of the internal parallel chips of the power module is analyzed by modeling the power module. The circuit topology of the power module is modeled according to the internal structure of the power module, and the current distribution characteristics of the parallel branches are analyzed without considering the difference of chip parameters.

[0047] It should be noted that the parallel branch refers to each branch in the power module, and the parasitic inductance of each branch can be different, and each branch corresponds to a chip. The power module is packaged into a module through packaging processes such as welding and bonding of multiple chips.

[0048] Specifically, the branch currents corresponding to each branch in the power module are obtained without considering the chip parameter difference. The chip parameter difference refers to that the default chip has the same characteristics, that is, the threshold voltage, the transfer curve and other parameters are consistent.

[0049] According to some example embodiments of the present application, the power module has k, the power module includes m branches, and the power semiconductor chip has N. K = N / m. The power semiconductor chips in the chip combination are sequentially connected into the branches in the branch combination, including: grouping the chip combination according to the serial number of the power semiconductor chip in the chip combination to obtain m first combinations arranged in sequence, each first combination includes k power semiconductor chips, wherein the serial numbers of all power semiconductor chips in the first first combination are 1-k, the serial numbers of all power semiconductor chips in the second first combination are k+1-2k, and the serial numbers of all power semiconductor chips in the mth first combination are N-k-N; sequentially sorting and numbering the k power modules to obtain a module combination; and sequentially connecting the power semiconductor chips in the ith first combination into the ith branch of each power module according to the serial number of the power module in the module combination.

[0050] In this embodiment, by grouping the power semiconductor chips in the chip combination according to the serial number of the power semiconductor chip in the chip combination, and sequentially connecting the power semiconductor chips in each first combination into the branches of each power module, the current load of the power semiconductor chips in each power module can be ensured to be relatively balanced. Through the sorting and numbering of the power modules in the module combination, the module can be conveniently managed and monitored, and the system maintenance is more convenient.

[0051] Specifically, when grouping the power semiconductor chips, if there are N power semiconductor chips that can be used with m branches, the power module has k, wherein k = N / m, and the power semiconductor chips are sequentially taken according to the chip parameter from small to large, that is, the 1-k power semiconductor chip is applied to the branch 1, the k+1 to 2k power semiconductor chip is applied to the branch 2, and so on, and the n-k to n power semiconductor chip is applied to the branch m.

[0052] According to some example embodiments of the present application, the power modules are k, the power modules include m branches, the power semiconductor chips are N, mk

[0053] In the present embodiment, by grouping and connecting the power semiconductor chips in a specified order, the order and number of the power semiconductor chips contained in each module are determined, which can effectively avoid the power semiconductor chips in some modules from being overloaded.

[0054] Specifically, when N / m has a remainder, the remaining several power semiconductor chips cannot be used. Assuming that t power semiconductor chips are left, the t power semiconductor chips can be taken from the largest power semiconductor chip in the order, and the number of the remaining power semiconductor chips is n=N-t, which can achieve k=n / m.

[0055] In yet some optional solutions of the present application, after the target power module is obtained, the above method further includes packaging the target power module.

[0056] In the present embodiment, the packaging of the target power module can protect the power semiconductor chips from damage caused by the external environment. By packaging, the heat and electrical signals between the parallel chips can be effectively isolated, ensuring that each chip can balance the load during operation. In addition, the packaging can reduce the mutual interference between the parallel chips, thereby improving the reliability and stability of the module, and facilitating the installation and use of the module.

[0057] Specifically, the power modules are packaged into k power modules, the power module 1 takes the chip with the smallest chip ranking in each group, the power module 2 takes the chip with the second smallest chip ranking in each group, and so on, and the power module k takes the chip with the largest chip ranking in each group, so that the k power modules packaged in this way all use chip parameters to adjust packaging parameters, and the overall adjustment effect is considered.

[0058] The technical scheme provided by the above-mentioned embodiment of the application solves the problem that the chip screening parameter cannot be associated with the circuit parameter in the prior art, does not require the threshold voltage of the chip to be consistent, can achieve good current sharing effect for chips with dispersion, improves the utilization rate of the power semiconductor chip parallel application, in addition, most of the modules on the market are asymmetrically arranged for higher power density, the method based on threshold voltage compensation compensates for the influence caused by the parasitic parameter difference of each branch through chip parameters to achieve the purpose of dynamic current sharing, is more widely used in practical application, has better effect, significantly improves the current distribution of SiC MOSFET, and improves the reliability and performance of the system.

[0059] As can be seen from the above, in the embodiment of the application, a power semiconductor chip parallel current sharing screening method is provided, the screening parameter of the screening method is simple and easy to measure, and can be associated with the circuit parameter, that is, for the branch with large parasitic parameters, a chip with small threshold voltage should be selected, can be used for dynamic parallel current sharing regulation based on chip parameters and circuit parameters, can meet the dynamic parallel current sharing application of multiple groups of chips, and the screening result can minimize the overall unbalanced current of multiple groups of chips, compared with the traditional method based on consistent threshold voltage, the utilization rate of the chip is greatly improved.

[0060] In summary, the power semiconductor chip parallel current sharing screening method provided by the embodiment of the application comprehensively considers multiple factors, the chip screening index proposed can be associated with the circuit parameter, can be used in the technical scheme of simultaneously regulating and controlling dynamic parallel current sharing based on chip parameters and circuit parameters, and can be used in parallel current sharing application between multiple groups of chips, so that the overall unbalanced current of multiple parallel chips is minimized, the effective utilization rate of the chip is greatly improved, and it has been verified by experiments that the power semiconductor chip screening method proposed in the present application can realize dynamic current sharing application of parallel chips.

[0061] In order to enable those skilled in the art to more clearly understand the technical scheme of the present application, the implementation process of the power semiconductor chip parallel current sharing screening method of the present application will be described in detail below in combination with specific embodiments.

[0062] The embodiment relates to a screening method for parallel current sharing of specific power semiconductor chips, the power semiconductor chips are multiple, a power module comprises multiple parallel branches, the power semiconductor chips are used to be connected into the branches one by one, and the method specifically comprises the following steps:

[0063] Step S1: selecting a measuring device to obtain threshold voltages of all the power semiconductor chips;

[0064] Step S2: sorting all the power semiconductor chips according to the threshold voltages, and numbering the power semiconductor chips as 1-N;

[0065] Step S3: modeling the power module, obtaining branch currents of the branches when the threshold voltages are consistent by default, and labeling the branch currents, with the branch current of the first rank being the smallest, and the branch current of the mth rank being the largest;

[0066] Step S4: grouping the power semiconductor chips: if there are N power semiconductor chips and each power semiconductor chip has m branches, k power modules can be packaged, wherein k=N / m (if N / m has a remainder, the remaining t chips cannot be used, and the t chips are taken from the largest chip in the order), the number of the remaining chips is n=N-t, and k=n / m can be achieved; according to the order from small to large threshold voltage, the k chips are taken in turn and applied to the m branches, that is, the first k chips are applied to the first branch, the k+1 to 2k chips are applied to the second branch, and the n-k to n chips are applied to the mth branch;

[0067] Step S5: packaging into k power modules: the power module 1 takes the smallest power semiconductor chip in each group, the power module 2 takes the second smallest power semiconductor chip in each group, and the power module k takes the largest power semiconductor chip in each group.

[0068] It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0069] The embodiment of the application provides a computer readable storage medium, which comprises a stored program, wherein the program controls a device where the computer readable storage medium is located to execute the Z method when the program is running.

[0070] Specifically, the screening method for parallel current sharing of power semiconductor chips comprises:

[0071] In step S201, chip parameters corresponding to each power semiconductor chip are obtained, and the plurality of power semiconductor chips are sorted according to the plurality of chip parameters to obtain a chip combination, the chip parameter being a parameter representing the characteristics of the power semiconductor chip.

[0072] In step S202, circuit parameters corresponding to each branch in the power module are obtained, and the plurality of branches are sorted according to the plurality of circuit parameters to obtain a branch combination, the circuit parameter being a parameter representing the characteristics of the branch.

[0073] In step S203, the power semiconductor chips in the chip combination are sequentially connected into the branches in the branch combination to obtain a target power module.

[0074] Optionally, the chip parameters corresponding to each power semiconductor chip are obtained, and the plurality of power semiconductor chips are sorted according to the plurality of chip parameters to obtain a chip combination, including: obtaining the threshold voltage corresponding to each power semiconductor chip, and sequentially sorting and numbering the plurality of power semiconductor chips according to the size of the threshold voltage corresponding thereto to obtain the chip combination, wherein the threshold voltage of the power semiconductor chip with a smaller serial number in the chip combination is smaller.

[0075] Optionally, the circuit parameters corresponding to each branch in the power module are obtained, and the plurality of branches are sorted according to the plurality of circuit parameters to obtain a branch combination, including: obtaining the branch current corresponding to each branch, and sequentially sorting and numbering the plurality of branches according to the size of the branch current corresponding thereto to obtain the branch combination, wherein the branch current of the branch with a smaller serial number in the branch combination is smaller.

[0076] Optionally, the branch current corresponding to each branch is obtained, including: modeling the circuit topology of the power module, and obtaining the branch current corresponding to each branch according to the modeled circuit topology.

[0077] Optionally, the power module has k, the power module includes m branches, the power semiconductor chip has N, k = N / m, the power semiconductor chips in the chip combination are sequentially connected into the branches in the branch combination, including: grouping the chip combination according to the serial numbers of the power semiconductor chips in the chip combination to obtain m first combinations arranged in order, each first combination including k power semiconductor chips, wherein the serial numbers of all power semiconductor chips in the first first combination are 1-k, the serial numbers of all power semiconductor chips in the second first combination are k+1-2k, and the serial numbers of all power semiconductor chips in the mth first combination are N-k-N; the k power modules are sequentially sorted and numbered to obtain a module combination; the power semiconductor chips in the i th first combination are sequentially connected into the i th branch of each power module according to the serial number of the power module in the module combination.

[0078] Optionally, the power module has k, the power module includes m branches, the power semiconductor chip has N, mk < N < m(k + 1), the power semiconductor chip in the chip combination is sequentially connected into the branch in the branch combination, including: removing all power semiconductor chips after the nth power semiconductor chip in the chip combination, obtaining the target chip combination, wherein n = mk, and the serial numbers of all power semiconductor chips in the target chip combination are 1-n; the target chip combination is grouped according to the serial numbers of the power semiconductor chips in the target chip combination, and m first combinations arranged in order are obtained, each first combination includes k power semiconductor chips, wherein the serial numbers of all power semiconductor chips in the first first combination are 1-k, the serial numbers of all power semiconductor chips in the second first combination are k+1-2k, and the serial numbers of all power semiconductor chips in the mth first combination are n-k-n; the k power modules are sequentially sorted and numbered to obtain a module combination; the power semiconductor chips in the ith first combination are sequentially connected into the ith branch of each power module according to the serial numbers of the power modules in the module combination.

[0079] Optionally, after obtaining the target power module, the method further includes packaging the target power module.

[0080] The application also provides a computer program product, including computer instructions, which are executed by a processor to implement at least the following method steps: step S201, obtaining chip parameters corresponding to each power semiconductor chip, and sorting a plurality of power semiconductor chips according to a plurality of chip parameters to obtain a chip combination, the chip parameter being a parameter representing the characteristics of the power semiconductor chip; step S202, obtaining circuit parameters corresponding to each branch in the power module, and sorting a plurality of branches according to a plurality of circuit parameters to obtain a branch combination, the circuit parameter being a parameter representing the characteristics of the branch; and step S203, sequentially connecting the power semiconductor chips in the chip combination into the branches in the branch combination to obtain a target power module.

[0081] Optionally, obtaining chip parameters corresponding to each power semiconductor chip, and sorting a plurality of power semiconductor chips according to a plurality of chip parameters to obtain a chip combination, includes: obtaining threshold voltages corresponding to each power semiconductor chip, and sequentially sorting and numbering a plurality of power semiconductor chips according to the sizes of the threshold voltages corresponding thereto to obtain a chip combination, wherein the threshold voltage of the power semiconductor chip with a smaller serial number in the chip combination is smaller.

[0082] Optionally, the circuit parameters corresponding to each branch of the power module are acquired, and the multiple branches are sorted according to the multiple circuit parameters to obtain the branch combination, including: acquiring the branch currents corresponding to each branch, and sequentially sorting and numbering the multiple branches according to the sizes of the branch currents corresponding to the multiple branches to obtain the branch combination, wherein the branch current of the branch with a smaller serial number in the branch combination is smaller.

[0083] Optionally, the branch currents corresponding to each branch are acquired, including: modeling the circuit topology of the power module, and acquiring the branch currents corresponding to each branch according to the modeled circuit topology.

[0084] Optionally, the power module has k, the power module includes m branches, the power semiconductor chip has N, mk

[0085] Optionally, the power module has k, the power module includes m branches, the power semiconductor chip has N, mk

[0086] Optionally, after obtaining the target power module, the method further includes: packaging the target power module.

[0087] The embodiment of the present application further provides an electronic device, comprising: one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs comprise a program for executing any one of the power semiconductor chip parallel current sharing screening methods.

[0088] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be realized by general computing devices, which can be centralized on a single computing device or distributed on a network composed of multiple computing devices, and can be realized by program codes executable by the computing devices, so that they can be stored in storage devices and executed by the computing devices, and in some cases, the steps shown or described can be executed in different sequences, or they can be manufactured into individual integrated circuit modules, or multiple modules or steps can be manufactured into a single integrated circuit module. Therefore, the present application is not limited to any particular combination of hardware and software.

[0089] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can adopt a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program codes.

[0090] The present application is described with reference to flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks can be realized by computer program instructions. These computer program instructions can be provided to a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to produce a machine, so that the instructions executed by the computer or other programmable data processing devices produce a device that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks Figure 1 The devices that realize the functions specified in one or more flows and / or blocks.

[0091] These computer program instructions can also be stored in a computer readable storage medium, which can guide the computer or other programmable data processing devices to work in a specific manner, so that the instructions stored in the computer readable storage medium produce a manufactured product including instruction devices, which realize the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocksFigure 1 the function(s) specified in the block or blocks.

[0092] These computer program instructions can also be loaded into computer or other programmable data processing devices to cause a series of operational steps to be performed on the computer or other programmable devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable devices provide steps for implementing the flowchart block(s) or flowchart flow(s) and / or portions thereof. Figure 1 Figure 1 the function(s) specified in the block or blocks.

[0093] In one typical configuration, the computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0094] The memory can include non-persistent memory and / or volatile memory, such as random access memory (RAM) about which the processor can execute instructions. The memory can also include non-volatile memory, such as read only memory (ROM), electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash memory, or a different type of nonvolatile memory. The memory can be a memory of a computer readable medium.

[0095] Computer readable media includes permanent and non-permanent, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), electrically programmable read only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital versatile disc (DVD), or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible to a computing device. According to the definition herein, computer readable media does not include transitory media, such as modulated data signals and carrier waves.

[0096] It should also be noted that the terms "comprising", "comprises", "including", "includes" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article or apparatus. Without limitation, an element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article or apparatus that includes the element.

[0097] ​From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effects:

[0098] In the screening method for parallel current sharing of power semiconductor chips, chip parameters corresponding to each power semiconductor chip are first obtained, and the multiple power semiconductor chips are sorted according to the multiple chip parameters to obtain a chip combination. Then, circuit parameters corresponding to each branch in the power module are obtained, and the multiple branches are sorted according to the multiple circuit parameters to obtain a branch combination. Finally, the power semiconductor chips in the chip combination are sequentially connected into the branches in the branch combination to obtain a target power module. Compared with the prior art method of screening chips based on threshold voltage consistency, which requires the threshold voltage of the chips to be consistent and thus leads to low chip utilization, the present application screens the chips according to the chip parameters and the circuit parameters, so that the chip screening index can be associated with the circuit parameters, ensuring that even if the circuit layout of the power module is asymmetric, parallel current sharing can be achieved based on the simultaneous regulation of the chip parameters and the circuit parameters, without the need for the threshold voltage of the chips to be consistent. For chips with dispersion, good current sharing effect can also be achieved, ensuring high chip utilization.

[0099] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Those skilled in the art can make various modifications and changes to the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for screening power semiconductor chips for parallel current sharing, characterized in that, There are multiple power semiconductor chips, and the power module includes multiple parallel branches. The power semiconductor chips are connected to the branches one-to-one. The method includes: Obtain the chip parameters corresponding to each of the power semiconductor chips, and sort the power semiconductor chips according to the multiple chip parameters to obtain a chip combination, wherein the chip parameters are parameters characterizing the characteristics of the power semiconductor chips; Obtain the circuit parameters corresponding to each branch in the power module, and sort the multiple branches according to the multiple circuit parameters to obtain a branch combination. The circuit parameters are parameters that characterize the characteristics of the branch. The power semiconductor chips in the chip assembly are sequentially connected to the branches in the branch assembly to obtain the target power module. Obtain the chip parameters corresponding to each of the power semiconductor chips, and sort the power semiconductor chips according to the multiple chip parameters to obtain a chip combination, including: The threshold voltage corresponding to each power semiconductor chip is obtained, and the multiple power semiconductor chips are sorted and numbered sequentially according to the magnitude of their corresponding threshold voltages to obtain the chip combination. In the chip combination, the power semiconductor chip with the smaller serial number has the smaller threshold voltage. Obtain the circuit parameters corresponding to each branch in the power module, and sort the multiple branches according to the multiple circuit parameters to obtain a branch combination, including: Obtain the branch current corresponding to each of the aforementioned branches, and sort and number the multiple branches according to the magnitude of their corresponding branch currents to obtain the branch combination. In the branch combination, the smaller the sequence number, the smaller the branch current of the branch. There are k power modules, each power module includes m branches, and there are N power semiconductor chips, where k = N / m. The power semiconductor chips in the chip assembly are sequentially connected to the branches in the branch assembly, including: According to the serial number of the power semiconductor chip in the chip combination, the chip combination is grouped to obtain m sequentially arranged first combinations. Each first combination includes k power semiconductor chips. In the first first combination, the serial numbers of all the power semiconductor chips are 1 to k. In the second first combination, the serial numbers of all the power semiconductor chips are k+1 to 2k. In the mth first combination, the serial numbers of all the power semiconductor chips are Nk to N. The k power modules are sequentially sorted and numbered to obtain a module combination; According to the sequence number of the power module in the module combination, the i-th power semiconductor chip in the first combination is sequentially connected to the i-th branch of each power module.

2. The screening method for parallel current sharing of power semiconductor chips according to claim 1, characterized in that, Obtaining the branch current corresponding to each of the aforementioned branches includes: The circuit topology of the power module is modeled, and the branch current corresponding to each branch is obtained based on the modeled circuit topology.

3. The screening method for parallel current sharing of power semiconductor chips according to claim 1, characterized in that, There are k power modules, each power module includes m branches, and there are N power semiconductor chips, where mk < N < m(k+1). The power semiconductor chips in the chip assembly are sequentially connected to the branches in the branch assembly, including: Remove all power semiconductor chips that are located after the nth power semiconductor chip in the chip combination to obtain the target chip combination, where n=mk, and the serial numbers of all power semiconductor chips in the target chip combination are 1~n; According to the serial number of the power semiconductor chip in the target chip combination, the target chip combination is grouped to obtain m first combinations arranged in order. Each first combination includes k power semiconductor chips. In the first first combination, the serial numbers of all the power semiconductor chips are 1 to k. In the second first combination, the serial numbers of all the power semiconductor chips are k+1 to 2k. In the mth first combination, the serial numbers of all the power semiconductor chips are nk to n. The k power modules are sequentially sorted and numbered to obtain a module combination; According to the sequence number of the power module in the module combination, the i-th power semiconductor chip in the first combination is sequentially connected to the i-th branch of each power module.

4. The screening method for parallel current sharing of power semiconductor chips according to claim 1, characterized in that, After obtaining the target power module, the method further includes: The target power module is then packaged.

5. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein, when the program is executed, it controls the device on which the computer-readable storage medium is located to perform the screening method for parallel current sharing of power semiconductor chips as described in any one of claims 1 to 4.

6. A computer program product comprising computer instructions, characterized in that, When the computer instructions are executed by the processor, they implement the screening method for parallel current sharing of power semiconductor chips as described in any one of claims 1 to 4.

7. An electronic device, characterized in that, include: One or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including a screening method for performing parallel current sharing of power semiconductor chips as described in any one of claims 1 to 4.

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