A drive circuit for inverter loads

Abstract

This invention provides a drive circuit for inverter loads, relating to the field of inverter technology. It includes a control module, a drive module, a power supply module, a signal acquisition and processing module, and a load matching module. The load matching module has impedance matching, tuning matching, and shaping filtering functions, providing universally adaptable drive capabilities for most types of motors and ultrasonic transducers. The power supply module uses high-speed MOSFETs, and the drive module uses a high-speed drive chip to adapt to the high-speed MOSFETs, offering a wide frequency range. A DDS waveform generation module is used to achieve PWM wave output at different frequencies, with extremely low frequency change steps and smooth transitions. Combining a variable step-size algorithm and a LADRC algorithm, it can automatically and accurately lock the operating resonant frequency of the inverter load within a certain frequency range. The employed linear LADRC algorithm adjusts the behavior of the drive circuit through real-time measurement and estimation, adapting to the variations and uncertainties in the complex working environments of motors and ultrasonic transducers.

Description

Technical Field

[0001] This invention belongs to the field of frequency converter technology, and particularly relates to a drive circuit for frequency converter loads. Background Technology

[0002] The power consumption of variable frequency loads varies with the drive frequency, a characteristic frequently observed in motor and ultrasonic fields. In motor applications, the torque and speed can be adjusted by changing the power supply frequency, allowing the motor to operate at its optimal power point. Ultrasonic transducers, as the main components that generate ultrasonic waves, utilize the inverse piezoelectric effect of piezoelectric ceramic sheets to convert electrical energy into mechanical energy. The ultrasonic transducer operates most efficiently near its resonant frequency; changes in external operating conditions alter its resonant frequency, significantly reducing efficiency. Existing drive power supplies often employ the maximum current method or phase comparison method for output frequency regulation, each with its own drawbacks when used individually. The maximum current method can cause overheating and power supply noise under conditions of frequent load changes, leading to performance degradation or even damage to the transducer. The phase comparison method, when dealing with frequency converters with multiple resonant points, may mistakenly track other undesirable resonant points, failing to achieve ideal frequency tracking. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides a drive circuit for inverter loads. This drive circuit can automatically adjust the frequency of the output drive signal, achieving automatic frequency sweeping and tracking within a wide frequency range. This allows it to be matched with different types of motors or ultrasonic transducers, enabling the motor to operate at optimal speed and torque, and also allowing the ultrasonic transducer to operate smoothly at its resonant frequency. This solves the deficiencies of existing inverter load drive circuits and frequency tracking methods.

[0004] A drive circuit for a frequency converter load includes: a control module, a drive module, a power supply module, a signal acquisition and processing module, and a load matching module;

[0005] The control module communicates with the drive module and the signal acquisition and processing module, analyzes the output information of the signal acquisition and processing module, calculates the drive frequency based on the output information, and outputs a control signal to the drive module to drive the power supply module according to the drive frequency, thereby enabling the inverter load to always operate at its resonant frequency; the output information includes phase difference information and peak current information.

[0006] The drive module is used to isolate the control module and the power module to prevent high current from damaging the control module. At the same time, it receives the control signals sent by the control module and performs level conversion on the control signals to drive the power module.

[0007] The power supply module is used to provide suitable voltages to the control module, drive module, and signal acquisition and processing module through different voltage conversion circuits. At the same time, it converts 220V, 50Hz mains power into AC voltage with adjustable frequency and peak value and outputs it to the inverter load through the load matching module to meet the drive requirements of the inverter load.

[0008] The signal acquisition and processing module is used to acquire current and voltage signals on both sides of the inverter load, filter and amplify the current and voltage signals, obtain the phase difference information of the amplified current and voltage signals and output them to the control module in the form of PWM wave duty cycle, and at the same time acquire the peak current information and output it to the control module in the form of high level.

[0009] The load matching module is used to achieve tuning matching and impedance matching between the power supply module and the inverter load.

[0010] Furthermore, the control module includes an MCU main control chip and a DDS waveform generation module;

[0011] The MCU main control chip is used to receive phase difference information and peak current information output by the signal acquisition and processing module, calculate the driving frequency through LADRC algorithm and variable step size algorithm, and output it to DDS waveform generation module. It is also used to control the switching of relays in the load matching module, thereby controlling the selection values ​​of matching inductor and matching capacitor in the load matching module.

[0012] The DDS waveform generation module is used to generate a control signal according to the driving frequency calculated by the MCU main control chip and output it to the driving module; the control signal is a square wave;

[0013] Furthermore, the driving frequency is calculated using a variable step size algorithm and a LADRC algorithm. Specifically, the optimal driving frequency is initially determined using a variable step size algorithm based on the peak current information. Then, the offset of the inverter load frequency is determined based on the phase difference information collected in real time. The change in the driving frequency that needs to be adjusted is calculated using the LADRC algorithm, thereby determining the current optimal driving frequency.

[0014] Furthermore, the power module includes a rectifier filter circuit, a Buck converter circuit, an inverter circuit, and an external power supply circuit;

[0015] The rectifier and filter circuit is used to convert AC voltage into pulsating DC voltage through a rectifier bridge composed of four diodes. Then, through the process of storing and releasing charge through the filter capacitor, additional current is provided to compensate for the ripple in the DC voltage and input to the Buck step-down circuit.

[0016] The Buck step-down circuit is used to control the conduction time of the MOSFET so that the input DC voltage is regulated and filtered by the inductor and capacitor under the control of the MOSFET, thereby reducing the output DC voltage of the rectifier and filter circuit, adjusting the output power, and outputting the stepped-down DC voltage.

[0017] The inverter circuit is used to convert the DC voltage stepped down by the Buck step-down circuit into AC voltage and output it to the load matching module.

[0018] The peripheral power supply circuit is used to provide the drive voltage required to enable the control module and drive module, as well as the negative voltage required by the operational amplifier in the signal acquisition and processing module, through the conversion circuit.

[0019] Furthermore, the driving module includes two parts: a Buck driving circuit and an inverter driving circuit. The Buck driving circuit and the inverter driving circuit are used to drive the Buck step-down circuit in the power supply module and the MOSFET in the inverter circuit, respectively. Both the Buck driving circuit and the inverter driving circuit include an optocoupler isolation section and a MOSFET driving section. The optocoupler isolation section is used to isolate the control module and the power supply module. The MOSFET driving section converts the control signal output by the control module into a level suitable for driving the MOSFET in the power supply module.

[0020] The signal acquisition and processing module includes a sampling circuit, a bandpass filter circuit, a signal amplification-peak monitoring circuit, and a phase detection circuit;

[0021] The sampling circuit includes multiple sampling resistors for acquiring current and voltage signals across the inverter load and transmitting them to the bandpass filter circuit.

[0022] The bandpass filter circuit is used to remove interference harmonics from the acquired current and voltage signals and input the filtered current and voltage signals to the signal amplification circuit.

[0023] Furthermore, the bandpass filter circuit is an SK active bandpass filter, which includes an SK second-order active low-pass filter and an SK second-order active high-pass filter.

[0024] The signal amplification-peak monitoring circuit includes a signal amplification circuit and a peak detection circuit;

[0025] The amplifier circuit amplifies the filtered voltage signal through a proportional amplifier circuit and outputs it to the phase detection circuit, and amplifies the filtered current signal through a differential amplifier circuit and outputs it to the peak detection circuit and the phase detection circuit.

[0026] The peak detection circuit includes a rectifier diode, an energy storage capacitor, and a discharge resistor, which are used to obtain peak current information and transmit it to the control module for analysis.

[0027] The phase detection circuit includes a voltage follower, a zero-crossing comparator, a D flip-flop, and an XOR gate, which are used to obtain the lead-lag relationship between the voltage signal and the current signal and the phase difference information between them, thereby completing the digital phase detection function.

[0028] The load matching module includes a tuning matching module and an impedance matching module;

[0029] The tuning matching module selects the LC matching method and achieves tuning matching by controlling the opening and closing of different relays to switch the matching inductor and matching capacitor.

[0030] The impedance matching module selects a transformer matching method and performs impedance transformation by changing the turns ratio n1 / n2 of the primary and secondary coils of the transformer to achieve impedance matching.

[0031] The beneficial effects of this invention are:

[0032] (1) The load matching module of the present invention has impedance matching, tuning matching and shaping filtering functions, and has universally adaptable driving capability for most types of motors and ultrasonic transducers.

[0033] (2) The power supply module of the present invention uses a high-speed MOSFET, and the drive module uses a high-speed drive chip to adapt to the high-speed MOSFET. The frequency application range is large. The DDS waveform generation module is used to realize the output of PWM waves of different frequencies. The frequency change step is extremely low and the change is smooth.

[0034] (3) This invention combines the variable step size algorithm and the LADRC algorithm, which can automatically and accurately lock the working resonant frequency of the variable frequency load within a certain frequency range.

[0035] (4) The linear LADRC algorithm used in this invention does not rely on an accurate system model, but adjusts the behavior of the drive circuit through real-time measurement and estimation. It can adapt to the changes and uncertainties in the complex working environment of motors and ultrasonic transducers, including changes in their own parameters and the influence of external factors. It is simple to implement and easy to debug and optimize. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the overall design scheme of a drive circuit for a frequency converter load according to an embodiment of the present invention;

[0037] Figure 2 This is a flowchart of the variable step size algorithm in an embodiment of the present invention;

[0038] Figure 3 This is a structural diagram of the LADRC controller in an embodiment of the present invention;

[0039] Figure 4This is a circuit design diagram of the control module in an embodiment of the present invention;

[0040] Figure 5 This is a circuit design diagram of the driving module in an embodiment of the present invention;

[0041] Figure 6 This is a circuit design diagram of the power module in an embodiment of the present invention;

[0042] Figure 7 This is a circuit design diagram of the signal acquisition and processing module in an embodiment of the present invention;

[0043] Figure 8 This is an overall design diagram of the load matching module in an embodiment of the present invention. Detailed Implementation

[0044] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. Similar elements in different embodiments are referred to by related similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the present application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present application are not shown or described in the specification. This is to avoid obscuring the core parts of the present application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0045] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0046] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0047] like Figure 1 As shown, a drive circuit for inverter load includes: a control module, a drive module, a power supply module, a signal acquisition and processing module, and a load matching module, which realizes frequency sweeping and automatic frequency tracking test of the load.

[0048] In this embodiment, the drive module, power module, and signal acquisition and processing module are integrated into a single PCB board. The control module and load matching module are connected to other modules by inserting pins into the PCB board.

[0049] The control module communicates with the drive module and the signal acquisition and processing module, analyzes the output information of the signal acquisition and processing module, calculates the drive frequency based on the output information, and outputs a control signal to the drive module according to the drive frequency, thereby driving the power supply module. The signal then passes through the load matching module to ensure that the variable frequency load motor operates smoothly at its optimal power level or the transducer operates at its maximum active power mode at its series resonant frequency. The output information includes phase difference information and peak current information.

[0050] In this embodiment, the present invention includes two functions: peak signal frequency sweeping based on a variable step size algorithm and frequency tracking function based on a phase detection frequency locking algorithm using the LADRC algorithm. The variable step size algorithm can lock the resonant point with the largest peak current signal in a relatively long frequency range, and can perform frequency sweeping at an initial set frequency far from the resonant frequency. After the initial frequency sweep is completed, the drive circuit automatically executes the frequency tracking function. By detecting the phase difference between the current and voltage of the inverter load in real time, it determines the degree of frequency deviation of the transducer during operation, and calculates the amount of frequency change that needs to be adjusted according to the LADRC algorithm, so that the motor and transducer always remain at the resonant point and operate at maximum power.

[0051] Variable step size algorithms, such as Figure 2 As shown, the frequency sweep includes two modes: large step sweep and small step sweep. First, the sweep range is determined, i.e., the upper and lower limits of the frequency. The program first enters state=1 (large step sweep mode), acquiring peak current information transmitted by the signal acquisition and processing module. If the peak current information is less than the first target threshold, the frequency of the output control signal is increased by a large step. If the peak current information is greater than the first target threshold, it enters state=2 (small step sweep mode), continuing to read peak current information. If the acquired peak current information is higher than the previously acquired peak current information, the frequency of the higher peak current information is selected as the pre-selected frequency, and the frequency of the output control signal is increased by a small step. If the peak current information collected is lower than the peak current information collected previously, the preselected frequency remains unchanged, and the program enters state=3. The difference between the peak current information corresponding to the preselected frequency and the peak current information when entering state=3 is compared with the second target threshold. If the difference between the peak current information corresponding to the preselected frequency and the peak current information when entering state=3 is higher than the second target threshold, the program ends, the preselected frequency is the optimal frequency for the inverter load, and its corresponding peak current information is the maximum value within the frequency sweep range. Otherwise, the frequency of the control signal is adjusted using both large step frequency sweep and small step frequency sweep modes.

[0052] Compared to the traditional PI algorithm, the LADRC algorithm features small overshoot, high accuracy, strong anti-interference capability, and less reliance on the model. It comprises three modules: a linear tracking differentiator (LTD), a linear state observer (LESO), and a linear state error feedback (LSEF). First, the desired input signal is input to the LTD for smoothing, and a transient process is designed to obtain the tracking signal and generate the differential signal of the desired signal. Simultaneously, the LESO utilizes the modeling information of the controlled object and external disturbances to transform and expand the internal and external disturbances of the controlled object into a new higher-order state variable, thereby extracting the higher-order disturbance signal. Finally, the LSEF receives the tracking signal from the LTD and the observed state variables of various orders acquired by the LESO for calculation. Then, a linear function is used to compensate for the total disturbance experienced by the controlled object in real time to achieve precise control. Figure 3 As shown, the first-order LADRC controller for phase detection is as follows:

[0053]

[0054] In the formula, e is the error between the detected value and the observed value, z1 and z2 are the observed values ​​of the state variable, and β 01 and β 02 It is the feedback gain coefficient of the linear state observer. The output of the controlled object is Δf, where Δf is the control output of the LADRC controller, b0 is the estimated system gain, u0 is the control output of the LSEF, and K is the control output of the LSEF controller. p x1 is the bandwidth of the LADRC controller, and x1 is the state variable representing the phase difference. It is the rate of change of the observed values ​​of the state variables;

[0055] The control module includes an MCU main control chip and a DDS waveform generation module;

[0056] The MCU main control chip is used to receive phase difference information and peak current information output by the signal acquisition and processing module, calculate the driving frequency through variable step size algorithm and LADRC algorithm, and output it to the DDS waveform generation module to ensure that it outputs a control signal of appropriate frequency. It is also used to control the switching of the relay in the load matching module, thereby controlling the selection value of the matching inductor and matching capacitor in the load matching module.

[0057] The DDS waveform generation module consists of a digital-to-analog converter, a high-speed comparator, and a programmable system. It is used to generate a spectrum-clean, frequency-programmable control signal according to the driving frequency calculated by the MCU main control chip and output it to the driving module. The control signal is a square wave.

[0058] like Figure 4As shown, in this embodiment, the MCU main control chip is selected as STM32F407. Compared with ordinary microcontroller chips, this chip has stronger computing power and better performance. Its main frequency is 168MHz, and it has 100 pins, three 12-bit ADCs, two DACs, one RTC and fourteen general-purpose timers. It also has communication interfaces such as USART. The DDS waveform generation module uses AD9850 chip, which has a maximum operating frequency of 125MHz, uses a 32-bit frequency control word, and has a maximum frequency resolution of 0.0291Hz, which can meet the accuracy requirements of frequency tracking.

[0059] The drive module is used to isolate the control module and the power module to prevent high current from damaging the control module. At the same time, it receives the control signals sent by the control module and performs level conversion on the control signals to drive the power module.

[0060] like Figure 5 As shown, the drive module includes two parts: a Buck drive circuit and an inverter drive circuit. The Buck drive circuit and the inverter drive circuit are used to drive the MOSFETs in the Buck step-down circuit and the inverter circuit, respectively. Both the Buck drive circuit and the inverter drive circuit include an optocoupler isolation section and a MOSFET drive section. In this embodiment, the optocoupler isolation section uses an HCPL-2630 optocoupler isolation chip, which integrates a light-emitting diode and a phototransistor. The supply voltage is 5V, which can effectively isolate the input and output circuits and prevent electrical noise, high voltage or other interference at the input end from affecting the output end, thereby improving the stability and safety of the drive circuit used for the inverter load. It has two channels. The Buck drive circuit receives one PWM signal and uses one channel. The MOSFET drive section uses an IR2113S MOSFET drive chip, which can withstand voltages up to 600V, has fast rise and fall times, a maximum frequency of 500kHz, a supply voltage of 12V, and includes two logic input pins for receiving signals output by the optocoupler isolation chip. The Buck drive circuit uses the high-side output of one IR2113S to control the switching of one MOSFET, while the inverter circuit uses the high and low pins of two IR2113S to control the switching of four MOSFETs. Therefore, the drive circuit module can amplify the weak control signal from the control module into an effective signal that can drive the power supply module.

[0061] The power supply module is used to provide suitable voltages to the control module, drive module, and signal acquisition and processing module through different voltage conversion circuits. At the same time, it converts 220V, 50Hz mains power into AC voltage with adjustable frequency and peak value and outputs it to the inverter load through the load matching module to meet the drive requirements of the inverter load.

[0062] like Figure 6As shown, the power module includes a rectifier and filter circuit, a Buck converter circuit, an inverter circuit, and an external power supply circuit.

[0063] The rectifier and filter circuit is used to convert AC voltage into a roughly pulsating DC voltage through a rectifier bridge composed of four diodes. Then, through the process of storing and releasing charge through the filter capacitor, additional current is provided to compensate for the ripple in the DC voltage and input to the Buck step-down circuit to ensure that the inverter load receives a stable DC voltage.

[0064] The Buck step-down circuit is used to control the conduction time of the MOSFET so that the input DC voltage is regulated and filtered by the inductor and capacitor under the control of the MOSFET, thereby reducing the output DC voltage of the rectifier and filter circuit, adjusting the output power, and outputting the stepped-down DC voltage.

[0065] The inverter circuit is used to convert the DC voltage stepped down by the Buck step-down circuit into a frequency-controllable AC voltage and output it to the load matching module.

[0066] Specifically, it consists of four MOSFETs and four anti-parallel diodes. The MOSFETs are arranged in a bridge configuration, forming two symmetrical pairs of switches, each pair containing two transistors, one in the upper half-bridge and the other in the lower half-bridge. The anti-parallel diodes provide a path for current to continue flowing when the switches are off, protecting the switches and ensuring proper circuit operation.

[0067] The peripheral power supply circuit is used to provide the 12V and 5V drive voltages required for enabling the control module and drive module, as well as the -5V and -12V negative voltages required for the operational amplifier in the signal acquisition and processing module, through the conversion circuit.

[0068] In this embodiment, the rectifier and filter circuit uses a GBJ5010 rectifier bridge with a withstand voltage of 1kV, offering advantages such as high integration and the ability to withstand large current loads. It consists of four diodes, which provide a path for current to continue flowing even when the switching transistor is off, ensuring circuit stability and efficiency. By controlling the conduction and cutoff of the diodes, the negative half-cycle of the AC current is converted to the positive half-cycle, resulting in an approximate DC voltage. An electrolytic capacitor is connected after the rectifier bridge to store charge and smooth the output DC voltage, reducing ripple. A 680uF / 450V electrolytic capacitor is selected to meet the requirements of higher power. The Buck converter uses an STP33N60M6-VB as the switching transistor, with a conduction frequency of 500kHz, low on-resistance, high current handling capacity, and high temperature resistance, making it suitable for high-power applications. When the MOSFET is on, the voltage source charges through the inductor; when the MOSFET is off, the energy stored in the inductor is released to the load through the diodes, thus achieving a stable voltage reduction effect. Similarly, the full-bridge inverter section also selects STP33N60M6-VB as the switching transistor, and connects a resistor-capacitor device in parallel to form an absorption buffer circuit to suppress the turn-off spike of the switching transistor. The diode is used to prevent the reverse electromotive force from being too high, which plays a protective role, and at the same time, it provides freewheeling current for the circuit when the switching transistor is turned off.

[0069] The signal acquisition and processing module is used to acquire weak current and voltage signals on both sides of the inverter load, filter and amplify the weak current and voltage signals, obtain the phase difference information of the amplified current and voltage signals and output them to the control module in the form of PWM wave duty cycle, and at the same time acquire the peak current information and output it to the control module in the form of high level.

[0070] The signal acquisition and processing module includes a sampling circuit, a bandpass filter circuit, a signal amplification-peak monitoring circuit, and a phase detection circuit;

[0071] The sampling circuit includes multiple sampling resistors for acquiring current and voltage signals across the inverter load and transmitting them to the bandpass filter circuit.

[0072] like Figure 7 As shown, in this embodiment, the sampling circuit uses a resistance sampling method to ensure the accuracy of current and voltage phase acquisition. A 10MΩ resistor and a 100kΩ resistor are connected in parallel with the inverter load, and the voltage across the 100kΩ resistor is used as the load voltage signal. A 1-ohm resistor is connected in series with the inverter load, and the voltage across it can be used to represent the current signal of the branch where the load is located. This method acquires accurate phase information while avoiding any impact on the load power.

[0073] The bandpass filter circuit is used to remove interference harmonics from the acquired current and voltage signals and input the filtered current and voltage signals to the signal amplification circuit.

[0074] Furthermore, the bandpass filter circuit is an SK active bandpass filter, which includes an SK second-order active low-pass filter and an SK second-order active high-pass filter, and the cutoff frequency is determined by the values ​​of the two resistors and the capacitor, respectively.

[0075] like Figure 7 As shown, in this embodiment, the bandpass filter circuit consists of two operational amplifiers. It uses an LM358A-SR chip and two sets of resistors and capacitors to form two active SK-type second-order filters. The high-pass filter uses capacitors and resistors with values ​​of C and C respectively. 20 =C 21 =C 24 =C 25 =1nF,R 33 =R 37 =11.2kΩ, R 34 =R 38 = 5.6kΩ, cutoff frequency 20kHz. The low-pass filter is selected with capacitor and resistor values ​​of C... 18 =C 22 =1nF,C 19 =C 23 =6.8nF,R 31 =R 35 =1.5kΩ, R 32 =R 36 =1kΩ, cutoff frequency is 65kHz.

[0076] The cutoff frequency of the SK second-order active high-pass filter is:

[0077]

[0078] In the formula, f is the cutoff frequency, and R 33 ,R 35 For the resistor of the high-pass filter, C 20 C 21 The capacitor is for the high-pass filter;

[0079] The cutoff frequency of the SK second-order active low-pass filter is:

[0080]

[0081] In the formula, R 31 ,R 32 For the resistor of the low-pass filter, C 18 C 19 The capacitor is for the low-pass filter;

[0082] The signal amplification-peak monitoring circuit includes a signal amplification circuit and a peak detection circuit;

[0083] The amplifier circuit amplifies the filtered voltage signal through a proportional amplifier circuit and outputs it to the phase detection circuit, and amplifies the filtered current signal through a differential amplifier circuit and outputs it to the peak detection circuit and the phase detection circuit.

[0084] The proportional amplifier circuit and the differential amplifier circuit include operational amplifiers and resistors;

[0085] In this embodiment, because the output signal value of the sampling circuit is relatively small, an amplification circuit is needed to amplify the signal accordingly in order to achieve the subsequent peak detection and phase detection functions. The operational amplifier chip selected is the LM358-SR chip, which has the advantages of low cost and strong anti-interference capability, and can amplify both voltage and current signals through dual channels. The voltage signal uses a non-inverting proportional amplification method, and its circuit consists of an operational amplifier and related resistors. 23 For R 24 and R 25 The union of R. 24 =35kΩ, R 25 =5kΩ, R 23 The impedance is 4.3kΩ, with a gain of 8. The current signal is amplified using a differential amplifier circuit, which consists of an operational amplifier and related resistors. Specifically, R... 29 =R 26 =5kΩ, R 28 =R 27 =50kΩ, amplification factor of 10.

[0086] The amplification ratio formula for the proportional amplifier circuit is:

[0087]

[0088] In the formula, Vout is the output voltage, Vin is the input voltage, and R... 24 R 25 This is an amplifying resistor.

[0089] The output value of the differential amplifier circuit is:

[0090]

[0091] In the formula, V2 and V1 are the two input signals of the operational amplifier, and R 28 R 29 This is an amplifying resistor.

[0092] The peak detection circuit includes a rectifier diode, an energy storage capacitor, and a discharge resistor. The current signal passes through the rectifier diode. Since the rectifier diode only allows the positive half-cycle of the signal to pass through, the current signal becomes a pulse sequence containing the peak value of the input signal. This pulse signal passes through an energy storage capacitor. Because the energy storage capacitor is transparent to DC signals but blocks AC signals, the peak value is thus maintained on the energy storage capacitor. The peak current information is obtained and transmitted to the control module for analysis. The discharge resistor is used to release the charge on the energy storage capacitor.

[0093] The phase detection circuit described in this embodiment includes a voltage follower, a zero-crossing comparator, a D flip-flop, and an XOR gate. The voltage follower uses a high-precision AD8672 operational amplifier chip to keep the input signal voltage constant, maintain waveform stability, and isolate the preceding and following circuits. The zero-crossing comparator uses an LM339 operational amplifier chip and peripheral circuitry to convert the input signal into a binary signal for subsequent processing. The D flip-flop 74LS74 and the XOR gate 74LS86 convert the two processed signals into signals recognizable by the main control chip. The D flip-flop outputs the phase difference status information: when the voltage leads the current, the output signal is set to 1; when the current leads the voltage, the output signal is set to 0. The XOR gate outputs the phase difference information, and the duty cycle of the high-level output PWM wave is the current-voltage phase difference.

[0094] The load matching module is used to realize the tuning matching and impedance matching between the power supply module and the inverter load, including a tuning matching module and an impedance matching module.

[0095] Tuning matching refers to the process where the control module controls the switching of different relays in the tuning matching module according to the different electrical characteristics of the load, switching the matching inductor and matching capacitor to achieve appropriate values, reducing the error between the lowest impedance point and the purely resistive point of the load. This is achieved by using programmable inductors and programmable capacitors, improving the power factor and power supply efficiency. Impedance matching, on the other hand, refers to the control of the total impedance of the circuit during the matching process, avoiding excessive total impedance to ensure the power supply output power. For ultrasonic vibration units, a good matching system can ensure good vibration conditions and increase the stability of the ultrasonic power supply.

[0096] Furthermore, the tuning matching module selects the LC matching method. The ultrasonic transducer is connected in series with a matching inductor and a matching capacitor. When the transducer operates at the series resonant frequency, the transducer can be equivalent to a circuit with a resistor and a capacitor in series. Therefore, a matching inductor is needed in series to eliminate the capacitive component of the series resonant frequency. The static capacitance may change with temperature, operating time, etc., which will have an adverse effect on tuning. Therefore, a matching capacitor is connected in parallel with the static capacitor to counteract the effect of static capacitance changes.

[0097] like Figure 8As shown, the load matching circuit in this embodiment consists of a programmable inductor and a programmable capacitor. In practice, a matching capacitor C1 with a value ten times that of the load's equivalent static capacitance C0 is selected and connected in parallel with the load. The formula for calculating the matching inductance L1 is:

[0098]

[0099] Where L1 is the matching inductance, C0 is the static capacitance of the load, and C1 is the matching capacitor; R m ω represents the dynamic resistance of the load, and ω is the angular frequency, indicating how quickly the current and voltage signals change over time. The seven series inductors designed in this invention have values ​​of L0 = 1mH, L1 = 2mH, L2 = 3mH, L3 = 3mH, L4 = 3mH, L5 = 3mH, and L6 = 3mH. They can be arbitrarily combined and connected, providing inductance values ​​from 0 to 18mH with an adjustment accuracy of 1mH. The seven parallel capacitors have values ​​of C0 = 0.1uF, C1 = 0.2uF, C2 = 0.3uF, C3 = 0.4uF, C4 = 0.5uF, C5 = 0.6uF, and C6 = 0.7uF. They can also be arbitrarily combined and connected, providing capacitance values ​​from 0 to 0.28uF with an adjustment accuracy of 0.1uF. Using both in combination allows this invention to meet the dynamic matching requirements of different loads.

[0100] The impedance matching module selects the transformer matching method. When the resistance of the resistive load is equal to the internal resistance of the power supply, the load can obtain the maximum power. This is achieved by changing the turns ratio n1 / n2 of the primary and secondary coils of the transformer, so that the load can obtain the maximum power.

Claims

1. A drive circuit for a frequency converter load, characterized in that, It includes a control module, a drive module, a power supply module, a signal acquisition and processing module, and a load matching module; The control module communicates with the drive module and the signal acquisition and processing module, analyzes the output information of the signal acquisition and processing module, calculates the drive frequency based on the output information, and outputs a control signal to the drive module to drive the power supply module according to the drive frequency, thereby enabling the inverter load to always operate at its resonant frequency; the output information includes phase difference information and peak current information. The drive module is used to isolate the control module and the power module to prevent high current from damaging the control module. At the same time, it receives the control signals sent by the control module and performs level conversion on the control signals to drive the power module. The power supply module is used to provide suitable voltages to the control module, drive module, and signal acquisition and processing module through different voltage conversion circuits. At the same time, it converts 220V, 50Hz mains power into AC voltage with adjustable frequency and peak value and outputs it to the inverter load through the load matching module to meet the drive requirements of the inverter load. The signal acquisition and processing module is used to acquire current and voltage signals on both sides of the inverter load, filter and amplify the current and voltage signals, obtain the phase difference information of the amplified current and voltage signals and output them to the control module in the form of PWM wave duty cycle, and at the same time acquire the peak current information and output it to the control module in the form of high level. The load matching module is used to achieve tuning matching and impedance matching between the power supply module and the inverter load. The drive frequency is calculated using a variable step size algorithm and a LADRC algorithm. Specifically, the optimal drive frequency is initially determined based on the peak current information using a variable step size algorithm. Then, the offset of the inverter load frequency is determined based on the real-time phase difference information. Finally, the change in the drive frequency that needs to be adjusted is calculated using the LADRC algorithm, thereby determining the current optimal drive frequency.

2. The drive circuit for a frequency converter load according to claim 1, characterized in that, The control module includes an MCU main control chip and a DDS waveform generation module; The MCU main control chip is used to receive phase difference information and peak current information output by the signal acquisition and processing module, calculate the driving frequency through LADRC algorithm and variable step size algorithm, and output it to DDS waveform generation module. It is also used to control the switching of relays in the load matching module, thereby controlling the selection values ​​of matching inductor and matching capacitor in the load matching module. The DDS waveform generation module is used to generate a control signal according to the driving frequency calculated by the MCU main control chip and output it to the driving module; the control signal is a square wave.

3. The drive circuit for a frequency converter load according to claim 1, characterized in that, The power module includes a rectifier and filter circuit, a Buck step-down circuit, an inverter circuit, and an external power supply circuit. The rectifier and filter circuit is used to convert AC voltage into pulsating DC voltage through a rectifier bridge composed of four diodes. Then, through the process of storing and releasing charge through the filter capacitor, additional current is provided to compensate for the ripple in the DC voltage and input to the Buck step-down circuit. The Buck step-down circuit is used to control the conduction time of the MOSFET so that the input DC voltage is regulated and filtered by the inductor and capacitor under the control of the MOSFET, thereby reducing the voltage value of the DC voltage output by the rectifier and filter circuit, adjusting the output power, and outputting the stepped-down DC voltage. The inverter circuit is used to convert the DC voltage stepped down by the Buck step-down circuit into AC voltage and output it to the load matching module. The peripheral power supply circuit is used to provide the drive voltage required to enable the control module and drive module, as well as the negative voltage required by the operational amplifier in the signal acquisition and processing module, through the conversion circuit.

4. A drive circuit for a frequency converter load according to claim 1, characterized in that, The driving module comprises two parts: a Buck driving circuit and an inverter driving circuit. The Buck driving circuit and the inverter driving circuit are used to drive the Buck step-down circuit in the power supply module and the MOSFET in the inverter circuit, respectively. Both the Buck driving circuit and the inverter driving circuit include an optocoupler isolation section and a MOSFET driving section. The optocoupler isolation section is used to isolate the control module and the power supply module. The MOSFET driving section converts the control signal output by the control module into a level suitable for driving the MOSFET in the power supply module.

5. A drive circuit for a frequency converter load according to claim 1, characterized in that, The signal acquisition and processing module includes a sampling circuit, a bandpass filter circuit, a signal amplification-peak monitoring circuit, and a phase detection circuit; The sampling circuit includes multiple sampling resistors for acquiring current and voltage signals across the inverter load and transmitting them to the bandpass filter circuit. The bandpass filter circuit is used to remove interference harmonics from the acquired current and voltage signals and input the filtered current and voltage signals to the signal amplification circuit. The signal amplification-peak monitoring circuit includes a signal amplification circuit and a peak detection circuit; The amplifier circuit amplifies the filtered voltage signal through a proportional amplifier circuit and outputs it to the phase detection circuit, and amplifies the filtered current signal through a differential amplifier circuit and outputs it to the peak detection circuit and the phase detection circuit. The peak detection circuit includes a rectifier diode, an energy storage capacitor, and a discharge resistor, which are used to obtain peak current information and transmit it to the control module for analysis. The phase detection circuit includes a voltage follower, a zero-crossing comparator, a D flip-flop, and an XOR gate, which are used to obtain the lead-lag relationship between the voltage signal and the current signal and the phase difference information between them, thereby completing the digital phase detection function.

6. A drive circuit for a frequency converter load according to claim 5, characterized in that, The bandpass filter circuit is an SK active bandpass filter, which includes an SK second-order active low-pass filter and an SK second-order active high-pass filter.

7. A drive circuit for a frequency converter load according to claim 1, characterized in that, The load matching module includes a tuning matching module and an impedance matching module; The tuning matching module selects the LC matching method and achieves tuning matching by controlling the opening and closing of different relays to switch the matching inductor and matching capacitor. The impedance matching module selects a transformer matching method and performs impedance transformation by changing the turns ratio n1 / n2 of the primary and secondary coils of the transformer to achieve impedance matching.

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