Multi-phase switching converter, phase controller and method for generating phase control signal

Abstract

The invention discloses a multiphase switching converter, a phase controller and a method for generating a phase control signal in the phase controller of the multiphase switching converter. A multiphase switching converter includes a plurality of power stages and a phase controller. Each power stage is designed to drive a respective inductor to cause a flow of a respective inductor current in accordance with a respective phase control signal, the respective inductor currents from each power stage together constituting a load current of the converter. The phase controller is designed to determine a frequency of the phase control signal based on the magnitude of the inductor current and to generate the phase control signal having the frequency. Each power stage sends information about a respective inductor current to the phase controller, and the phase controller determines that frequency as an optimal frequency at which the power stage operates at the optimal power efficiency. However, if at least one of a higher phase count demand, undershoot, and overcurrent is detected, the phase controller determines that frequency as a maximum frequency.

Description

[0001] priority

[0002] This patent application is related to and claims priority to a co-pending Indian provisional patent application, entitled “Automatic Efficiency Improvement (AEM) with Inductor Saturation Protection,” serial number 202341079957, filed on November 24, 2023, attorney docket number AURA-351-INPR, which is incorporated herein in its entirety to the extent consistent with the description herein. Technical Field

[0003] Embodiments of the present invention generally relate to a multiphase switching converter, and more particularly to a multiphase switching converter, a phase controller for generating a phase control signal in the multiphase switching converter, and a method for generating a phase control signal in a phase controller of the multiphase switching converter. Background Art

[0004] As known in the related art, a switching converter is a component that converts an input AC (alternating current) voltage or DC (direct current) voltage of one magnitude into an output DC voltage of a desired magnitude by using and operating a switch. A switching converter can be used as a standalone power supply, a voltage regulator module in a variety of environments such as laptop computers and mobile phones.

[0005] A switching converter typically uses multiple power stages to generate an adjustable DC voltage. Each power stage drives a corresponding inductor so that the corresponding inductor current flows in the corresponding phase of the phase sequence, so this switching converter is called a multi-phase switching converter. The corresponding inductor currents from all (activated) power stages together constitute the load current of the multi-phase switching converter.

[0006] It is desirable to operate switching converters with high efficiency, usually measured as the ratio of output power to input power. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Example embodiments of the present invention will be described with reference to the accompanying drawings which are briefly described below.

[0008] Figure 1 is a block diagram of an example system in which aspects of the invention may be implemented.

[0009] Figure 2 FIG. 4 is a block diagram showing details of a multi-phase switching converter according to an embodiment of the present invention.

[0010] Figure 3A FIG. 1 is a schematic diagram showing the implementation of a power stage in an embodiment of the present invention.

[0011] Figure 3BThe flowchart is a flowchart showing the manner in which the phase controller of a multi-phase switching converter operates to improve the efficiency of the switching converter according to an embodiment of the present invention.

[0012] Figure 4 FIG. 1 is a block diagram showing relevant parts of a phase controller in an embodiment of the present invention.

[0013] Figure 5 An example implementation of a data structure for determining the frequency of a control signal provided by a phase controller to each power stage in one embodiment of the present invention is shown.

[0014] Fig. 6A and Figure 6B FIG. 4 is a timing diagram showing the inductor current and the switching frequency of the control signal according to an embodiment of the present invention.

[0015] In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number. DETAILED DESCRIPTION

[0016] 1. Overview

[0017] Aspects of the present invention are directed to a multi-phase switching converter that provides a regulated supply voltage from an input voltage.

[0018] According to one aspect of the present invention, a multiphase switching converter includes a plurality of power stages and a phase controller. Each power stage is designed to drive a corresponding inductor to cause a corresponding inductor current to flow according to a corresponding phase control signal, and the corresponding inductor current of each power stage together constitutes a load current of the multiphase switching converter. The phase controller is designed to determine the frequency of the phase control signal based on the magnitude of the inductor current and generate a phase control signal having the frequency.

[0019] In one embodiment of the present invention, each power stage sends information of the corresponding inductor current to the phase controller, and the phase controller determines the frequency as the optimal frequency for the power stage to operate at the best power efficiency.

[0020] In another embodiment of the present invention, the phase controller determines the frequency to be a maximum frequency within the first duration if at least one of a higher phase count demand, an undershoot, and an overcurrent is detected.

[0021] Several aspects of the present invention are described below with reference to examples. However, those skilled in the relevant art will recognize that the present invention can be implemented without one or more specific details or using other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown in detail to avoid obscuring the features of the present invention. In addition, the described features / aspects can be practiced in various combinations, although for the sake of simplicity, only some combinations are described herein.

[0022] 2. Instance system

[0023] Figure 1 1 is a block diagram of an example system in which aspects of the present invention may be implemented. The illustrated system 100 includes a power supply 110, a central processing unit (CPU) 120, a memory 130, a network interface 140, and peripherals 150. In one embodiment, the system 100 corresponds to a computer (a desktop computer, a laptop computer, etc.), although in other embodiments, the system 100 may represent other types of systems. It should be understood that the system 100 may include more than one computer. Figure 1 More or fewer blocks as shown.

[0024] CPU 120 generally represents a processor or system on chip (SoC) and receives a pair of power supply voltages (Va and Vb) from respective paths 112A and 112B of power supply 110. For example, Va can be a smaller voltage than Vb and can be used to power the core portion of the CPU, which can include an arithmetic logic unit (ALU), a microprogram sequencer, registers, etc. Vb can be used to power the rest of CPU 120, such as input / output (I / O) units, I / O buffers, on-chip peripherals, etc. CPU 120 provides various signals (all of which are considered to be included in path 121) to power supply 110, which specify its power requirements. Examples of such signals can be signals that specify a specific operating mode (in terms of power consumption), such as PS1, PS2, PS3, etc. They refer to "power saving states for improving efficiency".

[0025] Memory 130 represents a memory that may include volatile and non-volatile memory. For example, in a personal computer, the memory may include magnetic memory (hard disk) and solid-state memory (RAM, flash memory, etc.). Memory 130 receives the power supply voltage on path 113 for powering the various circuits and blocks therein.

[0026] The network interface 140 is used to provide two-way communication between the system 100 and a computer network or the general Internet. The network controller 140 implements the electronic circuits required to communicate using a specific physical layer and data link layer standard such as Ethernet or Wi-Fi (TM). The network interface 140 may also include a network protocol stack to allow communication with other computers on the same local area network (LAN) and large-scale network communication through routable protocols such as the Internet Protocol (IP). The network interface 140 receives power on the path 114 for powering the internal circuits and blocks. The network interface 140 communicates with the external system and the CPU 120 on the path 141 and the path 124, respectively.

[0027] Peripheral device 150 represents one or more peripheral circuits, such as a speaker, a microphone, a user interface device, etc. Peripheral device 150 receives power on path 115 and communicates with external devices on path 151 .

[0028] The power supply 110 receives one or more power sources (e.g., batteries) on path 101 and provides the required power supply voltages on paths 112A, 112B, 113, 114, and 115. In one embodiment, the power supply 110 includes one or more DC-DC converters inside thereof to generate the power supply voltages. The power supply 110 responds to signals received from the CPU 120 on path 121 and reduces / increases current output based on specific signals (e.g., PS1, PS2, and PS3).

[0029] In one embodiment, power supply 110 is a voltage regulator module (VRM), sometimes also referred to as a processor power module (PPM), comprising one or more voltage regulators. The voltage regulators include step-down switching (buck) converters for generating several smaller voltages from a high voltage power supply. However, in other embodiments, other types of DC-DC converters, such as boost, buck-boost, hysteresis converters, etc., may be implemented in place of the buck converter. Using a VRM, multiple devices / ICs requiring different power supply voltages can be mounted on the same platform, such as a computer motherboard for a personal computer (PC). Therefore, continuing with the introduction of the embodiment of the present invention, the present invention is described in detail in detail below. Figure 2 The multiphase switching converter shown implements the VRM.

[0030] 3. Multiphase switching converter

[0031] Figure 2 To illustrate an embodiment of the present invention ( Figure 11 is a block diagram of the details of the power supply 110. The power supply 110 is shown implemented as a multiphase switching converter, generates two regulated power supplies (rails) Va (240) and Vb (250), and includes a phase controller 210, smart power stages (power stages) (SPS) SPSA-1 (220-1) to SPSA-6 (220-6), SPSB-1 ​​(230-1) to SPSB-3 (230-3), inductors 225A-1 to 225A-6, 227B-1 to 227B-3, output capacitors 226-1 to 226A-6, 228B-1 to 228B-3, and bootstrap capacitors 224A-1 to 224A-6, 224B-1 to 224B-3.

[0032] In this example, the power supply Va (240) is generated by a six-phase buck converter (with six SPSs, from 220-1 to 220-6), and the power supply Vb (250) is generated by a three-phase buck converter (with three SPSs, from 230-1 to 230-3). Nodes / paths 240 and 250 correspond to Figure 1 For simplicity, other power supply circuits that generate power on paths 113, 114 and 115 are not shown in FIG. Figure 2 Shown in.

[0033] As is known in the related art, each bootstrap capacitor associated with one SPS is connected between the corresponding nodes SW and BOOT of the corresponding SPS and provides the high voltage power required to drive the gate terminal of the high-side switch in the power stage when the high-side switch is implemented as an N-channel metal oxide semiconductor field effect transistor (MOSFET). Therefore, the bootstrap capacitor 224A-1 is connected between the switch nodes SWA-1 (221) and BOOTA-1 (215-1). Although the bootstrap capacitors are shown connected to the outside of each SPS, in an alternative embodiment, the bootstrap capacitors can be located inside the SPS.

[0034] It will be clear from the context that the power stages 220-1 to 220-6 and 230-1 to 230-3 are generally referred to hereinafter by the numerals 220 and 230, respectively. In addition, the signals / nodes 211-1 to 211-6, 213-1 to 213-6, 215-1 to 215-6, 216-1 to 216-3, 218-1 to 218-3, 229-1 to 229-3 are generally referred to by the corresponding numerals 211, 213, 215, 216, 218, and 229, which will also be clear from the context. Similar conventions are followed for other blocks / components / signals throughout the disclosure.

[0035] The combination of phase controller 210, power stage, inductor and capacitor (and corresponding circuits therein) form one "phase" of a multi-phase switching converter. Thus, for example, SPSA-1, inductor 225A-1, capacitor 226A-1, and corresponding portions within phase controller 210 represent one phase of a 6-phase buck converter.

[0036] Each power stage may be implemented as a high-side switch, a low-side switch, gate drive circuits for both switches, and other circuits. Examples of other circuits include, but are not limited to, temperature monitoring circuits, inductor current sensing (or simulation) circuits, etc., to provide information such as the temperature of the SPS / power stage, the magnitude of the inductor current, etc. to the phase controller 210. Each SPS receives a power supply as an input, which is connected to the high-side switch. In Figure 2 In the figure, the power supply is numbered 201 and its voltage is Vin. In one embodiment, the value of Vin is 21 volts (V), Va and Vb are 3.3V and 1.8V respectively. Each SPS is also shown as receiving a voltage Vcc on path 202. In one embodiment, Vcc has a voltage of 3.3V and is provided by phase controller 210.

[0037] Each SPS communicates with the phase controller 210 via respective signals PWM, CS and TMP. Thus, SPSA-1 is connected to the phase controller 210 via signals / paths PWMA-1 (211), CSA-1 (213) and TMPA (214). SPSA-6 communicates with the phase controller 210 via signals PWMA-6, CSA-6 and TMPA (214). Similarly, SPSB-1 ​​is connected to the phase controller 210 via signals / paths PWMB-1 (216), CSB-1 (218) and TMPB (219). SPSB-3 communicates with the phase controller 210 via signals PWMB-3, CSB-3 and TMPB (219). The other SPs have similar connections to the phase controller 210. In other embodiments, there may be a greater or lesser number of such signals as required by the particular operating environment.

[0038] Signal TMP is the output from the SPS to the phase controller 210 and provides information about the temperature in the SPS. The phase controller 210 can process the TMP signal (or the information contained therein) to adjust the current provided by that phase, or to shut down the VRM. The TMP outputs of each phase of the converter are wired together, and a single input is connected to the phase controller 210.

[0039] The signal CS (current sense) is the input from the SPS to the phase controller 210 and contains information representing the magnitude of the inductor current of that phase. This information may be in the form of current, voltage, digital value, etc.

[0040] Signal PWM is an input from phase controller 210 to the SPS and may be considered a "phase control signal" that controls the operation (on and off states) of the power switches in the SPS of the corresponding phase.

[0041] The phase controller 210 controls the operation of the power stage of the power rail to generate stable power supply voltages Va and Vb. The phase controller 210 generates PWM signals 211-1 to 211-6 and 216-1 to 216-3 for controlling the power switches of the corresponding rails to generate Va and Vb, which is well known in the relevant art. Generally, the frequency or duty cycle of the PWM signals is equal.

[0042] In one embodiment of the present invention, the phase controller 210 uses a variable frequency, adaptive on-time control technique to generate Va and Vb. Therefore, in such an embodiment, the signal PWM is a variable frequency, variable pulse width (adaptive on-time) signal. Alternatively, the phase controller 210 can use a variable frequency, constant on-time control technique to generate Va and Vb based on the specific implementation details of the power supply 110. In addition, the phase controller 210 can also use a fixed frequency pulse width modulation operation mode for certain load current ranges.

[0043] When the SPS detects a logic low on signal PWM, the low-side switch turns on, and when signal PWM is detected as a logic high, the high-side switch turns on. Upon detecting a high-impedance (hi-Z) state on signal PWM (typically a mid-rail voltage between power and ground), the SPS turns off both its high-side and low-side switches. Thus, the SPS is said to be "active" ("enabled") when the corresponding PWM signal switches between high and low states, and "inactive" when the corresponding PWM signal is in a high-impedance state. In other words, when the SPS detects a high-impedance value on the PWM signal for a period of time greater than a predetermined threshold, it does not generate voltage or supply current.

[0044] The power stages of the tracks provide current in an interleaved and sequential manner. In other words, the PWM signals to each SPS of the multi-phase switching converter 110 are staggered / interleaved, i.e., delayed in phase relative to each other, so that the start of the on-time of the corresponding high-side switches (and low-side switches) of the track is not simultaneous. The reasons for adopting this technique are, for example, to ensure that the peak instantaneous current drawn from Vin is relatively low, to reduce ripple in the regulated output voltage, etc.

[0045] The phase controller 210 controls the operation of the power stage through the above signals to provide various functions including the regulation function to activate the corresponding power stage group to generate the regulated voltages Va and Vb. Therefore, Va and Vb serve as inputs to the phase controller 210 to activate the operation of one or more feedback loops within the phase controller 210 to regulate Va and Vb.

[0046] The phase controller 210 receives inductor current information (current flowing through each inductor) from each SPS to activate various operations, such as current mode control for voltage regulation, current limiting, short circuit protection, and balancing the current generated by each SPS of the same rail (e.g., rail Va) so that the current from each SPS is substantially equal in magnitude. The phase controller 210 may additionally perform various other operations, which are not described here for the sake of simplicity.

[0047] Phase controller 210 is used to control the power stage (via corresponding PWM signals) to reduce or increase current output according to load demand. Phase controller 210 may also receive a signal from CPU 120 indicating the desired power state (e.g., PS1, PS2, etc., described above) in which the CPU is to operate from time to time. In response, phase controller 210 may disable / activate one or more of power stages 220 according to the power state and load current.

[0048] In summary, the specific number of phases (power stages) that the phase controller 210 enables to operate can vary depending on, for example, the magnitude of the load current drawn from the rail (e.g., Va 240). In general, the smaller the load current, the fewer phases are enabled, and vice versa. When the power stage is not activated (i.e., not working), the two power switches of the power stage are always off, and the power stage does not contribute any current (inductor current) when generating the regulated voltage (e.g., Va).

[0049] Phase controller 210 is used to detect undershoots in the regulated supply voltage (Va or Vb). An undershoot refers to a transient change in the regulated supply voltage, where the regulated supply voltage drops below an allowed lower limit (e.g., drops by at least 5% of the nominal regulated supply voltage). For example, such an undershoot may be due to a sudden spike / increase in load current (the current drawn by one or more loads from the regulated supply node (Va / Vb)).

[0050] The phase controller 210 is also used to detect an overcurrent condition in the inductor current (e.g., based on the CS signal received from the activated SPSs). An overcurrent condition is a condition where the inductor current of the power stage exceeds a threshold limit (referred to as an overcurrent limit). Additionally or alternatively, each power stage is designed to detect an overcurrent condition in (relative to) the inductor current generated by it (the power stage) and indicate such an overcurrent condition to the phase controller 210.

[0051] It is generally desirable that the efficiency of the power supply 110 be as high as possible. Efficiency refers to the ratio of the output power provided by the power supply to the input power that the power supply draws from the power supply source Vin. It is noted here that some of the power used for operation is drawn from Vcc and the source power supply phase controller 210. However, the power drawn from these sources is negligible compared to the power drawn from Vin and can therefore be ignored. Therefore, generally the most important component of power loss in the power supply 110 is the power loss in the power switch in each operating power stage (or the power loss caused by the power switch). Therefore, the details of the power stages in the embodiments of the present invention are provided and briefly described below.

[0052] Figure 3A 2 is a diagram showing the implementation of the power stage in an embodiment of the present invention. Figure 3A Other power stages can also be implemented similarly to the SPSA-1. For simplicity, the bootstrap capacitor and associated connections and circuits are not shown in Figure 3A The SPSA-1 shown includes a gate driver 310, a high-side (HS) switch 320, a low-side (LS) switch 330, a temperature sensor 335, and a current sensing block 340. The HS switch 320 and the LS switch 330 represent the power switches of the power stage (as described above). Figure 3A Also shown are inductor 225-1 and capacitor 226A-1. Node 240 provides a regulated supply voltage Vout (Va). Note that the specific implementation details of SPSA-1 are provided for illustration only. In other embodiments, the SPS may have more or fewer blocks.

[0053] Temperature sensor 335 periodically measures the ambient temperature at SPS 220A-1 and provides a temperature value on path 214. Phase controller 210 may receive temperature values ​​from time to time and take appropriate action if the temperature value exceeds an acceptable level.

[0054] The gate driver 310 receives the control signal PWMA-1 and generates appropriate voltages on the corresponding paths 312 (en-HS) and 313 (en-LS) in response to the logic level of PWMA-1 to turn on and off the HS switch 320 and the LS switch 330 in the corresponding intervals indicated by PWMA-1. The HS switch 320 and the LS switch 330 are both implemented as NMOS (N-channel metal oxide semiconductor field effect transistor MOSFET), where the gate driver 310 drives the gate terminal of the NMOS. Other implementations of the switch are also possible.

[0055] exist Figure 3AIn the example of FIG. 1 , when PWMA-1 is logic high (corresponding to the first interval of each PWM cycle), gate driver 310 generates corresponding appropriate voltages on paths 312 (en-HS) and 313 (en-LS) to turn on MOSFET 320 and turn off MOSFET 330. When PWMA-1 is logic low (corresponding to the second interval of each PWM cycle), gate driver 310 generates corresponding appropriate voltages on paths 312 and 313 to turn off MOSFET 320 and turn on MOSFET 330.

[0056] The current sensing block 340 is used to sense the inductor current (IL), thereby constructing a (scaled / unscaled) copy of the inductor current in each first interval (HS interval) and second interval (LS interval). Figure 3A In FIG. 1 , current sensing block 340 receives the respective voltage drops across switch 320 (based on paths 342 and 343) and switch 330 (based on paths 341 and 342) to generate a replica. Current sensing block 340 provides the scaled / unscaled replica to phase controller 210 on path CSA- 1 .

[0057] Phase controller 210 may utilize a copy of the inductor current reported by the activated power stage in one or more regulation feedback loops operating in phase controller 210 to provide a regulated voltage of a desired magnitude Vout as output 240, as well as for other purposes, such as detecting spikes in load current.

[0058] Generally speaking, loss components such as switching loss (loss due to turning on / off the power switch), conduction loss (voltage drop across the switch), dead time loss (short circuit between Vin and ground due to both power switches of the power stage being turned on at the same time), etc., represent the main loss components that affect the overall efficiency of the switching converter. Some of them, such as switching loss, depend on the switching frequency, while other parts, such as conduction loss, depend on the operating current level, ripple, etc.

[0059] Several aspects of the present invention are directed to improving the efficiency of a multi-phase switching converter, as described below.

[0060] 4. Flowchart

[0061] Figure 3B The flowchart is a flowchart showing the manner in which the phase controller of the multi-phase switching converter operates to improve the efficiency of the switching converter according to an embodiment of the present invention. Figure 1 and Figure 2The system / flowchart description of the multi-phase switching converter is for illustration only. However, without departing from the scope and spirit of several aspects of the present invention, many features can be implemented in other systems and / or other environments, which will be apparent to those skilled in the relevant art by reading the disclosure provided herein.

[0062] In addition, some steps may be performed in a different order than described below depending on the specific circumstances, which will be apparent to those skilled in the relevant art. Many such implementations are covered by several aspects of the present invention. The flow chart begins at step 351, where control immediately passes to step 360.

[0063] In step 360, the phase controller 210 receives the magnitude of the corresponding inductor current from the activated (i.e., enabled) power stages (SPSs). In one embodiment, the phase controller 210 receives the magnitude of the inductor current from the current sense (CS) output terminal of the power stage in the form of a scaled copy of the inductor current. However, in other embodiments, the phase controller 210 may receive the inductor current magnitude in other forms, such as a voltage, a digital value / number, etc. Control passes to step 370.

[0064] In step 370, the phase controller 210 determines the frequency of the generated phase control signal (PWM signal) based on the magnitude of the inductor current. As is well known in the relevant art, in each cycle of the PWM signal, when the HS switch of the power stage is turned on, the inductor current of the power stage increases linearly, and then when the LS switch of the stage is turned on, the inductor current decreases linearly. Therefore, the phase controller 210 calculates the average value of the inductor current in the PWM cycle based on the copy received from the above-mentioned CS output, and determines the frequency of the PWM signal based on the average value. As described above, the inductor currents of all activated power stages are equal. Therefore, the phase controller 210 only needs to process the inductor current information received from any one activated power stage. Alternatively, the phase controller 210 can determine the frequency based on the maximum value (peak value) of the inductor current, the minimum value (valley value) of the inductor current, etc., combined with the cycle duration (cycle) of the current PWM clock. The frequency is selected to optimize the power efficiency of the switching converter 110.

[0065] Generally, the lower the switching frequency, the lower the switching loss of the power switch. However, as the switching frequency decreases, other factors that cause power loss become increasingly important. For example, the ripple in the inductor current increases as the switching frequency decreases, which in turn increases the conduction loss, and the increased ripple may also cause the inductor current to saturate. Therefore, for a specific single inductor current value (average / peak / valley, etc.), or a given inductor current value (average / peak / valley, etc.), there is an optimal switching frequency that provides maximum efficiency. The phase controller 210 determines the value of this optimal switching frequency based on the current / received magnitude of the inductor current. In addition to the consideration of maximizing efficiency, or alternatively, the phase controller 210 determines the switching frequency to be a frequency that provides sufficient inductor current saturation margin. In other words, the phase controller 210 selects a sufficiently high switching frequency value (for the corresponding inductor current magnitude or magnitude range) so that for a predetermined jump (increase) in the load current, any corresponding increase in the inductor current (if allowed) will not cause the inductor to saturate. Regardless of the factors taken into account by the phase controller 210 to determine the switching frequency value, the determined switching frequency value is considered here to be "optimal", or in other words, the determined switching frequency causes the activated power stage (and therefore the entire switching converter) to operate at "optimal power efficiency".

[0066] Control then passes to step 380 .

[0067] In step 380, the phase controller 210 generates a PWM signal having a determined frequency and provides the PWM signal to the activated power stage. Then, control passes to step 399, where the flowchart ends.

[0068] Using the inductor current magnitude to determine the desired PWM switching frequency may be preferred over using the load current magnitude to determine the desired PWM switching frequency. This is because the load current magnitude alone cannot indicate which (and how many) power stages are currently active, which may require additional time and therefore delay changing the PWM switching frequency when necessary. In addition, at least in some cases, the accuracy and / or resolution of measuring the load current magnitude may be poorer than the accuracy and / or resolution of measuring the inductor current magnitude because the inductor current range is typically much smaller than the load current range.

[0069] Phase controller 210 repeats Figure 3B The process continuously monitors and regulates the switching frequency. For example, as long as at least one SPS is active.

[0070] Next, some implementation details of the phase controller 210 for generating a PWM signal with an optimal frequency according to an embodiment of the present invention are provided.

[0071] 5. Phase controller

[0072] Figure 4 The block diagram of the phase controller 210 is to illustrate the relevant parts of the embodiment of the present invention. The phase controller 210 includes a telemetry block 410, a frequency determination block 420 and a control block 430. The frequency determination block 420 further includes a processing block 440 and a data structure 450, and the control block 430 further includes a PWM generator block 460, an automatic phase management (APM) block 470, an undershoot detection (USD) block 480 and an overcurrent limit (OCL) block 490. Figure 4 The section / block shown is used to control the power level of track A (Va). It should be noted here that Figure 4 Only those blocks relevant to understanding the disclosure herein are depicted. It should be understood that the phase controller 210 may include more Figure 4 More or fewer blocks may be shown. For example, Figure 4 Some of the blocks in may be duplicated (with appropriate inputs) to provide corresponding functionality for track Vb (250). The internal modules of phase controller 210 may be powered by a source not shown. Figure 4 The blocks can be implemented in a known manner.

[0073] The telemetry block 410 receives the CS signal 213, which contains information representing the magnitude (but typically the average value) of the corresponding inductor current from the corresponding activated SPS, and converts the analog signal into a digital value. In one embodiment, the CS signal 213 received from the SPS is a scaled-down replica of the corresponding inductor current. The telemetry block 410 calculates the average value of the digital value of any one replica current within the PWM cycle. Alternatively, the telemetry block 410 can store the peak or valley value of the replica in the PWM cycle. In the following description, it is assumed that the telemetry block 410 calculates the average value of the replica current, so other peak values, valley values ​​or other characteristics that may also be used instead will not be involved. The telemetry block 410 multiplies the average value by the inverse of the reduction factor used in the power stage and forwards the resulting (actual) value of the (average) inductor current to the processing block 440.

[0074] It should be noted that the telemetry block 410 receives CS signals from all power stages of the track A (Va), and the telemetry block 410 also receives information from the APM block 470 (via the processing block 440) indicating which power stages are currently active / enabled. Therefore, as described above, the telemetry block 410 can process only one of those CS signals corresponding to the currently active power stage, because all inductor currents are equal, i.e., have substantially the same average value, and forward a suitable scaled value of the average value to the processing block 440 on the path 412. Alternatively, when there are small variations between the average values ​​of the individual inductor currents of the active power stages, the telemetry block 410 can forward scaled values ​​of these different average values ​​to the processing block 440 on the path 412 (the processing block 440 then calculates the average value of the received average values), or the telemetry block 410 can further calculate the average value of the average values ​​of the individual inductor currents and forward a suitable scaled value of the average value to the processing block 440 on the path 412.

[0075] The APM block 470 determines the magnitude of the load current currently being drawn from rail Va, and if the magnitude is greater / less than the magnitude of the previous (or immediately preceding a predetermined interval) PWM cycle, generates a signal on path 424 indicating whether more / fewer power stages need to be activated. In an example implementation, the APM block 470 determines the magnitude of the load current based on the CS signal 213. The APM block 470 adds the individual inductor currents reported in the CS signal to obtain the load current magnitude. In an alternative embodiment, the APM block 470 includes circuitry to directly measure the load current drawn from Va. Based on changes in the load current, the APM block 470 determines the number of power stages that should be enabled / activated and which power stages, and forwards such information to the processing block 440. In addition, the APM block 470 will forward this information to the PWM generator block 460 (although in Figure 4 Path not shown in the figure) so that a PWM signal can be generated for the activated power stage. Any update from the APM block 470 on path 424 may indicate an increase in load current and indicate that more power stages need to be run / activated than the currently activated power stages.

[0076] In an exemplary implementation, the APM block 470 generates an n-bit wide signal, where “n” is the total number of phases (i.e., power stages) in the multi-phase switching converter 110, and each bit indicates whether the corresponding phase is activated. For example, for a medium load current obtained from the track Va (240), the APM block 470 can generate a signal “111000” on the path 424, indicating that SPSA-1 (220-1) to SPSA-3 (220-3) need to be in an active mode, and SPSA-4 (220-4) to SPSA-6 (220-6) need to be in an inactive mode. For a high load current, the APM block 470 can generate a signal “111111”, indicating that all six power stages (SPSA-1 (220-1) to SPSA-6 (220-6)) need to be in an active mode. It can be understood that an n-bit signal can be sent whenever the number of activated power stages needs to change (based on the corresponding change in the load current).

[0077] USD block 480 continuously senses / measures the voltage on output node Va (240). If voltage Va drops below a predetermined threshold (e.g., 5%) below the desired regulated value of voltage Va, USD block 480 generates a logic signal on path 426 to indicate "undershoot". For example, USD block 480 may be implemented using a comparator (with hysteresis) and a reference voltage. An undershoot indication on path 426 indicates that the load current has increased significantly.

[0078] The OCL block 490 receives the current sense signal CS213 from the power stage. The OCL block 490 includes one or more comparators to determine whether the instantaneous per-phase current (i.e., the sensed inductor current / scaled copy from the power stage) has exceeded the overcurrent limit. The OCL block 490 can similarly compare the other per-phase currents to the same overcurrent limit. In one embodiment, the overcurrent limit represents a value that is slightly lower than the maximum instantaneous per-phase current that the power stage can handle and the saturation current of the corresponding inductor (the smaller of the two).

[0079] Upon detecting that the instantaneous inductor current of at least one power stage has exceeded the overcurrent limit, the OCL block 490 uses a logic signal to indicate that the overcurrent limit has been exceeded on path 428. This indication also indicates that the load current has increased.

[0080] Data structure 450 maps different ranges of magnitudes of the inductor current to corresponding optimal frequencies. The range is selected to improve the overall efficiency of the switching converter. In one embodiment, data structure 450 is implemented in a rewritable memory, and the data in data structure 450 (including the mapping between the magnitudes of the inductor current and the corresponding optimal frequencies) can be updated / changed. Data structure 450 can be implemented using techniques known in the relevant art.

[0081] In one embodiment, data structure 450 is implemented as a look-up table (LUT), an example of which is Figure 5 As shown. Figure 5 As shown, column 502 ("Inductor Current Range (Amperes)") specifies the range of inductor current magnitudes (the magnitudes represent the average values ​​in the PWM cycle), and column 504 ("PWM Frequency (KHz)") specifies the optimal frequency for the corresponding inductor current range. Thus, row 510 specifies an inductor current range of "0-0.5A" (column 502) and a corresponding optimal PWM switching frequency of "100KHz" (column 504). Similarly, other rows of LUT 450 specify corresponding optimal frequencies for other ranges of inductor current. Figure 5 In the example of , it is assumed that 3 A is the expected maximum inductor current. It will be appreciated that the values ​​in LUT 450 are for illustration only and that these values ​​may be selected taking into account various factors.

[0082] Processing block 440 is used to select a PWM switching frequency from LUT 450 (accessed via path 442) and send the selected frequency on path 422 to PWM generator block 460, which in turn generates a PWM signal at the received frequency. PWM generator block 460 will be further described below. In one embodiment of the present invention, processing block 440 evaluates whether a new PWM frequency (applied from the end of the current PWM cycle) must be determined (based on the entries in LUT 450) at the current PWM switching frequency at intervals of one cycle of the PWM signal. In other embodiments, the evaluation may be performed at lower frequency intervals. However, if any of the signals / data received on paths 424, 426, and 428 indicate an increase in load current, processing block 440 selects the highest value of the PWM switching frequency in LUT 450 as the new PWM frequency (applied from the end of the current PWM cycle) and forwards the highest value to PWM generator block 460. The highest PWM switching frequency is selected to prevent the possibility of saturation of one or more inductors of the power stage. As is well known in the related art, the lower the PWM switching frequency, the larger the inductor current ripple. Therefore, if the inductor current is increased without increasing the PWM switching frequency, there is a possibility of inductor saturation, which is undesirable because saturation causes the inductor's inductance to decrease and thus negatively affects the operation of the switching converter.

[0083] The processing block 440 receives the average inductor current magnitude from the telemetry block 410 on path 412. For example, depending on the speed / design of the telemetry block 410, the processing block 440 may receive the average inductor current magnitude at the end of each PWM cycle or at less frequent intervals. The processing block 440 also receives data and signals sent on paths 424, 426, and 428 from the APM block 470, the USD block 480, and the OCL block 490, respectively, when data and signals are sent (usually only when there is a change from a previous or normal condition). Based on the received inputs on paths 412, 424, 426, and 428, the processing block 440 retrieves the appropriate PWM switching frequency from the LUT 450.

[0084] If none of the data / signals received on paths 424 , 426 , and 428 indicate an increase in load current, the processing block 440 retrieves the PWM switching frequency value corresponding to the inductor current magnitude currently received from the telemetry block 410 from the LUT 450 , and sends the retrieved PWM switching frequency value to the PWM generator block 460 .

[0085] However, if at least one of the data / signals received on paths 424, 426, and 428 indicates an increase in load current, processing block 440 selects the highest value of the PWM switching frequency in LUT 450 and forwards the highest value to PWM generator block 460, also as described above. In addition, one or more inactive power stages may be activated to enable the switching converter to meet the increased load current demand. Although Figure 4 4, but processing block 440, upon receiving assertion of one or more of signals 424, 426, and 428, will send a signal to a stage activation block (not shown). The stage activation block obtains the number and identity of currently activated power stages from APM block 470, and in response to the communication from processing block 440, activates the desired number of inactive power stages.

[0086] It will be appreciated that the data / signals received on paths 424, 426 and 428 merely indicate an increase in load current, but not the amount of increase. Nevertheless, processing block 440 is used to retrieve the highest PWM switching frequency, and PWM generator block 460 sets the PWMA (211) signal with the retrieved switching frequency to preempt any possibility of inductor current saturation.

[0087] Therefore, the phase controller 210 generates a PWM signal with an optimal frequency to achieve maximum power efficiency while also preventing inductor current saturation.

[0088] An example of selecting the PWM switching frequency is shown in the following example.

[0089] In the case of no "higher phase count requirement" and no "undershoot detection" and no "exceeding overcurrent limit"

[0090] If the data on path 424 does not indicate a “higher phase count demand” (i.e., no additional power stage needs to be enabled), if the signal on path 426 does not indicate an “undershoot” condition, and if the signal on path 428 does not indicate that an overcurrent limit has been exceeded, then processing block 440 determines the PWM switching frequency based solely on the magnitude of the inductor current currently received on path 412.

[0091] As an example, if SPSA-1, SPSA-2, and SPSA-3 are activated SPSs and processing block 440 receives 0.69A, 0.7A, and 0.71A as the corresponding average inductor currents of the 3 activated power stages on path 412, processing block 440 determines by checking LUT 450 that all digital values ​​are in the same range (i.e., 0.5-1A in LUT 450) and retrieves the corresponding frequency item in the LUT (i.e., 200KHz) through path 442.

[0092] However, if the average inductor currents happen to fall within different ranges (e.g., one within the range of 0-0.5A and the other two within the range of 0.5-1A), processing block 440 may calculate the average of the three currents and retrieve the frequency corresponding to the range that the average falls within. For example, if SPSA-1, SPSA-2, and SPSA-3 are the activated SPSs, and processing block 440 receives 0.49A, 0.51A, and 0.53A as the corresponding inductor currents, processing block 440 determines that the currents fall within different ranges in LUT 450. Therefore, processing block 440 calculates the average (0.51A) and retrieves the value 200KHz accordingly.

[0093] Alternatively, if the inductor current falls within different ranges, the processing block 440 may output a PWM frequency corresponding to the highest or lowest value of the inductor current.

[0094] Fig. 6A The relationship between the (average) inductor current (IL) and the selected PWM switching frequency is illustrated. Fig. 6A In the illustration, it is assumed that only SPSA-1, SPSA-2, and SPSA-3 are active and the inductor currents of all active power stages are the same.

[0095] like Fig. 6AAs shown, at time t630, processing block 440 receives 0.15A, 0.15A, and 0.15A as the inductor current values ​​corresponding to SPSA-1, SPSA-2, and SPSA-3. Processing block 440 checks LUT 450 and determines that the received values ​​are all within the same range of 0-0.5A ( Figure 5 Therefore, processing block 440 outputs 100KHz as the PWM frequency value on path 422.

[0096] Similarly, at t632, t634 and t636, respectively, the processing block 440 outputs 200KHz (inductor current is 0.7A, within the range of 0.5 to 1.0A), 300KHz (inductor current is 1.1A, within the range of 1.0 to 1.5A) and 200KHz (inductor current is 0.85A, within the range of 0.5 to 1.0A).

[0097] In case of "higher phase count demand" or "undershoot detection" or "exceeding overcurrent limit"

[0098] If the data on path 424 indicates a "higher phase count demand" (i.e., an additional power stage needs to be enabled), or if the signal on path 426 indicates an "undershoot" condition, or if the signal on path 428 indicates that the overcurrent limit has been exceeded, then processing block 440 ignores the signal on path 412 and selects the highest value of the PWM switching frequency in LUT 450 and stores that highest value (in Figure 5 The processing block 440 outputs a different higher frequency (rather than the highest frequency of 600 KHz) based on, for example, an estimate of load current variation.

[0099] After sending the highest frequency value to the PWM generator block 460, the processing block 440 monitors the inductor current magnitude received on the path 412. If the inductor current magnitude drops below a predefined threshold and remains below the threshold for a certain duration (referred to as the debounce time), the processing block 440 reduces the switching frequency to a corresponding lower value based on the LUT 450.

[0100] Figure 6B An example graph showing the correspondence between the load current, the inductor current (IL), the signal on path 426 indicating an "undershoot" condition, and the selected PWM switching frequency. Figure 6B In the illustration of FIG. 1 , it is assumed that only SPSA-1, SPSA-2, and SPSA-3 are active and the inductor current of all active power stages is the same.

[0101] like Figure 6B As shown, at time t680, the load current is 0.6A, and the inductor currents of SPSA-1, SPSA-2, and SPSA-3 are all 0.2A. Processing block 440 receives 0.2A, 0.2A, and 0.2A as the inductor current values ​​corresponding to SPSA-1, SPSA-2, and SPSA-3. Processing block 440 checks LUT 450 and determines that the received values ​​are all within the same range of 0-0.5A ( Figure 5 Therefore, processing block 440 outputs 100KHz as the PWM frequency value on path 422.

[0102] At time t682, processing block 440 outputs 100 KHz (inductor current is 0.3 A, within the range of 0-0.5 A).

[0103] However, at time t684, the load current suddenly increases, causing the voltage Va to "undershoot". The USD module 480 detects the "undershoot" condition and sends a logic high signal on path 426 to indicate the "undershoot" condition. The processing block 440 detects the logic high signal on path 426, ignores the input on path 412, and selects 600KHz (the highest frequency in LUT 450) and forwards it to the PWM generator block 460 on path 422.

[0104] At time t686, the processing block 440 receives 0.8 A (an inductor current falling within a lower range) as the value of the inductor current on the path 412. However, the processing block 440 does not immediately output the optimal frequency corresponding to 0.8 A. At time t688, the processing block 440 again receives 0.8 A as the value of the inductor current, and determines that the debounce time has passed and the inductor current is still within the lower range, and outputs 200 KHz (a frequency corresponding to 0.8 A) as the optimal frequency.

[0105] Thus, when an "undershoot" condition is detected, processing block 440 prevents the inductor from going into saturation by forwarding the highest frequency in LUT 450 as the optimal frequency.

[0106] Similarly, in the case of higher phase count requirements or over-current detection, processing block 440 prevents the inductor from going into saturation by forwarding the highest frequency in LUT 450 as the optimal frequency.

[0107] The processing block 440 may be implemented using techniques known in the relevant art, which will be apparent to those skilled in the art.

[0108] The PWM generator block 460 receives the optimal PWM switching frequency from the processing block 440 on path 422. The PWM generator block 460 determines the on-time (T-ON, i.e., logic high pulse duration) to be set for the PWM signal provided on path PWMA-211 based on the received optimal PWM switching frequency and the desired duty cycle of the PWM signal. The desired duty cycle (D) is equal to Vout / Vin, where Vout is the regulated output voltage (here Va 240) and Vin is the voltage of the input power supply (e.g., Figure 2 and Figure 3A 201). The PWM generator block 460 may be implemented in a known manner.

[0109] The techniques of the present invention may be particularly advantageous when the switching converter is operated in continuous conduction mode (CCM), where load current is typically high and it is desirable to increase the efficiency of the switching converter while also preventing the inductor from going into saturation.

[0110] It is noted here that in an embodiment of the present invention, the entries of LUT 450 are determined a priori based on measurements in a laboratory setting by varying the switching converter 110, particularly the power stage (e.g., 220-1, etc.) with load current (e.g., a variable test load connected to node 240 (Va)), and making various related measurements (and / or using formulas), such as switching losses, conduction losses, margin available for inductor current saturation, etc., for various PWM switching frequencies. The entries so determined are then stored in non-volatile memory in the phase controller 210 and used during normal operation.

[0111] It will also be appreciated that the techniques of the present invention are capable of setting the PWM switching frequency to a value (within a range of nearby or continuous values) that results in maximum power efficiency for the switching converter at least when the load current is constant (fixed single value) or only changes slowly. Sudden and significant changes in load current will typically be reflected in one or more outputs of the APM module 470, the USD module 480, and the OCL module 490. By reacting to any such indication from the modules to apply the highest switching frequency, the technique ensures that inductor current saturation never occurs. The highest switching frequency of the LUT 450 (e.g., 600KHz) will be tested and confirmed during the above-mentioned test measurements to not result in inductor current saturation for the maximum expected load current for which the switching converter is designed.

[0112] 6. Conclusion

[0113] References to "one embodiment", "an embodiment" or similar language in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. Therefore, phrases "in one embodiment", "in an embodiment" and similar language appearing throughout the specification may, but do not necessarily, all refer to the same embodiment.

[0114] Despite Figure 1 , Figure 2 , Figure 3A and Figure 4 In the illustrations of , while terminals / nodes are shown as being directly connected (i.e., "connected to") various other terminals, it should be understood that additional components (as appropriate to the particular environment) may also be present in the path and, therefore, the connections may be viewed as being "electrically coupled" to the same connection terminals.

[0115] In the present invention, the power supply and ground terminals are referred to as constant reference potentials.

[0116] Although various embodiments of the present invention have been described above, it should be understood that these embodiments are intended to be exemplary rather than limiting. Therefore, the breadth and scope of the present invention should not be limited by any of the above embodiments, but should only be defined in accordance with the following claims and their equivalents.

Claims

1. A multiphase switching converter for providing a regulated supply voltage according to an input voltage, wherein the multiphase switching converter comprises: a plurality of power stages, each power stage driving a corresponding inductor according to a corresponding phase control signal to cause a flow of a corresponding inductor current, wherein the corresponding inductor current from each of the plurality of power stages together constitutes a load current of the multi-phase switching converter; and A phase controller is configured to determine a frequency of the phase control signal based on the magnitude of the inductor current and generate the phase control signal having the frequency.

2. The multiphase switching converter of claim 1 , wherein each of the plurality of power stages sends information about a corresponding inductor current to the phase controller, The phase controller determines the frequency as an optimal frequency for the plurality of power stages to operate at an optimal power efficiency.

3. The multiphase switching converter according to claim 2, wherein: If at least one of a higher phase count demand, undershoot, and overcurrent is detected, the phase controller determines the frequency to be a maximum frequency for a first duration, wherein the higher phase count requirement refers to a situation where the load current drawn from the rail in one cycle requires a greater number of power stages to be in active mode than in the previous cycle; wherein the undershoot is a decrease in the magnitude of the regulated supply voltage, wherein the magnitude of the regulated supply voltage is below an allowable lower limit of the regulated supply voltage; and The overcurrent is a situation where the inductor current corresponding to the power level exceeds the maximum limit.

4. The multiphase switching converter of claim 3, wherein the phase controller generates the phase control signal having the frequency and a duty cycle, the duty cycle being determined by at least the magnitude of the regulated supply voltage and the magnitude of the input voltage.

5. The multiphase switching converter of claim 3 , wherein each of the plurality of power stages generates a current sensing signal representative of a magnitude of the corresponding inductor current, wherein the phase controller comprises: a telemetry block for receiving the current sensing signal and generating a digital value representing the magnitude of the quantity; a frequency determination block coupled to receive the digital value and output the frequency; and A control block is coupled to receive the frequency and generate the phase control signal having the frequency and the duty cycle.

6. The multi-phase switching converter of claim 5, wherein the frequency determination block comprises a lookup table (LUT) that maps different combinations of magnitudes of the inductor current to corresponding optimal frequencies, wherein the frequency is determined by checking the lookup table.

7. A method for generating a phase control signal in a phase controller of a multi-phase switching converter, the method comprising: receiving magnitudes of respective inductor currents from a plurality of power stages of the multi-phase switching converter, wherein the respective inductor currents from the plurality of power stages collectively constitute a load current of the multi-phase switching converter; determining a frequency for generating the phase control signal based on the magnitude of the corresponding inductor current; and The phase control signal is generated at the determined frequency and provided to the plurality of power stages.

8. The method of claim 7, wherein each of the plurality of power stages sends information about a corresponding inductor current to the phase controller, The phase controller determines the frequency as an optimal frequency for the plurality of power stages to operate at an optimal power efficiency.

9. The method according to claim 8, wherein: If at least one of a higher phase count demand, undershoot, and overcurrent is detected, the frequency is determined to be the maximum frequency in the first duration, wherein the higher phase count requirement refers to a situation where the load current drawn from the rail in one cycle requires a greater number of power stages to be in active mode than in the previous cycle; wherein the undershoot is a decrease in the magnitude of a regulated supply voltage provided by the multi-phase switching converter, wherein the magnitude of the regulated supply voltage is below an allowable lower limit for the regulated supply voltage; and The overcurrent is a situation where the inductor current corresponding to the power level exceeds the maximum limit.

10. The method of claim 9, further comprising generating the phase control signal having the frequency and a duty cycle, the duty cycle being determined by at least a magnitude of the regulated supply voltage and a magnitude of the input voltage.

11. The method according to claim 9, further comprising: receiving a current sense signal from each of the plurality of power stages, wherein the current sense signal represents a magnitude of the corresponding inductor current, and generating a digital value representing the magnitude; receiving the digital value and determining the frequency; and The phase control signal is generated having the determined frequency and the duty cycle.

12. The method of claim 11, wherein the frequency is determined by checking a lookup table (LUT) that maps different combinations of magnitudes of the inductor current to corresponding optimal frequencies.

13. A phase controller for generating a phase control signal in a multi-phase switching converter, the phase controller being used to: receiving magnitudes of respective inductor currents from a plurality of power stages of the multi-phase switching converter, wherein the respective inductor currents from the plurality of power stages collectively constitute a load current of the multi-phase switching converter; determining a frequency for generating the phase control signal based on the magnitude of the corresponding inductor current; and The phase control signal is generated at the determined frequency and provided to the plurality of power stages.

14. The phase controller of claim 13, wherein each of the plurality of power stages sends information about a corresponding inductor current to the phase controller, The frequency is determined to be an optimal frequency at which the plurality of power stages operate at an optimal power efficiency.

15. The phase controller of claim 14, wherein the phase controller is configured to determine the frequency to be the maximum frequency in the first duration upon detecting at least one of a higher phase count demand, undershoot, and overcurrent, wherein the higher phase count requirement refers to a situation where the load current drawn from the rail in one cycle requires a greater number of power stages to be in active mode than in the previous cycle; wherein the undershoot is a decrease in the magnitude of a regulated supply voltage provided by the multi-phase switching converter, wherein the magnitude of the regulated supply voltage is below an allowable lower limit for the regulated supply voltage; and The overcurrent is a situation where the inductor current corresponding to the power level exceeds the maximum limit.

16. The phase controller of claim 15, wherein the phase controller generates the phase control signal having the frequency and a duty cycle, the duty cycle being determined by at least the magnitude of the regulated supply voltage and the magnitude of the input voltage.

17. The phase controller according to claim 15, comprising: a telemetry block for receiving the current sensing signal and generating a digital value representing the magnitude of the quantity; a frequency determination block coupled to receive the digital value and output the frequency; and A control block is coupled to receive the frequency and generate the phase control signal having the frequency and the duty cycle.

18. The phase controller of claim 17, wherein the frequency determination block comprises a lookup table (LUT) that maps different combinations of magnitudes of the inductor current to corresponding optimal frequencies, wherein the frequency is determined by checking the lookup table.

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