USB-PD power adapter, power converter and method thereof

Abstract

The invention discloses a USB-PD power adapter, a power converter and a method thereof. A USB-PD power converter has a primary side controller and a secondary side controller in bidirectional communication with each other. In one embodiment, a USB-PD power converter has a first transformer in data communication with a primary side controller and a secondary side controller. The secondary side controller is configured to generate a control signal and receive an acknowledgement signal from the primary side controller via the first transformer. The primary side controller is configured to generate an acknowledgement signal and receive a control signal from the secondary side controller via the first transformer.

Description

Technical Field

[0001] The present disclosure relates generally to the field of power conversion, and more particularly to bidirectional communication between a primary side controller and a secondary side controller of an isolation converter. Background Art

[0002] An electrical power converter is a device used to convert electrical power from one form to another. A flyback converter is one type of converter. This disclosure will be made with respect to a flyback converter, it being understood that the disclosure may also be applied to other types of power converters. Summary of the invention

[0003] One aspect of the present invention provides a method for a secondary-side controlled Universal Serial Bus Power Transmission (USB-PD) converter, the method comprising: a secondary-side controller of the USB-PD converter generates a first control signal; a primary-side controller of the USB-PD converter receives the first control signal via a first transformer of the USB-PD converter; in response to the primary-side controller receiving the first control signal via the first transformer, the primary-side controller activates or deactivates a first primary-side switch coupled to a primary winding of a second transformer of the USB-PD converter; in response to the primary-side controller receiving the first control signal via the first transformer, the primary-side controller generates a first confirmation signal; and the secondary-side controller receives the first confirmation signal via the first transformer.

[0004] Another aspect of the present invention provides a universal serial bus power transmission USB-PD power converter, comprising: a pulse transformer; a secondary side controller for data communication with the pulse transformer; a primary side controller for data communication with the pulse transformer; wherein the secondary side controller is configured to generate a control signal; wherein the secondary side controller is configured to receive a confirmation signal from the primary side controller via the pulse transformer; wherein the primary side controller is configured to generate a confirmation signal; wherein the primary side controller is configured to receive a control signal from the secondary side controller via the pulse transformer.

[0005] Another aspect of the present invention provides a Universal Serial Bus Power Delivery (USB-PD) power adapter, comprising: a USB-C port; a flyback transformer coupled to the USB-C port; a pulse transformer; a primary side controller coupled to the pulse transformer and configured to control the operation of the flyback transformer; and a secondary side controller coupled to the USB-C port and the pulse transformer, the secondary side controller being configured to communicate data with the primary side controller in the USB-PD power adapter via the pulse transformer; wherein the secondary side controller is configured to generate a control signal for indirectly controlling a switch connected to the primary winding of the flyback transformer; wherein the secondary side controller is configured to receive a confirmation signal from the primary side controller via the pulse transformer; wherein the secondary side controller is configured to: control the secondary side switch connected to the secondary winding of the flyback transformer based on the confirmation signal received from the primary side controller via the pulse transformer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like reference numerals refer to similar elements and in which:

[0007] Figure 1 is a block diagram showing relevant components of a flyback converter.

[0008] Figure 2 is a block diagram showing relevant components of a flyback converter employing one embodiment of the present disclosure.

[0009] Figure 3 is a flow chart illustrating relevant aspects of a method employing one embodiment of the present disclosure.

[0010] Figure 4 is a flow chart illustrating relevant aspects of a method employing one embodiment of the present disclosure.

[0011] Figure 5 is a flow chart illustrating relevant aspects of a method employing one embodiment of the present disclosure.

[0012] Fig. 6A is a flow chart illustrating relevant aspects of a method employing one embodiment of the present disclosure.

[0013] Figure 6B and Figure 6C Collectively, flow charts illustrating relevant aspects of a method employing one embodiment of the present disclosure are shown.

[0014] Figure 7 is a block diagram showing a system of USB devices. DETAILED DESCRIPTION

[0015] The following description sets forth numerous specific details, such as examples of specific systems, components, methods, etc., in order to provide a good understanding of various implementations of the techniques described herein for bidirectional communication between a primary side controller and a secondary side controller in a flyback converter.

[0016] However, it will be apparent to those skilled in the art that at least some embodiments may be practiced without these specific details. In other instances, in order to avoid unnecessarily obscuring the techniques described herein, known components, elements, or methods are presented in simple block diagram format without being described in detail. Therefore, the specific details set forth below are merely exemplary. Specific implementations may differ from these exemplary details and are still considered to be within the spirit and scope of the present invention.

[0017] References in the description to "an embodiment," "one embodiment," "example embodiment," "some embodiments," and "various embodiments" mean that a particular feature, structure, step, operation, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. In addition, the phrases "an embodiment," "one embodiment," "example embodiment," "some embodiments," and "various embodiments" appearing in various places in the description do not necessarily all refer to the same embodiment.

[0018] The description includes references to the accompanying drawings, which form a part of the specific embodiments. The accompanying drawings show diagrams according to exemplary embodiments. These embodiments, which may also be referred to as "examples" herein, are described in sufficient detail to enable those skilled in the art to practice the embodiments of the claimed subject matter described herein. The embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable those skilled in the art to practice, manufacture, and / or use the subject matter.

[0019] Various embodiments of techniques for bidirectional communication between a primary-side controller and a secondary-side controller in a flyback converter for use in an electronic device that can transfer power in accordance with the USB Power Delivery (USB-PD) specification are described herein. Examples of such electronic devices include, but are not limited to, personal computers (e.g., laptop computers, notebook computers, etc.), mobile computing devices (e.g., tablets, tablet computers, e-reader devices, etc.), mobile communication devices (e.g., smart phones, cell phones, personal digital assistants, messaging devices, handheld personal computers, etc.), connection and charging devices (e.g., hubs, docking stations, adapters, chargers, etc.), audio / video / data recording and / or playback devices (e.g., cameras, recorders, handheld scanners, monitors, etc.), and other similar electronic devices that can use a USB connector (interface) for communication, battery charging, and / or power transfer. The embodiments described herein can be used for AC to DC power adapters, GaN-based power adapters operating at 600kHz frequencies, power adapters with primary-side controllers or secondary-side controllers, power adapters operating in operating modes such as quasi-resonant mode (QR), discontinuous conduction mode (DCM), continuous conduction mode (CCM), etc. The embodiments described herein can be used in power adapter solutions together with USB Type-CPD capabilities. These embodiments allow for more efficient performance, enabling the use of lower-rated and thus cheaper FETs by engaging active clamp field effect transistors (FETs) on the primary side by a secondary-side controller that determines to turn the active clamp FET on / off based on parameters determined or detected on the secondary side. The active clamp circuit can also help reduce electromagnetic interference (EMI), which helps reduce filters on the input end.

[0020] The electronic device or system that USB enables can comply with at least one version of the USB specification. Examples of such USB specifications include, but are not limited to, USB specification revision 2.0, USB 3.0 specifications, USB 3.1 specifications and / or various supplements thereof (e.g., such as supplementary versions USB On-The-Go or USB OTG), versions and errata. The USB specification generally defines the features (e.g., attributes, protocol definitions, transaction types, bus management, programming interfaces, etc.) of the differential serial bus required for designing and building standard communication systems and peripheral devices. For example, the peripheral device that USB enables is attached to the host device through the USB port of the host device that USB enables to form a system that USB enables. The USB 2.0 port includes a 5V power supply voltage line (denoted as VBUS), a differential pair of data lines (denoted as D+ or DP and D- or DN) and a ground line (denoted as GND) for power return. The USB 3.0 port also provides a VBUS line, a D+ line, a D- line and a GND line for backward compatibility with USB 2.0. In addition, to support a faster differential bus (USB SuperSpeed ​​bus), the USB 3.0 port also provides a differential pair of transmitter data lines (denoted as SSTX+ and SSTX-), a differential pair of receiver data lines (denoted as SSRX+ and SSRX-), a power line for power supply (denoted as DPWR), and a ground line for power return (denoted as DGND). The USB 3.1 port provides the same lines as those of the USB 3.0 port to be backward compatible with USB 2.0 communication and USB 3.0 communication. However, it extends the performance of the SuperSpeed ​​bus through a series of features called Enhanced SuperSpeed.

[0021] The latest technology for USB connectors, referred to as USB Type-C (also referred to as USB-C), is defined in various releases and / or versions (e.g., such as release 1.0, release 1.1, etc.) of the USB Type-C specification. The USB Type-C specification defines a Type-C receptacle, a Type-C plug, and a Type-C cable, which may support power transmission and USB communication through the newer USB power transmission protocol defined in various revisions / versions of the USB-PD specification. Examples of USB Type-C functions and requirements may include, but are not limited to, data and other communications according to USB2.0 and USB 3.0 / USB 3.1 / USB 3.2, electromechanical definitions and performance requirements for Type-C cables, electromechanical definitions and performance requirements for Type-C receptacles, electromechanical definitions and performance requirements for Type-C plugs, requirements for Type-C on traditional cable assemblies and adapters, requirements for Type-C-based device detection and interface configuration, requirements for optimizing power transmission of Type-C connectors (also referred to as USB-C connectors), and the like. According to the USB Type-C specification, the Type-C port provides VBUS line, D+ line, D- line, GND line, SSTX+ line, SSTX- line, SSRX+ line and SSRX- line, etc. In addition, the Type-C port also provides a sideband use (denoted as SBU) line for signaling of sideband functions and a configuration channel (denoted as CC) line for discovering, configuring and managing connections on the Type-C cable. The Type-C port can be associated with a Type-C plug and / or a Type-C socket. The Type-C plug and Type-C socket are designed as a reversible pair that can operate regardless of the orientation of the plug to the socket for ease of use. Therefore, a standard USB Type-C connector set as a standard Type-C plug or socket provides pins for the following lines: four VBUS lines, four ground return (GND) lines, two D+ lines (DP1 and DP2), two D- lines (DN1 and DN2), two SSTX+ lines (SSTXP1 and SSTXP2), two SSTX- lines (SSTXN1 and SSTXN2), two SSRX+ lines (SSRXP1 and SSRXP2), two SSRX- lines (SSRXN1 and SSRXN2), two CC lines (CC1 and CC2), and two SBU lines (SBU1 and SBU2), etc.

[0022] Some USB-enabled electronic devices may comply with a specific revision and / or version of the USB-PD specification (e.g., such as revision 1.0, revision 2.0, etc., or subsequent revisions / versions thereof). The USB-PD specification defines a standard protocol designed to maximize the functionality of USB-enabled devices by providing more flexible power delivery and data communication over a single USB Type-C cable through a USB Type-C port. The USB-PD specification also describes the architecture, protocols, power delivery behaviors, parameters, and cables necessary to manage power delivery over a USB Type-C cable at up to 100W (or even higher in the case of an extended power range EPR implementation). According to the USB-PD specification, a device with a USB Type-C port (e.g., a USB-enabled device) can negotiate more current and / or higher or lower voltages over a USB Type-C cable than allowed in older USB specifications (e.g., USB 2.0 specification, USB 3.1 specification, USB Battery Charging Specification Revision 1.1 / 1.2, etc.). For example, the USB-PD specification defines requirements for a power delivery contract (PD contract) that can be negotiated between a pair of USB-enabled devices. The PD contract can specify both the power levels and the direction of power delivery that both devices can accommodate, and can be dynamically renegotiated upon request by either device and / or in response to various events and conditions such as power role swaps, data role swaps, hard resets, power failures, etc. (e.g., without unplugging the devices).

[0023] A flyback converter (e.g., such as a USB-PD adapter) can convert AC power to DC power, or convert DC power to DC power. The present disclosure will be made with reference to a flyback converter that converts AC power to DC power, but it should be understood that the present disclosure should not be limited thereto.

[0024] The flyback converter is a simple and widely used topology for isolated AC / DC power conversion. It uses a coupled inductor to transfer energy between the input and the output. The coupled inductor consists of a transformer, an inherent magnetizing inductance connected in parallel with the primary winding of the transformer, and an inherent leakage inductance connected in series with the parallel combination of the magnetizing inductance and the primary winding.

[0025] The flyback converter switches between charging and discharging in each operating cycle. During the charging portion of the switching cycle, energy is stored in the form of a magnetic field in the magnetic inductance of the coupled inductor and the leakage inductance of the coupled inductor. During the discharge portion, the magnetic field decays and the energy in the magnetic inductance is transferred to the output through the transformer.

[0026] The active clamp (AC) flyback converter is an enhanced version of the traditional flyback converter and is designed to improve efficiency and reduce stress on the converter components. AC flyback converters are typically used to convert power in the low to medium power range (approximately 2W to 100W). In general, AC flyback converters are widely used in various applications, such as power supplies for electronic devices, battery chargers, and other low to medium power applications that require voltage conversion.

[0027] The AC flyback converter transfers the energy stored in the leakage inductance, which would traditionally be dissipated in a passive clamp snubber resistor during the discharge portion of the switching cycle. The present disclosure will be made with respect to an AC flyback converter, it being understood that the non-active clamping aspects of the present disclosure may be applied to conventional flyback converters.

[0028] The AC flyback converter includes an active clamp circuit that provides a path to the output of the AC flyback converter for the energy stored in the leakage inductance of the coupled inductor. The active clamp circuit generally includes a clamp capacitor and a clamp switch. For the purpose of illustration only, the switch of the present disclosure will take the form of a MOSFET, and it should be understood that the term switch should not be limited thereto.

[0029] The switching cycle of an AC flyback converter has three parts; a charging part, a discharging part, and an ACF part. The charging part of both the conventional flyback converter and the AC flyback converter is essentially the same. In both, energy is stored in the form of a magnetic field in the magnetic inductance and the leakage inductance. The discharging part of the switching cycle in the AC flyback converter and the conventional flyback converter has similarities. In both, the magnetic field in the leakage inductance and the magnetic inductance decays, and the energy in the magnetic field of the magnetic inductance is transferred to the secondary side of the ideal transformer. However, during the discharging part in the AC flyback converter, the energy from the decaying field in the leakage inductance is transferred to the clamping capacitor via the forward biased diode of the clamping MOSFET and stored in the clamping capacitor.

[0030] As described, the AC flyback converter includes an active clamp portion in its switching cycle. During the active clamp portion, the energy stored in the clamp capacitor is transferred to the secondary side of the ideal transformer through the activated clamp MOSFET, rather than being dissipated as heat through the snubber circuit.

[0031] A primary side controlled converter and a secondary side controlled converter are two different methods for controlling the operation of a conventional flyback converter and an AC flyback converter. In both types, the primary side typically includes an input rectifier, a clamping MOSFET, a primary MOSFET, and a primary side controller (PSC), while the secondary side includes a secondary MOSFET, an output capacitor, and a secondary side controller (SSC). The main difference between a primary side controlled converter and a secondary side controlled converter relates to whether the PSC or the SSC controls the converter operation. In a secondary side controlled flyback converter, the SSC is responsible for controlling the operation of the flyback converter, while the PSC plays a secondary role. The present disclosure will be made with reference to a secondary side controlled flyback converter and an AC flyback converter, it should be understood that the present disclosure should not be limited thereto.

[0032] Most secondary-side controlled AC flyback converters (and conventional secondary-side controlled flyback converters) are flawed. To illustrate, Figure 1 An example secondary-side controlled USB-PD AC flyback converter 100 with an active clamp circuit is shown. The power output of the USB-PD AC flyback converter 100 is connected to a USB-C connector.

[0033] The USB-PD AC flyback converter 100 includes a conductive inductor, which is represented as an ideal transformer 102 having a primary winding and a secondary winding, an inherent magnetic inductance 103, and an inherent leakage inductance 104. The inherent magnetic inductance and leakage inductance are artifacts of the conductive inductor and are represented by dashed lines in the figure. A diode rectifier 105 is coupled between the transformer 102 and a power input terminal for receiving AC input power. The bridge rectifier 105 converts the AC input voltage into a rectified input voltage provided to the transformer 102.

[0034] The primary side of the USB-PD AC flyback converter 100 includes a PSC 106, a primary MOSFET 112, and an active clamp (AC) circuit including a clamp MOSFET 110 and a clamp capacitor CP. The PSC 106 controls the clamp MOSFET 110 and the primary MOSFET 112 based on control signals received from a secondary side controller 114, as will be described more fully below.

[0035] The secondary side of the USB-PD AC flyback converter 100 includes a secondary capacitor CS and an SSC 114 that controls a secondary-side MOSFET 116. The SSC 114 indirectly controls the clamp MOSFET 110 and the primary MOSFET 112 through the PSC 106. The pulse transformer 120 transfers the control signal from the SSC 114 to the PSC 106 to control the MOSFETs 110 and 112. As a secondary-side controlled converter, the USB-PD AC flyback converter 200 is not configured to transfer the signal from the PSC 106 to the SSC 114 through the pulse transformer 120.

[0036] The SSC 114 includes an SSC logic circuit 122 and a signal transmitter 124. The PSC 106 includes a PSC logic circuit 128 and a receiver 126 that receive control signals from the SSC logic circuit 122 via the pulse transformer 120.

[0037] The SSC logic circuit 122 may generate signals that control secondary side components such as the secondary MOSFET 116. The SSC logic circuit 122 may also generate control signals that are sent to the PSC 106 via the transmitter 124 and the pulse transmitter 120. In response to receiving the control signal, the PSC logic circuit 128 may activate or deactivate the MOSFET 110 or 112. For example, in response to receiving a first control signal from the SSC logic circuit 122 via the pulse transformer 120, the PSC logic circuit 128 may activate the primary MOSFET 112 at the beginning of the charging portion of the switching cycle. The USB-PD AC flyback converter 100 should be operated so that the primary MOSFET 112 and the secondary MOSFET 116 are not activated at the same time. Therefore, when the SSC logic circuit 122 sends the first control signal for activating the primary MOSFET 112 to the PSC logic circuit 128, the SSC logic circuit 122 should deactivate the secondary MOSFET 116. After the primary MOSFET 112 is activated, the current energizes the magnetic inductance 103 and the leakage inductance 104. After a predetermined amount of time, the discharge portion of the switching cycle begins. More specifically, the SSC logic circuit 122 generates a second control signal for deactivating the primary MOSFET 112 and sends it to the PSC logic circuit 128. The SSC logic circuit 122 should also activate the secondary MOSFET 116 when it sends the second control signal. In response to receiving the second control signal, the PSC logic circuit 128 deactivates the primary MOSFET 112. When deactivated, the magnetic field in the magnetic inductance 103 decays and energy is transferred to the secondary winding. The magnetic field in the leakage inductance 104 also decays, thereby sending current to charge the active clamp capacitor CP via the forward biased body diode of the clamp MOSFET 110. After a predetermined amount of time, the discharge portion of the switching cycle ends and the ACF portion begins. More specifically, while the secondary MOSFET 116 remains in an activated state, the SSC logic circuit 122 sends a third control signal for activating the clamp MOSFET 110. In response to receiving the third control signal via the pulse transformer 120, the PSC logic circuit 128 activates the clamping MOSFET 110 to allow the clamping capacitor CP to discharge through the primary winding, thereby transferring energy to the secondary winding. Finally, the SSC logic circuit 122 sends a fourth control signal to the PSC logic circuit 128 to deactivate the clamping MOSFET 110 and end the ACF section. With the clamping MOSFET 110 deactivated, the current drawn by the primary winding of the transformer 102 can discharge the parasitic capacitance between the drain d and the source s of the primary MOSFET 112 to zero voltage or near zero voltage.Discharging the parasitic capacitance enables zero or near zero volt activation of the primary MOSFET 112 in the next switching cycle of the USB-PD AC flyback converter 100, which reduces the switching losses that would otherwise occur in the primary MOSFET 112. However, the effectiveness of discharging the parasitic capacitance depends on the time when the clamping MOSFET 110 is activated. After the PSC logic circuit 128 deactivates the MOSFET 110, the switching cycle repeats, with the SSC logic again sending the first control signal. Importantly, the primary MOSFET 112 and the secondary MOSFET 116 should not be activated at the same time.

[0038] Figure 1 The pulse transformer 120 in the embodiment is used for unidirectional signal transmission from the SSC logic circuit 122 to the PSC logic circuit 128 as described above. The PSC logic circuit 128 does not send a signal to the logic circuit 122. Therefore, the PSC logic circuit 128 cannot send a signal confirming that it has received a control signal for activating or deactivating the clamping MOSFET 110 or the primary MOSFET 112. Likewise, the PSC logic circuit 128 cannot send a signal confirming that the clamping MOSFET 110 or the primary MOSFET 112 has been activated or deactivated. If the PSC logic circuit 128 receives all control signals from the SSC logic circuit 122 as described above, and if the PSC logic circuit 128 does not receive an erroneous control signal, the USB-PD AC flyback converter 100 works well. However, if the PSC logic circuit 128 does not receive a control signal sent by the SSC logic circuit 122, or if the PSC logic circuit 128 receives an erroneous control signal, the USB-PD AC flyback converter 100 may be placed in a state in which both the primary MOSFET 112 and the secondary MOSFET 116 are activated at the same time. For example, the receiver 126 may receive an erroneous control signal from the pulse transformer 120 caused by, for example, a nearby ESD event. Unfortunately, the erroneous control signal may cause the PSC logic circuit 128 to activate the primary MOSFET 112 when the secondary MOSFET 116 is activated. The lack of bidirectional communication in the USB-PD AC flyback converter 100 also complicates the active clamp flyback mode. If the PSC logic circuit 128 misses the third control signal or the fourth control signal mentioned above, the cycle becomes chaotic. In addition, the SSC logic circuit 122 cannot receive information about the voltage at the drain d of the primary MOSFET 110, which can be used to adjust the timing of when the next switching cycle should start by the SSC logic circuit 122 to achieve true zero-volt switching of the MOSFET 110. The USB-PD AC flyback converter 100 may also have other defects.

[0039] A novel duplex communication scheme is proposed in which the PSC and the SSC communicate with each other bidirectionally in a secondary-side controlled USB-PD flyback converter to make it more reliable and efficient. As described above, in an existing flyback converter or an existing conventional flyback converter, the SSC generally does not know whether the PSC has received a control signal. To avoid this situation, the PSC of the present disclosure includes a confirmation generator that can be used to send confirmations and other signals to the SSC. For example, whenever the PSC successfully receives a control signal from the SSC for activating or deactivating a primary MOSFET or a clamping MOSFET, the PSC can send a high voltage pulse signal or a low voltage pulse signal to the SSC as a confirmation. In one embodiment of the present disclosure, a receiver is added to the SSC to detect confirmations and other signals from the PSC. The SSC can use the confirmations and other signals it receives through the receiver to prepare for its next action. Other advantages of the present disclosure are described below.

[0040] Figure 2 A USB-PD AC flyback converter 200 with secondary side control using bidirectional communication according to one embodiment of the present disclosure is shown. The USB-PD AC flyback converter 200 includes Figure 1 Many of the components of the USB-PD AC flyback converter 100 shown are the same as those of the components of the USB-PD AC flyback converter 100. For example, the USB-PD AC flyback converter 200 includes a bridge rectifier 105 connected to a coupled inductor, which includes a transformer 102, an inherent magnetic inductance 103, and an inherent leakage inductance. The primary side includes a PSC 202, a primary MOSFET 112 (also referred to as a low-side FET), and an active clamp circuit, which in turn includes a clamp MOSFET 110 (also referred to as a high-side FET) and a clamp capacitor CP. The PSC 202 controls the clamp MOSFET 110 and the primary MOSFET 112 based on a control signal received from the SSC 204, as will be described more fully below. The term control signal is widely used to include a single signal or multiple signals. The control signal can take many different forms. For example, the signal can be a high voltage pulse signal or a low voltage pulse signal. The signal can take the form of a leading edge or a falling edge of a pulse. The signal may take the form of a ramp signal in which the signal voltage rises from a low value at a linear rate until it reaches a maximum value at which the signal immediately drops to a low voltage value. The control signal may include two or more signals of different forms. For example, the control signal may include two high voltage pulses followed by a low voltage pulse. Or the control signal may include a high voltage pulse followed by a ramp pulse. The term control signal shall not be limited to any number, combination or form of signals.

[0041] The secondary side of the USB-PD AC flyback converter 200 includes a secondary capacitor CS, a resistor RS, and an SSC 204, which controls the secondary side MOSFET 116 and indirectly controls the clamp MOSFET 110 and the primary MOSFET 112 via the PSC 202. The SSC monitors the voltage at the drain d of the secondary MOSFET 116 through the resistor RS. The USB-PD AC flyback converter 200 includes a pulse transformer 120 for sending signals back and forth between the PSC 202 and the SSC 204 in both directions.

[0042] The PSC 202 includes a PSC logic circuit 206 that controls the gates of the MOSFETs 110 and 112. The PSC logic circuit 206 may include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software, firmware, or a combination thereof. The PSC logic circuit 206 may measure the voltage between the drain and source of the primary MOSFET 112 via a resistor RP. The PSC logic circuit 206 also controls a signal generator, which in turn includes gate drivers 212 and 214 and switches 220 and 222 (e.g., MOSFETs). The PSC logic circuit controls the gate drivers 212 and 214, which in turn control the gates of switches 220 and 222, which are connected in series between the power supply voltage Vcc and the primary side ground. As will be described more fully below, a signal generator including a combination of gate drivers 212 and 214 and switches 212 and 222 enables the PSC logic circuit 206 to send a high voltage signal and / or a low voltage signal to the SSC 204 via the pulse transformer 120. The PSC 202 also includes a receiver 210 in data communication with the pulse transformer 120. The receiver 210 is configured to receive a control signal from the SSC 204 via the pulse transformer 120. An output of the receiver 210 is connected to an input of the PSC logic circuit 206. As will be described more fully below, the PSC logic circuit 206 controls the clamp MOSFET 110 and the primary MOSFET 112 based on the control signal it receives from the SSC 204 via the receiver 210.

[0043] The SSC 204 includes an SSC logic circuit 208 that communicates data with a receiver circuit 230 and a transmitter circuit 124, each of which communicates data with the PSC 202 via the pulse transformer 120. The SSC logic circuit 208 may include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software, firmware, or a combination thereof. The receiver 230 is configured to receive and forward signals (e.g., high voltage pulse signals and / or low voltage pulse signals) received from the PSC 202 via the pulse transformer 120. The SSC logic circuit 208 implements various methods in response to receiving these signals, as will be described more fully below. The transmitter 124 sends control signals to the receiver 210 via the pulse transformer 120. The PSC logic circuit 206 responds to these control signals, as will be described more fully below.

[0044] The SSC logic circuit 208 and the PSC logic circuit 206 communicate bidirectionally with each other to achieve safer and more efficient operation of the USB-PD AC flyback converter 200. Figure 2 , Figure 3 FIG. 2 shows the general aspects of bidirectional communication between the SSC logic circuit 208 and the PSC logic circuit 206 according to one embodiment of the present disclosure. As shown in step 302, when the SSC logic circuit 208 generates a control signal Figure 3 The method in step 306 begins. For example, the SSC logic circuit 208 can generate a control signal for activating or deactivating the clamping MOSFET 110 or the primary MOSFET 112. The control signal is sent to the PSC logic circuit 206 via the pulse transformer 120. In step 306, the PSC logic circuit 206 responds to the control signal. For example, in response to the PSC logic circuit 206 receiving the control signal sent by the SSC logic circuit 206 via the pulse transformer 120, the PSC logic circuit 206 activates or deactivates the primary MOSFET 112 or the clamping MOSFET 110. In step 310, the PSC logic circuit 206 generates a high voltage confirmation signal or a low voltage confirmation signal in response to the PSC logic circuit 206 receiving the control signal. For example, the confirmation signal can be generated before, after, or at the same time as the PSC logic circuit 206 activates or deactivates the primary MOSFET 112 or the clamping MOSFET 110. In step 312, the PSC logic circuit 206 sends a confirmation signal to the SSC logic circuit 208 via the pulse transformer 120.

[0045] As mentioned above Figure 1As described in the USB-PD AC flyback converter 100 of FIG. 1 , there is a significant reliability issue during operation of the USB-PD AC flyback converter 100. When the secondary MOSFET 116 is active and conducting current to the load, a system ESD event may cause the PSC logic circuit 206 to erroneously activate the primary MOSFET 112. If this happens, a short circuit may result, which will damage the converter. The duplex communication system using the present disclosure can solve this problem. Figure 2 , PSC logic circuit 206 may send a confirmation signal to SSC logic circuit 208 before, simultaneously with, or shortly after activating primary MOSFET 112, regardless of whether PSC logic circuit activates primary MOSFET 112 in response to receiving a corresponding control signal from SSC logic circuit 208. If SSC logic circuit 208 receives a confirmation signal that PSC logic circuit 206 activated primary MOSFET 112, SSC logic circuit 208 may quickly deactivate secondary MOSFET 116 and (optionally) send a control signal for deactivating primary MOSFET 112, thereby protecting the converter. Figure 4 An example method performed by the PSC logic circuit 206 and the SSC logic circuit 208 to implement a solution to the hazards caused by an ESD event is shown. When the SSC logic circuit 208 begins the charging portion of the switching cycle and activates the secondary MOSFET 116 as shown in step 402, Figure 4The process shown begins. The SSC logic circuit 208 starts a timer. The SSC logic circuit 208 then generates and sends a control signal for deactivating the primary MOSFET 112. The signal is sent to the PSC 206 via the pulse transformer 120. If the SSC logic circuit does not receive a separate confirmation signal from the PSC logic circuit 206 before the timer expires that the PSC logic circuit 206 has received the control signal sent in step 406 and that the PSC logic circuit 206 has deactivated the primary MOSFET 112, then the SSC logic circuit 208 deactivates the secondary MOSFET 116 in step 414 to prevent damage to the converter. If the SSC logic circuit 208 receives a separate confirmation signal in step 410, the SSC logic circuit 208 begins the process in step 412, in which the SSC logic circuit 208 monitors the signal from the PSC control logic 206 that it has activated the primary MOSFET 112 while the secondary MOSFET 116 remains activated. If this occurs, an ESD event is presumed, and the SSC logic circuit 208 deactivates the secondary MOSFET 116, as shown in step 414. The loop implemented by the SSC logic circuits 208 and 412 ensures safe and reliable operation of the AC flyback converter 200.

[0046] The USB-PD AC flyback converters 100 and 200 can provide output power to the device in accordance with USB-PD requirements. For example, the USB-PD AC flyback converters 100 and 200 provide output power to a USB-C connector, which requires the output power to be within + / - 5% of the specification. If the PSC logic circuit 128 in the converter 100 misses the control signal from the SSC logic circuit 208 to activate the primary MOSFET 112, then no power will be transferred to the output during that switching cycle, and the output will begin to drop and fail to meet the specification requirements. Utilizing the improved communications provided by the present disclosure, if the PSC logic circuit 206 misses the control signal to activate the primary MOSFET 112, the SSC logic circuit 208 will wait a predefined amount of time and resend the same control signal. Continue to refer to Figure 2 , Figure 5 FIG. 2 shows an example process implemented by the SSC logic circuit 208 for reissuing the control signal for activating the primary MOSFET 112 according to an embodiment of the present disclosure. When the SSC logic circuit 208 deactivates the secondary MOSFET 116 at the beginning of the charging cycle of the AC flyback converter 200, Figure 5The process shown in FIG. 5 begins with step 502. In step 504, SSC logic circuit 208 starts a timer. In step 506, SSC control logic 208 generates a control signal for activating primary MOSFET 112 and sends it to PSC control logic 206. Then in step 510, SSC logic circuit 208 begins a process of monitoring for a separate confirmation signal from PSC logic circuit 206 indicating that PSC logic circuit 206 received the control signal sent in step 506 and that PSC logic circuit 206 activated primary MOSFET 112. If SSC logic circuit 208 does not receive two confirmation signals from PSC logic circuit 206 before the timer expires, SSC logic circuit 208 resends the signal for activating primary MOSFET 112.

[0047] In a secondary-side controlled USB-PD AC-DC converter, the SSC controls both the clamping MOSFET and the primary MOSFET via the PSC. The present disclosure implements multi-level communication to control the clamping MOSFET and the primary MOSFET. The SSC logic circuit 208 can send a low voltage control signal or a high voltage control signal during a switching cycle. In one embodiment, the SSC logic circuit 208 can send a single low voltage control signal followed by a single high voltage control signal to control the primary MOSFET 112, or the SSC logic circuit 208 can send two low voltage control signals followed by a single high voltage signal to control the clamping MOSFET 110. Fig. 6AAn example multi-level communication process for controlling the clamp MOSFET 110 and the primary MOSFET 112 is shown. The process is implemented at any point in the switching cycle of the converter 200. In step 602, the PSC logic circuit 206 receives a high voltage control signal or a low voltage control signal from the SSC control logic 208 via the pulse transformer 120. The PSC logic circuit 206 determines whether the control signal received in step 602 is a high voltage control signal or a low voltage control signal, as shown in step 604. If it is a high voltage control signal, the PSC logic circuit 206 infers that the charging portion of the switching cycle begins. In step 606, the PSC control logic 206 generates a high voltage confirmation signal by quickly opening and closing the switch 220. The confirmation signal is sent to the SSC logic circuit 208 through the pulse transformer 120. In step 610, the PSC logic circuit 206 activates the primary MOSFET 112. Although not shown, the PSC logic circuit 206 can send another signal to the SSC logic circuit 208 to confirm the activation of the primary MOSFET 112. However, if the PSC logic circuit 206 receives a low voltage control signal in step 602, the SSC logic circuit 208 may intend to end the charging portion of the switching cycle or start the ACF portion with the low voltage signal. In step 612, the PSC logic circuit 206 determines whether it received a low voltage control signal immediately before the PSC logic circuit 206 received the low voltage control signal at step 602. If not, the PSC logic circuit 206 infers that the low voltage signal is a command to end the charging cycle. In step 614, the PSC logic circuit 206 generates an acknowledgement signal and sends it to the SSC logic circuit 208. Then in step 616, the PSC logic circuit 206 deactivates the primary MOSFET 112, at which point the PSC logic circuit 206 returns to monitoring the next high voltage control signal or low voltage control signal from the SSC logic circuit 208. On the other hand, if the PSC logic circuit 206 determines in step 612 that the low voltage control signal received in step 602 was immediately preceded by a low voltage control signal, the PSC logic circuit 206 infers that the ACF portion of the switching cycle will begin. The process continues to step 620, where the PSC logic circuit 206 monitors the high voltage control signal from the SSC logic circuit 208 via the pulse transformer 120 to begin the ACF portion. When the PSC logic circuit 206 receives the high voltage control signal in step 620, the PSC logic circuit 206 generates an acknowledgement signal and sends it to the SSC logic circuit 208, as shown in step 622. The PSC logic circuit 206 then activates the clamp MOSFET 110 to begin the ACF portion of the switching cycle, as shown in step 624.Then, in step 626, the PSC logic circuit 206 monitors the low voltage control signal from the SSC logic circuit 208 for deactivating the clamping MOSFET 110. Upon receiving the signal, the PSC logic circuit 206 generates an acknowledgement signal and sends the acknowledgement signal to the SSC logic circuit 208 via the pulse transformer 120 in step 630. Finally, the PSC logic circuit 206 deactivates the clamping MOSFET 110, as shown in step 632. The PSC logic circuit 206 is then placed in a state where it is monitoring the next high voltage control signal or low voltage control signal from the SSC logic circuit 208, as shown in step 602.

[0048] Figure 1 Another problem in the ACF mode is that the SSC 114 lacks information about the drain-source voltage on the MOSFET 112. Since the SSC 114 cannot obtain this information, the SSC 114 operates on a predictive / planning basis to decide the best time to deactivate the clamping MOSFET 110 during the ACF mode to achieve zero or near zero voltage between the current terminals of the primary MOSFET 112. The present disclosure solves this problem and provides a PSC that can iteratively send information about the drain-source voltage on the primary MOSFET 112 to the SSC. The SSC can use this information to dynamically increase or decrease the duration that the clamping MOSFET 110 is activated, which in turn affects the switching losses in the primary MOSFET 112.

[0049] Continue to refer to Figure 2 , Figure 6BAn example process is shown according to one embodiment of the present disclosure, in which the PSC control logic 206 can provide drain-source voltage information to the SSC control logic 208, which can use the information to calibrate the time when the clamping MOSFET 110 is activated to achieve zero voltage switching of the primary MOSFET 112. When the PSC logic circuit 206 receives a control signal (e.g., a high voltage control signal) from the SSC logic circuit 208 to activate the clamping MOSFET 110 and start the ACF portion of the switching cycle of the converter 200, the process begins at step 603. In response, the PSC logic circuit 206 activates the clamping MOSFET 110 in step 605 and sends an acknowledgement signal to the SSC logic circuit 208 in step 607 by, for example, quickly closing and opening the switch 220 as shown. The PSC logic circuit 206 then waits to receive a control signal (e.g., a low voltage control signal) from the SSC control logic 208 to deactivate the clamping MOSFET 110, as shown in step 611. Upon receipt, the PSC logic circuit 206 deactivates the clamping MOSFET 110 and sends an acknowledgement signal to the SSC logic circuit 208 in step 615 by, for example, quickly closing and opening the switch 222. After a predetermined delay, the PSC logic circuit 206 measures the voltage between the current terminals of the primary MOSFET 112, as shown in step 617, and determines in step 621 whether the measured voltage is greater than a predetermined negative voltage V- (e.g., -1 volt) and less than a predetermined positive voltage (e.g., +1 volt). Ideally, the source-drain voltage of the primary MOSFET 112 should be as close to zero as possible to minimize switching losses in the MOSFET 112. If the PSC logic circuit 206 determines that the source-drain voltage of the primary MOSFET 112 is greater than V- and less than V+, then the switching losses in the primary MOSFET 112 will be zero or close to zero during the next cycle, and the process returns to step 603 without the SSC logic circuit 208 adjusting the duration that the clamping MOSFET 110 is activated. Otherwise, the PSC logic circuit 206 begins a calibration process 623 through 641 , in which the PSC logic circuit 206 provides information to the SSC logic circuit 208 , which the SSC logic circuit 208 can use to adjust the duration that the clamp MOSFET 110 is activated.

[0050] In a first step 623, the PSC logic circuit 206 monitors the control signal from the SSC logic circuit 208 for activating the clamping MOSFET 110. When the control signal is received, the PSC logic circuit 206 activates the clamping MOSFET 110 in step 625 and sends an acknowledgement signal to the SSC logic circuit 208. Then, shortly after the PSC logic circuit 206 activates the clamping MOSFET 110 and before the PSC logic circuit 206 receives a deactivation control signal from the SSC logic circuit 208 for deactivating the clamping MOSFET 110, the PSC logic circuit 206 deactivates the clamping MOSFET 110 as shown in step 627. The PSC logic circuit 206 determines whether the most recently measured voltage between the current terminals of the primary MOSFET 112 is positive (i.e., greater than a predetermined positive voltage V+) or negative (i.e., less than a negative predetermined voltage V-). If neither is true, the most recently measured voltage is zero or close to zero. When the calibration process of 623 to 641 is started or restarted for the first time after step 621 , the voltage measured in step 617 is regarded as the most recently measured voltage.

[0051] The PSC logic circuit 206 responds in one of three ways depending on the magnitude of the most recently measured voltage. During the first iteration of the calibration process shown in steps 623 to 641, the measured voltage should be greater than the positive predetermined voltage V+ or less than the negative predetermined voltage V-. If it is negative (i.e., less than the negative predetermined voltage V-), the PSC logic circuit 206 generates a low voltage confirmation signal and sends it to the SSC logic circuit 208, and the low voltage confirmation signal should be sent before the PSC logic circuit 206 receives the next control signal from the SSC logic circuit 208 to deactivate the clamping MOSFET 110, as shown in step 633. The low voltage confirmation signal can be generated by closing the switch 222. The SSC logic circuit 208 should recognize that it receives the low voltage confirmation signal from the PSC logic 206 before the SSC logic circuit 208 sends the next control signal to the PSC logic circuit 206 to deactivate the clamping MOSFET 110, and the SSC logic circuit 208 interprets this as an indication that the time when the clamping MOSFET 110 is activated should be reduced by a predetermined amount T in the next cycle. If the PSC logic circuit 206 determines in step 631 that the measured voltage is positive (i.e., greater than the positive predetermined voltage V+), the PSC logic circuit 206 generates and sends a low voltage confirmation signal to the SSC logic circuit 208, and the low voltage confirmation signal should be sent a predetermined amount of time after the PSC logic circuit 206 receives the next control signal for deactivating the clamp MOSFET 110 from the SSC logic circuit 208, as shown in step 635. The SSC logic circuit 208 should recognize that it receives the low voltage confirmation signal from the PSC logic 206 with a delay after the SSC logic circuit 208 sends the deactivation control signal to the PSC logic circuit 206, and the SSC logic circuit 208 interprets this delay as an indication that the time when the clamp MOSFET 110 is activated should be increased by T in the next cycle. Depending on whether the SSC logic circuit 208 receives the low voltage confirmation signal sent in step 633 or step 635, the SSC logic circuit 208 increases or decreases the time between sending the clamp activation signal and the clamp deactivation signal in the next cycle. In step 637, a predetermined amount of time after PSC logic circuit 206 deactivates clamp MOSFET 110 in step 627, PSC logic circuit 206 remeasures the drain-source voltage of primary MOSFET 110, and processing returns to step 623, as shown in FIG. Figure 6CAfter one or more iterations of the calibration process shown in steps 623 to 641, the most recently measured voltage should be zero or close to zero (between V+ and V-). When it is determined in step 631 that the most recently measured voltage across primary MOSFET 112 is zero or close to zero, PSC logic circuit 206 sends a low voltage confirmation signal before PSC logic circuit 206 receives the next control signal from SSC logic circuit 208 to deactivate the clamp MOSFET, as shown in step 641, and the calibration process ends by returning to step 603.

[0052] Figure 7 is a block diagram illustrating a system 700 for a USB device with a secondary controlled AC flyback circuit for use in USB power delivery according to some embodiments. The system 700 may include a peripheral subsystem 710, which includes several components for use in USB power delivery (USB-PD). The peripheral subsystem 710 may include a peripheral interconnect 711, which includes a clock module, i.e., a peripheral clock (PCLK) 712, for providing a clock signal to various components of the peripheral subsystem 710. The peripheral interconnect 711 may be a peripheral bus such as a single-stage or multi-stage advanced high-performance bus (AHB), and may provide a data and control interface between the peripheral subsystem 710, the CPU subsystem 730, and the system resources 740. The peripheral interconnect 711 may include a controller circuit such as a direct memory access (DMA) controller, which may be programmed to transfer data between peripheral blocks without input, control, or load of the CPU subsystem 730.

[0053] Peripheral interconnect 711 may be used to couple components of peripheral subsystem 710 to other components of system 700. Coupled to peripheral interconnect 711 may be a plurality of general purpose input / outputs (GPIO) 715 for sending and receiving signals. GPIO 715 may include circuits configured to implement various functions such as pull-ups, pull-downs, input threshold selection, input and output buffer enable / disable, single multiplexing, etc. Still, other functions may be implemented by GPIO 715. One or more timer / counter / pulse width modulators (TCPWM) 717 may also be coupled to the peripheral interconnect and include circuit systems for implementing timing circuits (timers), counters, pulse width modulator (PWM) decoders, and other digital functions that may operate on I / O signals and provide digital signals to system components of system 700. The peripheral subsystem 710 may also include one or more serial communication blocks (SCBs) 719 for implementing serial communication interfaces such as I2C, a serial peripheral interface (SPI), a universal asynchronous receiver / transmitter (UART), a controller area network (CAN), a clock expansion peripheral interface (CXPI), etc.

[0054] In order to implement the bidirectional communication technology by the primary side controller (PSC) or the secondary side controller (SSC) as described in the present disclosure, the peripheral subsystem 710 may include a USB-PD subsystem 720, which is coupled to the peripheral interconnect and includes a set of USB-PD modules 721 for use in USB power transmission. The USB-PD module 721 can be coupled to the peripheral interconnect 711 through a USB-PD interconnect 723. The USB-PD module 721 may include: an analog-to-digital conversion (ADC) module for converting various analog signals into digital signals; an error amplifier (AMP) for adjusting the output voltage on the VBUS line according to the PD contract; a high voltage (HV) regulator for converting the power supply voltage into a precise voltage (such as 3.5V to 5V) to power the system 700; a low-side current sensing amplifier (LSCSA) for accurately measuring the load current; an overvoltage protection module and an overcurrent protection module for providing overcurrent protection (OCP) and overvoltage protection (OVP) on the VBUS line with configurable thresholds and response times; one or more gate drivers for external power field effect transistors (FETs) used in USB power transmission in provider and consumer configurations; and a communication channel PHY (CC BB PHY) module for supporting communication on the Type-C communication channel (CC) line. The USB-PD module 721 may also include: a charger detection module for determining that a charging circuit is present and coupled to the system 700; and a VBUS discharge module for controlling the discharge of the voltage on the VBUS. The discharge control module can be configured to couple to a power node on the VBUS line or to an output (power dissipater) node on the VBUS line and discharge the voltage on the VBUS line to a desired voltage level (i.e., the voltage level negotiated in the PD contract). The USB power transmission subsystem 720 may also include pads 727 for external connections and an electrostatic discharge (ESD) protection circuit system 729 that may be required on the Type-C port. The USB-PD module 721 may also include a communication module for retrieving and transmitting information such as control signals from a secondary side controller to a primary side controller. In one embodiment, the USB-PD module 721 includes an active clamp control module in the secondary side controller to control an active clamp FET set on the primary side (e.g., the primary side of an AC-DC flyback converter).

[0055] GPIO 715, TCPWM 717, and SCB 719 may be coupled to an input / output (I / O) subsystem 750, which may include a high-speed (HS) I / O matrix 751 coupled to a plurality of GPIOs 753. GPIO 715, TCPWM 717, and SCB 719 may be coupled to GPIO 753 via HS I / O matrix 751.

[0056] The system 700 may also include a central processing unit (CPU) subsystem 730 for processing commands, storing program information and data. The CPU subsystem 730 may include one or more processing units 731 for executing instructions and reading and writing memory locations in multiple memories from multiple memories. The processing unit 731 may be a processor suitable for operating in an integrated circuit (IC) or a system on a chip (SOC) device. In some embodiments, the processing unit 731 may be optimized using extended clock gating for low-power operation. In this embodiment, various internal control circuits may be implemented for the operation of the processing unit in various power states. For example, the processing unit 731 may include a wake-up interrupt controller (WIC) configured to wake up the processing unit from a sleep state, thereby allowing power to be turned off when the IC or SOC is in a sleep state. The CPU subsystem 730 may include one or more memories, and the one or more memories include a flash memory 733, a static random access memory (SRAM) 735, and a read-only memory (ROM) 737. Flash memory 733 may be a non-volatile memory (NAND flash memory, NOR flash memory, etc.) configured to store data, programs, and / or other firmware instructions. Flash memory 733 may include a read accelerator and may improve access times by being integrated into CPU subsystem 730. SRAM 735 may be a volatile memory configured to store data and firmware instructions accessible by processing unit 731. ROM 737 may be configured to store startup routines, configuration parameters, and other firmware parameters and settings that do not change during operation of system 700. SRAM 735 and ROM 737 may have associated control circuits. Processing unit 731 and memory may be coupled to system interconnect 739 to route signals to and from various components of CPU subsystem 730 to other blocks or modules of system 700. System interconnect 739 may be implemented as a system bus, such as a single-stage or multi-stage AHB. System interconnect 739 may be configured as an interface to couple various components of CPU subsystem 730 to each other. System interconnect 739 may be coupled to peripheral interconnect 711 to provide signal paths between components of CPU subsystem 730 and components of peripheral subsystem 710 .

[0057] The system 700 may also include a plurality of system resources 740, including a power module 741, a clock module 743, a reset module 745, and a test module 747. The power module 741 may include a sleep control module, a wake-up interrupt control (WIC) module, a power-on reset (POR) module, a plurality of voltage references (REF), and a PWRSYS module. In some embodiments, the power module 741 may include circuits that allow the system 700 to draw power from an external source and / or provide power to an external source at different voltage levels and / or current levels and to support the controller to operate in different power states such as an active state, a low power state, or a sleep state. In various embodiments, more power states may be achieved as the system 700 throttles back into operation to achieve the desired power consumption or output. For example, the secondary side controller may access secondary electrical parameters on the secondary side. At low line and light load, the secondary side controller may determine that the power state is not beneficial for turning on the active clamp FET. The clock module 743 may include a clock control module, a watchdog timer (WDT), an internal low speed oscillator (ILO), and an internal main oscillator (IMO). The reset module 745 may include a reset control module and an external reset (XRES) module. The test module 747 may include a module for controlling and entering a test mode and a test control module for analog and digital functions (digital test and analog DFT).

[0058] The system 700 can be implemented in a monolithic (e.g., single) semiconductor die. In other embodiments, various parts or modules of the system 700 can be implemented on different semiconductor dies. For example, the memory modules of the CPU subsystem 730 can be on-chip or separate. In other embodiments, the separate die circuits can be packaged into a single "chip", or kept separate and provided as separate components on a circuit board (or in a USB cable connector).

[0059] System 700 can be implemented in many application environments to provide USB-PD functions therein. In each application environment, an IC controller or SOC implementing system 700 can be set and configured in an electronic device (e.g., a USB-enabled device) to perform operations according to the techniques described herein. In one example embodiment, system 700 can be set and configured in a personal computer (PC) power adapter for a laptop computer, a notebook computer, etc. In another example embodiment, system 700 can be set and configured in a power adapter (e.g., a wall charger) for a mobile electronic device (e.g., a smart phone, a tablet computer, etc.). In another example embodiment, system 700 can be set and configured in a wall socket configured to be powered by a USB Type-A and / or Type-C port. In yet another example embodiment, system 700 can be set and configured in a power group that can be charged and then powered to another electronic device through a USB Type-A or Type-C port. In other embodiments, a system such as system 700 can be configured with a power switch gate control circuit system described herein, and can be set in various other USB-enabled electronic devices or electromechanical devices.

[0060] In the above description, some parts of the specific embodiment are presented according to the algorithm and symbolic representation of the operation of the data bit in the analog signal and / or digital signal or non-transient storage medium. These algorithmic descriptions and representations are the means by which the technical personnel in the field of data processing are used to convey the essence of their work to other technical personnel in the field most effectively. Here, the algorithm is generally considered to be a self-consistent sequence of the steps leading to the desired result. These steps are the steps required for physical manipulation of physical quantities. Usually, although not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, transferred, combined, compared and otherwise manipulated. It has been proved that it is convenient to refer to these signals as data, bits, values, elements, symbols, characters, items, numbers, etc., mainly for general purposes.

[0061] References in the description to "an embodiment," "one embodiment," "example embodiment," "some embodiments," and "various embodiments" mean that a particular feature, structure, step, operation, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. In addition, the phrases "an embodiment," "one embodiment," "example embodiment," "some embodiments," and "various embodiments" appearing in various places in the description do not necessarily all refer to the same embodiment.

[0062] The description includes reference to the accompanying drawings, which form a part of the detailed description. The accompanying drawings show diagrams according to exemplary embodiments. These embodiments, which may also be referred to as "examples" herein, are described in sufficient detail to enable those skilled in the art to practice the embodiments of the claimed subject matter described herein. The embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable those skilled in the art to practice, manufacture, and / or use the subject matter.

[0063] It should be remembered, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise stated, as will be apparent from the above discussion, it should be understood that throughout the description, discussions utilizing terms such as "execute," "generate," "determine," "place," and the like refer to the actions and processes of an integrated circuit (IC) controller or similar electronic device that manipulate data represented as physical (e.g., electronic) quantities within the controller's registers and memories and convert that data into other data similarly represented as physical quantities within the controller's memories or registers or other such non-transitory storage media of information.

[0064] The words "example" or "exemplary" are used herein to mean serving as an example, instance or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be interpreted as being preferred or advantageous over other aspects or other designs. Rather, the use of the words "example" or "exemplary" is intended to present the concept in a specific manner. As used in this application, the term "or" is intended to mean an inclusive "or", not an exclusive "or". Unless otherwise specified or clear from the context, "X includes A or B" is intended to mean any natural inclusive arrangement. That is, if X includes A; X includes B; or X includes both A and B, "X includes A or B" is satisfied in any of the foregoing cases. In addition, unless otherwise specified or clearly directed to a singular form from the context, the articles "one" and "an" used in this application and the appended claims should generally be interpreted as meaning "one or more". In addition, unless so described, the use of the term "embodiment" or "one embodiment" or "embodiment" or "one embodiment" throughout the text is not intended to mean the same embodiment or embodiment.

[0065] The above description sets forth many specific details, such as examples of specific systems, components, methods, etc., to provide a good understanding of several embodiments of the present disclosure. It should be understood that the above description is intended to be illustrative rather than restrictive. After reading and understanding the above description, many other embodiments will be apparent to those skilled in the art. Therefore, the scope of the present disclosure should be determined with reference to the attached claims together with the full range of equivalents to which these claims are entitled.

Claims

1. A method for a secondary-side controlled Universal Serial Bus Power Delivery (USB-PD) converter, the method comprising: The secondary side controller of the USB-PD converter generates a first control signal; The primary side controller of the USB-PD converter receives the first control signal via the first transformer of the USB-PD converter; In response to the primary-side controller receiving the first control signal via the first transformer, the primary-side controller activates or deactivates a first primary-side switch coupled to a primary winding of a second transformer of the USB-PD converter; In response to the primary side controller receiving the first control signal via the first transformer, the primary side controller generating a first confirmation signal; The secondary-side controller receives the first confirmation signal via the first transformer.

2. The method according to claim 1: in, The first control signal comprises a pulse signal; Wherein, the first confirmation signal includes a pulse signal.

3. The method according to claim 2, further comprising: In response to the primary side controller receiving the first control signal via the first transformer, the primary side controller generates a first signal for activating or deactivating the first primary side switch; In which, in response to the primary-side controller generating the first signal, the primary-side controller generates the first confirmation signal.

4. The method according to claim 1: in, In response to the primary side controller receiving the first control signal via the first transformer, the primary side controller activates the first primary side switch; Wherein, the method further comprises: The secondary side controller generates a second control signal; The primary side controller receives the second control signal via the first transformer; In response to the primary side controller receiving the second control signal via the first transformer, the primary side controller deactivates the first primary side switch; In response to the primary side controller receiving the second control signal via the first transformer, the primary side controller generating a second confirmation signal; The secondary-side controller receives the second confirmation signal via the first transformer.

5. The method according to claim 4: in, The first control signal and the second control signal are respectively a positive voltage pulse signal and a negative voltage pulse signal; The first confirmation signal and the second confirmation signal are respectively a positive voltage pulse signal and a negative voltage pulse signal.

6. The method according to claim 4, further comprising: In response to the secondary-side controller receiving the second confirmation signal via the first transformer, the secondary-side controller activating a secondary-side switch coupled to a secondary winding of the second transformer; The primary side controller activates the first primary side switch if the secondary side switch is activated; In response to the primary side controller activating the first primary side switch when the secondary side switch is activated, the primary side controller generates a third confirmation signal; The secondary-side controller receives the third confirmation signal via the first transformer when the secondary-side switch is activated; In response to the secondary-side controller receiving the third confirmation signal via the first transformer, the secondary-side controller deactivates the secondary-side switch.

7. The method according to claim 1, further comprising: The secondary side controller generates a second control signal; In response to the secondary-side controller not receiving an acknowledgement signal within a predetermined amount of time after the secondary-side controller generates the second control signal, the secondary-side controller generates a third control signal.

8. The method according to claim 5, further comprising: The secondary side controller generates a negative voltage control signal; The primary side controller receives the negative voltage control signal via the first transformer; the secondary side controller generating a positive voltage control signal in response to the secondary side controller receiving a third confirmation signal from the primary side controller via the first transformer within a predetermined amount of time after the secondary side controller generates the negative voltage control signal; The primary side controller receives the positive voltage control signal via the first transformer; In response to the primary side controller receiving the positive voltage control signal via the first transformer, the primary side controller activates a second primary side switch (a high-side clamp FET) coupled to the primary winding; In the event that the secondary side controller does not receive the third confirmation signal from the primary side controller via the first transformer within a predetermined amount of time after the secondary side controller generates the negative voltage control signal, the secondary side controller generates an additional negative voltage control signal.

9. The method according to claim 1, further comprising: include: in, In response to the primary side controller receiving the first control signal via the first transformer, the primary side controller activates the first primary side switch; Wherein, the method further comprises: wherein, in response to the primary side controller receiving a second control signal via the first transformer, the primary side controller deactivates the first primary side switch; The primary side controller measures a voltage between current terminals of the second primary side switch; The primary side controller compares the measured voltage with a predefined voltage range; In response to the primary side controller determining that the measured voltage is not within the predefined voltage range, the secondary side controller adjusts the duration of a time period during which the first primary side switch is activated in a subsequent cycle.

10. A universal serial bus power transmission USB-PD power converter, comprising: Pulse transformer; a secondary-side controller in data communication with the pulse transformer; a primary-side controller in data communication with the pulse transformer; wherein the secondary side controller is configured to generate a control signal; wherein the secondary side controller is configured to receive a confirmation signal from the primary side controller via the pulse transformer; wherein the primary-side controller is configured to generate the confirmation signal; Wherein, the primary side controller is configured to receive the control signal from the secondary side controller via the pulse transformer.

11. The USB-PD power converter according to claim 10, further comprising: A flyback transformer including a primary winding and a secondary winding; a first primary side switch connected to the primary winding and controlled by the primary side controller based on a control signal received by the primary side controller from the secondary side controller via the pulse transformer; A secondary side switch is connected to the secondary winding and is controlled by the secondary side controller based on a confirmation signal received from the primary side controller via the pulse transformer.

12. The USB-PD power converter according to claim 11: in, The primary side controller is configured to receive a first control signal from the secondary side controller via the pulse transformer; wherein the primary side controller is configured to activate or deactivate the first primary side switch in response to the primary side controller receiving the first control signal via the pulse transformer; wherein the primary side controller is configured to generate a first confirmation signal in response to the primary side controller receiving the first control signal via the pulse transformer; Wherein, the secondary side controller is configured to receive the first confirmation signal via the pulse transformer.

13. The USB-PD power converter according to claim 12: in, The first control signal includes one of a positive voltage pulse signal and a negative voltage pulse signal; Wherein, the first confirmation signal includes one of a positive voltage pulse signal and a negative voltage pulse signal.

14. The USB-PD power converter according to claim 12: in, the primary side controller being configured to activate the first primary side switch in response to the primary side controller receiving the first control signal via the pulse transformer; wherein the secondary-side controller is configured to generate a second control signal; wherein the primary side controller is configured to receive the second control signal via the pulse transformer; wherein the primary side controller is configured to deactivate the first primary side switch in response to the primary side controller receiving the second control signal via the pulse transformer; wherein the primary side controller is configured to generate a second confirmation signal in response to the primary side controller receiving the second control signal via the pulse transformer; Wherein, the secondary side controller is configured to receive the second confirmation signal via the pulse transformer.

15. The USB-PD power converter according to claim 14: in, The first control signal and the second control signal are respectively a positive voltage pulse signal and a negative voltage pulse signal; The first confirmation signal and the second confirmation signal are respectively a positive voltage pulse signal and a negative voltage pulse signal.

16. The USB-PD power converter according to claim 14: in, the secondary-side controller being configured to activate a secondary-side switch coupled to a secondary winding of the flyback transformer in response to the secondary-side controller receiving the second confirmation signal via the pulse transformer; wherein the primary side controller is configured to activate the first primary side switch if the secondary side switch is activated; wherein the primary side controller is configured to generate a third confirmation signal in response to the primary side controller activating the first primary side switch when the secondary side switch is activated; wherein the secondary-side controller is configured to receive the third confirmation signal via the pulse transformer when the secondary-side switch is activated; Wherein, the secondary side controller is configured to deactivate the secondary side switch in response to the secondary side controller receiving the third confirmation signal via the pulse transformer.

17. The USB-PD power converter according to claim 12: in, The secondary side controller is configured to generate a second control signal; Wherein, the secondary-side controller is configured to generate a third control signal in response to the secondary-side controller not receiving an acknowledgement signal within a predetermined amount of time after the secondary-side controller generates the second control signal.

18. The USB-PD power converter according to claim 15, further comprising: in, The secondary side controller is configured to generate a negative voltage control signal; wherein the primary side controller is configured to receive the negative voltage control signal via the pulse transformer; wherein the secondary side controller is configured to: generate a positive voltage control signal in response to the secondary side controller receiving a third confirmation signal from the primary side controller via the pulse transformer within a predetermined amount of time after the secondary side controller generates the negative voltage control signal; wherein the primary side controller is configured to receive the positive voltage control signal via the pulse transformer; Wherein, the primary side controller is configured to: activate a second primary side switch coupled to the primary winding in response to the primary side controller receiving the positive voltage control signal via the pulse transformer; Wherein, the secondary side controller is configured to generate another negative voltage control signal when the secondary side controller does not receive the third confirmation signal from the primary side controller via the pulse transformer within a predetermined amount of time after the secondary side controller generates the negative voltage control signal.

19. The USB-PD power converter according to claim 12: in, The primary side controller is configured to: activate the first primary side switch in response to the primary side controller receiving the first control signal via the pulse transformer; wherein the primary side controller is configured to deactivate the first primary side switch in response to the primary side controller receiving a second control signal via the pulse transformer; wherein the primary side controller is configured to measure a voltage between current terminals of the second primary side switch; wherein the primary side controller is configured to compare the measured voltage with a predefined voltage range; Wherein the secondary side controller is configured to adjust the duration of a time period during which the first primary side switch is activated in a subsequent cycle in response to the primary side controller determining that the measured voltage is not within the predefined voltage range.

20. A universal serial bus power transmission USB-PD power adapter, comprising: USB-C port; a flyback transformer coupled to the USB-C port; Pulse transformer; a primary side controller coupled to the pulse transformer and configured to control operation of the flyback transformer; as well as a secondary-side controller coupled to the USB-C port and the pulse transformer, the secondary-side controller being configured to communicate data with the primary-side controller in the USB-PD power adapter via the pulse transformer; wherein the secondary-side controller is configured to generate a control signal for indirectly controlling a switch connected to a primary winding of the flyback transformer; wherein the secondary side controller is configured to receive a confirmation signal from the primary side controller via the pulse transformer; Wherein, the secondary side controller is configured to control a secondary side switch connected to a secondary winding of the flyback transformer based on a confirmation signal received from the primary side controller via the pulse transformer.

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