Driving circuit of high-side switch, high-side switch chip and electronic equipment

Abstract

The invention provides a driving circuit of a high-side switch, a high-side switch chip and electronic equipment, the driving circuit comprises a pulse signal generation circuit and a latch circuit, the input end of the pulse signal generation circuit receives a power failure indication signal of a power supply; the pulse signal generation circuit generates a pulse signal based on the rising edge of the power failure indication signal and transmits the pulse signal to the latch circuit; and the latch circuit is used for receiving the pulse signal and latching a latch signal output by the latch circuit as a high level according to the pulse signal, so that when the power supply is powered on after power failure, the high-side switch is controlled to be switched from a first state to a second state after a preset duration, the first state is a turn-off state, and the second state is a turn-on state. The high-side switch is controlled to be switched on after being delayed for the preset duration, so that the voltage of the power supply is increased to normal voltage, and the condition that the high-side switch MP is switched on and switched off repeatedly is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a high-side switch driving circuit, a high-side switch chip and an electronic device. Background Art

[0002] The high-side switch is also called a high-side switch, which is used to control the on and off of the load current. The high-side switch is based on power semiconductor technology and uses MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) as a switching element.

[0003] The high-side switch chip integrates the drive circuit, protection circuit and MOSFET tube to achieve efficient current control and protection functions. It plays an important role in analog circuits and load drive circuits, especially in automotive applications, industrial lighting and motor control, and can provide high current load control capabilities. Summary of the invention

[0004] The present application provides a high-side switch driving circuit, a high-side switch chip and an electronic device, which reduce the situation where the high-side switch MP is continuously turned on and off due to repeated triggering of VS undervoltage caused by excessive load current.

[0005] In a first aspect, the present application provides a driving circuit for a high-side switch, the driving circuit comprising: a pulse signal generating circuit and a latch circuit, the input end of the pulse signal generating circuit receiving a power failure indication signal of a power supply, the output end of the pulse signal generating circuit being electrically connected to the input end of the latch circuit;

[0006] The pulse signal generating circuit is used to generate a pulse signal based on the rising edge of the power failure indication signal, and transmit the pulse signal to the latch circuit, wherein the pulse signal indicates that the power supply has a power failure;

[0007] The latch circuit is used to receive the pulse signal and latch the latch signal output by itself as a high level according to the pulse signal, so that when the power supply is powered on after power failure, the high-side switch is controlled to switch from the first state to the second state after a preset time, wherein the first state is the off state and the second state is the on state.

[0008] In the embodiment of the present application, when the power supply fails, a pulse signal generating circuit is used to generate a pulse signal that can indicate that the power supply fails, and then the pulse signal is received by the latch circuit, and according to the pulse signal, the latch signal outputted by itself is latched to a high level, so that when the power supply fails and then powers on, the high-side switch is controlled to switch from the first state to the second state after a preset time. By using the pulse signal generating circuit and the latch circuit, when the power supply fails and then powers on, the high-side switch is controlled to be turned on after a delay of a preset time, so that the voltage can be increased to a normal voltage when the power supply fails and then powers on, so that the situation that the high-side switch MP is continuously turned on and off due to repeated triggering of VS undervoltage caused by excessive load current can be reduced.

[0009] In a possible design, the pulse signal generating circuit includes: a rising edge delayer, a first NOT gate, a second NOT gate and a NAND gate;

[0010] The input end of the rising edge delay device is electrically connected to the input end of the pulse signal generating circuit, and the output end of the rising edge delay device is electrically connected to the input end of the first NOT gate;

[0011] The output terminal of the first NOT gate is electrically connected to the second input terminal of the NAND gate;

[0012] The first input terminal of the NAND gate is electrically connected to the input terminal of the pulse signal generating circuit, and the output terminal of the NAND gate is electrically connected to the input terminal of the second NAND gate;

[0013] The output end of the second NOT gate is electrically connected to the output end of the pulse signal generating circuit.

[0014] In a possible design, the latch circuit includes: a first resistor, a second resistor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a current source, a third NOT gate, and a fourth NOT gate;

[0015] The first end of the first resistor is electrically connected to the first end of the second resistor and the high-side switch control signal respectively, and the second end of the first resistor is electrically connected to the first end of the first switch and the control end of the second switch respectively;

[0016] The second end of the second resistor is electrically connected to the control end of the first switch tube, the first end of the second switch tube, the first end of the third switch tube and the control end of the fourth switch tube respectively;

[0017] The second end of the first switch tube, the second end of the second switch tube, the second end of the third switch tube and the second end of the fourth switch tube are all grounded;

[0018] The control end of the third switch tube is electrically connected to the input end of the latch circuit;

[0019] The first end of the fourth switch tube is electrically connected to the output end of the current source and the input end of the third NOT gate respectively;

[0020] The input end of the current source is electrically connected to the system power supply;

[0021] The output end of the third NOT gate is electrically connected to the input end of the fourth NOT gate;

[0022] The output end of the fourth NOT gate is electrically connected to the output end of the latch circuit.

[0023] In a possible design, the delay time of the rising edge delay device is proportional to the duration of the pulse signal.

[0024] In a possible design, the resistance value of the second resistor is smaller than the resistance value of the first resistor, and the tube length ratio of the first switch tube is larger than the tube length ratio of the second switch tube.

[0025] In a possible design, when the high-side switch control signal is controlled to be a high level, the latch signal output by the latch circuit is latched to a high level; when the high-side switch control signal is controlled to switch from a low level to a high level, the latch signal output by the latch circuit is unlocked to a low level.

[0026] In a possible design, the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are all MOS tubes.

[0027] In a second aspect, the present application provides a high-side switch chip, comprising: a driving circuit and a voltage detection circuit as described in the first aspect;

[0028] The input end of the voltage detection circuit is electrically connected to the power supply, and the output end of the voltage detection circuit is electrically connected to the input end of the drive circuit;

[0029] The voltage detection circuit is used to detect the power supply, output a power failure indication signal, and transmit the power failure indication signal to the drive circuit.

[0030] In a possible design, when the voltage value of the power supply is higher than a preset undervoltage threshold, the power-off indication signal is at a low level;

[0031] When the voltage value of the power supply is lower than a preset undervoltage threshold, the power-off indication signal is at a high level.

[0032] In a third aspect, the present application provides an electronic device, comprising: the driving circuit as described in the first aspect, or the high-side switch chip as described in the second aspect.

[0033] The beneficial effects provided in the above-mentioned second aspect and various possible designs of the above-mentioned second aspect can refer to the beneficial effects brought about by the above-mentioned first aspect and various possible implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A simplified working principle diagram of a high-side switch chip provided for related technology;

[0035] Figure 2 A schematic diagram of a driving circuit structure of a high-side switch provided in an embodiment of the present application;

[0036] Figure 3 A timing diagram of a pulse signal generating circuit provided in an embodiment of the present application;

[0037] Figure 4 A circuit diagram of a pulse signal generating circuit provided in an embodiment of the present application;

[0038] Figure 5 A circuit diagram of a latch circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0040] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0041] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0042] See also Figure 1 , Figure 1 A simplified working principle diagram of a high-side switch chip provided in the related art is shown in FIG. Figure 1 As shown, the high-side switch chip may include a VS pin and an IN pin, wherein the VS pin is a power supply and the IN pin is a high-side switch control signal. Under normal circumstances, if the VS power supply is normal, that is, when there is no undervoltage, the IN signal is at a high level, and the protection circuit is not triggered, the high-side switch MP will be in the on state, and VS provides power to the load through the high-side switch MP. It can be understood by those skilled in the art that Figure 1 Only some pins of the high-side switch chip are shown, and the pins of the high-side switch chip that are not related to the present application are not shown.

[0043] When the power supply VS is normally supplied, the high-side switch chip controls the high-side switch control signal IN to make the high-side switch in the on state or the off state. For example, when the VS is normally supplied, IN is at a high level, and the high-side switch MP is in the on state; when the VS is normally supplied, IN is at a low level, and the high-side switch MP is in the off state. When the high-side switch chip is undervoltage in VS, IN is at a high level, and the high-side switch MP is in the off state.

[0044] See also Figure 1 The voltage detection circuit can monitor the voltage value of the power supply VS in real time, and output a power-off indication signal through the comparator inside the voltage detection circuit to indicate whether the power supply VS is under-voltage.

[0045] See also Figure 1In the related art, after the power supply VS is powered off, IN is still at a high level. If the power supply VS is powered on again after being powered off, as the voltage of the power supply VS increases, when the voltage of the power supply VS rises to above the undervoltage threshold, the comparator in the voltage detection circuit will flip, causing the power-off indication signal output by the voltage detection circuit to flip, thereby controlling the high-side switch MP to be in the on state. When the current of the load is too large, the VS voltage may be pulled down to below the undervoltage threshold, thereby controlling the high-side switch MP to be in the off state again. When the VS voltage rises to above the undervoltage threshold again, the high-side switch MP will be in the on state again, and then, due to the excessive current of the load, the VS voltage may be pulled down to below the undervoltage threshold again, thereby controlling the high-side switch MP to be in the off state again. Even if there is a hysteresis voltage on the rising edge or falling edge of the comparator in the voltage detection circuit, if the load current is too large, the VS voltage is not high enough, or there is a large parasitic inductance on the VS power connection line, the phenomenon of the above-mentioned high-side switch MP repeatedly switching between the on state and the off state still exists.

[0046] In the related art, when the high-side switch control signal IN is at a high level, after the power supply VS is powered off and then powered on, the high-side switch MP will be turned on when the voltage of the power supply VS just rises above the undervoltage threshold. If the load current is too large, the VS undervoltage will be repeatedly triggered, causing the high-side switch MP to be continuously turned on and off.

[0047] In order to solve the problem in the related art that the high-side switch MP is constantly turned on and off due to excessive load current, the present application provides a high-side switch driving circuit, a high-side switch chip and an electronic device.

[0048] The driving circuit of the high-side switch may be a chip or a circuit module.

[0049] Among them, the driving circuit of the high-side switch can be integrated in the high-side switch chip.

[0050] In this application, electronic devices may include, but are not limited to: chargers, tablet computers, smart home devices, vehicles, and wearable devices.

[0051] See also Figure 2 , Figure 2 A schematic diagram of a high-side switch driving circuit 1000 provided in this application is shown in FIG. Figure 2 As shown, the driving circuit 1000 may include: a pulse signal generating circuit 100 and a latch circuit 200, the input end of the pulse signal generating circuit 100 receives the power-off indication signal VS_UVLO of the power supply, and the output end of the pulse signal generating circuit 100 is electrically connected to the input end of the latch circuit 200.

[0052] The pulse signal generating circuit 100 is used to generate a pulse signal PULSE based on the rising edge of the power-off indication signal VS_UVLO, and transmit the pulse signal PULSE to the latch circuit, wherein the pulse signal PULSE can indicate that the power supply VS is powered off.

[0053] The latch circuit 200 is used to receive a pulse signal PULSE, and latch its own output latch signal LATCH as a high level according to the pulse signal PULSE, so that when the power supply is powered on after power failure, the high-side switch is controlled to switch from a first state to a second state after a preset time, wherein the first state is an off state and the second state is an on state.

[0054] The power-off indication signal VS_UVLO is the output signal of the voltage detection circuit. When the power-off indication signal VS_UVLO is at a high level, it indicates that the power supply VS is powered off, that is, the power supply VS is undervoltage; when the power-off indication signal VS_UVLO is at a low level, it indicates that the power supply VS is not powered off and the power supply VS is supplying power normally. Normally, when the voltage value of the power supply VS is higher than the undervoltage threshold, the power-off indication signal VS_UVLO is at a low level; when the voltage value of the power supply VS is lower than the undervoltage threshold, the power-off indication signal VS_UVLO is at a high level.

[0055] See also Figure 3 , Figure 3 This is the timing diagram of the pulse signal generating circuit, such as Figure 3 As shown, when the voltage value of VS is lower than the undervoltage threshold ( Figure 3 When the power failure indication signal VS_UVLO is at a high level, the pulse signal generating circuit generates a pulse signal PULSE based on the rising edge of the power failure indication signal VS_UVLO. Since the pulse signal is generated when the power supply VS fails to supply power, the pulse signal PULSE can be used to identify the situation in which the power supply VS fails to supply power. Therefore, the pulse signal can indicate that the power supply VS fails to supply power.

[0056] The latch circuit is a latch circuit, which is used to receive a pulse signal PULSE, and latch the latch signal LATCH output by itself as a high level according to the pulse signal PULSE. LATCH is an identification signal, which can indicate the control signal of the high-side switch when it is latched as a high level. When the power supply is powered on after a power failure, the high-side switch is controlled to switch from the off state to the on state after a preset time period, that is, when the control signal of the high-side switch is latched as a high level after receiving LATCH, when the power supply is powered on after a power failure, the high-side switch is controlled to be turned on after a preset time period. In this application, LATCH is an identification signal, which is only used to indicate the delayed turn-on of the high-side switch, and does not directly control the turn-on or turn-off of the high-side switch. In actual project applications, the control circuit of the high-side switch can control the high-side switch to perform a delayed turn-off action according to the level of the latch signal LATCH.

[0057] Among them, the preset duration can be set according to the needs of the user. In a possible embodiment, the timing can be started when the power supply VS is higher than the undervoltage threshold, and stopped when the power supply VS is equal to the normal voltage, and the time from the undervoltage threshold to the normal voltage is set to the preset duration. The preset duration can ensure that the voltage can be increased to the normal voltage when the power supply is powered on after power failure, so as to reduce the situation where the power supply VS is repeatedly triggered due to excessive load current. Undervoltage, causing the high-side switch MP to be continuously turned on and off.

[0058] In the embodiment of the present application, when the power supply fails, a pulse signal generating circuit is used to generate a pulse signal that can indicate that the power supply fails, and then the pulse signal is received by the latch circuit, and according to the pulse signal, the latch signal outputted by itself is latched as a high level, so that when the power supply fails and then powers on, the high-side switch is controlled to switch from the first state to the second state after a preset time. By using the pulse signal generating circuit and the latch circuit, when the power supply fails and then powers on, the high-side switch is controlled to be turned on after a preset time delay, which can ensure that the voltage can be increased to a normal voltage when the power supply fails and then powers on, so as to reduce the situation that the VS undervoltage is repeatedly triggered due to excessive load current, thereby causing the high-side switch MP to be continuously turned on and off.

[0059] In one possible embodiment, see Figure 4 , Figure 4 is a circuit diagram of a pulse signal generating circuit 100, such as Figure 4 As shown, the pulse signal generating circuit 100 may include: a rising edge delayer F1, a first NOT gate D1, a second NOT gate D2 and a NAND gate U1.

[0060] An input end of the rising edge delay device F1 is electrically connected to an input end of the pulse signal generating circuit 100 , and an output end of the rising edge delay device F1 is electrically connected to an input end of the first NOT gate D1 .

[0061] The output terminal of the first NOT gate D1 is electrically connected to the second input terminal of the NAND gate U1 .

[0062] The first input terminal of the NAND gate U1 is electrically connected to the input terminal of the pulse signal generating circuit 100 , and the output terminal of the NAND gate U1 is electrically connected to the input terminal of the second NAND gate D2 .

[0063] The output end of the second NOT gate D2 is electrically connected to the output end of the pulse signal generating circuit 100 .

[0064] In the examples of this application, see Figure 4 The specific working principle of the pulse signal generating circuit 100 is as follows: when the voltage value of the power supply VS is higher than the undervoltage threshold, the power-off indication signal VS_UVLO is low level, and point A is low level at this time. After the inversion of the first NOT gate D1, point B is high level, and after passing through the NOT gate U1 and the second NOT gate D2, the pulse signal PULSE is a continuous low level; when the voltage value of the power supply VS is lower than the undervoltage threshold, the power-off indication signal VS_UVLO changes from low level to high level, and point A is high level at this time. Due to the existence of the rising edge delay F1, point B still maintains a high level during the delay period, and after passing through the NOT gate U1 and the second NOT gate D2, the pulse signal PULSE is high level, that is, the pulse signal generating circuit outputs a high level pulse signal when the power supply VS is powered off. The timing diagram of the power supply VS, the power-off indication signal VS_UVLO and the pulse signal PULSE in the pulse signal generating circuit can also be found. Figure 3 .

[0065] In a possible embodiment, the delay time of the rising edge delayer is proportional to the duration of the pulse signal. Since the pulse signal PULSE is high only when both point A and point B are high, when the power supply VS is powered off, the high level duration of point B depends on the delay time of the rising edge delayer F1. Therefore, the high level duration of the pulse signal PULSE is proportional to the delay time of the rising edge delayer F1.

[0066] In addition, in actual project applications, there are many ways to implement the rising edge delay F1. It can be implemented through a chip, or through a combination of discrete electronic components to achieve the function of rising edge delay. In a possible embodiment, the delay function is achieved by connecting a resistor and a capacitor in series. This application does not specifically limit the specific circuit structure of the rising edge delay.

[0067] In an embodiment of the present application, a pulse signal generating circuit is used to generate a pulse signal PULSE on the rising edge of the power failure indication signal VS_UVLO when the power supply VS is powered off, thereby providing a trigger signal for the subsequent latch circuit, thereby realizing control of the high-side switch.

[0068] In one possible embodiment, see Figure 5 , Figure 5 is a circuit diagram of a latch circuit 200, such as Figure 5 As shown, the latch circuit 200 may include: a first resistor R1, a second resistor R2, a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a current source I1, a third NOT gate D3 and a fourth NOT gate D4.

[0069] The first end of the first resistor R1 is electrically connected to the first end of the second resistor R2 and the high-side switch control signal IN respectively, and the second end of the first resistor R1 is electrically connected to the first end of the first switch M1 and the control end of the second switch M2 respectively.

[0070] The second end of the second resistor R2 is electrically connected to the control end of the first switch tube M1 , the first end of the second switch tube M2 , the first end of the third switch tube M3 , and the control end of the fourth switch tube M4 , respectively.

[0071] A second end of the first switch tube M1 , a second end of the second switch tube M2 , a second end of the third switch tube M3 , and a second end of the fourth switch tube M4 are all grounded.

[0072] A control end of the third switch tube M3 is electrically connected to an input end of the latch circuit 200 .

[0073] A first end of the fourth switch tube M4 is electrically connected to the output end of the current source I1 and the input end of the third NOT gate D3 respectively.

[0074] An input terminal of the current source I1 is electrically connected to a system power supply VDD.

[0075] The output terminal of the third NOT gate D3 is electrically connected to the input terminal of the fourth NOT gate D4.

[0076] An output terminal of the fourth NOT gate D4 is electrically connected to an output terminal of the latch circuit 200 .

[0077] In a possible embodiment, the resistance value of the second resistor R2 is smaller than the resistance value of the first resistor R1 , and the tube length ratio of the first switch tube M1 is larger than the tube length ratio of the second switch tube M2 .

[0078] In one possible embodiment, see Figure 5The first switch tube M1, the second switch tube M2, the third switch tube M3 and the fourth switch tube M4 are all MOS tubes.

[0079] MOS is the abbreviation of MOSFET, which is Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).

[0080] In the embodiment of the present application, when the first switch tube M1, the second switch tube M2, the third switch tube M3 and the fourth switch tube M4 are all MOS tubes, the control ends of the first switch tube M1, the second switch tube M2, the third switch tube M3 and the fourth switch tube M4 all refer to the gate of the MOS tube, and the first ends of the first switch tube M1, the second switch tube M2, the third switch tube M3 and the fourth switch tube M4 are all the drain or source of the MOS tube. Correspondingly, the second ends of the first switch tube M1, the second switch tube M2, the third switch tube M3 and the fourth switch tube M4 are all the source or drain of the MOS tube.

[0081] In a specific embodiment, see Figure 5 The first switch tube M1, the second switch tube M2, the third switch tube M3 and the fourth switch tube M4 are all N-type MOS tubes.

[0082] In the embodiment of the present application, IN is the high-side switch control signal. VDD is the system power supply, which is used to provide power to the inside of the chip. Figure 5The specific working principle of the latch circuit 200 is as follows: when the high-side switch control signal IN is converted from a low level to a high level, since the resistance value of R2 is smaller than the resistance value of R1, the charging current at the VA point is greater than the charging current at the VB point, and the voltage at the VA point rises faster than the voltage at the VB point; in addition, since the tube length ratio of the first switch tube M1 is greater than the tube length ratio of the second switch tube M2, the pull-down capability of the first switch tube M1 is greater than the pull-down capability of the second switch tube M2. In summary, the first switch tube M1 will be turned on before the second switch tube M2, and the voltage at the VB point will be pulled down to 0V. At this time, the second switch tube M2 will not be turned on, and the voltage at the VA point will be pulled up to the same voltage value as the high-side switch control signal IN, that is, a high level. At this time, the fourth switch tube M4 is in a conducting state, the VC point is connected to the ground at a low level, and the latch signal LATCH outputted from the output end of the latch circuit is a low level. When the voltage value of VS is lower than the under-voltage threshold, the power-off indication signal VS_UVLO changes from a low level to a high level. When the pulse signal PULSE is generated, the pulse signal PULSE is at a high level, the third switch tube M3 is in an on state, the VA point is connected to the ground and is pulled down to a low level, the first switch tube M1 is in an off state, the voltage at the VA point is pulled up, the second switch tube M2 is in an on state, the fourth switch tube M4 is in an off state, and the voltage at the VC point is pulled up. At this time, the latch signal LATCH outputted from the output end of the latch circuit is at a high level.

[0083] LATCH is an identification signal, which can indicate the control signal of the high-side switch when it is latched at a high level. When the power supply is powered on after a power failure, the high-side switch is controlled to switch from the off state to the on state after a preset time. That is, when the control signal of the high-side switch is latched at a high level after receiving LATCH, when the power supply is powered on after a power failure, the high-side switch is controlled to be turned on after a preset time delay. It can be understood that LATCH in the present application is an identification signal, which is only used to indicate the delay of the high-side switch to be turned on, and does not directly control the turning on or off of the high-side switch.

[0084] In the embodiment of the present application, the pulse signal generated by the pulse signal generating circuit is received by the latch circuit, and according to the pulse signal, the latch signal outputted by itself is latched to a high level, so that when the power supply is powered on after power failure, the high-side switch is controlled to switch from the first state to the second state after a preset time. By using the pulse signal generating circuit and the latch circuit, when the power supply is powered on after power failure, the high-side switch is controlled to be turned on after a preset time delay, so as to ensure that the voltage can be increased to a normal voltage when the power supply is powered on after power failure, and reduce the situation that the high-side switch MP is continuously turned on and off due to repeated undervoltage of the power supply VS caused by excessive load current.

[0085] In a possible embodiment, when the high-side switch control signal IN is controlled to be high, the latch signal LATCH output by the latch circuit is latched to a high level; when the high-side switch control signal IN is controlled to be switched from a low level to a high level, the latch signal LATCH output by the latch circuit is unlocked to a low level.

[0086] When the power supply VS is powered normally, the high-side switch control signal IN is controlled to make the high-side switch in the on state or the off state. Under normal working conditions, when the power supply VS is powered normally, the high-side switch control signal IN is at a high level. After the power supply VS is powered off, the high-side switch MP will be in the off state, but at this time, the high-side switch control signal IN is still at a high level. In the process of powering on after the power supply VS is powered off, the high-side switch control signal IN always maintains a high level state, and the VA point is always latched as a low level. At this time, the latch signal LATCH output by the latch circuit is latched as a high level; unless the high-side switch control signal IN is switched from a low level to a high level, the VA point will be unlocked as a high level, and the latch signal LATCH output by the latch circuit will be unlocked as a low level.

[0087] An embodiment of the present application further provides a high-side switch chip, which includes: the above-mentioned drive circuit and a voltage detection circuit.

[0088] An input end of the voltage detection circuit is electrically connected to the power supply VS, and an output end of the voltage detection circuit is electrically connected to an input end of the driving circuit 1000 .

[0089] The voltage detection circuit is used to detect the power supply VS, output a power failure indication signal, and transmit the power failure indication signal to the driving circuit 1000.

[0090] In a possible embodiment, when the voltage value of the power supply is higher than a preset undervoltage threshold, the power-off indication signal is at a low level; when the voltage value of the power supply is lower than the preset undervoltage threshold, the power-off indication signal is at a high level.

[0091] The preset undervoltage threshold is a voltage determination point set by the user to indicate whether the power supply VS is undervoltage. Normally, when the voltage value of the power supply VS is higher than the preset undervoltage threshold, the power supply VS is supplying normally, and the power-off indication signal VS_UVLO is at a low level; when the voltage value of the power supply VS is lower than the preset undervoltage threshold, the power supply VS is undervoltage, and the power-off indication signal VS_UVLO is at a high level.

[0092] An embodiment of the present application further provides an electronic device, which includes: the above-mentioned driving circuit, or the above-mentioned high-side switch chip.

[0093] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A driving circuit for a high side switch, characterized in that: The driving circuit comprises: a pulse signal generating circuit and a latch circuit, wherein an input end of the pulse signal generating circuit receives a power failure indication signal of a power supply, and an output end of the pulse signal generating circuit is electrically connected to an input end of the latch circuit; The pulse signal generating circuit is used to generate a pulse signal based on the rising edge of the power failure indication signal, and transmit the pulse signal to the latch circuit, wherein the pulse signal indicates that the power supply has a power failure; The latch circuit is used to receive the pulse signal and latch the latch signal output by itself as a high level according to the pulse signal, so that when the power supply is powered on after power failure, the high-side switch is controlled to switch from the first state to the second state after a preset time, wherein the first state is the off state and the second state is the on state.

2. The driving circuit according to claim 1, characterized in that: The pulse signal generating circuit comprises: a rising edge delayer, a first NOT gate, a second NOT gate and a NAND gate; The input end of the rising edge delay device is electrically connected to the input end of the pulse signal generating circuit, and the output end of the rising edge delay device is electrically connected to the input end of the first NOT gate; The output terminal of the first NOT gate is electrically connected to the second input terminal of the NAND gate; The first input terminal of the NAND gate is electrically connected to the input terminal of the pulse signal generating circuit, and the output terminal of the NAND gate is electrically connected to the input terminal of the second NAND gate; The output end of the second NOT gate is electrically connected to the output end of the pulse signal generating circuit.

3. The driving circuit according to claim 1, characterized in that: The latch circuit includes: a first resistor, a second resistor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a current source, a third NOT gate and a fourth NOT gate; The first end of the first resistor is electrically connected to the first end of the second resistor and the high-side switch control signal respectively, and the second end of the first resistor is electrically connected to the first end of the first switch and the control end of the second switch respectively; The second end of the second resistor is electrically connected to the control end of the first switch tube, the first end of the second switch tube, the first end of the third switch tube and the control end of the fourth switch tube respectively; The second end of the first switch tube, the second end of the second switch tube, the second end of the third switch tube and the second end of the fourth switch tube are all grounded; The control end of the third switch tube is electrically connected to the input end of the latch circuit; The first end of the fourth switch tube is electrically connected to the output end of the current source and the input end of the third NOT gate respectively; The input end of the current source is electrically connected to the system power supply; The output end of the third NOT gate is electrically connected to the input end of the fourth NOT gate; The output end of the fourth NOT gate is electrically connected to the output end of the latch circuit.

4. The driving circuit according to claim 2, characterized in that: The delay time of the rising edge delay device is proportional to the duration of the pulse signal.

5. The driving circuit according to claim 3, characterized in that: The resistance value of the second resistor is smaller than the resistance value of the first resistor, and the tube length ratio of the first switch tube is larger than the tube length ratio of the second switch tube.

6. The driving circuit according to claim 3, characterized in that: When the high-side switch control signal is controlled to be high level, the latch signal output by the latch circuit is latched to be high level; when the high-side switch control signal is controlled to be switched from low level to high level, the latch signal output by the latch circuit is unlocked to be low level.

7. The driving circuit according to claim 3, characterized in that: The first switch tube, the second switch tube, the third switch tube and the fourth switch tube are all MOS tubes.

8. A high-side switch chip, characterized in that: include: The driving circuit and the voltage detection circuit according to any one of claims 1 to 7; The input end of the voltage detection circuit is electrically connected to the power supply, and the output end of the voltage detection circuit is electrically connected to the input end of the drive circuit; The voltage detection circuit is used to detect the power supply, output a power failure indication signal, and transmit the power failure indication signal to the drive circuit.

9. The high side switch chip according to claim 8, characterized in that: When the voltage value of the power supply is higher than the preset undervoltage threshold, the power-off indication signal is at a low level; When the voltage value of the power supply is lower than a preset undervoltage threshold, the power-off indication signal is at a high level.

10. An electronic device, characterized in that: include: A driving circuit as described in any one of claims 1 to 7, or a high-side switch chip as described in any one of claims 8 to 9.

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