High-speed Pipe-SAR-ADC circuit and module for CIS

Abstract

The present invention relates to the field of image sensor design technology, and in particular to a high-speed Pipe-SAR-ADC circuit and module for CIS. The circuit of the present invention first samples and holds an input signal, amplifies the gain, and introduces a fixed offset through a CDS-PGA unit to obtain a differential signal; then performs 6-bit quantization on the differential signal through a first-stage SAR-ADC unit to obtain a 6-bit numerical code and a residual signal; then amplifies the residual signal through an MDAC unit to obtain an amplified signal; then performs 7-bit quantization on the amplified signal through a second-stage SAR-ADC unit to obtain a 7-bit numerical code; finally, a redundant calibration unit performs redundant calibration based on the 6-bit numerical code and the 7-bit numerical code to obtain a final 12-bit digital code. The present invention can not only meet a higher input signal range and a higher signal-to-noise ratio, but also reduce noise, eliminate offset voltage, and achieve high speed, low noise, and high resolution.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensor design, and more specifically to: 1. a high-speed Pipe-SAR-ADC circuit for CIS; 2. a high-speed Pipe-SAR-ADC module for CIS. Background Art

[0002] Currently, the market demand for high-speed, high dynamic range, high resolution, and low-noise CMOS image sensors (CIS) is increasing. Since analog-to-digital converters (ADCs) are the fundamental building blocks of CISs, improving ADC performance is an important research direction for improving CISs.

[0003] Pipe-SAR ADCs, or pipelined successive approximation register (SAAR) ADCs, are a popular architecture that is compatible with increasingly advanced process technologies (i.e., shrinking transistor minimum feature sizes) and can operate at low supply voltages. However, existing Pipe-SAR ADCs also have drawbacks: 1. Speed limitations; 2. Complex capacitor arrays and wiring required for high resolution.

[0004] After analysis, the inventors found that this is because the existing Pipe-SAR ADC lacks a reasonable circuit design when processing pixel signals to the sub-ADC, resulting in problems such as a small input range, high noise, and low speed, which in turn affects the operation of the sub-ADC. Summary of the Invention

[0005] Based on this, it is necessary to provide a high-speed Pipe-SAR-ADC circuit and module for CIS to achieve high speed and low noise.

[0006] The present invention is achieved by adopting the following technical solutions:

[0007] In a first aspect, the present invention provides a high-speed Pipe-SAR-ADC circuit for CIS, comprising: a CDS-PGA section, a first-stage SAR-ADC section, an MDAC section, a second-stage SAR-ADC section, and a redundant calibration section.

[0008] The CDS-PGA section is used to combine the reference voltages VREFP and VREFN to generate the input signal V signal Perform sampling and holding, gain amplification, and introduce a fixed offset ΔV to obtain the differential signal V OP 、V ON ;Wherein, ΔV=VREFP-VREFN.

[0009] The first stage SAR-ADC is used to combine VREFP, VREFN, common mode voltage VCM to V OP 、VON Perform 6-bit quantization to obtain a 6-bit numerical code D1<12:7> and residual signals CAP_UP and CAP_DN.

[0010] The MDAC part is used to amplify CAP_UP and CAP_DN in combination with VCM to obtain the amplified signal V IN2+ 、V IN2- .

[0011] The second stage SAR-ADC is used to combine the reference voltage VREFP1, VREFN1, and VCM to V IN2+ 、V IN2- Perform 7-bit quantization to obtain a 7-bit numerical code D2<6:0>.

[0012] The redundancy calibration unit is used to perform redundancy calibration based on D1<12:7> and D2<6:0> to obtain a final 12-bit digital code D<11:0>.

[0013] The implementation of the high-speed Pipe-SAR-ADC circuit for CIS is in accordance with the method or process of an embodiment of the present disclosure.

[0014] In a second aspect, the present invention discloses a high-speed Pipe-SAR-ADC module for CIS, which adopts the layout of the high-speed Pipe-SAR-ADC circuit for CIS disclosed in the first aspect.

[0015] The implementation of the storage and calculation circuit based on the high-speed Pipe-SAR-ADC circuit for CIS is based on the method or process of an embodiment of the present disclosure.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] 1. The present invention combines CDS function and PGA function to design CDS-PGA part, and introduces Pipe-SAR ADC to realize the input signal V signal It performs sampling and holding, gain amplification, and introduces a fixed offset. The CDS-PGA unit can select different gains according to the input signal to achieve a high dynamic range. Moreover, the CDS-PGA unit is based on a differential circuit design, which achieves a higher signal-to-noise ratio. The CDS-PGA unit uses different capacitors for sampling during the reset and exposure stages, which reduces the readout time by half and achieves high-speed processing.

[0018] 2. This invention implements a CDS function through the CDS-PGA section, eliminating fixed-pattern noise and offset voltage. This eliminates the need for an additional CDS circuit, thus saving circuit area. Furthermore, the CDS-PGA section provides a differential output with a fixed offset, preventing circuit saturation in dark environments. The fixed offset overrides the inherent offset of the PGA, further eliminating offset.

[0019] 3. The present invention also improves the structural design of the first-stage SAR-ADC unit, the MDAC unit, and the second-stage SAR-ADC unit, making them more adaptable to the working mode of the CDS-PGA unit, and improving the speed of the overall Pipe-SAR-ADC circuit and reducing the power consumption of the overall Pipe-SAR-ADC circuit.

[0020] 4. The circuit of the present invention first processes the input signal V through the CDS-PGA part. signal Perform sampling and holding, gain amplification, and introduce a fixed offset to obtain the differential signal V OP 、V ON ; Then the differential signal V is converted by the first stage SAR-ADC OP 、V ON Perform 6-bit quantization to obtain a 6-bit numerical code D1<12:7> and residual signals CAP_UP and CAP_DN; then use the MDAC part to amplify the residual signals CAP_UP and CAP_DN to obtain the amplified signal V IN2+ 、V IN2- Then the second stage SAR-ADC part is used to amplify the signal V IN2+ 、V IN2- 7-bit quantization is performed to obtain a 7-bit numerical code D2<6:0>; finally, a redundant calibration unit performs redundant calibration based on the 6-bit numerical code D1<12:7> and the 7-bit numerical code D2<6:0> to obtain a final 12-bit digital code D<11:0>. The present invention can not only meet a higher input signal range and a higher signal-to-noise ratio, but also reduce noise, eliminate offset voltage, and achieve high speed, low noise, and high resolution. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 This is an overall structural diagram of a high-speed Pipe-SAR-ADC circuit for CIS provided in Example 1 of the present invention;

[0023] Figure 2 for Figure 1 Circuit connection diagram of CDS-PGA section;

[0024] Figure 3 for Figure 1 Part of the circuit diagram of the first-stage SAR-ADC unit;

[0025] Figure 4 for Figure 1 Another part of the circuit diagram of the first stage SAR-ADC section;

[0026] Figure 5 for Figure 4 The circuit structure diagram of Comp1;

[0027] Figure 6 for Figure 1 Circuit connection diagram of the middle MDAC part;

[0028] Figure 7 for Figure 6 The circuit structure diagram of OPA2;

[0029] Figure 8 for Figure 1 Part of the circuit diagram of the second-stage SAR-ADC section;

[0030] Figure 9 for Figure 1 Another part of the circuit diagram of the second-stage SAR-ADC section;

[0031] Figure 10 for Figure 9 The circuit structure diagram of Comp2;

[0032] Figure 11 for Figure 1 Calculation process diagram of the redundant calibration part. DETAILED DESCRIPTION

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0034] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component. When a component is considered to be "fixed to" another component, it may be directly fixed to the other component or there may be a central component.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0036] Example 1

[0037] See Figure 1 , which is a circuit diagram of a high-speed Pipe-SAR-ADC circuit for CIS, provided in Example 1. Functionally, this Pipe-SAR-ADC circuit includes a CDS-PGA section, a first-stage SAR-ADC section, an MDAC section, a second-stage SAR-ADC section, and a redundant calibration section.

[0038] First, the working process of the Pipe-SAR-ADC circuit is explained from the overall signal processing and transmission process:

[0039] The CDS-PGA section is used to combine the reference voltages VREFP and VREFN to generate the input signal V signal Perform sampling and holding, gain amplification, and introduce a fixed offset ΔV to obtain the differential signal V OP 、V ON Where, ΔV = VREFP - VREFN.

[0040] The first stage SAR-ADC is used to combine VREFP, VREFN, common mode voltage VCM to V OP 、V ON Perform 6-bit quantization to obtain a 6-bit numerical code D1<12:7> and residual signals CAP_UP and CAP_DN.

[0041] The MDAC part is used to amplify CAP_UP and CAP_DN in combination with VCM to obtain the amplified signal V IN2+ 、V IN2- .

[0042] The second stage SAR-ADC is used to combine the reference voltage VREFP1, VREFN1, and VCM to V IN2+、V IN2- Perform 7-bit quantization to obtain a 7-bit numerical code D2<6:0>.

[0043] The redundancy calibration unit is used to perform redundancy calibration based on D1<12:7> and D2<6:0> to obtain a final 12-bit digital code D<11:0>.

[0044] It should be noted that the present Pipe-SAR-ADC circuit uses multiplexing to process pixel signals of different columns, which greatly saves circuit area compared to the existing traditional method of using one SAR-ADC for each column.

[0045] The following describes each part one by one:

[0046] 1. The CDS-PGA unit integrates the CDS function and the PGA function and applies them to the Pipe-SAR ADC, which is an important invention of the present invention.

[0047] See Figure 2 From the perspective of components, the CDS-PGA part can be designed to include: 10 switches S101~S110, 2 switches SN109~SN110, 4 switches SR1~SR4, 2 switches SRN1~SRN2, 1 operational amplifier OPA1, 5 capacitors C11~C15, and 5 capacitors C21~C25.

[0048] According to the functional division, the CDS-PGA section can be designed to include: up-sampling sub-section, down-sampling sub-section, and gain amplification sub-section. Among them, the up-sampling sub-section is used to combine VREFP and VREFN to adjust the V signal Sampling is performed to obtain the sampling voltage V UP The down sampling subsection is used to combine VREFP and VREFN to reset the V signal Sampling is performed to obtain the sampling voltage V DN The gain amplifier section is used to adjust the V UP 、V DN Perform adjustable gain amplification to obtain V OP 、V ON .

[0049] Among them, V DN 、V UP Satisfaction: V DN -V UP =(V exp -V reset )+ λ ΔV;

[0050] Where V exp V represents the exposure stage signal ; Vreset Represents the reset phase V signal ; λ Indicates the offset coefficient.

[0051] Since VREFP and VREFN are fixed reference voltages, sampling not only introduces V exp and V reset In order to take into account the difference between them, a fixed offset ΔV is introduced between VREFP and VREFN, thereby achieving the goal of uniform signal distribution.

[0052] Then, matching the components of the CDS-PGA section with the three functional areas, we have:

[0053] ① The upsampling subsection includes: 4 switches S101~S104, 1 switch S109, 1 switch SR1, 1 switch SRN1, and 3 capacitors C11~C13.

[0054] ② The downsampling sub-section includes: 4 switches S105~S108, 1 switch S110, 1 switch SR2, 1 switch SRN2, and 3 capacitors C21~C23.

[0055] ③ The gain amplifier section includes: 1 operational amplifier OPA1, 2 capacitors C14~C15, 2 capacitors C24~C25, 2 switches SN109~SN110, and 2 switches SR3~SR4.

[0056] The specific component connection method is as follows:

[0057] The first ends of C11~C13 are connected to V through S101 signal , the second end is connected to the negative input terminal of OPA1 through S109;

[0058] The second end of C11 is connected to the first end of S102 and the first end of SRN1; the second end of S102 is grounded;

[0059] The second end of C12 is connected to the second end of SRN1 and the first end of SR1;

[0060] The second end of C13 is connected to the second end of SR1, the first end of S104, and the first end of S103; the second end of S104 is grounded; the second end of S103 is connected to VREFP;

[0061] The first ends of C21~C23 are connected to V through S105 signal , the second end is connected to the positive input terminal of OPA1 through S110;

[0062] The second end of C21 is connected to the first end of S106 and the first end of SRN2; the second end of S106 is grounded;

[0063] The second end of C22 is connected to the second end of SRN2 and the first end of SR2;

[0064] The second end of C23 is connected to the second end of SR2, the first end of S107, and the first end of S108; the second end of S108 is grounded; the second end of S107 is connected to VREFN;

[0065] The positive output terminal of OPA1 is used to output V OP , the negative output terminal is used to output V ON ;

[0066] The first ends of C14 and S109 are connected to the positive output of OPA1, and the second ends are connected to the negative input of OPA1; the first end of C15 is connected to the positive output of OPA1, and the second end is connected to the first end of SR3; the second end of SR3 is connected to the negative input of OPA1;

[0067] The first ends of C24 and S110 are connected to the negative output end of OPA1, and the second ends are connected to the positive input end of OPA1; the first end of C25 is connected to the negative output end of OPA1, and the second end is connected to the first end of SR4; the second end of SR4 is connected to the positive input end of OPA1.

[0068] It should be noted that the capacitance values of C11 and C21 are the same; the capacitance values of C12 and C22 are the same; and the capacitance values of C13 and C23 are the same.

[0069] Furthermore, in the CDS-PGA section, the control relationship of each switch is as follows:

[0070] SR1, SR2, SR3, and SR4 are turned on or off synchronously; SRN1 and SRN2 are turned on or off synchronously;

[0071] When SR1 is turned on, SRN1 is turned off; when SR2 is turned off, SRN1 is turned on;

[0072] S109 and S110 are turned on or off synchronously; SN109 and SN110 are turned on or off synchronously;

[0073] When S109 is turned on, SN109 is turned off; when S109 is turned off, SN109 is turned on.

[0074] The CDS-PGA unit based on the above design works as follows:

[0075] V signal As the input of CDS-PGA, it has a reset phase (at this time V signal called V reset ), exposure stage (at this time V signal Called V exp ).

[0076] First, during the reset phase, the upper capacitor array consisting of C11, C12, and C13 is sampled:

[0077] 101, first turn on S101, S102, S103, turn off S104, the second end of C11 is grounded; turn on SR1, turn off SRN1, the second ends of C12 and C13 are connected to VREFP, so that C11, C12, and C13 are connected to V exp , VREFP charges; the total charge stored in C11, C12, and C13 is Q UP .

[0078] Among them, Q UP It can be expressed as: Q UP =C12(V reset -V GND )+(C12+C13)(V reset -VREFP); where V GND Indicates the ground voltage.

[0079] 102, then disconnect S101 and S103, turn on S104, S102 is first disconnected and then turned on, the second ends of C12 and C13 are switched from VREFP to ground, so that the sampling voltage V is formed at the first ends of C11, C12, and C13. UP .

[0080] Since the capacitor is not connected to the new power supply, the total charge value remains unchanged. Considering that the switch S109 is open, based on the assumption of charge conservation and ignoring offset, Q UP Can be rewritten as:

[0081] Q UP =(C11+C12+C13)(V up -V GND );

[0082] Then, through transformation we get:

[0083] V UP =V reset -(C12+C13)(VREFP-V GND ) / (C11+C12+C13).

[0084] Then, during the exposure phase, the lower capacitor array composed of C21, C22, and C23 is sampled:

[0085] 111, first turn on S105, S106, S107, turn off S108, the second end of C21 is grounded; turn on SR2, turn off SRN2, the second ends of C22 and C23 are connected to VREFN, so that C21, C22, and C23 are connected to Vsignal , VREFN charging;

[0086] 112, then disconnect S105 and S107, turn on S108, first disconnect S106 and then turn it on, the second ends of C22 and C23 are switched from VREFN to ground, so that the sampling voltage V is formed at the first ends of C21, C22 and C23. DN .

[0087] Similar to the principles of 101 and 102, we get:

[0088] V DN =V exp -(C22+C23)(VREFP-V GND ) / (C21+C22+C23).

[0089] Since the capacitance values of C11 and C21 are the same; the capacitance values of C12 and C22 are the same; the capacitance values of C13 and C23 are the same, then: (C12+C13) / (C11+C12+C13)=(C22+C23) / (C21+C22+C23).

[0090] Then, the gain amplification stage is carried out, S109 and S110 are turned on, SN109 and SN110 are turned off, and V UP Input the negative input terminal of OPA1, V DN Inputting into the positive input terminal of OPA1 realizes the CDS function.

[0091] Among them, V DN 、V UP satisfy:

[0092] .

[0093] In this embodiment 1, the capacitance values of C11, C21, C12, C22, C13, and C23 are the same; the capacitance values of C14, C24, C15, and C25 are the same; and the capacitance value of C11 is twice the capacitance value of C14.

[0094] Then, OPA1 is based on V UP 、V DN Gain amplification is performed to obtain the differential signal V OP 、V ON :

[0095] If SR3 and SR4 are turned on, the formula for calculating the gain multiplier is:

[0096] (C11+C12+C13) / (C14+C15)=3;

[0097] If SR3 and SR4 are disconnected, the formula for calculating the gain multiplier is:

[0098] (C11+C12+C13) / C14=6;

[0099] This can be done according to V signal To select different gains, thus achieving a high dynamic range: If V signal If V signal If it is too large, select 3 times gain.

[0100] In addition, since V UP 、V DN is obtained based on the differential circuit, so that V signal The input range is extended, enabling a higher signal-to-noise ratio.

[0101] In general, the CDS-PGA section implements the CDS function to eliminate fixed pattern noise (FPN) and offset voltages:

[0102] Ⅰ. The gain-adjustable OPA1 is introduced to reduce amplifier noise, thus achieving the goal of low noise;

[0103] II. No additional CDS circuit is required to implement the CDS function, thus saving circuit area.

[0104] III. A differential output with a fixed offset is generated through differential circuit design, which is evenly distributed on the positive and negative sides of OPA1 to prevent the circuit from saturating in a dark environment. The fixed offset is used to cover the inherent offset of the PGA to further eliminate the offset.

[0105] IV. Different capacitors are used for sampling during the reset and exposure phases. Compared to sampling with the same capacitor, this approach reduces the readout time by half, enabling high-speed processing.

[0106] 2. The first stage SAR-ADC part should output V op 、V on Sampling and quantization are performed.

[0107] The first-stage SAR-ADC part may adopt an existing conventionally designed SAR ADC, which only needs to be able to perform 6-bit quantization and generate residual signals CAP_UP and CAP_DN.

[0108] Of course, you can also use Figure 3 、 Figure 4Design - The first-stage SAR-ADC part is designed to include: 1 CDAC circuit part CDAC1, 1 comparator Comp1, and 1 SAR logic part SAR-logic1; this design has the advantages of high speed, low power consumption, and high resolution.

[0109] CDAC1 is used to combine VREFP, VREFN, and VCM to V under the control of SAR-logic1. OP Processing is performed to obtain CAP_UP, and VREFP, VREFN, and VCM are combined under the control of SAR-logic1 to ON Processed to obtain CAP_DN.

[0110] Comp1 is used to process CAP_UP, CAP_DN, and VCM under the control of SAR-logic1 to obtain comparison signals VOUTP1 and VOUTN1.

[0111] SAR-logic1 is used to obtain D<12:7> based on VOUTP1 and VOUTN1, and generate control signals for CDAC1 and Comp1.

[0112] Specifically, the various parts of the first-stage SAR-ADC unit can be designed as follows:

[0113] Ⅰ, CDAC1 includes: 4 groups of capacitor arrays C301~C304, 4 groups of switch arrays S301~S304, 2 sampling switches S201~S202, 4 single-pole triple-throw switches SW1~SW4, and 4 capacitors C305~C308;

[0114] S301~S304 each include 6 single-pole triple-throw switches, and the switching is controlled by SAR-logic1;

[0115] SW1~SW4 are also switched by SAR-logic1;

[0116] C301~C304 each includes 6 capacitors;

[0117] Among them, the first ends of the six capacitors of C301 are connected to VCM through S201; the first ends of the six capacitors of C301 are also connected to CAP_UP;

[0118] The second end of the nth capacitor of C301 is connected to V OP , VREFP, VREFN; n∈[1,6];

[0119] The first ends of the six capacitors C302 are connected to VCM through S201; the second ends of the six capacitors C302 are also connected to CAP_UP;

[0120] The second end of the nth capacitor of C302 is connected to V OP , VREFP, VREFN;

[0121] The first ends of the six capacitors of C303 are connected to VCM through S202; the first ends of the seven capacitors of C302 are also connected to CAP_DN;

[0122] The second end of the nth capacitor of C303 is connected to V ON , VREFP, VREFN;

[0123] The first ends of the six capacitors C304 are connected to VCM through S202; the second ends of the seven capacitors C304 are also connected to CAP_DN;

[0124] The second end of the nth capacitor of C304 is connected to V ON , VREFP, VREFN;

[0125] The first end of C305 is connected to VCM through S201, and the first end of C305 is also connected to CAP_UP;

[0126] The second end of C305 is connected to V OP , VREFP, VREFN;

[0127] The first end of C306 is connected to VCM through S201, and the first end of C306 is also connected to CAP_UP;

[0128] The second end of C306 is connected to V OP , VREFP, VREFN;

[0129] The first end of C307 is connected to VCM through S202, and the first end of C307 is also connected to CAP_UP;

[0130] The second end of C307 is connected to V ON , VREFP, VREFN;

[0131] The first end of C308 is connected to VCM through S201, and the first end of C308 is also connected to CAP_UP;

[0132] The second end of C308 is connected to V ON , VREFP, VREFN;

[0133] It should be noted that:

[0134] The capacitance values of the six capacitors in C305 and C301 are Cu, Cu, 2Cu, 4Cu, 8Cu, 16Cu, and 32Cu respectively;

[0135] The capacitance ratio of the six capacitors in C306 and C302 is Cu, Cu, 2Cu, 4Cu, 8Cu, 16Cu, and 32Cu;

[0136] The capacitance ratio of the six capacitors in C307 and C303 is Cu, Cu, 2Cu, 4Cu, 8Cu, 16Cu, and 32Cu;

[0137] The capacitance ratio of the six capacitors in C308 and C304 is Cu, Cu, 2Cu, 4Cu, 8Cu, 16Cu, and 32Cu.

[0138] This makes it convenient to use the ADC comparison dichotomy method in conjunction with Comp1 and SAR-logic1 for quantization.

[0139] Ⅱ. The positive input of Comp1 is connected to CAP_UP, the negative input is connected to CAP_DN, the reference input is connected to VCM, the timing control terminal is connected to the control signal CLK2, the positive output is used to output VOUTP1, and the negative output is used to output VOUTN1.

[0140] Comp1 can be used as Figure 5 The designed two-stage structure primarily consists of a pre-amplifier (Pre-amp-1) and a comparison (Latch-1). Pre-amp-1 pre-amplifies CAP_UP and CAP_DN before feeding them into Latch-1 for processing. Latch-1 then compares the signals to obtain VOUTP1 and VOUTN1. This allows for amplification even when the difference between CAP_UP and CAP_DN is minimal. This prevents situations where Latch-1 fails to resolve the signal within the specified timeframe, or where the resolution is too slow or takes too long, thus ensuring that Comp1 can meet high-speed requirements.

[0141] See Figure 5 Pre-amp-1 includes seven NMOS transistors, M208 through M214. Specifically, the sources of M208 and M209 are connected to VDD; the gates of M208 and M209 are connected to CLK2; the drain of M208 is connected to the drains of M210 and M211; the drain of M209 is connected to the drains of M212 and M213; the gate of M210 is connected to CAP_UP; the gate of M211 is connected to VCM; the gate of M212 is connected to VCM; the gate of M213 is connected to CAP_DN; the sources of M210, M211, M212, and M213 are connected to the drain of M214; the gate of M214 is connected to CLK2; and the source of M214 is grounded.

[0142] Latch-1 includes seven NMOS transistors, M201 through M207, and two inverters, INV1 and INV2. Specifically, the source of M201 is connected to VDD; its gate is connected to the timing signal, CLK2N; its drain is connected to the sources of M202 and M203; M202, M203, M205, and M206 are cross-coupled; the drain of M202 is connected to the input of INV1 and the drain of M204; the output of INV1 is used to output VOUTP1; the drain of M203 is connected to the input of INV2 and the drain of M207; the output of INV2 is used to output VOUTN1; the sources of M204, M205, M206, and M207 are grounded; the gate of M204 is connected to the source of M208; and the gate of M207 is connected to the source of M209.

[0143] In addition, CLK2 and CLK2N are opposite signals: an inverter INV0 can be set in Comp1; CLK2 is connected to the input end of INV0, and the output end of INV0 is used to output CLK2N.

[0144] Comp1 based on the above structure works as follows:

[0145] First, M210 and M213 of Pre-amp-1 receive CAP_UP and CAP_DN. When CLK2 is 1, they control the pre-amplification of CAP_UP and CAP_DN. The differential output results XP (transmitted from the drain of M208 to the gate of M204) and XN (transmitted from the drain of M209 to the gate of M207) are passed to Latch-1.

[0146] Since CAP_UP and CAP_DN are of different sizes, the size difference between XP and XN is even greater, which will lead to different operating currents of M204 and M205 tubes, and the charging and discharging speeds of the two output branches where the two tubes are located will also be different; after the positive feedback of M202, M205, M203, and M206, one of VOUTP1 and VOUTN1 will eventually be pulled up to VDD and the other will be pulled down to GND.

[0147] Since Pre-amp-1 is set in Comp1, it plays a gain role, thereby improving the resolution, reducing the probability of error, and speeding up the resolution.

[0148] Therefore, Comp1 can achieve fast, high-precision and accurate comparison functions:

[0149] ① The introduction of Pre-amp-1 improves resolution and reduces the probability of error;

[0150] ② Pre-amp-1 uses NMOS transistors as input transistors. Compared with PMOS transistors, they have greater gain and are more suitable for situations where the first-stage SAR-ADC part needs to make stable and accurate judgments.

[0151] ③ The number of stacked MOS tubes in the traditional comparator circuit is reduced, which allows it to operate at a lower power supply voltage and reduce power consumption;

[0152] ④ The two-stage separation circuit structure disconnects the parasitic capacitance connection between the output and input, effectively eliminating kickback noise, reducing comparator noise, and reducing input offset voltage.

[0153] III, SAR-logic1 uses asynchronous SAR logic to increase the conversion speed.

[0154] Specifically, input terminal 1 of SAR-logic1 is connected to VOUTP1, input terminal 2 is connected to VOUTN1, the code value output terminal is used to output D<12:7>, switch control terminal 1 is used to output control signals for S301~S304, switch control terminal 2 is used to output control signals for SW1~SW4, and the comparison control terminal is used to output CLK2.

[0155] Note that SAR-logic1's switch control terminal 1 outputs not just one control signal, but four signals: one signal for each single-pole, triple-throw switch (S301-S304). Similarly, SAR-logic1's switch control terminal 2 outputs not just one control signal, but four signals: one signal for each of SW1-SW4.

[0156] The first-stage SAR-ADC part based on the above design works as follows:

[0157] Entering the sampling state: first turn on S201 and S202, connect the first ends of C301~C304 and C305~C308 to VCM, and start sampling; SAR-logic1 controls S301 and S302 to switch, so that the second ends of C301 and C302 are connected to V OP , connect the second end of C303 and C304 to V ON SAR-logic1 controls Comp1 to reset, VOUTP1 and VOUTN1 are low level.

[0158] After sampling is completed, the system enters the set state: S201 and S202 are disconnected, and SAR-logic1 controls S301 and S302 to switch, so that the second ends of C301 and C303 are connected to VREFN, and the second ends of C302 and C304 are connected to VREFP; according to the law of charge conservation, the charge on the capacitor array will be redistributed, and CAP_UP and CAP_DN will be regained.

[0159] After the set state, the quantization period begins: SAR-logic1 controls Comp1 to compare CAP_UP and CAP_DN at this time. On the one hand, SAR-logic1 internally quantizes to obtain the highest bit of D1<12:7>, and on the other hand, adjusts the voltage connected to the capacitor with a capacitance value of 32Cu in the capacitor array according to the comparison result; if CAP_UP>CAP_DN, SAR-logic1 controls S302 and S303 to switch, so that the second end of the capacitor with a capacitance value of 32Cu in C302 is connected to VREFN, and the second end of the capacitor with a capacitance value of 32Cu in C303 is connected to VREFP; if CAP_UP<CAP_DN, SAR-logic1 controls S301 and S304 to switch, so that the second end of the capacitor with a capacitance value of 32Cu in C301 is connected to VREFP, and the second end of the capacitor with a capacitance value of 32Cu in C304 is connected to VREFN. After the connection is changed, according to the law of charge conservation, the charge on the capacitor array is redistributed, and CAP_UP and CAP_DN are restored. SAR-Logic1 then controls Comp1 to compare CAP_UP and CAP_DN again. SAR-Logic1 internally quantizes the second-highest bit of D1<12:7> and, based on the comparison result, adjusts the voltage connected to the 16-cubic-meter capacitor in the capacitor array. If CAP_UP > CAP_DN, SAR-Logic1 controls S302 and S303 to connect the second end of the 16-cubic-meter capacitor in C302 to VREFN, and the second end of the 16-cubic-meter capacitor in C303 to VREFP. If CAP_UP < CAP_DN, SAR-Logic1 controls S301 and S304 to connect the second end of the 16-cubic-meter capacitor in C301 to VREFP, and the second end of the 16-cubic-meter capacitor in C304 to VREFN. This process continues in this order until the six bits of D1<12:7> are obtained.

[0160] It should be noted that C305~C308 are only dummy capacitors used to adjust the weight:

[0161] When the first-stage SAR-ADC is sampling, SAR-logic1 controls SW1~SW4 to switch, so that C305~C306 are connected to V OP, connect C307~C308 to V ON When the first-stage SAR-ADC part performs quantization, SAR-logic1 controls SW1~SW4 to switch, so that C305 and C307 are connected to VREFN, and C306 and C308 are connected to VREFP.

[0162] In general, C301-C304 adopt a VCM-based switching strategy and capacitor splitting technology, which allows the capacitor array to switch only half of the capacitors each time, speeding up the DAC settling speed and reducing power consumption by up to 87%, further improving the SAR ADC conversion speed, thereby achieving high speed, low power consumption, and high resolution.

[0163] 3. The MDAC section is designed to amplify the CAP_UP and CAP_DN outputs of the first-stage SAR-ADC section.

[0164] The MDAC part may adopt an existing conventionally designed MDAC, which only needs to be able to effectively amplify CAP_UP and CAP_DN.

[0165] Of course, you can also use Figure 6 Design - The MDAC part is designed to include: 10 switches S901~S910, 2 capacitors C31~C22, and 1 residual amplifier OPA2; this design has the advantages of high precision and low power consumption.

[0166] Specifically, CAP_DN is connected to the first end of S901, and the second end of S901 is connected to the negative input end of OPA2;

[0167] VCM is connected to the second end of S901 through S903;

[0168] CAP_UP passes through the first end of S902, and the second end of S902 is connected to the positive input terminal of OPA2;

[0169] VCM is connected to the second end of S902 through S904;

[0170] The positive output terminal of OPA2 is used to output V IN2- , the negative output terminal is used to output V IN2+ ;

[0171] The positive output of OPA2 is connected to the negative input of OPA2 through S905;

[0172] The positive output of OPA2 is connected to the first end of C32 and the first end of S909 through S907; VCM is connected to the second end of S909; the second end of C32 is connected to the negative input of OPA2;

[0173] The negative output of OPA2 is connected to the positive input of OPA2 through S906;

[0174] The negative output terminal of OPA2 is connected to the first terminal of C31 and the first terminal of S910 through S908; VCM is connected to the second terminal of S910; and the second terminal of C31 is connected to the positive input terminal of OPA2.

[0175] Among them, S901~S910 are controlled by two-phase non-overlapping clocks CK1 and CK2:

[0176] CK1 controls S903~S906, S909, and S910; CK2 controls S901~S902, S907, and S908.

[0177] It should be noted that the OPA2 achieves gain boost based on gain bootstrapping technology (based on the folded cascode, with two auxiliary amplifiers added to the common-gate terminal). Since gain bootstrapping has no effect on the op amp's input transconductance and output capacitance, it does not require frequency compensation, which reduces the area.

[0178] To further illustrate the special design of OPA2, let the input signal of the positive input terminal of OPA2 be VIP, the input signal of the negative input terminal be VIN, the output signal of the positive output terminal be VOP, and the output signal of the negative output terminal be VON. Figure 7 , OPA2 can be designed to include: 17 NMOS tubes M1~M17, 4 capacitors C401~C404, 2 auxiliary amplifiers A1~A2, and 1 current source I1.

[0179] like Figure 7As shown, the gate of M1 is connected to VIP; the gate of M2 is connected to VIN, the source is connected to the drain of M3, and the drain is connected to VDD; the gate of M3 is connected to the voltage signal Vbp1, and the drain is connected to VDD; the gate of M4 is connected to Vbp1, and the source is connected to VDD; the gate of M5 is connected to Vbp1, and the source is connected to VDD; the source of M6 is connected to the drain of M4; the source of M7 is connected to the drain of M5; the negative input terminal of A1 is connected to the drain of M4, the positive input terminal is connected to the drain of M5, the positive output terminal is connected to the gate of M7, the negative output terminal is connected to the gate of M6, and the reference terminal is connected to the voltage signal Vcmn; the first end of C401 is connected to the gate of M6, and the second end is connected to the drain of M6; the first end of C402 is connected to the gate of M7, and the second end is connected to the drain of The negative input terminal of A2 is connected to the drain of M11, the positive input terminal is connected to the drain of M10, the positive output terminal is connected to the gate of M8, the negative output terminal is connected to the gate of M9, the reference terminal 1 is connected to the voltage signal Vcmp, and the reference terminal 2 is connected to the voltage signal bn1; the first end of C403 is connected to the gate of M8, and the second end is connected to the drain of M8; the first end of C404 is connected to the gate of M9, and the second end is connected to the drain of M9.

[0180] The source of M12 is grounded; the gate and drain of M12 are connected to the voltage signal Vbn; one end of I1 is connected to the drain of M12, and the other end is connected to VDD; the gate of M13 is connected to the drain of M6, the source is connected to VDD, and the drain is connected to VON; the gate of M14 is connected to the gate of M13, the source is connected to the drain of M17, and the drain is connected to VON; the gate of M15 is connected to the drain of M7, the source is connected to VDD, and the drain is connected to VOP; the gate of M16 is connected to the gate of M15, and the drain is connected to VOP; the gate of M17 is connected to the voltage signal Vcmd, the source is grounded, and the drain is connected to the source of M14 and the source of M16.

[0181] Among them, Vbp1, Vcmn, and Vcmp are all bias corrections provided by the bandgap reference; Vcmc, Vcmd, Vbn, and bn1 are all correction voltages used to correct the offset of the output common-mode voltage, prevent level drift caused by device mismatch, and stabilize the output common-mode level.

[0182] The MDAC part based on the above design works as follows:

[0183] C301 - C304 and C305 - C308 serve as the feedback capacitor C1 of the MDAC section; C31 and C32 serve as the sampling capacitor C2.

[0184] In the first embodiment, the capacitance value of C1 is (1+1+2+4+8+16+32)×Cu; the capacitance value of C2 is 8×Cu.

[0185] When CK1 is high and CK2 is low, the MDAC is in the sampling phase. CK1 turns on S903-S906, S909, and S910, while CK2 turns off S901-S902, S907, and S908. During this phase, the first-stage SAR-ADC completes sampling, setting, and quantization, generating CAP_UP and CAP_DN, eliminating the need for additional digital control logic in the MDAC. The charge stored in C1 represents CAP_UP and CAP_DN. Because S904 and S910 are closed, the charge stored in C2 is zero.

[0186] When CK1 is low and CK2 is high, the MDAC is in the hold phase (i.e., the amplification phase). CK1 turns off S903-S906, S909, and S910, while CK2 turns on S901-S902, S907, and S908. OPA2 amplifies the gain of CAP_UP and CAP_DN. In this first embodiment, the amplification factor can reach C1 / C2 = 16 times.

[0187] In general, the MDAC part adopts a closed-loop residual amplifier design, and the amplification factor is designed based on a negative feedback mechanism. It is basically not affected by the process, temperature and voltage, so it can achieve higher precision.

[0188] 4. The second stage SAR-ADC part should output V IN2+ 、V IN2- Sampling and quantization are performed.

[0189] Similar to the first-stage SAR-ADC section, the second-stage SAR-ADC section may adopt an existing conventionally designed SAR ADC, which only needs to be capable of 7-bit quantization.

[0190] Of course, you can also use the reference Figure 8 、 Figure 9 The second-stage SAR-ADC part can be divided into: 1 CDAC circuit part CDAC2, 1 comparator Comp2, and 1 SAR logic part SAR-logic2; this design has the advantages of high speed, low power consumption, and high resolution.

[0191] CDAC2 is used to combine VREFP1, VREFN1, and VCM to V under the control of SAR-logic2. IN2+ Processing is performed to obtain the residual signal C_UP, which is then combined with VREFP1, VREFN1, and VCM to V under the control of SAR-logic2. IN2-The residual signal C_DN is obtained by processing.

[0192] Comp2 is used to process C_UP and C_DN under the control of SAR-logic2 to obtain comparison signals VOUTP2 and VOUTN2.

[0193] SAR-logic2 is used to obtain D<6:0> based on VOUTP2 and VOUTN2, and generate control signals for CDAC2 and Comp2.

[0194] Specifically, the various parts of the second-stage SAR-ADC section can be designed as follows:

[0195] I. CDAC2 includes: 4 capacitor arrays C501~C504, 4 switch arrays S501~S504, 2 sampling switches S401~S402, 4 single-pole triple-throw switches SW11~14, and 4 capacitors C505~C508;

[0196] S501~S504 each include 7 single-pole triple-throw switches, and the switching is controlled by SAR-logic2;

[0197] SW11~SW14 are also switched by SAR-logic2;

[0198] C501~C504 each includes 7 capacitors;

[0199] Among them, the first ends of the 7 capacitors of C501 are connected to VCM through S401; the first ends of the 7 capacitors of C501 are also connected to C_UP;

[0200] The second end of the mth capacitor of C501 is connected to V IN2+ , VREFP1, VREFN1; m∈[1,7];

[0201] The first ends of the seven capacitors C502 are connected to VCM through S401; the second ends of the seven capacitors C502 are also connected to C_UP;

[0202] The second end of the mth capacitor of C502 is connected to V IN2+ , VREFP1, VREFN1;

[0203] The first ends of the seven capacitors of C503 are connected to VCM through S402; the first ends of the seven capacitors of C502 are also connected to C_DN;

[0204] The second end of the mth capacitor of C503 is connected to V IN2-, VREFP1, VREFN1;

[0205] The first ends of the seven capacitors C504 are connected to VCM through S402; the second ends of the seven capacitors C504 are also connected to C_DN;

[0206] The second end of the mth capacitor of C504 is connected to V IN2- , VREFP1, VREFN1;

[0207] The first end of C505 is connected to VCM via S401, and the first end of C505 is also connected to C_UP;

[0208] The second end of C505 is connected to V IN2+ , VREFP1, VREFN1;

[0209] The first end of C506 is connected to VCM via S401, and the first end of C506 is also connected to C_UP;

[0210] The second end of C506 is connected to V IN2+ , VREFP1, VREFN1;

[0211] The first end of C507 is connected to VCM via S402, and the first end of C507 is also connected to C_DN;

[0212] The second end of C507 is connected to V IN2- , VREFP1, VREFN1;

[0213] The first end of C508 is connected to VCM via S401, and the first end of C508 is also connected to C_DN;

[0214] The second end of C508 is connected to V IN2- , VREFP1, VREFN1;

[0215] It should be noted that:

[0216] The capacitance values of the seven capacitors in C505 and C501 are Cu, Cu, 2Cu, 4Cu, 8Cu, 16Cu, 32Cu, and 64Cu respectively;

[0217] The capacitance values of the seven capacitors in C506 and C502 are Cu, Cu, 2Cu, 4Cu, 8Cu, 16Cu, 32Cu, and 64Cu respectively;

[0218] The capacitance values of the seven capacitors in C507 and C503 are Cu, Cu, 2Cu, 4Cu, 8Cu, 16Cu, 32Cu, and 64Cu respectively;

[0219] The capacitance values of the seven capacitors in C508 and C504 are Cu, Cu, 2Cu, 4Cu, 8Cu, 16Cu, 32Cu, and 64Cu respectively.

[0220] This makes it convenient to use the ADC comparison dichotomy method in conjunction with Comp2 and SAR-logic2 for quantization.

[0221] Ⅱ. The positive input terminal of Comp2 is connected to C_UP, the negative input terminal is connected to C_DN, the timing control terminal is connected to the control signal CLK3, the positive output terminal is used to output VOUTP2, and the negative output terminal is used to output VOUTN2.

[0222] Similar to the design concept of Comp1, Comp2 can adopt Figure 10 The designed two-stage structure primarily consists of a pre-amplifier, Pre-amp-2, and a comparator, Latch-2. Pre-amp-2 pre-amplifies C_UP and C_DN before feeding them into Latch-2 for processing. Latch-2 then compares the signals to produce VOUTP2 and VOUTN2. This allows amplification even when the difference between C_UP and C_DN is minimal. This prevents situations where Latch-2 fails to resolve the result within the specified timeframe, or where the resolution is too slow or takes too long, thus ensuring that Comparator 2 can meet high-speed requirements.

[0223] See Figure 10 Pre-amp-2 includes: 5 PMOS transistors M301~M305; the source of M301 is connected to VDD, the gate is connected to the timing signal CLK3N, and the drain is connected to the sources of M302 and M303; the gate of M302 is connected to C_UP; the gate of M303 is connected to C_DN; the drain of M302 is connected to the drain of M304; the drain of M303 is connected to the drain of M305; the gates of M304 and M305 are connected to CLK3N; the sources of M304 and M305 are grounded.

[0224] Latch-2 includes: 7 PMOS transistors M306~M312; the gate of M306 is connected to the drain of M304; the sources of M306, M307, M308, and M309 are connected to VDD; M307, M308, M310, and M311 are cross-coupled; the drain of M306 is connected to the drain of M307 and is used to output VOUTP2; the drain of M309 is connected to the drain of M308 and is used to output VOUTN2; the sources of M310 and M311 are connected to the drain of M312; the gate of M312 is connected to CLK3, and the source is grounded.

[0225] In addition, CLK3 and CLK3N are opposite signals: an inverter INV4 can be set in Comp2; CLK3 is connected to the input end of INV4, and the output end of INV4 is used to output CLK3N.

[0226] Comp1 based on the above structure works as follows:

[0227] First, CLK3 is 1, and Pre-amp-2 is reset first; M304 and M305 are turned on as reset transistors, so that the drains of M302 and M303 are connected to GND and become the same potential, so that Pre-amp-2 can quickly perform voltage resolution in the next comparison;

[0228] M302 and M303 receive C_UP and C_DN and perform pre-amplification. The differential output results XP1 (transmitted from the drain of M302 to the gate of M306) and XN1 (transmitted from the drain of M303 to the gate of M309) are passed to Latch-2;

[0229] Since C_UP and C_DN are of different sizes, the size difference between XP1 and XN1 is even greater, which will lead to different operating currents of M306 and M305, and the charging and discharging speeds of the two output branches where the two tubes are located will also be different; after the positive feedback of M307, M308, M310, and M311, one of VOUTP2 and VOUTN2 will eventually be pulled up to VDD and the other will be pulled down to GND.

[0230] Therefore, Comp2 can achieve fast, high-precision and accurate comparison functions:

[0231] ① The introduction of Pre-amp-2 improves resolution and reduces the probability of error;

[0232] ② The Pre-amp-2 PMOS transistor is used as the input pair transistor. Compared with the NMOS transistor, it is faster and produces less noise. It can also connect the substrate and source to eliminate the body effect and stabilize the threshold voltage. It is more suitable for the second-stage SAR-ADC part to process small residual voltage signals for comparison.

[0233] ③ The number of stacked MOS tubes in the traditional comparator circuit is reduced, which allows it to operate at a lower power supply voltage and reduce power consumption;

[0234] ④ The two-stage separation circuit structure disconnects the parasitic capacitance connection between the output and input, effectively eliminating kickback noise, reducing comparator noise, and reducing input offset voltage.

[0235] In general, using PMOS transistors as input transistors is faster and produces less noise than NMOS transistors, and the substrate and source can be connected to eliminate the body effect and stabilize the threshold voltage.

[0236] III, SAR-logic2 uses asynchronous SAR logic to increase conversion speed.

[0237] Specifically, input terminal 1 of SAR-logic2 is connected to VOUTP2, input terminal 2 is connected to VOUTN2, the code value output terminal is used to output D<6:0>, switch control terminal 1 is used to output control signals for S501~S504, switch control terminal 2 is used to output control signals for SW11~SW14, and the comparison control terminal is used to output CLK3.

[0238] Note that SAR-logic2's switch control terminal 1 outputs not just one control signal, but four signals: one signal for each single-pole, triple-throw switch (S501-S504). Similarly, SAR-logic2's switch control terminal 2 outputs not just one control signal, but four signals: one signal for each of SW11-SW14.

[0239] The second-stage SAR-ADC section works in a similar way to the first-stage SAR-ADC section:

[0240] Entering the sampling state: first turn on S401 and S402, connect the first ends of C501~C504 and C505~C508 to VCM, and start sampling; SAR-logic2 controls S401 and S402 to switch, so that the second ends of C501 and C502 are connected to V IN2+ , connect the second end of C503 and C504 to V IN2- SAR-logic2 controls Comp2 to reset, VOUTP2 and VOUTN2 are low level;

[0241] After sampling is completed, the system enters the set state: S401 and S402 are disconnected, and SAR-logic2 controls S501 and S502 to switch, so that the second ends of C501 and C503 are connected to VREFN1, and the second ends of C502 and C504 are connected to VREFP1; according to the law of charge conservation, the charge on the capacitor array will be redistributed, and C_UP and C_DN will be regained.

[0242] After the set state, the quantization period begins: SAR-logic2 controls Comp2 to compare C_UP and C_DN at this time. On the one hand, SAR-logic2 internally quantizes to obtain the highest bit of D2<6:0>, and on the other hand, adjusts the voltage connected to the capacitor with a capacitance value of 64Cu in the capacitor array according to the comparison result; if C_UP>C_DN, SAR-logic2 controls S502 and S503 to switch, so that the second end of the capacitor with a capacitance value of 64Cu in C502 is connected to VREFN1, and the second end of the capacitor with a capacitance value of 64Cu in C503 is connected to VREFP; if C_UP<C_DN, SAR-logic2 controls S501 and S504 to switch, so that the second end of the capacitor with a capacitance value of 64Cu in C501 is connected to VREFP1, and the second end of the capacitor with a capacitance value of 64Cu in C504 is connected to VREFN1. After the connection is changed, according to the law of charge conservation, the charge on the capacitor array is redistributed, and C_UP and C_DN are restored. SAR-Logic2 then controls Comp2 to compare C_UP and C_DN again. SAR-Logic2 internally quantizes the second-highest bit of D2<6:0> and, based on the comparison result, adjusts the voltage connected to the 32Cu capacitor in the capacitor array. If C_UP > C_DN, SAR-Logic2 controls S502 and S503 to connect the second end of the 32Cu capacitor in C502 to VREFN1, and the second end of the 32Cu capacitor in C503 to VREFP1. If C_UP < C_DN, SAR-Logic2 controls S501 and S504 to connect the second end of the 32Cu capacitor in C501 to VREFP1, and the second end of the 32Cu capacitor in C504 to VREFN1. This process continues in this order until all seven bits of D2<6:0> are obtained.

[0243] It should be noted that C505~C508 are only dummy capacitors used to adjust the weight:

[0244] When the second-stage SAR-ADC is sampling, SAR-logic2 controls SW11~SW14 to switch, so that C505~C506 are connected to V IN2+ , connect C507~C508 to V IN2+ When the second-stage SAR-ADC part performs quantization, SAR-logic2 controls SW11~SW14 to switch, so that C505 and C507 are connected to VREFN1, and C506 and C508 are connected to VREFP1.

[0245] The design and control ideas of the second-stage SAR-ADC unit are similar to those of the first-stage SAR-ADC unit, and can also achieve high speed, low power consumption and high resolution.

[0246] It should also be noted that the gain effect of the MDAC section (i.e., inter-stage gain) is determined by the quantization accuracy of the first-stage SAR-ADC section, the quantization accuracy of the second-stage SAR-ADC section, and the number of redundant bits.

[0247] In the first embodiment, the redundant bit is one. Thus, the reference voltages VREFN1 and VREFP1 of the second-stage SAR-ADC section can be reduced to half of VREFN and VREFP, respectively, by utilizing the inter-stage gain, thereby reducing the power consumption of the second-stage SAR-ADC section.

[0248] 5. The redundant calibration section is designed to perform redundant calibration to eliminate possible quantization errors.

[0249] After the first-stage SAR-ADC completes quantization of the 6-bit digital code D1<12:7>, it is stored. After the second-stage SAR-ADC completes quantization of the 7-bit digital code D2<6:0>, it is also stored. As mentioned above, because the first-stage SAR-ADC includes a redundant bit, D1<12:7> and D2<6:0> require staggered addition. Furthermore, because the second-stage SAR-ADC does not have a full rail-to-rail quantization range, the offset error (000000100000) must be subtracted from the staggered addition of the two digital codes.

[0250] That is, see Figure 11 The method for the redundant calibration unit to perform redundant calibration includes:

[0251] First, shift D1<12:7> down one position, add it to D2<6:0>, and then subtract the offset error 000000100000 to get D<11:0>;

[0252] Where D1<12:7>=H 12 H 11 H 10 H9H8H7;D2<6:0>=L6L5L4L3L2L1L0;

[0253] D<11:0>=D 11 D 10 D9D8D7D6D5D4D3D2D1D0;

[0254] D<11:0>=H 12 H 11 H 10 H9H8H7000000+00000L6L5L4L3L2L1L0-000000100000;

[0255] Where H 12 、H 11 、H 10 , H9, H8, H7 represent the 6 bits of D1<12:7>;

[0256] L6, L5, L4, L3, L2, L1, L0 represent the 7 bits of D2<6:0>;

[0257] D 11 、D 10 , D9, D8, D7, D6, D5, D4, D3, D2, D1, D0 represent the 12 bits of D<11:0>.

[0258] So far, the entire process of the Pipe-SAR-ADC circuit has been completed, and the V signal 12-bit quantization.

[0259] The Pipe-SAR-ADC circuit proposed in this embodiment 1 has advantages in power consumption, speed, and resolution, and has good application prospects.

[0260] Example 2

[0261] This embodiment 2 discloses a high-speed Pipe-SAR-ADC module for CIS, which adopts the layout of the high-speed Pipe-SAR-ADC circuit for CIS disclosed in embodiment 1. The module packaging mode makes it easier to promote and apply the above circuit.

[0262] This embodiment 2 also discloses a CIS module, which includes the high-speed Pipe-SAR-ADC module for CIS disclosed above. Integrating the high-speed Pipe-SAR-ADC module for CIS into the CIS module also facilitates the promotion and application of the above circuit.

[0263] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0264] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A high-speed Pipe-SAR-ADC circuit for CIS, characterized in that: It includes: CDS-PGA part, which is used to combine the reference voltage VREFP and VREFN to input signal V signal Perform sampling and holding, gain amplification, and introduce a fixed offset ΔV to obtain the differential signal V OP 、V ON ;Where, ΔV=VREFP-VREFN; The CDS-PGA section includes an upsampling subsection, a downsampling subsection, and a gain amplification subsection. The up-sampling subsection is used to combine VREFP with the V signal Sampling is performed to obtain the sampling voltage V UP ; The down sampling subsection is used to combine VREFN with the V signal Sampling is performed to obtain the sampling voltage V DN ; The gain amplifier section is used to adjust the V UP 、V DN Perform adjustable gain amplification to obtain V OP 、V ON ; Among them, V DN -V UP =(V exp -V reset )+ λ ΔV; where V exp V represents the exposure stage signal ; V reset Represents the reset phase V signal ; λ represents the offset coefficient; The first stage SAR-ADC part is used to combine VREFP, VREFN, common mode voltage VCM to V OP 、V ON 6-bit quantization is performed to obtain a 6-bit numerical code D1<12:7> and residual signals CAP_UP and CAP_DN. The first-stage SAR-ADC section includes: a CDAC circuit section CDAC1, a comparator Comp1, and a SAR logic section SAR-logic1. CDAC1 is used to: combine VREFP, VREFN, and VCM to V under the control of SAR-logic1. OP Processing is performed to obtain CAP_UP, and VREFP, VREFN, and VCM are combined under the control of SAR-logic1 to ON Processing to obtain CAP_DN; Comp1 is used to: process CAP_UP, CAP_DN, and VCM under the control of SAR-logic1 to obtain comparison signals VOUTP1 and VOUTN1; SAR-logic1 is used to: obtain D<12:7> based on VOUTP1 and VOUTN1, and generate control signals for CDAC1 and Comp1; The MDAC part is used to amplify CAP_UP and CAP_DN in combination with VCM to obtain the amplified signal V IN2+ 、V IN2- The MDAC section includes: 10 switches S901-S910, 2 capacitors C31-C32, and 1 residual amplifier OPA2; CAP_DN is connected to the first end of S901, and the second end of S901 is connected to the negative input end of OPA2; VCM is connected to the second end of S901 through S903; CAP_UP passes through the first end of S902, and the second end of S902 is connected to the positive input terminal of OPA2; VCM is connected to the second end of S902 through S904; The positive output terminal of OPA2 is used to output V IN2- , the negative output terminal is used to output V IN2+ ; The positive output of OPA2 is connected to the negative input of OPA2 through S905; The positive output of OPA2 is connected to the first end of C32 and the first end of S909 through S907; VCM is connected to the second end of S909; the second end of C32 is connected to the negative input of OPA2; The negative output of OPA2 is connected to the positive input of OPA2 through S906; The negative output terminal of OPA2 is connected to the first terminal of C31 and the first terminal of S910 through S908; VCM is connected to the second terminal of S910; the second terminal of C31 is connected to the positive input terminal of OPA2; The second stage SAR-ADC part is used to combine the reference voltage VREFP1, VREFN1, VCM to V IN2+ 、V IN2- 7-bit quantization is performed to obtain a 7-bit numerical code D2<6:0>; the second-stage SAR-ADC section includes: a CDAC circuit section CDAC2, a comparator Comp2, and a SAR logic section SAR-logic2; CDAC2 is used to: combine VREFP1, VREFN1, and VCM to V under the control of SAR-logic2 IN2+ Processing is performed to obtain the residual signal C_UP, which is then combined with VREFP1, VREFN1, and VCM under the control of SAR-logic2. IN2- Comp2 is used to process C_UP and C_DN under the control of SAR-logic2 to obtain comparison signals VOUTP2 and VOUTN2. SAR-logic2 is used to obtain D<6:0> based on VOUTP2 and VOUTN2, and generate control signals for CDAC2 and Comp2. as well as A redundancy calibration unit, configured to perform redundancy calibration based on D1<12:7> and D2<6:0> to obtain a final 12-bit digital code D<11:0>; The method for the redundant calibration unit to perform redundant calibration includes: First, shift D1<12:7> down one position, add it to D2<6:0>, and then subtract the offset error 000000100000 to get D<11:0>; Where D1<12:7>=H 12 H 11 H 10 H9H8H7;D2<6:0>=L6L5L4L3L2L1L0; <h2 style=";text-align:left;direction:ltr">D<11:0>=D<h2 style=";text-align:left;direction:ltr"> 11 <h2 style=";text-align:left;direction:ltr"> D<h2 style=";text-align:left;direction:ltr"> 10 <h2 style=";text-align:left;direction:ltr"> D9D8D7D6D5D4D3D2D1D0; D<11:0>=H 12 H 11 H 10 H9H8H7000000+00000L6L5L4L3L2L1L0-000000100000; Where H 12 、H 11 、H 10 , H9, H8, H7 represent the 6 bits of D1<12:7>; L6, L5, L4, L3, L2, L1, L0 represent the 7 bits of D2<6:0>; D 11 、D 10 , D9, D8, D7, D6, D5, D4, D3, D2, D1, D0 represent the 12 bits of D<11:0>; The high-speed Pipe-SAR-ADC circuit for CIS utilizes multiplexing to process pixel signals of different columns.

2. The high-speed Pipe-SAR-ADC circuit for CIS according to claim 1, characterized in that: The upsampling subsection includes: 4 switches S101 to S104, 1 switch S109, 1 switch SR1, 1 switch SRN1, and 3 capacitors C11 to C13; The downsampling subsection includes: 4 switches S105-S108, 1 switch S110, 1 switch SR2, 1 switch SRN2, and 3 capacitors C21-C23; The gain amplifier section includes: 1 operational amplifier OPA1, 2 capacitors C14~C15, 2 capacitors C24~C25, 2 switches SN109~SN110, and 2 switches SR3~SR4; Among them, the first end of C11~C13 is connected to V through S101. signal , the first end is connected to the negative input terminal of OPA1 through S109; The second end of C11 is connected to the first end of S102 and the first end of SRN1; the second end of S102 is grounded; The second end of C12 is connected to the second end of SRN1 and the first end of SR1; The second end of C13 is connected to the second end of SR1, the first end of S104, and the first end of S103; the second end of S104 is grounded; the second end of S103 is connected to VREFP; The first ends of C21~C23 are connected to V through S105 signal , the first end is connected to the positive input terminal of OPA1 through S110; The second end of C21 is connected to the first end of S106 and the first end of SRN2; the second end of S106 is grounded; The second end of C22 is connected to the second end of SRN2 and the first end of SR2; The second end of C23 is connected to the second end of SR2, the first end of S107, and the first end of S108; the second end of S108 is grounded; the second end of S107 is connected to VREFN; The positive output terminal of OPA1 is used to output V OP , the negative output terminal is used to output V ON ; The first ends of C14 and SN109 are connected to the positive output of OPA1, and the second ends are connected to the negative input of OPA1; the first end of C15 is connected to the positive output of OPA1, and the second end is connected to the first end of SR3; the second end of SR3 is connected to the negative input of OPA1; The first ends of C24 and SN110 are connected to the negative output of OPA1, and the second ends are connected to the positive input of OPA1; the first end of C25 is connected to the negative output of OPA1, and the second end is connected to the first end of SR4; the second end of SR4 is connected to the positive input of OPA1; Among them, the capacitance values of C11 and C21 are the same; the capacitance values of C12 and C22 are the same; the capacitance values of C13 and C23 are the same; λ =(C12+C13) / (C11+C12+C13).

3. The high-speed Pipe-SAR-ADC circuit for CIS according to claim 1, characterized in that: CDAC1 includes: 4 groups of capacitor arrays C301~C304, 4 groups of switch arrays S301~S304, 2 sampling switches S201~S202, 4 single-pole triple-throw switches SW1~SW4, and 4 capacitors C305~C308; S301~S304 each include 6 single-pole triple-throw switches, and the switching is controlled by SAR-logic1; SW1~SW4 are also switched by SAR-logic1; C301~C304 each includes 6 capacitors; Among them, the first ends of the six capacitors of C301 are connected to VCM through S201; the first ends of the six capacitors of C301 are also connected to CAP_UP; The second end of the nth capacitor of C301 is connected to V OP , VREFP, VREFN; n∈[1,6]; The first ends of the six capacitors C302 are connected to VCM through S201; the second ends of the six capacitors C302 are also connected to CAP_UP; The second end of the nth capacitor of C302 is connected to V OP , VREFP, VREFN; The first ends of the six capacitors C303 are connected to VCM through S202; the first ends of the six capacitors C303 are also connected to CAP_DN; The second end of the nth capacitor of C303 is connected to V ON , VREFP, VREFN; The first ends of the six capacitors C304 are connected to VCM through S202; the first ends of the six capacitors C304 are also connected to CAP_DN; The second end of the nth capacitor of C304 is connected to V ON , VREFP, VREFN; The first end of C305 is connected to VCM through S201, and the first end of C305 is also connected to CAP_UP; The second end of C305 is connected to V OP , VREFP, VREFN; The first end of C306 is connected to VCM through S201, and the first end of C306 is also connected to CAP_UP; The second end of C306 is connected to V OP , VREFP, VREFN; The first end of C307 is connected to VCM via S202, and the first end of C307 is also connected to CAP_DN; The second end of C307 is connected to V ON , VREFP, VREFN; The first end of C308 is connected to VCM via S201, and the first end of C308 is also connected to CAP_DN; The second end of C308 is connected to V ON , VREFP, VREFN.

4. The high-speed Pipe-SAR-ADC circuit for CIS according to claim 1, wherein: Comp1 includes: pre-amplifier Pre-amp-1, comparison part Latch-1; Pre-amp-1 is used to pre-amplify CAP_UP and CAP_DN before sending them to Latch-1 for processing; Latch-1 is used to perform signal comparison to obtain VOUTP1 and VOUTN1; Pre-amp-1 includes seven NMOS transistors M208 to M214. The sources of M208 and M209 are connected to VDD. The gates of M208 and M209 are connected to the control signal CLK2. The drain of M208 is connected to the drains of M210 and M211. The drain of M209 is connected to the drains of M212 and M213. The gate of M210 is connected to CAP_UP. The gate of M211 is connected to VCM. The gate of M212 is connected to VCM. The gate of M213 is connected to CAP_DN. The sources of M210, M211, M212, and M213 are connected to the drain of M214. The gate of M214 is connected to CLK2. The source of M214 is grounded. Latch-1 includes: 7 NMOS transistors M201~M207, 2 inverters INV1~INV2; the source of M201 is connected to VDD; the gate of M201 is connected to the timing signal CLK2N; the drain of M201 is connected to the sources of M202 and M203; M202, M203, M205, and M206 are cross-coupled; The gate of M202, the gate of M205, the drain of M203, and the drain of M206 are connected together; the gate of M203, the gate of M206, the drain of M202, and the drain of M205 are connected together; The drain of M202 is connected to the input of INV1 and the drain of M204; the output of INV1 is used to output VOUTP1; the drain of M203 is connected to the input of INV2 and the drain of M207; the output of INV2 is used to output VOUTN1; the sources of M204, M205, M206, and M207 are grounded; the gate of M204 is connected to the source of M208; the gate of M207 is connected to the source of M209; CLK2 and CLK2N are opposite signals.

5. The high-speed Pipe-SAR-ADC circuit for CIS according to claim 1, wherein: OPA2 includes: 17 NMOS transistors M1~M17, 4 capacitors C401~C404, 2 auxiliary amplifiers A1~A2, and 1 current source I1; The input signal of the positive input terminal of OPA2 is VIP, the input signal of the negative input terminal is VIN, the output signal of the positive output terminal is VOP, and the output signal of the negative output terminal is VON; the gate of M1 is connected to VIP; the gate of M2 is connected to VIN, and the source is connected to the drain of M3; the gate of M3 is connected to the voltage signal Vbp1, and the drain is connected to VDD; the gate of M4 is connected to Vbp1, and the source is connected to VDD; the gate of M5 is connected to Vbp1, and the source is connected to VDD; the source of M6 is connected to the drain of M4; the source of M7 is connected to the drain of M5; A1 The negative input terminal is connected to the drain of M4, the positive input terminal is connected to the drain of M5, the positive output terminal is connected to the gate of M7, the negative output terminal is connected to the gate of M6, and the reference terminal is connected to the voltage signal Vcmn; the first terminal of C401 is connected to the gate of M6, and the second terminal is connected to the drain of M6; the first terminal of C402 is connected to the gate of M7, and the second terminal is connected to the drain of M7; the drain of M8 is connected to the drain of M6; the drain of M9 is connected to the drain of M7; the gate of M10 is connected to the voltage signal Vcmc, the source is grounded, and the drain is connected to the drain of M1 and the source of M8; the gate of M11 Connect to Vcmc, the source is grounded, the drain is connected to the drain of M2 and the source of M9; the negative input of A2 is connected to the drain of M11, the positive input is connected to the drain of M10, the positive output is connected to the gate of M8, the negative output is connected to the gate of M9, the reference terminal 1 is connected to the voltage signal Vcmp, and the reference terminal 2 is connected to the voltage signal bn1; the first end of C403 is connected to the gate of M8, and the second end is connected to the drain of M8; the first end of C404 is connected to the gate of M9, and the second end is connected to the drain of M9; the source of M12 is grounded; the gate and drain of M12 are connected to the voltage Signal Vbn; one end of I1 is connected to the drain of M12, and the other end is connected to VDD; the gate of M13 is connected to the drain of M6, the source is connected to VDD, and the drain is connected to VON; the gate of M14 is connected to the gate of M13, the source is connected to the drain of M17, and the drain is connected to VON; the gate of M15 is connected to the drain of M7, the source is connected to VDD, and the drain is connected to VOP; the gate of M16 is connected to the gate of M15, and the drain is connected to VOP; the gate of M17 is connected to the voltage signal Vcmd, the source is grounded, and the drain is connected to the source of M14 and the source of M16; Among them, Vbp1, Vcmn, and Vcmp are all bias corrections; Vcmc, Vcmd, Vbn, and bn1 are all correction voltages.

6. The high-speed Pipe-SAR-ADC circuit for CIS according to claim 1, characterized in that: CDAC2 includes: 4 capacitor arrays C501~C504, 4 switch arrays S501~S504, 2 sampling switches S401~S402, 4 single-pole triple-throw switches SW11~14, and 4 capacitors C505~C508; S501~S504 each include 7 single-pole triple-throw switches, and the switching is controlled by SAR-logic2; SW11~SW14 are also switched by SAR-logic2; C501~C504 each includes 7 capacitors; Among them, the first ends of the 7 capacitors of C501 are connected to VCM through S401; the first ends of the 7 capacitors of C501 are also connected to C_UP; The second end of the mth capacitor of C501 is connected to V IN2+ , VREFP1, VREFN1; m∈[1,7]; The first ends of the seven capacitors of C502 are connected to VCM through S401; the first ends of the seven capacitors of C502 are also connected to C_UP; The second end of the mth capacitor of C502 is connected to V IN2+ , VREFP1, VREFN1; The first ends of the seven capacitors of C503 are connected to VCM through S402; the first ends of the seven capacitors of C503 are also connected to C_DN; The second end of the mth capacitor of C503 is connected to V IN2- , VREFP1, VREFN1; The first ends of the seven capacitors C504 are connected to VCM through S402; the first ends of the seven capacitors C504 are also connected to C_DN; The second end of the mth capacitor of C504 is connected to V IN2- , VREFP1, VREFN1; The first end of C505 is connected to VCM via S401, and the first end of C505 is also connected to C_UP; The second end of C505 is connected to V IN2+ , VREFP1, VREFN1; The first end of C506 is connected to VCM via S401, and the first end of C506 is also connected to C_UP; The second end of C506 is connected to V IN2+ , VREFP1, VREFN1; The first end of C507 is connected to VCM via S402, and the first end of C507 is also connected to C_DN; The second end of C507 is connected to V IN2- , VREFP1, VREFN1; The first end of C508 is connected to VCM via S402, and the first end of C508 is also connected to C_DN; The second end of C508 is connected to V IN2- , VREFP1, VREFN1.

7. The high-speed Pipe-SAR-ADC circuit for CIS according to claim 1, characterized in that: Comp2 includes: pre-amplifier Pre-amp-2, comparison part Latch-2; Pre-amp-2 is used to pre-amplify C_UP and C_DN before sending them to Latch-2 for processing; Latch-2 is used to perform signal comparison to obtain VOUTP2 and VOUTN2; Pre-amp-2 includes five PMOS transistors, M301 to M305. M301's source is connected to VDD, its gate is connected to the timing signal CLK3N, and its drain is connected to the sources of M302 and M303. M302's gate is connected to C_UP. M303's gate is connected to C_DN. M302's drain is connected to M304's drain. M303's drain is connected to M305's drain. M304 and M305's gates are connected to CLK3N. M304 and M305's sources are grounded. Latch-2 includes: 7 PMOS transistors M306 to M312; the gate of M306 is connected to the drain of M304; the sources of M306, M307, M308, and M309 are connected to VDD; M307, M308, M310, and M311 are cross-coupled; The gate of M307, the gate of M310, the drain of M308, and the drain of M311 are connected together; the gate of M308, the gate of M311, the drain of M307, and the drain of M310 are connected together; The drain of M306 is connected to the drain of M307 and is used to output VOUTP2; the drain of M309 is connected to the drain of M308 and is used to output VOUTN2; the sources of M310 and M311 are connected to the drain of M312; the gate of M312 is connected to the control signal CLK3, and the source is grounded; CLK3 and CLK3N are opposite signals.

8. A high-speed Pipe-SAR-ADC module for CIS, characterized in that: It adopts the layout of the high-speed Pipe-SAR-ADC circuit for CIS as claimed in any one of claims 1 to 7.

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