A data converter based on voltage-controlled oscillator and implementation method thereof

Abstract

The present invention discloses a data converter based on a voltage-controlled oscillator and an implementation method thereof. The data converter based on a voltage-controlled oscillator implemented by the present invention includes a sampling circuit, a multi-bit successive approximation data converter and a multi-bit multi-order Delta-Sigma data converter; the incremental scaling data converter based on the voltage-controlled oscillator is improved, and a feedforward compensation method suitable for the voltage-controlled oscillator is designed, which makes full use of the characteristics of the Delta-Sigma data converter clock, first adds the feedforward phase to the total differential phase of the voltage-controlled oscillator, and subtracts it after quantization, thereby equivalently realizing the feedforward compensation in the phase domain. The present invention does not introduce a new timing sequence, and the implementation cost is low; and the voltage-controlled oscillator is completely isolated from the sensitive nodes in the circuit, avoiding kickback noise; the present invention can more simply construct a high-efficiency data converter based on a voltage-controlled oscillator, which can be widely used in the fields of the Internet of Things, smart medical care, etc.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and relates to data converter design technology, and in particular to a high-energy-efficiency data converter based on a voltage-controlled oscillator and an implementation method thereof. Background Art

[0002] Under advanced technology, the intrinsic gain of transistors gradually decreases, and the power supply voltage gradually decreases, making it increasingly difficult to design high-performance operational transconductance amplifiers and comparators. Transistors with advanced technology have higher cutoff frequencies. The time-domain data conversion system uses time-domain variables (such as frequency and phase) to process analog signals by building some simple digital modules (such as inverters), making full use of the advantages of advanced technology and having high energy efficiency. As a typical time-domain data converter, the data converter based on voltage-controlled oscillator has received widespread attention.

[0003] The data converter based on voltage-controlled oscillator has the following advantages: 1) The voltage-controlled oscillator is a digital structure that can work normally at a lower power supply voltage and consume less power; 2) The voltage-controlled oscillator has the characteristic of intrinsic phase domain integration, has infinite DC gain in the phase domain, is not limited by the intrinsic gain of the transistor, and can build a more ideal integrator; 3) The voltage-controlled oscillator has an intrinsic phase domain quantization characteristic, and low-cost multi-bit quantization can be achieved through a trigger, avoiding the need for a low-offset comparator in the oversampling system of multi-bit quantization.

[0004] However, some application scenarios such as the Internet of Things and smart healthcare often require the use of high-order noise-shaping time-domain data converters to complete analog signal processing, and high-order loops require compensation technology to ensure loop stability. Feedforward compensation is a common compensation technology with the advantages of high linearity and low hardware overhead, but the integration and quantization functions of the voltage-controlled oscillator are both performed in the phase domain, and the two are tightly coupled together, making it difficult for data converters based on voltage-controlled oscillators to achieve loop stability through feedforward compensation.

[0005] Therefore, it is currently difficult to design a high-efficiency voltage-controlled oscillator-based data converter suitable for the Internet of Things, smart medical care and other fields using existing technologies. Summary of the invention

[0006] In view of the problem that the high-order data converter based on the voltage-controlled oscillator in the above-mentioned prior art is difficult to feedforward compensate, the present invention provides a method for realizing a data converter based on the voltage-controlled oscillator with high energy efficiency, and specifically relates to a phase domain feedforward method for the data converter with high energy efficiency and low cost, and realizes loop stability through the feedforward compensation of the voltage-controlled oscillator. Through this technology, it is easier to build a data converter based on the voltage-controlled oscillator with high energy efficiency (such as an analog-to-digital converter, a capacitive sensor readout circuit, etc.), which is suitable for application scenarios such as the Internet of Things and smart medical care.

[0007] The technical solution of the present invention is:

[0008] An incremental scaling data converter based on a voltage-controlled oscillator first adds a feedforward phase to the total differential phase of the voltage-controlled oscillator and then subtracts it after quantization, thereby equivalently realizing feedforward compensation in the phase domain and achieving loop stability through feedforward compensation of the voltage-controlled oscillator.

[0009] The incremental scaling data converter system based on a voltage-controlled oscillator of the present invention comprises: a sampling circuit, a multi-bit successive approximation (SAR) data converter, and a multi-bit multi-order Delta-Sigma data converter. The sampling circuit completes the sampling and conversion of the analog signal; the SAR data converter is used as the first stage of the data conversion system to complete the coarse quantization of the analog signal; the Delta-Sigma data converter is used as the second stage of the data conversion system to complete the fine quantization of the analog signal. The multi-bit SAR data converter and the multi-bit multi-order Delta-Sigma data converter share a digital-to-analog converter (DAC), which is composed of two capacitor arrays with different encoding methods. The entire data conversion system works in two steps. First, a coarse quantization is performed, and the DAC corresponding to the multi-bit SAR is switched, which is called a coarse quantization DAC. Then, several fine quantizations are performed, and the DAC corresponding to the multi-bit multi-order Delta-Sigma data converter is switched, which is called a fine quantization DAC.

[0010] The specific components of the incremental scaling data converter based on the voltage-controlled oscillator proposed by the present invention are described in detail below.

[0011] A. Sampling Circuit

[0012] In specific implementation, the data converter of the present invention realizes the corresponding sampling circuit front end according to the specific application scenario. For example, for the analog-to-digital conversion system, the sampling switch and the DAC shared by the multi-bit SAR data converter and the multi-bit multi-order Delta-Sigma data converter constitute the sampling circuit; for the capacitive sensor readout circuit, a capacitance-to-voltage converter can be built as the system front end to form a separate sampling circuit, or the sensing capacitor and the DAC can be connected in parallel to form a sampling circuit with the sampling switch.

[0013] B. Coarse Quantization SAR Data Converter

[0014] In specific implementation, the SAR data converter used in the present invention includes four parts: sampling circuit, coarse quantization DAC, comparator, and digital logic. The DAC top plate generates a differential voltage, the comparator determines the polarity of the differential voltage, and switches the capacitor corresponding to the DAC through digital logic. After multiple capacitor switching from large to small, the DAC top plate voltage is reduced to a suitable range.

[0015] C. Fine-scale Delta-Sigma Data Converter

[0016] In specific implementation, the Delta-Sigma data converter used in the present invention includes four parts: fine quantization DAC, loop filter, phase domain quantizer, and digital logic. When working, the input of the fine quantization Delta-Sigma data converter is the residual voltage after coarse quantization. The loop filter integrates and feeds forward the difference between the input voltage and the output of the fine quantization DAC. The phase domain quantizer is located after the loop filter, performs quantization, and switches the fine quantization DAC through digital logic to complete the closed loop. The specific details of the loop filter and the phase domain quantizer are as follows:

[0017] C1. Loop filter

[0018] The loop filter is composed of two stages of integrators, namely the first stage integrator (first stage loop filter) and the second stage integrator (second stage loop filter). The first stage integrator is a universal integrator that can be implemented as a highly energy-efficient open-loop integrator or a highly robust closed-loop integrator. The second stage integrator adopts a voltage-controlled oscillator structure, and utilizes the aforementioned characteristics of the voltage-controlled oscillator, such as low power consumption, infinite DC gain, and intrinsic multi-bit quantization, to improve the accuracy and energy efficiency of the data converter based on the voltage-controlled oscillator.

[0019] In a specific implementation, the voltage-controlled oscillator is in the form of a cascade of an operational transconductance amplifier and a current-controlled oscillator. The operational transconductance amplifier converts the input voltage into current, and the current-controlled oscillator maps the current to frequency and integrates it into phase information.

[0020] The high-order Delta-Sigma loop needs compensation to ensure loop stability. The present invention adopts feedforward compensation to improve system linearity and reduce the hardware cost of the system. It is specifically implemented as follows: the input transistor and capacitor of the operational transconductance amplifier are split into two parts, that is, the positive input end and the negative input end of the voltage-controlled oscillator each include 2 input transistors and input capacitors, the source electrodes of the 2 input transistors are connected, the drain electrodes are connected, and the gate is disconnected. The characteristics of the multi-bit multi-order Delta-Sigma data converter clock are used. In the half fine quantization cycle before phase quantization, the split input transistors are connected in parallel, and the split input capacitors are also connected in parallel. The capacitor top plate connects the gate of the input transistor. At this time, the split input transistors generate their own differential currents, and flow into the current-controlled oscillator at the same time, realizing the change of the total differential phase. In the half cycle after phase quantization, the two parallel capacitors are disassembled, and each of the positive input end and the negative input end of the voltage-controlled oscillator is used as the load capacitor of the first-stage integrator, and the remaining 1 capacitor of the positive input end and the negative input end is used for the realization of the feedforward path. At the same time, connect the gates of the input transistors at the positive and negative inputs of the voltage-controlled oscillator to the common-mode reference voltage (V CM ), which is equivalent to no differential current flowing through the current-controlled oscillator, and the gate of the other input transistor at the positive input and the negative input is cross-connected to the aforementioned capacitor that does not serve as the load of the first-stage integrator. The cross-connection is equivalent to generating input signals of equal magnitude and opposite polarity in this half-fine quantization cycle, thereby generating a differential phase of equal magnitude and opposite polarity to the previous half-cycle, which is subtracted from the total differential phase. That is, the phase change of each fine quantization cycle is divided into two parts, one part of which is permanently added to the total differential phase to achieve phase integration; the other part of the phase is first added to the total differential phase, and then quantized in the phase domain. After the quantization is completed, it is subtracted from the total differential phase, without any impact on the second-stage loop filter, which is equivalent to realizing a feedforward path from the second-stage loop filter input to the phase domain quantizer input. This implementation method completely isolates the voltage-controlled oscillator and the DAC, avoiding the kick-back noise from the voltage-controlled oscillator; at the same time, the ratio of the integrated phase and the fed-forward phase is the input current ratio of the current-controlled oscillator, that is, the size ratio of the split input transistors, so a more accurate ratio of the integral coefficient and the feed-forward coefficient can be achieved.

[0021] C2. Phase Domain Quantizer

[0022] In specific implementation, the phase domain quantizer uses a dual frequency detector to quantize the output of the voltage-controlled oscillator. The characteristics of the phase change of the voltage-controlled oscillator make the quantized digital code follow the change of the center frequency of the voltage-controlled oscillator and select the corresponding capacitor in the DAC. This characteristic is called intrinsic clock averaging (ICLA), which can solve the capacitor mismatch problem in fine-quantization DAC.

[0023] The implementation of the voltage-controlled oscillator-based data converter proposed by the present invention includes the following steps:

[0024] 1) Prepare a multi-bit SAR data converter, which includes four parts: sampling circuit, DAC, comparator, and digital logic unit. Structurally, a multi-bit SAR data converter is used as the coarse quantization stage of a voltage-controlled oscillator-based data converter system to coarsely quantize the input signal of the voltage-controlled oscillator-based data converter.

[0025] 2) Prepare a multi-bit multi-order Delta-Sigma data converter, which includes four parts: DAC, loop filter, phase domain quantizer, and digital logic unit. Among them, the DAC of the multi-bit multi-order Delta-Sigma data converter is a three-value DAC; the loop filter is composed of two stages of integrators, respectively called the first stage integrator (first stage loop filter) and the second stage integrator (second stage loop filter). The first stage integrator is a universal integrator, which can use a high-efficiency open-loop integrator or a more robust closed-loop integrator, and the second stage integrator uses a voltage-controlled oscillator; the phase domain quantizer uses a dual frequency detector and phase detector to perform multi-bit quantization in the phase domain; the digital logic converts the quantization result into a code that can be used by the three-value DAC.

[0026] 3) The multi-bit SAR data converter and the multi-bit multi-order Delta-Sigma data converter share a DAC component. The DAC component is composed of two parts of capacitor array top plates with different encoding methods connected together. The multi-bit SAR data converter and the multi-bit multi-order Delta-Sigma data converter each control a part of the DAC. Specifically, the two parts have different encoding methods. The DAC of the multi-bit SAR data converter is a binary DAC, that is, the digital code controlling the DAC has only two inputs, 0 and 1, which is called a coarse quantization DAC; the DAC of the multi-bit multi-order Delta-Sigma data converter is a three-value DAC, that is, the digital code controlling the DAC has three inputs, -1, 0 and 1, which is called a fine quantization DAC.

[0027] 4) Prepare a voltage-controlled oscillator with phase-domain feedforward control logic, where the voltage-controlled oscillator adopts a cascade structure of an operational transconductance amplifier and a current-controlled oscillator; the input transistor of the operational transconductance amplifier is split into two parts, the input capacitor is split into two parts, and the connection method of the input transistor gate is determined by the phase-domain feedforward control logic. Structurally, the voltage-controlled oscillator with phase-domain feedforward control logic is used as the second-stage integrator of a multi-bit multi-order Delta-Sigma data converter.

[0028] 5) A multi-bit SAR data converter is used as the first stage, a multi-bit multi-order Delta-Sigma data converter is used as the second stage, and the first stage data converter and the second stage data converter are connected through a DAC top plate to obtain an improved data converter based on a voltage controlled oscillator.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] The present invention provides a high-order Delta-Sigma data converter based on a voltage-controlled oscillator, wherein the voltage-controlled oscillator acts as a last-stage integrator, fully utilizing the characteristics of the voltage-controlled oscillator's digital structure, infinite DC gain, and low-cost multi-bit quantization, thereby improving the accuracy and energy efficiency of the data conversion system and enabling the data conversion system implementation method to be expanded to more advanced processes, and being suitable for application scenarios such as the Internet of Things and smart medical care.

[0031] The present invention provides a method for implementing feedforward compensation of the above-mentioned data converter based on a voltage-controlled oscillator. The timing characteristics of the Delta-Sigma data converter itself are fully utilized, and the two time periods corresponding to the high and low levels of the Delta-Sigma data converter clock are used to perform addition and subtraction of the phase domain integrator respectively, and phase domain quantization is performed after addition. In this way, feedforward compensation in the phase domain is equivalently performed to ensure the stability of the high-order loop. The present invention enables the data converter based on the voltage-controlled oscillator to take advantage of the feedforward compensation, i.e., smaller hardware cost and higher linearity.

[0032] The feedforward compensation scheme provided by the present invention has a higher matching degree and lower noise. Under this method, the ratio of the feedforward coefficient and the integral coefficient is the transconductance ratio of the input tube, that is, the size ratio of the transistor, so it has a higher matching degree, and the coefficient ratio fluctuates less during the production process. Furthermore, this method allows the subsequent integrator based on the voltage-controlled oscillator to be completely separated from the sensitive node in the data conversion system-the top plate of the capacitor digital-to-analog converter, avoiding the noise from the voltage-controlled oscillator from coupling to the top plate of the capacitor digital-to-analog converter through parasitic capacitance, reducing the kickback noise of the voltage-controlled oscillator, thereby improving the system accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1The figure is an overall structural diagram of a data converter based on a voltage-controlled oscillator according to the present invention.

[0034] Among them C S represents the input sensing capacitor, 9bSAR represents the first level of the entire data conversion system, i.e., the coarse quantization level, D1 is the output digital code of the coarse quantization level, D2 represents the output digital code of the fine quantization level, and D OUT The ICLA is the output digital code of the entire data converter system. It stands for Intrinsic Clocked Averaging, which is based on the intrinsic properties of the voltage-controlled oscillator and can solve the mismatch problem between components of the capacitive digital-to-analog converter.

[0035] Figure 2 The circuit structure diagram of the data converter based on the voltage-controlled oscillator of the present invention.

[0036] Among them G m2 It is an operational transconductance amplifier that converts the input voltage into current and is combined with a current-controlled oscillator to form a voltage-controlled oscillator.

[0037] Figure 3 It is a working timing diagram of the data converter based on the voltage-controlled oscillator of the present invention.

[0038] Among them, Φ S is the sampling clock, Φ SAR is the coarse quantization clock, Φ DSM is the fine quantization clock, Φ Chop is the chopping clock and OSR is the oversampling rate.

[0039] Figure 4 The figure is a working principle diagram of the feedforward compensation of the data converter based on the voltage-controlled oscillator of the present invention.

[0040] Among them, V IN is the input signal of the fine quantization level, that is, the residual signal after coarse quantization; k1 is the first-stage integrator coefficient, k2 is the second-stage integrator coefficient, k f is the feedforward coefficient of the second-stage integrator, k d is the feedback coefficient corresponding to the digital-to-analog converter, E q is the quantization noise injected by the phase domain quantizer, D2 is the fine quantization output digital code, G m -CCO is a loop filter based on a voltage-controlled oscillator; Φ1Φ2 are two phases corresponding to the high and low levels of the Delta-Sigma data converter clock.

[0041] Figure 5 The structure diagram of the feedforward compensation circuit of the voltage-controlled oscillator-based data converter of the present invention.

[0042] Among them, Gm1 is the first-stage integrator of the fine quantization stage, C 1p C 1n C 2p C 2n is the split capacitance, M k2 M kf is the input transistor of the loop filter based on the voltage controlled oscillator, which controls the oscillation frequency of the voltage controlled oscillator. diff,kf I diff,k2 They respectively represent the feedforward and integrated input differential current of the current controlled oscillator that constitutes the voltage controlled oscillator, and φ[i] represents the phase difference between the current controlled oscillators at both ends, which is equivalent to the output of the integrator based on the voltage controlled oscillator. DETAILED DESCRIPTION

[0043] The present invention will be further described below by way of embodiments in conjunction with the accompanying drawings, but the scope of the present invention is not limited in any way.

[0044] The invention provides an incremental scaling data converter based on a voltage-controlled oscillator, which realizes loop stability through feed-forward compensation of the voltage-controlled oscillator.

[0045] The incremental scaling data converter system based on a voltage-controlled oscillator of the present invention comprises: a sampling circuit, a multi-bit successive approximation (SAR) data converter, and a multi-bit multi-order Delta-Sigma data converter. The sampling circuit completes the sampling and conversion of the analog signal; the SAR data converter is used as the first stage of the data conversion system to complete the coarse quantization of the analog signal; the Delta-Sigma data converter is used as the second stage of the data conversion system to complete the fine quantization of the analog signal. The multi-bit SAR data converter and the multi-bit multi-order Delta-Sigma data converter share a digital-to-analog converter (DAC), which is composed of two capacitor arrays with different encoding methods. The entire data conversion system works in two steps. First, a coarse quantization is performed, and the DAC corresponding to the multi-bit SAR is switched, which is called a coarse quantization DAC. Then, several fine quantizations are performed, and the DAC corresponding to the multi-bit multi-order Delta-Sigma data converter is switched, which is called a fine quantization DAC.

[0046] The data converter based on the voltage-controlled oscillator provided by the present invention is specifically applied to the capacitance sensor readout circuit, such as Figure 1~Figure 3As shown, the application of the technology of the present invention makes it easier to construct a high-order scaling structure based on a voltage-controlled oscillator for the capacitive sensor readout circuit. The structure of the voltage-controlled oscillator makes the capacitive sensor readout circuit have higher energy efficiency; the high-order loop reduces the system quantization noise and improves the accuracy of the system; the intrinsic multi-bit quantization characteristics of the voltage-controlled oscillator enable the capacitive sensor readout circuit to have a smaller oversampling rate, thereby improving the measurement speed; the implementation of the phase domain feedforward compensation path improves the linearity and stability of the system at a very low cost; at the same time, the feedforward method provided by the present invention ensures the matching between the loop correlation coefficients and reduces the errors caused by mismatch.

[0047] like Figure 1~Figure 3 As shown, when the data converter based on the voltage controlled oscillator of the present invention is implemented, a 9-bit SAR CDC is used for the first stage of coarse quantization, one bit of which is redundant, and a 5-bit second-order Delta-Sigma CDC is used for the second stage of fine quantization. The SARCDC and Delta-Sigma CDC share a DAC component. The fine quantization stage adopts a loop filter based on the voltage controlled oscillator, which is composed of an operational transconductance amplifier G m2 The system is composed of a current controlled oscillator and a phase domain quantizer to implement feedforward compensation to ensure the stability of the loop. After the current controlled oscillator, the phase domain quantizer performs quantization and feeds the digital code back to the shared DAC. When the entire system is working, sampling is first performed, then a coarse quantization is performed, and then an OSR sub-fine quantization is performed. During the fine quantization, the chopping phase is periodically modified to eliminate the offset and 1 / f noise of the first-stage integrator.

[0048] Specifically, its working mode is as follows:

[0049] 1) Sampling phase

[0050] Capacitive sensor readout circuit for sensing capacitance C S Sampling is performed, that is, a portion proportional to C S The charge is transferred to C S The top plate shared by the DAC allows the subsequent phase to quantize the charge. During the sampling phase, the first-stage integrator and the current-controlled oscillator are reset to eliminate the memory effect. For the current-controlled oscillator, the reset operation disconnects the positive feedback loop of the current-controlled oscillator, and the inputs and outputs of the seven cascaded inverters are connected to a fixed level. There are two types of fixed levels: the low level is 0, and the high level is a fixed level provided outside the chip. The specific size of the high level is the voltage of the drain of the PMOS transistor when the current-controlled oscillator is working normally.

[0051] 2) Coarse quantization phase

[0052] After sampling, the first-level coarse quantization CDC, namely SARCDC, completes the coarse quantization of the charge. Its specific working method is to gradually switch the bottom plate voltage of each capacitor in the DAC in the order of capacitance from large to small. Before each switch, the voltage at both ends of the comparator is used to determine the sensor capacitor C. S After the coarse quantization is completed, the SAR digital code is stored using a latch structure, and finally combined with the second-level fine quantization digital code, and finally the final digital code is obtained through a downsampling filter.

[0053] 3) Fine quantization phase

[0054] After the coarse quantization, fine quantization is performed, and a total of OSR fine quantizations are performed. Each fine quantization cycle corresponds to one first-stage integrator integration, one voltage-controlled oscillator integration, and one phase quantization. During fine quantization, a chopping operation is performed to eliminate the offset and 1 / f noise of the first-stage integrator. Each fine quantization cycle corresponds to a chopping phase. In the OSR fine quantization, the sequence corresponding to the chopping phase is "+1, -1, -1, +1", which is a second-order chopping, suitable for a second-order incremental scaling architecture.

[0055] Figure 4 and Figure 5 The specific circuit operation of each fine quantization cycle is shown. The working clock of Delta-SigmaCDC is a clock with a duty cycle of 50%, and the phases corresponding to its low level and high level are named Φ1 and Φ2 respectively. Before phase quantization, that is, Φ1 phase, C 1p (C 1n ) and C 2p (C 2n ) in parallel, the top plate is also connected to M kf and M k2 The gate of C 1p,n The output of the first-stage integrator is pre-stored on C. Connecting two capacitors in parallel actually stores the output of the first-stage integrator on C. 1p (C 1n ) and C 2p (C 2n ) to share charge. kf and M k2 A differential current will be generated at the same time and flow through the 7-level current controlled oscillator, and a phase difference will be generated between the left and right current controlled oscillators. kf and M k2 The ratio of the differential current generated is determined by the size of the two transistors. At this time, the quantized phase is φ[n-1]+φ k2 [n]+φ kf [n]. After phase quantization, C 1p (C 1n ) and C2p (C 2n ) disconnect, C 1p,n Connected to the output of the first-stage integrator, the first-stage integrator works and updates C 1p,n The voltage on C 2p and C 2n Interchangeable, top plate connected to M kf The gate, M k2 The gate connection V CM , therefore, M kf A differential current opposite to that of Φ1 is generated, and M k2 The resulting differential current is 0. Since the time of Φ1 and Φ2 is the same, the phase difference between the two current controlled oscillators is reduced by a Φ that is the same as the previous Φ1 time. kf [n], that is, each fine quantization cycle has only φ k2 [n] is integrated into the phase difference of the two current-controlled oscillators. Therefore, the quantized phase of a fine quantization cycle is φ[n-1]+φ k2 [n]+φ kf [n], and the phase to be integrated is φ k2 [n], equivalent to realizing the phase domain feedforward. It is worth noting that the voltage-controlled oscillator is located in the second-stage integrator, and the input of the second-stage integrator is not connected to the output of the first-stage integrator or the front-end circuit, which ensures that the high-noise voltage-controlled oscillator will not kick back to the most sensitive node in the circuit - C S The top plate shared with the DAC ensures the accuracy of the system; at the same time, the integral of the phase domain φ k2 [n] and feedforward quantity φ kf The ratio of [n] is equal to the current I diff,k2 and current I diff,kf ratio, and the current I diff,k2 and current I diff,kf The ratio is equal to the transistor M k2 and transistor M kf The transconductance ratio of transistor M k2 and transistor M kf The size ratio can be well controlled during the production process, thereby reducing the mismatch between the system feedforward coefficient and the integral coefficient, and ensuring the robustness of the design to a certain extent.

[0056] The incremental scaling data converter based on a voltage-controlled oscillator provided by the present invention first adds the feedforward phase to the total differential phase of the voltage-controlled oscillator and subtracts it after quantization, thereby equivalently realizing feedforward compensation in the phase domain and achieving loop stability through feedforward compensation of the voltage-controlled oscillator.

[0057] The voltage-controlled oscillator in the present invention is specifically implemented in the form of a cascade of an operational transconductance amplifier and a current-controlled oscillator. The voltage-controlled oscillator feedforward compensation specifically refers to splitting the input transistor and capacitor of the operational transconductance amplifier into two parts. In the half fine quantization cycle before phase quantization, the split input transistors are connected in parallel, and the split input capacitors are also connected in parallel. The top plate of the capacitor is connected to the gate of the input transistor. At this time, the split input transistors generate their own differential currents, which flow into the current-controlled oscillator at the same time, realizing the change of the voltage-controlled total differential phase. In the half cycle after phase quantization, the two parallel capacitors are disassembled, and one capacitor at each of the positive input and negative input ends of the voltage-controlled oscillator is used as the load capacitor of the first-stage integrator, and the remaining one capacitor at each of the positive input and negative input ends is used to realize the feedforward path. Connecting the gate of one input transistor at each of the positive and negative input ends of the voltage-controlled oscillator to the common-mode reference level (VCM) is equivalent to no differential current flowing through the current-controlled oscillator, and cross-connecting the gate of the other input transistor at the positive and negative input ends to the capacitor that does not serve as the load of the first-stage integrator is equivalent to generating input signals of equal magnitude and opposite polarity in this half-fine quantization cycle, generating a differential phase of equal magnitude and opposite polarity to the previous half cycle, which is subtracted from the total differential phase. That is, the phase change of each fine quantization cycle is divided into two parts, one part of which is permanently added to the total differential phase to achieve phase integration; the other part of the phase is first added to the total differential phase, and then quantized in the phase domain. After the quantization is completed, it is subtracted from the total differential phase, which is equivalent to achieving feedforward compensation.

[0058] The present invention improves the incremental scaling data converter based on the voltage-controlled oscillator, designs a feedforward compensation method suitable for the voltage-controlled oscillator, makes full use of the characteristics of the Delta-Sigma data converter clock, first adds the feedforward phase to the total differential phase of the voltage-controlled oscillator, and subtracts it after the quantization is completed, thereby equivalently realizing the feedforward compensation in the phase domain. The method does not introduce a new timing sequence and is a low-cost implementation method; at the same time, the method completely isolates the voltage-controlled oscillator from the sensitive nodes in the circuit, avoiding the kickback noise. Through this method, a high-energy-efficiency data converter based on a voltage-controlled oscillator can be constructed more simply, and has a wide range of application scenarios in the fields of the Internet of Things and smart medical care. Compared with the traditional incremental scaling data converter based on the voltage-controlled oscillator, the loop stability of the present invention is realized by the voltage-controlled oscillator feedforward compensation. The voltage-controlled oscillator integral function and the quantization function are closely coupled together, making the feedforward compensation difficult. Although a few works realize the feedforward compensation, they will introduce problems such as large mismatch between the feedback coefficient and the integral coefficient and large kickback noise of the voltage-controlled oscillator. The present invention realizes the feedforward compensation of the voltage-controlled oscillator through a simple method, solves the above-mentioned problem, and simplifies the realization of the data converter based on the voltage-controlled oscillator.

[0059] It should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A method for implementing a data converter based on a voltage-controlled oscillator, characterized in that: The feedforward phase is first added to the total differential phase of the voltage-controlled oscillator and then subtracted after quantization, thereby realizing the feedforward compensation in the phase domain and realizing loop stability through the voltage-controlled oscillator feedforward compensation; the steps include: 1) Prepare a multi-bit successive approximation data converter, including a sampling circuit, a digital-to-analog converter DAC, a comparator, and a digital logic unit; wherein the digital-to-analog converter DAC is a binary DAC, which is a coarse quantization DAC; use the prepared multi-bit successive approximation data converter as a coarse quantization stage of a data converter system to coarsely quantize an input signal; 2) Prepare a multi-bit multi-order Delta-Sigma data converter, including a digital-to-analog converter DAC, a loop filter, a phase domain quantizer, and a digital logic unit; wherein the digital-to-analog converter DAC is a three-value DAC; the loop filter includes a first-stage integrator and a second-stage integrator; the phase domain quantizer uses a dual frequency and phase detector to perform multi-bit quantization in the phase domain; the digital logic unit converts the quantization result into a code used by the three-value DAC; 3) A multi-bit successive approximation data converter and a multi-bit multi-order Delta-Sigma data converter share a DAC component; that is, the DAC component is composed of two parts of capacitor array top plates with different encoding methods connected together; 4) Prepare a voltage-controlled oscillator including phase-domain feedforward control logic; the voltage-controlled oscillator adopts a cascade structure of an operational transconductance amplifier and a current-controlled oscillator; the input transistor of the operational transconductance amplifier is split into two parts, the input capacitor is split into two parts, and the connection method of the input transistor gate is determined by the phase-domain feedforward control logic; the voltage-controlled oscillator including the phase-domain feedforward control logic is used as the second-stage integrator of a multi-bit multi-order Delta-Sigma data converter; 5) A multi-bit successive approximation data converter is used as the first stage to complete the coarse quantization of the analog signal; a multi-bit multi-order Delta-Sigma data converter is used as the second stage to complete the fine quantization of the analog signal; the first stage and the second stage are connected through a DAC top plate; an improved data converter based on a voltage-controlled oscillator can be obtained.

2. The method for implementing a data converter based on a voltage-controlled oscillator as claimed in claim 1, characterized in that: The DAC of a multi-bit successive approximation data converter is a binary DAC, that is, the digital code that controls the DAC has only two inputs, 0 and 1; the DAC of a multi-bit multi-level data converter is a ternary DAC, that is, the digital code that controls the DAC has three inputs, -1, 0 and 1.

3. The method for implementing a data converter based on a voltage controlled oscillator as claimed in claim 1, characterized in that: The prepared voltage-controlled oscillator containing phase-domain feedforward control logic is in the form of a cascade of an operational transconductance amplifier and a current-controlled oscillator. The operational transconductance amplifier converts the input voltage into current, and the current-controlled oscillator maps the current to frequency and integrates it into phase information.

4. The method for implementing a data converter based on a voltage-controlled oscillator as claimed in claim 3, characterized in that: The operational transconductance amplifier differential input transistor and input capacitor of the voltage-controlled oscillator are each split into two, that is, the positive input end and the negative input end of the voltage-controlled oscillator each include two input transistors and input capacitors, and the sources and drains of the two input transistors are connected, and the gates are disconnected.

5. The method for implementing a data converter based on a voltage-controlled oscillator as claimed in claim 4, characterized in that: Before phase quantization, the multi-bit multi-order Delta-Sigma data converter connects the two split capacitors in parallel, and the top plates of the capacitors are simultaneously connected to the gates of the two split input transistors. That is, at this time, the positive input and negative input ends of the voltage-controlled oscillator each include two parallel input transistors and input capacitors. The input transistors generate a differential current flowing through the current-controlled oscillator, and the phase to be integrated and the phase to be fed forward are added to the total differential phase.

6. The method for implementing a data converter based on a voltage-controlled oscillator as claimed in claim 5, characterized in that: After bit quantization, one capacitor each at the positive input and negative input of the voltage-controlled oscillator is connected to the positive output and negative output of the preceding integrator to act as load capacitors. The remaining capacitors at the positive input and negative input of the voltage-controlled oscillator are interchanged and connected to the gate of a split transistor. The gates of the remaining transistors at the positive input and negative input of the voltage-controlled oscillator are simultaneously connected to the reference common-mode voltage, thereby subtracting the phase that needs to be fed forward in the first half of the fine quantization cycle from the total differential phase, thereby realizing a feedforward path from the voltage-controlled oscillator input to the phase domain quantizer input.

7. A data converter based on a voltage-controlled oscillator implemented by the method of claim 1, characterized in that: include: A sampling circuit, a multi-bit successive approximation data converter, and a multi-bit multi-order Delta-Sigma data converter; wherein: The sampling circuit is used to sample and convert analog signals; A multi-bit successive approximation data converter is used as the first stage of the voltage-controlled oscillator-based data converter to perform coarse quantization of analog signals; the multi-bit successive approximation data converter comprises a sampling circuit, a digital-to-analog converter DAC, a comparator, and a digital logic unit; A multi-bit multi-order Delta-Sigma data converter is used as the second stage of the voltage-controlled oscillator-based data converter to complete fine quantization of analog signals; the multi-bit multi-order Delta-Sigma data converter includes a digital-to-analog converter DAC, a loop filter, a phase domain quantizer, and a digital logic unit; A multi-bit successive approximation data converter and a multi-bit multi-order Delta-Sigma data converter share a digital-to-analog converter DAC component, and the DAC component is composed of two parts of capacitor arrays with different encoding methods.

8. The voltage controlled oscillator based data converter according to claim 7, characterized in that: When the data converter based on the voltage-controlled oscillator works, it is carried out in two steps. First, a coarse quantization is performed, and the DAC corresponding to the multi-bit successive approximation data converter, that is, the coarse quantization DAC, is switched; then multiple fine quantizations are performed, and the DAC corresponding to the multi-bit multi-order Delta-Sigma data converter, that is, the fine quantization DAC, is switched.

9. The voltage controlled oscillator based data converter according to claim 7, characterized in that: For the analog-to-digital converter, the sampling switch and the DAC shared by the multi-bit successive approximation data converter and the multi-bit multi-order Delta-Sigma data converter form a sampling circuit; for the capacitive sensor readout circuit, a capacitor-to-voltage converter is built to form a separate sampling circuit, or the sensing capacitor and the DAC are connected in parallel to form a sampling circuit with the sampling switch.

10. The voltage controlled oscillator based data converter according to claim 7, characterized in that: The phase domain quantizer uses a dual frequency detector to quantize the output of the voltage-controlled oscillator. The phase change of the voltage-controlled oscillator makes the quantized digital code follow the change of the center frequency of the voltage-controlled oscillator and select the corresponding capacitor in the DAC, that is, the inherent clock average.

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