Two-dimensional LDPC error correction method for flash memory, flash memory controller and storage device

Abstract

The present invention discloses a two-dimensional LDPC error correction method, a flash memory controller, and a storage device suitable for flash memory, belonging to the field of flash memory technology. The encoding steps include: performing two-dimensional LDPC encoding on each K information bits in a flash memory page, storing the resulting parity bits in the OOB area of ​​the flash memory page, and completing the encoding of the flash memory page; the two-dimensional LDPC encoding includes: dividing the K information bits into B information bit blocks of size k, taking each c consecutive information bit blocks as a row in an information matrix, and obtaining an information matrix with r rows and c columns; encoding each row in the information matrix using a first LDPC code to generate horizontal parity bits corresponding to each row; and encoding each column in the information matrix using a second LDPC code to generate vertical parity bits corresponding to each column. The present invention can significantly reduce the decoding delay of a flash memory system using LDPC codes without increasing redundant space.

Description

Technical Field

[0001] The present invention belongs to the technical field of flash memory, and more specifically, relates to a two-dimensional LDPC error correction method applicable to flash memory, a flash memory controller, and a storage device. Background Art

[0002] Flash-based solid-state drives (SSDs) are becoming the mainstream storage medium for various embedded systems, personal computers, and high-performance platforms due to their advantages such as small size, high performance, low energy consumption, and non-volatility. To increase storage capacity and reduce cell costs, manufacturers are continuously reducing cell pitch and storing more bits of information within a single cell. From MLC to the now commonly used TLC, the number of bits stored within a single cell has increased, and the number of error bits within flash memory has increased by more than tenfold. Therefore, while flash memory capacity and storage density are rapidly increasing, crosstalk between memory cells poses a significant threat to data storage reliability. Error correction codes are an effective means of combating flash channel interference and ensuring data storage reliability.

[0003] Traditional BCH codes are widely used in commercial solid-state drives, but are limited by the capacity of the OOB (Out of Band) area in flash memory pages, and the amount of checksum information that can be stored is limited. Therefore, the data storage reliability of large-capacity flash memory cannot be guaranteed.

[0004] LDPC codes, with their superior error correction capabilities, have attracted widespread attention from both academia and industry. LDPC codes use soft decoding to achieve high reliability, but this comes at the cost of significantly increased decoding latency. This can lead to a loss of high performance in flash memory and degrade service quality. Summary of the Invention

[0005] In response to the defects of the existing technology and the need for improvement, the present invention provides a two-dimensional LDPC error correction method, a flash memory controller and a storage device suitable for flash memory. Its purpose is to significantly reduce the decoding delay of a flash memory system using LDPC code without increasing additional redundant space.

[0006] To achieve the above object, according to one aspect of the present invention, a two-dimensional LDPC error correction method applicable to a flash memory is provided, comprising: an encoding step; the encoding step comprises:

[0007] After performing two-dimensional LDPC encoding on each K information bits in the flash memory page, the resulting parity bits are stored in the OOB area of ​​the flash memory page to complete the encoding of the flash memory page;

[0008] Two-dimensional LDPC coding includes:

[0009] Construct an information matrix: divide the K information bits into B information bit blocks of size k, and use each c consecutive information bit blocks as a row in the information matrix, resulting in an information matrix with r rows and c columns.

[0010] Horizontal coding: For each row of information bit blocks in the information matrix, use the first LDPC code to encode them and generate m1 horizontal parity bits corresponding to each row;

[0011] Longitudinal coding: For each column of information bit blocks in the information matrix, the second LDPC code is used to encode them and generate m2 longitudinal parity bits corresponding to each column;

[0012] The parity bits include horizontal parity bits and vertical parity bits; the code rate R≥S for flash memory page encoding info / S page , S page Indicates the flash memory page size, S info Indicates the size of the information bit storage area in the flash memory page; K is divisible by S info is a positive integer, and k is a positive integer that can divide K.

[0013] Furthermore, the two-dimensional LDPC error correction method for flash memory provided by the present invention further includes: a decoding step; the decoding step includes:

[0014] For each K information bits in the flash memory page, two-dimensional LDPC decoding is performed to complete the encoding of the flash memory page;

[0015] Two-dimensional LDPC decoding includes:

[0016] Initialization: Calculate the initial LLR information and obtain the information matrix M corresponding to the K information bits;

[0017] Horizontal decoding: For each row of information bit blocks in the information matrix M, the corresponding m1 horizontal parity bits are obtained from the OOB area of ​​the flash memory page. The current LLR information is used as the LLR information for LDPC decoding and decoded using the first LDPC code. After each row is decoded, the LLR information is updated.

[0018] Vertical decoding: For each column of information bit blocks in the information matrix M, the corresponding m2 longitudinal parity bits are obtained from the OOB area of ​​the flash memory page. The current LLR information is used as the LLR information for LDPC decoding, and decoding is performed using the second LDPC code. After each column is decoded, the LLR information is updated.

[0019] Iteration control: Iteratively execute horizontal decoding and vertical decoding until any preset iteration termination condition is reached.

[0020] Furthermore, the iteration termination conditions include:

[0021] In the current iteration, the number of error rows successfully corrected in horizontal decoding FlagRow=0 and the number of error columns successfully corrected in vertical decoding FlagCol=0.

[0022] Furthermore, the preset iteration termination conditions include:

[0023] Reach the maximum number of iterations Cycle;

[0024] Among them, if r=c, then Cycle=r; if r≠c, Cycle=min(r,c)+1; min means taking the minimum value.

[0025] Furthermore, if min(r,c)>th, the preset iteration termination condition also includes:

[0026] Reach the preset number of iterations T;

[0027] Among them, th and T are both preset positive integers, T <Cycle。

[0028] Furthermore, the method for determining the number of iterations T includes:

[0029] Select multiple information matrices of the same size as the information matrix M as the observation matrix;

[0030] For each measurement matrix, perform horizontal decoding and vertical decoding iteratively, and record the change of the bit error rate of each measurement matrix with the number of iterations;

[0031] The number of iterations corresponding to when the bit error rate of each observation matrix drops to a preset reliable threshold is obtained and the average value is calculated as the pre-iteration number T.

[0032] Furthermore, in horizontal coding, the coding of each row of information bit blocks in the information matrix is ​​performed in parallel; in vertical coding, the coding of each column of information bit blocks in the information matrix is ​​performed in parallel;

[0033] In horizontal decoding, the decoding of information bit blocks in each row of the information matrix M is performed in parallel; in vertical decoding, the decoding of information bit blocks in each column of the information matrix M is performed in parallel.

[0034] Furthermore, the first LDPC code and the second LDPC code are the same LDPC code.

[0035] According to another aspect of the present invention, there is provided a flash memory controller, comprising:

[0036] a computer-readable storage medium for storing a computer program;

[0037] and a processor for reading a computer program stored in a computer-readable storage medium and executing the two-dimensional LDPC error correction method applicable to flash memory provided by the present invention.

[0038] According to another aspect of the present invention, there is provided a flash memory-based storage device, comprising:

[0039] A flash memory chip and the flash memory controller provided by the present invention.

[0040] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects:

[0041] (1) The traditional LDPC code is a one-dimensional LDPC code, that is, all information bits in the entire flash memory are uniformly encoded, and the codeword is long, which will lead to a long decoding delay in the entire decoding process. The present invention controls the code rate to ensure that the check information generated by the encoding can be completely stored in the OOB area. Each time, K information bits in the entire flash memory page are encoded. During encoding, the K information bits are further organized into an information matrix. The K information bits are encoded by performing LDPC encoding on the rows and columns of the information matrix respectively, thereby realizing a two-dimensional LDPC encoding. Through such an encoding method, the codeword length is greatly shortened, thereby effectively improving the decoding efficiency and reducing the decoding delay.

[0042] (2) During the decoding process, the present invention iteratively performs horizontal decoding and vertical decoding, so that horizontal decoding and vertical decoding are continuously and alternately performed. When horizontal decoding or vertical decoding fails in a certain iteration, it may be because the vertical decoding or horizontal decoding performed subsequently corrects some error bits, so that in the next iteration, horizontal decoding or vertical decoding plays a role again, effectively ensuring the effectiveness of the entire decoding step. When in a certain iteration, the number of error rows successfully corrected in horizontal decoding FlagRow=0 and the number of error columns successfully corrected in vertical decoding FlagCol=0, it means that after the previous iteration, all error bits in the information matrix have been corrected, or there are still error bits in the information matrix, but new error bits cannot be corrected through subsequent iterations. The present invention uses this as one of the preset iteration termination conditions, which can avoid invalid iterations without affecting the error correction capability, further improve decoding efficiency, and reduce iteration overhead.

[0043] (3) According to the two-dimensional coding method adopted in the present invention, the number of iterations required to correct all correctable error bits during decoding can be calculated. Specifically, when the number of rows and columns of the information matrix is ​​equal, the number of iterations is the number of rows or columns. When the number of rows and columns of the information matrix is ​​not equal, the number of iterations is the sum of the smaller value of the number of rows or columns and 1. In the preferred embodiment of the present invention, the number of iterations is calculated and set to the maximum number of iterations as one of the iteration termination conditions in the decoding process. Compared with terminating the iteration according to the number of rows and columns successfully corrected in the iteration, the number of iterations can be further reduced without affecting the error correction capability, thereby improving the decoding efficiency.

[0044] (4) When the scale of the information matrix is ​​large and the errors are randomly distributed in the information matrix, most of the error bits can often be corrected in the first few iterations. In subsequent iterations, each iteration can only correct a small number of bit errors. In the preferred embodiment of the present invention, if the scale of the information matrix is ​​large, the number of iterations at which the iteration is terminated is set to be less than the maximum number of iterations. In other words, the iteration process is terminated before all correctable errors are corrected. This allows for a better balance between error correction capability and the number of iterations. Without significantly affecting the error correction capability, the number of iterations is effectively reduced, further improving decoding efficiency. In a further preferred embodiment, the number of iterations at which the iteration is terminated is specifically determined based on the change in the bit error rate of multiple information matrices of the same size with the number of iterations, ensuring that the reliability of data storage can be effectively guaranteed while improving decoding efficiency.

[0045] (5) In the preferred embodiment of the present invention, the encoding / decoding of the information bit blocks in each row of the information matrix is ​​performed in parallel, and the encoding / decoding of the information bit blocks in each column of the information matrix is ​​performed in parallel, thereby achieving a degree of parallelism that one-dimensional LDPC codes do not have, and further improving the encoding / decoding efficiency.

[0046] (6) In the preferred embodiment of the present invention, the same LDPC code is used in the horizontal and vertical directions, thereby simplifying the overall encoding and decoding logic. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic diagram of a two-dimensional LDPC error correction method applicable to flash memory provided by an embodiment of the present invention;

[0048] Figure 2 A schematic diagram of two-dimensional LDPC coding provided by an embodiment of the present invention;

[0049] Figure 3 A schematic diagram of two-dimensional LDPC decoding provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0051] In the present invention, the terms "first", "second", etc. (if any) in the present invention and the drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0052] In order to solve the problem that the existing LDPC error correction method has a large decoding delay and affects the performance of flash memory when improving the data reliability of flash memory, the present invention provides a two-dimensional LDPC error correction method, a flash memory controller and a storage device suitable for flash memory. The overall idea is to improve the traditional one-dimensional LDPC error correction method and propose a new two-dimensional coding structure. Without increasing the code rate, the codeword length of LDPC encoding / decoding is greatly shortened, thereby effectively improving the decoding efficiency and further improving the performance of flash memory.

[0053] To make the technical solution provided by the present invention clearer and more detailed, the relevant principles of LDPC (Low-Density Parity-Check codes) are briefly introduced as follows:

[0054] LDPC codes are linear codes defined by a sparse, non-systematic parity check matrix H, used to correct errors that occur during transmission. These codes have an error correction capability very close to the Shannon limit, offering strong ability to correct multiple random errors. They are widely used in communications and storage. Before performing LDPC encoding, a parity check matrix H must be constructed. This matrix contains only 0s and 1s, with the number of 0s significantly exceeding the number of 1s. The number of 1s in each row of the matrix is ​​called the row weight, and the number of 1s in each column is called the column weight.

[0055] Each column in the parity check matrix corresponds to a codeword bit and is called a variable node. Each row corresponds to a check equation and is called a check node. The parity check matrix can be converted into a corresponding Tanner graph. Each element 1 in the parity check matrix corresponds to an edge in the Tanner graph. During decoding, the information of the variable nodes and check nodes is updated through the edges in the Tanner graph.

[0056] The encoding process of LDPC code mainly includes two steps: first, construct a parity check matrix H of size (NK) × K, where N is used to represent the length of the transmitted codeword C, K is the length of the information bit, and NK is the length of the parity check information; then, construct a generator matrix G based on the parity check matrix H, multiply the received information bit by each element of each row of the matrix, and then add them together to satisfy H·C T =0, the encoding is successful.

[0057] There are two decoding schemes for LDPC codes: hard-decision decoding and soft-decision decoding. Hard-decision decoding directly estimates the value of bit nodes and then makes a threshold decision. Soft-decision decoding extracts LLR information and iteratively updates it to achieve error correction. Hybrid decoding is a common decoding scheme used in flash memory today. Hard-decision decoding is first used for preliminary decoding. If decoding fails, soft-decision decoding is used to further refine the decoding based on quantization levels from 1 to 7. A common decoding algorithm is the minimum-sum algorithm. The specific decoding process includes inputting initial LLR information, updating check nodes, updating variable nodes, and finally making a decoding decision.

[0058] The specific LDPC code can be expressed as LDPC(n i ,j i ,k i ), where n i 、j i and k i Respectively represent the number of columns, column weight and row weight of the subcode check matrix. In addition, m i Represents the function of the check matrix, then the relevant parameters satisfy m i =n i ×j i / k i ,j i <k i ,j i <<m i ,k i <<n i .

[0059] The following are examples.

[0060] Example 1:

[0061] A two-dimensional LDPC error correction method suitable for flash memory, such as Figure 1 As shown, it includes: encoding step and decoding step.

[0062] like Figure 1 As shown, in this embodiment, the encoding step includes:

[0063] After performing two-dimensional LDPC encoding on each K information bits in the flash memory page, the resulting parity bits are stored in the OOB area of ​​the flash memory page to complete the encoding of the flash memory page;

[0064] Two-dimensional LDPC coding includes:

[0065] Construct an information matrix: divide the K information bits into B information bit blocks of size k, and use each c consecutive information bit blocks as a row in the information matrix, resulting in an information matrix with r rows and c columns; B = r*c;

[0066] Horizontal coding: For each row of information bit blocks in the information matrix, use the first LDPC code to encode them and generate m1 horizontal parity bits corresponding to each row;

[0067] Longitudinal coding: For each column of information bit blocks in the information matrix, the second LDPC code is used to encode them and generate m2 longitudinal parity bits corresponding to each column;

[0068] The parity bits include horizontal parity bits and vertical parity bits; the code rate R≥S for flash memory page encoding info / S page , S page Indicates the flash memory page size, S info Indicates the size of the information bit storage area in the flash memory page; K is divisible by S info is a positive integer, and k is a positive integer that can divide K.

[0069] like Figure 1 As shown, in this embodiment, the decoding step includes:

[0070] For each K information bits in the flash memory page, two-dimensional LDPC decoding is performed to complete the encoding of the flash memory page;

[0071] Two-dimensional LDPC decoding includes:

[0072] Initialization: Calculate the initial LLR information and obtain the information matrix M corresponding to the K information bits;

[0073] Horizontal decoding: For each row of information bit blocks in the information matrix M, the corresponding m1 horizontal parity bits are obtained from the OOB area of ​​the flash memory page. The current LLR information is used as the LLR information for LDPC decoding and decoded using the first LDPC code. After each row is decoded, the LLR information is updated.

[0074] Vertical decoding: For each column of information bit blocks in the information matrix M, the corresponding m2 longitudinal parity bits are obtained from the OOB area of ​​the flash memory page. The current LLR information is used as the LLR information for LDPC decoding, and decoding is performed using the second LDPC code. After each column is decoded, the LLR information is updated.

[0075] Iteration control: Iteratively execute horizontal decoding and vertical decoding until any preset iteration termination condition is reached.

[0076] This embodiment controls the code rate to ensure that the check information generated by the encoding can be completely stored in the OOB area. At each time, K information bits in the entire flash memory page are encoded. During encoding, the K information bits are further organized into an information matrix. The K information bits are encoded by performing LDPC encoding on the rows and columns of the information matrix respectively, thereby realizing a two-dimensional LDPC encoding. With this encoding method, the codeword length is greatly shortened, thereby effectively improving decoding efficiency and reducing decoding delay.

[0077] Optionally, in this embodiment, the size of each flash memory page is 4KB, and the size of the OOB area in the flash memory page is 512B; in this embodiment, when encoding, half of the flash memory page data is selected each time, that is, K=2*1024*8=16384.

[0078] like Figure 2 As shown, for K information bits, this embodiment divides each 512B of information bits into an information bit block, resulting in a total of four information bit blocks. Every two consecutive information bit blocks form a row, constructing a 2-row, 2-column information matrix, i.e., r = 2, c = 2. Each row contains 1KB of information bits, and each column also contains 1KB of information bits.

[0079] In order to simplify the overall encoding / decoding logic, when the present invention performs two-dimensional LDPC encoding on K information bits, the first LDPC encoding and the second LDPC encoding use the same LDPC encoding, which are respectively denoted as LDPC1 and LDPC2. After encoding each row and each column, 512b check bits are generated respectively, that is, m1=m2=512. Specifically, after encoding each row in the information matrix using LDPC1, 2×512b horizontal check bits are generated, and after encoding each column in the information matrix using LDPC2, 2×512b vertical check bits are generated.

[0080] The code length of the codeword generated by encoding is:

[0081] N=K+r×m1+c×m2=16384+1024+1024=18432;

[0082] Therefore, the encoding rate is R=K / N=16384 / 18432=8 / 9. Therefore, the generated parity bits can be completely stored in the OOB area of ​​the flash memory page.

[0083] After performing the above two-dimensional LDPC encoding on each K information bits in the flash memory page, the horizontal parity bits and vertical parity bits generated by the encoding are both stored in the OOB area of ​​the flash memory page.

[0084] This embodiment performs two-dimensional LDPC decoding on K information bits in the flash memory page each time, such as Figure 3 As shown, the decoding process includes multiple iterations, each of which includes one horizontal decoding and one vertical decoding. Therefore, horizontal decoding and vertical decoding are continuously performed alternately throughout the entire iteration. If horizontal decoding or vertical decoding fails in a certain iteration, the subsequent vertical decoding or horizontal decoding may correct some of the error bits, allowing horizontal decoding or vertical decoding to work again in the next iteration, effectively ensuring the effectiveness of the entire decoding process. In addition, each successful horizontal decoding or vertical decoding updates the LLR information, ensuring that the next vertical decoding or horizontal decoding process has more accurate LLR information, further improving the efficiency of LDPC decoding.

[0085] In the two-dimensional LDPC decoding process proposed in this embodiment, when, in a certain iteration, the number of error rows successfully corrected in the horizontal decoding FlagRow = 0 and the number of error columns successfully corrected in the vertical decoding FlagCol = 0, it means that after the previous iteration, all error bits in the information matrix have been corrected, or error bits still exist in the information matrix, but new error bits cannot be corrected through subsequent iterations.

[0086] Figure 3 The figure shows a flowchart of performing multiple iterations of row-based two-dimensional LDPC decoding on the information matrix with 2 rows and 2 columns, when each information bit block has errors. Figure 3 It can be seen that each round of horizontal and vertical decoding must achieve at least one row or one column of correction, otherwise the iteration stops.

[0087] Based on the above findings, in order to avoid invalid iterations without affecting the error correction capability, further improve decoding efficiency, and reduce iteration overhead, as a preferred implementation, in this embodiment, the iteration termination conditions include:

[0088] In the current iteration, the number of error rows successfully corrected in horizontal decoding FlagRow=0 and the number of error columns successfully corrected in vertical decoding FlagCol=0.

[0089] In this embodiment, since each time horizontal encoding is performed, multiple rows in the information matrix are independently encoded, and each time vertical encoding is performed, multiple classes in the information matrix are independently encoded, therefore, as a preferred embodiment, in this embodiment, the encoding of the information bit blocks in each row of the information matrix is ​​performed in parallel, and the encoding of the information bit blocks in each column of the information matrix is ​​performed in parallel, thereby achieving a degree of parallelism that is not available in one-dimensional LDPC codes, further improving coding efficiency. Similarly, since each time horizontal decoding is performed, multiple rows in the information matrix are independently decoded, and each time vertical decoding is performed, multiple classes in the information matrix are independently decoded, therefore, as a preferred embodiment, in this embodiment, the decoding of the information bit blocks in each row of the information matrix is ​​performed in parallel, and the decoding of the information bit blocks in each column of the information matrix is ​​performed in parallel, further improving decoding efficiency.

[0090] Similarly, the encoding / decoding processes between K information bits and K information bits in the flash memory page can also be executed in parallel to further improve the encoding / decoding efficiency.

[0091] It is easy to understand that the above parallelism can be achieved by improving the flash memory controller.

[0092] It should be noted that the above-mentioned descriptions regarding the flash memory page size, information matrix parameters, and the selection of LDPC codes are merely exemplary descriptions and should not be understood as the sole limitation on the present invention. In other embodiments of the present invention, the relevant parameters can be flexibly adjusted according to the actual flash memory error correction requirements, and the first LDPC code and the second LDPC code may also use different LDPC codes.

[0093] In general, this embodiment implements horizontal and vertical LDPC encoding / decoding of information bits in flash memory based on one-dimensional LDPC codes. On the one hand, it greatly shortens the codeword length and effectively improves decoding efficiency. On the other hand, it can further improve decoding efficiency through parallel operations. Under the premise of ensuring that no additional redundant space is added, the decoding delay of the flash memory system using LDPC codes is significantly reduced.

[0094] Example 2:

[0095] A two-dimensional LDPC error correction method applicable to flash memory. This embodiment is similar to the above-mentioned embodiment 1, except that this embodiment further optimizes the iteration termination condition in the two-dimensional LDPC decoding process.

[0096] The two-dimensional encoding method employed by the present invention calculates the number of iterations required to correct all correctable error bits during decoding. Specifically, when the number of rows and columns of the information matrix is ​​equal, the number of iterations is the number of rows or columns. When the number of rows and columns of the information matrix is ​​unequal, the number of iterations is the sum of the smaller of the number of rows or columns and 1. Based on this consideration, this embodiment precalculates the number of iterations required to correct all correctable error bits and sets it as the maximum number of iterations, Cycle. Reaching the maximum number of iterations, Cycle, is used as one of the iteration termination conditions.

[0097] The maximum number of iterations Cycle is calculated as follows:

[0098] If r=c, then Cycle=r; if r≠c, Cycle=min(r,c)+1; min means taking the minimum value.

[0099] This embodiment stops iterations after all correctable error bits in the information matrix have been corrected. In contrast, in Example 1, after all correctable error bits in the information matrix have been corrected, one more iteration is required before determining that FlagRow = 0 and FlagCol = 0, thereby stopping the iterations. In comparison, this embodiment can further improve decoding efficiency and reduce iteration overhead without compromising error correction capability.

[0100] by Figure 3 For example, after two iterations, all the erroneous bits in the information matrix can be corrected. According to the iteration termination condition set in Example 1, the iteration will not stop until the third iteration is executed; and according to the iteration termination condition set in this embodiment, the maximum number of iterations can be calculated as Cycle=2, that is, the iteration is terminated after executing 2 iterations, further reducing the number of iterations.

[0101] In this embodiment, the specific implementation of other steps can refer to the description in the above embodiment 1 and will not be repeated here.

[0102] Example 3:

[0103] A two-dimensional LDPC error correction method applicable to flash memory. This embodiment is similar to the above-mentioned embodiment 2, except that this embodiment further optimizes the iteration termination condition in the two-dimensional LDPC decoding process.

[0104] When the scale of the information matrix is large and the errors are randomly distributed in the information matrix, since it is difficult for the correction of a single row or column to affect the entire information matrix, it is difficult to carry out the iteration to the end. Most of the error bits can be corrected in the first few iterations. In subsequent iterations, only a few bit errors can be corrected each time, but more iterations will lead to an increase in decoding delay. Based on this discovery, in order to balance the error correction ability and decoding efficiency, in this embodiment, for an information matrix with a large scale, its iteration termination condition is set as follows:

[0105] Reaching the preset number of iterations T;

[0106] where T is a preset positive integer, and T < Cycle. Cycle is the number of iterations required to correct all the correctable error bits, and its calculation method can refer to the description in Embodiment 2 above.

[0107] In this embodiment, for an information matrix with a small scale, the same iteration termination condition as in Embodiment 2 above is adopted.

[0108] In practical applications, a threshold th can be set to distinguish the scale of the information matrix. If min(r, c) > th, it is determined that the information matrix has a large scale; otherwise, it is determined that the information matrix has a small scale.

[0109] For an information matrix with a large scale, in order to effectively ensure the reliability of data storage while improving the decoding efficiency, this embodiment will determine the number of iterations T according to the actual data storage reliability requirements. Specifically, multiple information matrices with the same scale as the information matrix M are selected as the observation matrices;

[0110] For each observation matrix, horizontal decoding and vertical decoding are iteratively executed respectively, and the change of the bit error rate of each observation matrix with the number of iterations is recorded;

[0111] Obtain the number of iterations corresponding to when the bit error rate of each observation matrix drops to the preset reliable threshold and calculate the average value as the pre-iteration number T.

[0112] In this embodiment, the specific implementation manners of other steps can refer to the description in Embodiment 1 above and will not be repeated here.

[0113] Embodiment 4:

[0114] A flash memory controller, comprising:

[0115] A computer-readable storage medium for storing a computer program;

[0116] and a processor, configured to read a computer program stored in a computer-readable storage medium and execute the two-dimensional LDPC error correction method applicable to a flash memory provided in any one of the above-mentioned embodiments 1 to 3.

[0117] Example 5:

[0118] A flash memory-based storage device comprising:

[0119] A flash memory chip and the flash memory controller provided in the above embodiment 4.

[0120] It will be easily understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A two-dimensional LDPC error correction method suitable for flash memory, characterized in that: include: Coding steps; The encoding step comprises: After performing two-dimensional LDPC encoding on each K information bits in a flash memory page, the obtained parity bits are stored in the OOB area of ​​the flash memory page to complete the encoding of the flash memory page; The two-dimensional LDPC coding includes: Construct an information matrix: divide the K information bits into B information bit blocks of size k, and use each c consecutive information bit blocks as a row in the information matrix, resulting in an information matrix with r rows and c columns. Horizontal coding: For each row of information bit blocks in the information matrix, use the first LDPC code to encode them respectively to generate m1 horizontal parity bits corresponding to each row; Longitudinal coding: For each column of information bit blocks in the information matrix, use the second LDPC code to encode them respectively to generate m2 longitudinal parity bits corresponding to each column; The parity bits include horizontal parity bits and vertical parity bits; the code rate R≥S info / S page , S page Indicates the flash memory page size, S info Indicates the size of the information bit storage area in the flash memory page; K is divisible by S info is a positive integer, and k is a positive integer that can divide K.

2. The two-dimensional LDPC error correction method for flash memory according to claim 1, wherein: Also includes: Decoding steps; The decoding step comprises: For each K information bits in the flash memory page, perform two-dimensional LDPC decoding to complete the encoding of the flash memory page; The two-dimensional LDPC decoding includes: Initialization: Calculate the initial LLR information and obtain the information matrix M corresponding to the K information bits; Horizontal decoding: For each row of information bit blocks in the information matrix M, after obtaining the corresponding m1 horizontal parity bits from the OOB area of ​​the flash memory page, using the current LLR information as the LLR information for LDPC decoding, and decoding using the first LDPC code, after each row of decoding is completed, the LLR information is updated; Vertical decoding: For each column of information bit blocks in the information matrix M, after obtaining the corresponding m2 longitudinal parity bits from the OOB area of ​​the flash memory page, using the current LLR information as the LLR information for LDPC decoding, and decoding using the second LDPC code, after each column decoding is completed, updating the LLR information; Iterative control: iteratively executing the horizontal decoding and the vertical decoding until any preset iteration termination condition is reached.

3. The two-dimensional LDPC error correction method for flash memory according to claim 2, wherein: The iteration termination conditions include: In the current iteration, the number of error rows successfully corrected in horizontal decoding FlagRow=0 and the number of error columns successfully corrected in vertical decoding FlagCol=0.

4. The two-dimensional LDPC error correction method for flash memory according to claim 2, wherein: The preset iteration termination conditions include: Reach the maximum number of iterations Cycle; Among them, if r=c, then Cycle=r; if r≠c, Cycle=min(r,c)+1; min means taking the minimum value.

5. The two-dimensional LDPC error correction method for flash memory according to claim 4, wherein: If min(r,c)>th, the preset iteration termination condition also includes: Reach the preset number of iterations T; Among them, th and T are both preset positive integers, T <Cycle。 6. The two-dimensional LDPC error correction method for flash memory according to claim 5, wherein: The method for determining the number of iterations T includes: Selecting multiple information matrices of the same size as the information matrix M as observation matrices; For each measurement matrix, iteratively perform the horizontal decoding and the vertical decoding, and record the change of the bit error rate of each measurement matrix with the number of iterations; The number of iterations corresponding to when the bit error rate of each observation matrix drops to a preset reliability threshold is obtained and the average value is calculated as the pre-iteration number T.

7. The two-dimensional LDPC error correction method for flash memory according to any one of claims 2 to 5, characterized in that: In the horizontal coding, the coding of each row of information bit blocks in the information matrix is ​​performed in parallel; in the vertical coding, the coding of each column of information bit blocks in the information matrix is ​​performed in parallel; In the horizontal decoding, decoding of information bit blocks in each row of the information matrix is ​​performed in parallel; in the vertical decoding, decoding of information bit blocks in each column of the information matrix is ​​performed in parallel.

8. The two-dimensional LDPC error correction method for flash memory according to any one of claims 1 to 6, characterized in that: The first LDPC code and the second LDPC code are the same LDPC code.

9. A flash memory controller, characterized in that: include: a computer-readable storage medium for storing a computer program; and a processor, configured to read the computer program stored in the computer-readable storage medium and execute the two-dimensional LDPC error correction method applicable to flash memory according to any one of claims 1 to 8.

10. A flash memory based storage device, characterized in that: include: A flash memory chip and the flash memory controller as claimed in claim 9.

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