CAN transceiver

Abstract

The application discloses a CAN transceiver. The CAN transceiver comprises a delay driving circuit, an input end of the delay driving circuit receiving a sending data signal, K high-side control signals and K low-side control signals being provided, a high-side control circuit receiving the K high-side control signals and outputting a high-side signal, and a low-side control circuit receiving the K low-side control signals and outputting a low-side signal. The sending data signal increases to a first proportional threshold value at a first time, the difference between the high-side signal and the low-side signal decreases to a first threshold value at a second time, the second time is delayed by N step delays compared with the first time, the sending data signal decreases to a second proportional threshold value at a third time, the difference between the high-side signal and the low-side signal increases to a second threshold value at a fourth time, the fourth time is delayed by N step delays compared with the third time, N and K are positive integers and 2≤N

Description

Technical Field

[0001] The present application relates to the technical field of CAN transceivers, and in particular to a CAN transceiver. Background Art

[0002] With the development of automotive electronics, the amount of data that the vehicle body needs to process is getting bigger and bigger. Therefore, the CAN bus widely used in automotive communications also needs to have a faster bus transmission speed. However, the faster the bus transmission speed, the higher the timing requirements for the CAN transceiver. In CAN communication, the CAN transceiver usually receives the transmit data signal TX from the transmit data port TXD, and changes the differential signal between the high-side signal port and the low-side signal port of the CAN transceiver according to the logic potential of the transmit data signal, and outputs the output signal in a dominant position or a recessive position. However, in the process of changing the logic potential of the transmit data signal, when the transmit data signal switches from a logic low potential to a logic high potential, the transmit data signal is confirmed to be at a logic high potential only when the real-time value is higher than a certain ratio threshold. Similarly, when switching from a logic high potential to a logic low potential, the transmit data signal is confirmed to be at a logic low potential only when the real-time value is lower than a certain ratio threshold, such as Figure 1 As shown in the figure, the time difference between the logic high and logic low levels of the transmit data signal is called the bit width time tbit(TXD). When the transmit data signal is confirmed to be a logic high level, the differential voltage begins to decrease. When the differential voltage drops to the first threshold, the CAN transceiver is in the recessive position. When the transmit data signal is confirmed to be a logic low level, the differential voltage begins to increase. When the differential voltage increases to the second threshold, the CAN transceiver is in the dominant position. The time difference between the recessive and dominant positions of the CAN transceiver is called the bus threshold time tbit(BUS). Because the time it takes for the differential voltage to decrease from its highest value to the first threshold is generally longer than the time it takes to increase from its lowest value to the second threshold, a time difference occurs between the bit width time tbit(TXD) and the bus threshold time tbit(BUS), namely the bit width change time Δtbit(BUS). High-speed CAN bus data transmission requires a smaller bit width change time. If the bit width change time is too long, it may cause signal distortion, thereby affecting the correct reception of data. Summary of the Invention

[0003] The present application provides a CAN transceiver, which aims to solve the problem in the prior art that the CAN bus bit width time is too large, resulting in signal distortion and affecting the correct reception of data.

[0004] According to the first aspect of the present application, the present application provides a CAN transceiver, comprising: a transmitting data port, receiving a transmitting data signal; a high-side bus port, outputting a high-side signal; a low-side bus port, outputting a low-side signal; a delay driving circuit, having an input end for receiving a transmitting data signal, having K high-side output ends for providing K high-side control signals, and K low-side output ends for providing K low-side control signals, wherein the delay driving circuit generates K high-side control signals and K low-side control signals according to the transmitting data signal; a high-side control circuit, having K input ends for receiving K high-side control signals, having an output end coupled to the high-side bus port and outputting a high-side signal, wherein the high-side control circuit generates A high-side signal; a low-side control circuit having K input terminals receiving K low-side control signals, an output terminal coupled to the low-side bus port and outputting the low-side signal, wherein the low-side control circuit generates a low-side signal according to the K low-side control signals; the transmitted data signal increases to a first proportional threshold at a first time, and the difference between the high-side signal and the low-side signal decreases to a first threshold at a second time, wherein the second time is delayed by N step delays compared to the first time; the transmitted data signal decreases to a second proportional threshold at a third time, and the difference between the high-side signal and the low-side signal increases to a second threshold at a fourth time, wherein the fourth time is delayed by N step delays compared to the third time, wherein N and K are positive integers, and 2≤N<K.

[0005] Through one or more of the above embodiments of the present invention, at least the following technical effects can be achieved:

[0006] The CAN transceiver provided in the present application sets a delay driving circuit, which delays the time when the difference between the high-side signal and the low-side signal is at the first threshold by N step delays compared to the time when the data signal is sent at the first proportional threshold, and delays the time when the difference between the high-side signal and the low-side signal is at the second threshold by N step delays compared to the time when the data signal is sent at the second proportional threshold, so that the time difference between the bit width time tbit(TXD) and the bus threshold time tbit(BUS) (i.e., the bit width change time) is reduced to 0, thereby improving the reliability and fidelity of CAN bus data transmission and being able to match higher CAN bus signal transmission speeds. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0008] Figure 1A structural diagram of a CAN bus system according to an embodiment of the present invention is provided;

[0009] Figure 2 The signal waveform diagram of the existing CAN transceiver when the dominant and recessive bits are switched is given;

[0010] Figure 3 A schematic structural diagram of a CAN transceiver according to an embodiment of the present invention is provided;

[0011] Figure 4 Given Figure 3 The waveform diagram of each signal in the CAN transceiver is shown. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0013] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0014] It should be understood that in the following description, a "circuit" refers to a conductive loop formed by at least one element or subcircuit connected electrically or electromagnetically. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected" between two nodes, it can be directly coupled or connected to the other element or there can be intermediate elements. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two elements.

[0015] Figure 1The structure diagram of a CAN bus system according to an embodiment of the present application is shown. The CAN bus system includes a CAN controller and a CAN transceiver, and the CAN transceiver includes a transmitting data port TXD and a receiving data port RXD. The CAN transceiver receives a transmitting data signal TX generated by the CAN controller and converts it into a high-side signal VH and a low-side signal VL conforming to the CAN bus signal specification for transmission on the CAN bus. The CAN transceiver demodulates, amplifies and converts the high-side signal VH and the low-side signal VL received into a receiving data signal RX and outputs the receiving data signal RX from its receiving data port RXD to the CAN controller. In CAN bus communication, different data bits (dominant or recessive) are represented by changing the level difference between the high-side signal VH and the low-side signal VL, so that data transmission and reception are achieved. The switching of dominant bits and recessive bits determines the differential voltage on the CAN bus. In a dominant bit, the differential voltage Vdiff between the high-side signal VH and the low-side signal VL is large; in a recessive bit, the differential voltage Vdiff between the high-side signal VH and the low-side signal VL is small or even close to 0.

[0016] Figure 2 The signal waveform diagram of the existing CAN transceiver in dominant / recessive bit switching is shown. In a CAN bus system, the typical dominant bit differential voltage Vdiff is 2.2V, which can ensure the noise tolerance and data reliability in the communication process. In the transformation process of the differential voltage Vdiff from a dominant bit to a recessive bit, when the differential voltage Vdiff is less than a first threshold Vth1, it is determined that the CAN transceiver is in a recessive bit, and in the transformation process from a recessive bit to a dominant bit, when the differential voltage Vdiff is greater than a second threshold Vth2, it is determined that the CAN transceiver is in a dominant bit, as shown in Figure 2 the time difference between the first threshold Vth1 and the second threshold Vth2 is the bus threshold time tbit(BUS), i.e. the transition period between the CAN transceiver detecting that the voltage is less than the first threshold Vth1 and detecting that the voltage is not greater than the second threshold Vth2, and in order to prevent the interference of noise and interference, a stable time needs to be maintained in this range. Similarly, for the transmitting data signal TX received by the CAN transceiver, when the value of TX reaches the first proportional threshold A1 of the logic high level value when it is switched from a logic low level to a logic high level, it is determined that the transmitting data signal TX is a logic high level, and when the value of TX reaches the second proportional threshold A2 of the logic high level value when it is switched from a logic high level to a logic low level, it is determined that the transmitting data signal TX is a logic low level. The time difference between the first proportional threshold A1 and the second proportional threshold A2 is the bit width time tbit(TXD). And the bus threshold time tbit(BUS) minus tbit(TXD) is the bit width change time Atbit(BUS) of the bus BUS, and the calculation formula is:

[0017] Δtbit(BUS) = tbit(BUS) - tbit(TXD)

[0018] Bit width change time is an important parameter of CAN bus system, directly affecting the reliability and speed of bus data transmission, the lower the bit width change time (i.e. the shorter the bit time), generally means higher communication rate and better real-time performance. In the prior art, the delay of the transmission data signal TX from explicit to implicit is consistent with the delay of the transmission data signal TX from implicit to explicit, the first proportion threshold A1 + the second proportion threshold A2 is 100%, and since the delay of the differential voltage Vdiff from explicit to implicit is greater than the delay of the differential voltage Vdiff from implicit to explicit, the first threshold Vth1 + the second threshold Vth2 is less than the explicit value of the differential voltage, thereby causing the bit width change time to be too high.

[0019] Figure 3 A structure schematic diagram of a CAN transceiver according to an embodiment of the present application is given. The CAN transceiver includes a transmission data port TXD, a high-side bus port CANH, a low-side bus port CANL, a delay driving circuit 10 and a low-side control circuit 30.

[0020] The transmission data port TXD receives a transmission data signal TX, the high-side bus port CANH outputs a high-side signal VH, and the low-side bus port CANL outputs a low-side signal VL. The delay driving circuit 10 has an input end receiving the transmission data signal TX, has K high-side output ends to provide K high-side control signals VCH, and has K low-side output ends to provide K low-side control signals VCL, the delay driving circuit 10 generates the K high-side control signals VCH and the K low-side control signals VCL according to the transmission data signal TX. The high-side control circuit 20 has K input ends receiving the K high-side control signals VCH, has an output end coupled to the high-side bus port CANH and outputs the high-side signal VH, and the high-side control circuit 20 generates the high-side signal VH according to the K high-side control signals VCH. The low-side control circuit 30 has K input ends receiving the K low-side control signals VCL, has an output end coupled to the low-side bus port CANL and outputs the low-side signal VL, and the low-side control circuit 30 generates the low-side signal VL according to the K low-side control signals VCL.

[0021] In Figure 3In the illustrated embodiment, the delay driving circuit 10 includes a delay circuit 11, a logic circuit 12, and a driving circuit 13. The delay circuit 11 has an input terminal for receiving a transmit data signal TX and an output terminal for providing a delayed signal. The delay circuit 11 generates the delayed signal based on the transmit data signal TX. The logic circuit 12 has a first input terminal for receiving the delayed signal, a second input terminal for receiving the transmit data signal TX, and an output terminal for providing a logic signal. The logic circuit 12 performs a logical operation based on the delayed signal and the transmit data signal TX to generate the logic signal. The driving circuit 13 has an input terminal for receiving the logic signal, K high-side output terminals for providing K high-side control signals VCH, and K low-side output terminals for providing K low-side control signals VCL. The driving circuit 13 generates K high-side control signals VCH and K low-side control signals VCL based on the logic signals.

[0022] exist Figure 3 In the embodiment shown, the delay circuit 11 includes NM step delay circuits 11 connected in series, and the output signal of the subsequent step delay circuit 11 is separated from the output signal of the previous step delay circuit 11 by one step delay. The input end of the first-stage step delay circuit B1 receives the transmit data signal TX. The input end of the second-stage step delay circuit B2 is coupled to the output end of the first-stage step delay circuit B1 and receives the output signal of the first-stage step delay circuit B1. The output signal of the first-stage step delay circuit B1 is separated from the input signal of the first-stage step delay circuit B1 (i.e., the transmit data signal TX) by one step delay. Similarly, the output signal of the second-stage step delay circuit B2 is separated from the input signal of the second-stage step delay circuit B2 (i.e., the output signal of the first-stage step delay circuit B1) by one step delay, and is separated from the input signal of the first-stage step delay circuit B1 by one step delay. Similarly, the output signal (i.e., the delay signal) of the NMth step delay circuit 11 is separated from the transmit data signal TX by NM step delays. Exemplarily, the step delay circuit 11 may include a buffer.

[0023] exist Figure 3 In the embodiment shown, the logic circuit 12 includes a logic OR circuit having a first input end for receiving the delayed signal, a second input end for receiving the transmit data signal TX, and an output end for providing the logic signal. The logic OR circuit performs an OR operation on the delayed signal and the transmit data signal TX to generate the logic signal.

[0024] exist Figure 3In the illustrated embodiment, the driving circuit 13 includes K step driving circuits 13 coupled in series, which provide corresponding K high-side control signals VCH and K low-side control signals VCL, including a first high-side control signal VCH1 to a Kth high-side control signal VCHK, a first low-side control signal VCL1 to a Kth low-side control signal VCLK. A first step driving circuit 13 has an input terminal, a high-side output terminal and a low-side output terminal, wherein the input terminal receives the logic signal, the high-side output terminal provides the first high-side control signal VCH1, and the low-side output terminal provides the first low-side control signal VCL1, and the first step driving circuit 13 generates the first high-side control signal VCH1 and the first low-side control signal VCL1 according to the logic signal, wherein the first high-side control signal VCH1 is inverted from the first low-side control signal VCL1. A Kth step driving circuit 13 has an input terminal, a high-side output terminal and a low-side output terminal, wherein the input terminal is coupled to the high-side output terminal of a K-1th step driving circuit 13 to receive a K-1th high-side control signal VCHK-1, the high-side output terminal provides a Kth high-side control signal VCHK, and the low-side output terminal provides a Kth low-side control signal VCLK, and the Kth step driving circuit 13 generates the Kth high-side control signal VCHK and the Kth low-side control signal VCLK according to the K-1th high-side control signal VCHK-1, wherein the Kth high-side control signal VCHK is delayed from the K-1th high-side control signal VCHK-1 by one step delay.

[0025] In some embodiments, the step driving circuit 13 includes a first inverter and a second inverter, the first inverter has an input terminal and an output terminal, wherein the input terminal receives a logic signal or a high-side control signal VCH provided by a previous step driving circuit 13, and the output terminal provides a low-side control signal VCL, and the first inverter generates the low-side control signal VCL inverted from the logic signal or the high-side control signal VCH provided by the previous step driving circuit 13. The second inverter has an input terminal and an output terminal, wherein the input terminal receives the low-side control signal VCL, and the output terminal provides the high-side control signal VCH, and the second inverter generates the high-side control signal VCH inverted from the low-side control signal VCL.

[0026] In some embodiments, the step driving circuit 13 includes a first inverter and a second inverter, the first inverter has an input terminal and an output terminal, wherein the input terminal receives a logic signal or a high-side control signal VCH provided by a previous step driving circuit 13, and the output terminal provides a low-side control signal VCL, and the first inverter generates the low-side control signal VCL inverted from the logic signal or the high-side control signal VCH provided by the previous step driving circuit 13. The second inverter has an input terminal and an output terminal, wherein the input terminal receives the low-side control signal VCL, and the output terminal provides the high-side control signal VCH, and the second inverter generates the high-side control signal VCH inverted from the low-side control signal VCL. Figure 3In the illustrated embodiment, the high-side control circuit 20 includes K P-type switching transistors MP1 to MPK. Each of the switching transistors MP1 to MPK has a first terminal coupled to a power supply voltage, a third terminal coupled to a high-side bus port CANH, and a second terminal receiving a high-side control signal VCH. Each switching transistor receives a corresponding high-side control signal VCH. The low-side control circuit 30 includes K N-type switching transistors MN1 to MNK. Each of the switching transistors MN1 to MNK has a first terminal coupled to a low-side bus port CANL, a third terminal coupled to a reference ground, and a second terminal receiving a low-side control signal VCL. Each switching transistor receives a corresponding low-side control signal VCL.

[0027] Figure 4 Given Figure 3 The waveform diagram of each signal in the CAN transceiver is shown in Figure 2. Figure 3 The CAN transceiver structure shown is Figure 4 The waveforms of the various signals in the Figure 4 In the illustrated embodiment, the first state is a logic low state, and the second state is a logic high state.

[0028] At the first time t1, the data transmission signal TX increases to the first proportional threshold value A1, the data transmission signal TX is at a logic high level, and the logic signal provided by the logic circuit 12 is switched from the first state to the second state. For example, the first high-side control signal VCH is switched from the first state to the second state. After a step delay, the second high-side control signal VCH is switched from the first state to the second state. Since each high-side control signal VCH is coupled to the second end of a P-type switch tube in the high-side control circuit 20, the P-type switches in the high-side control circuit 20 are turned off one by one, and the high-side control circuit 20 is switched from the power supply voltage to the second state. The high-side step impedance RH between the high-side bus port CANH gradually increases. Similarly, when the logic signal switches from the first state to the second state, the first low-side control signal VCL switches from the second state to the first state. After a step delay, the second low-side control signal VCL switches from the second state to the first state. Since each low-side control signal VCL is coupled to the second terminal of an N-type switch in the low-side control circuit 30, the N-type switches in the low-side control circuit 30 are turned off one by one, and the low-side step impedance RL between the power supply voltage and the high-side bus port CANH in the low-side control circuit 30 gradually increases. Due to the increase in the high-side step impedance RH and the low-side step impedance RL, the differential voltage Vdiff between the high-side bus port CANH and the low-side bus port CANL gradually decreases.

[0029] At the second time t2, after N step delays, the differential voltage Vdiff decreases to the first threshold Vth1 at the second time t2, and the CAN transceiver switches from a dominant bit to a recessive bit.

[0030] Between the second time t2 and the third time t3, after K-1 step delays, the K high-side control signals VCH all switch to the second state, the K low-side control signals VCL all switch to the first state, the high-side step impedance RH and the low-side step impedance RL reach their maximum values, and the differential voltage Vdiff drops to its minimum value. After the differential voltage Vdiff drops to its minimum value for a period of time, the transmit data signal TX begins to decrease.

[0031] At the third time t3 , the transmission data signal TX decreases to the second proportional threshold A2 , and the transmission data signal TX is at a logic low level.

[0032] Between the fifth time t5 and the third time t3, after NM step delays of the delay circuit 11, the logic signal output by the logic circuit 12 is switched from the second state to the first state at the fifth time t5, and the first high-side control signal VCH is switched from the second state to the first state. After one step delay, the second high-side control signal VCH is switched from the second state to the first state. Similarly, the first low-side control signal VCL is switched from the first state to the second state. After one step delay, the second low-side control signal VCL is switched from the first state to the second state, and so on.

[0033] At the fourth time t4, after M step delays, the differential voltage Vdiff decreases to the second threshold Vth2 at the second time t2, and the CAN transceiver switches from a recessive position to a dominant position. After K-1 step delays, the K high-side control signals VCH all switch to the first state. When the logic signal switches from the second state to the first state, after K-1 step delays, the K low-side control signals VCL all switch to the second state.

[0034] exist Figure 3In the illustrated embodiment, the difference between the high-side signal VH and the low-side signal VL decreases to a first threshold Vth1 at a second time t2, wherein the second time t2 is delayed by N time steps compared to the first time t1. The transmit data signal TX decreases to a second proportional threshold A2 at a third time t3, and the difference between the high-side signal VH and the low-side signal VL increases to a second threshold Vth2 at a fourth time t4, wherein the fourth time t4 is delayed by N time steps compared to the third time t3, where N and K are positive integers and 2≤N<K. The logic signal switches from the second state to the first state at a fifth time t5, wherein the fifth time t5 is earlier by M time steps compared to the fourth time t4 and delayed by NM time steps compared to the third time t3, where M is a positive integer and 2≤M<N.

[0035] In some embodiments, the first ratio threshold A1 is 70%, the second ratio threshold A2 is 30%, the first threshold Vth1 is 500 mV, and the second threshold Vth2 is 900 mV.

[0036] In some embodiments, when the K high-side control signals VCH are all switched to the second state, the difference between the high-side signal VH and the low-side signal VL is 0V; when the K high-side control signals VCH are all switched to the first state, the difference between the high-side signal VH and the low-side signal VL is 2.2V.

[0037] The present invention delays the transmission of the transmission data signal TXTX at the time when the falling edge changes to a logic low level through the delay driving circuit 10, so that the time from the time when the rising edge of the transmission data signal TX changes to a logic high level to the time when the CAN transceiver outputs a recessive state is equal to the time from the time when the transmission data signal TX changes to a logic low level at the falling edge to the time when the CAN transceiver outputs a dominant state, both of which are N step delays, thereby making the bus threshold time tbit(BUS) and the bit width time tbit(TXD), and further making the bit width change time Δtbit(BUS)=0, greatly improving the reliability and speed of CAN bus data transmission.

[0038] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A CAN transceiver, characterized in that: include: Sending data port, receiving and sending data signals; High-side bus port, outputs high-side signal; Low-side bus port, outputs low-side signal; A delay driving circuit having an input terminal for receiving a transmit data signal, K high-side output terminals for providing K high-side control signals, and K low-side output terminals for providing K low-side control signals, wherein the delay driving circuit generates K high-side control signals and K low-side control signals according to the transmit data signal; A high-side control circuit has K input terminals for receiving K high-side control signals, and an output terminal coupled to the high-side bus port for outputting the high-side signal, wherein the high-side control circuit generates a high-side signal according to the K high-side control signals; a low-side control circuit having K input terminals for receiving K low-side control signals, and an output terminal coupled to the low-side bus port for outputting the low-side signal, wherein the low-side control circuit generates a low-side signal according to the K low-side control signals; The transmitted data signal increases to a first proportional threshold at a first time, and the difference between the high-side signal and the low-side signal decreases to a first threshold at a second time, wherein the second time is delayed by N step delays compared to the first time; the transmitted data signal decreases to a second proportional threshold at a third time, and the difference between the high-side signal and the low-side signal increases to a second threshold at a fourth time, wherein the fourth time is delayed by N step delays compared to the third time, wherein N and K are positive integers, and 2≤N<K.

2. The CAN transceiver according to claim 1, wherein: The first ratio threshold is 70%, the second ratio threshold is 30%, the first threshold is 500 mV, and the second threshold is 900 mV.

3. The CAN transceiver according to claim 1, wherein: The delay driving circuit comprises: A delay circuit having an input end for receiving a transmission data signal and an output end for providing a delay signal, wherein the delay circuit generates the delay signal according to the transmission data signal; a logic circuit having a first input terminal for receiving the delay signal, a second input terminal for receiving the transmission data signal, and an output terminal for providing a logic signal, wherein the logic circuit generates the logic signal by performing a logic operation based on the delay signal and the transmission data signal; The driving circuit has an input end for receiving a logic signal, K high-side output ends for providing K high-side control signals, and K low-side output ends for providing K low-side control signals. The driving circuit generates K high-side control signals and K low-side control signals according to the logic signal.

4. The CAN transceiver according to claim 3, characterized in that When the transmitted data signal increases to a first proportional threshold at a first time, the logic signal switches from the first state to the second state; when the transmitted data signal decreases to a second proportional threshold at a third time, the logic signal remains in the second state; and the logic signal switches from the second state to the first state at a fifth time. The fifth time is earlier than the fourth time by M step delays, and the fifth time is delayed by NM step delays compared to the third time, where M is a positive integer and 2≤M<N.

5. The CAN transceiver according to claim 3, characterized in that: The delay circuit includes NM serially connected step delay circuits, and the output signal of the next step delay circuit is separated from the output signal of the previous step delay circuit by a step delay.

6. The CAN transceiver according to claim 3, characterized in that: The logic circuit includes a logic OR circuit having a first input end for receiving the delay signal, a second input end for receiving the transmission data signal, and an output end for providing the logic signal. The logic OR circuit performs an OR operation on the delay signal and the transmission data signal to generate the logic signal.

7. The CAN transceiver according to claim 3, characterized in that The driving circuit includes K stepping driving circuits coupled in series, The first stepper drive circuit has an input terminal, a high-side output terminal and a low-side output terminal, wherein the input terminal receives the logic signal, the high-side output terminal provides a first high-side control signal, and the low-side output terminal provides a first low-side control signal, and the first stepper drive circuit generates a first high-side control signal and a first low-side control signal according to the logic signal, wherein the first high-side control signal is inverted with respect to the first low-side control signal; The Kth stepper drive circuit has an input end, a high-side output end and a low-side output end, wherein the input end is coupled to the high-side output end of the K-1th stepper drive circuit to receive the K-1th high-side control signal, the high-side output end provides the Kth high-side control signal, and the low-side output end provides the Kth low-side control signal. The Kth stepper drive circuit generates the Kth high-side control signal and the Kth low-side control signal according to the K-1th high-side control signal, wherein the Kth high-side control signal is delayed by one step delay compared to the K-1th control signal.

8. The CAN transceiver according to claim 7, characterized in that: K serially coupled stepper drive circuits provide corresponding K high-side control signals and K low-side control signals, including a first high-side control signal to a K-th high-side control signal and a first low-side control signal to a K-th low-side control signal; When the logic signal is switched from the first state to the second state, the first high-side control signal is switched from the first state to the second state, after a step delay, the second high-side control signal is switched from the first state to the second state, after K-1 step delays, the K high-side control signals are all switched to the second state; when the logic signal is switched from the first state to the second state, the first low-side control signal is switched from the second state to the first state, after a step delay, the second low-side control signal is switched from the second state to the first state, after K-1 step delays, the K low-side control signals are all switched to the first state; When the logic signal switches from the second state to the first state, the first high-side control signal switches from the second state to the first state, and after one step delay, the second high-side control signal switches from the second state to the first state, and after K-1 step delays, the K high-side control signals are all switched to the first state; when the logic signal switches from the second state to the first state, the first low-side control signal switches from the first state to the second state, and after one step delay, the second low-side control signal switches from the first state to the second state, and after K-1 step delays, the K low-side control signals are all switched to the second state.

9. The CAN transceiver according to claim 8, characterized in that: When the K high-side control signals are all switched to the second state, the difference between the high-side signal and the low-side signal is 0V; when the K high-side control signals are all switched to the first state, the difference between the high-side signal and the low-side signal is 2.2V.

10. The CAN transceiver according to claim 7, characterized in that: The stepping drive circuit comprises: a first inverter having an input end and an output end, wherein the input end receives a logic signal or a high-side control signal provided by a previous stepper drive circuit, and the output end provides a low-side control signal, and the first inverter generates a low-side control signal inverted thereto according to the logic signal or the high-side control signal provided by the previous stepper drive circuit; The second inverter has an input terminal and an output terminal, wherein the input terminal receives a low-side control signal and the output terminal provides a high-side control signal. The second inverter generates a high-side control signal inverted to the low-side control signal according to the low-side control signal.

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