Multi-channel LVDS format data receiving and storing device

Abstract

The invention relates to the technical field of electronics, in particular to a multichannel LVDS (Low Voltage Differential Signaling) format data receiving and storing device, which comprises an LVDS data conversion module, a data signal extraction module, a channel data caching module, a data integration module and a data storage module, wherein the channel data caching module is realized based on FIFO (First In First Out) in an FPGA (Field Programmable Gate Array), a channel alignment function of image data is completed, and compared with a shift register, the channel data caching module has the advantages that the caching depth is deeper, clocks with different frequencies are supported to be read and written, and the system stability is higher.

Description

Technical Field

[0001] The invention belongs to the technical field of electronics, and in particular relates to a multi-channel LVDS format data receiving and storage device. Background Art

[0002] The resolution and frame rate of image sensors are constantly improving, which puts higher requirements on the image sensor drivers. The common method in the industry is to crop a high-resolution image into multiple channels for output. Take a two-dimensional image as an example, which has an x-axis and a y-axis. Existing image sensors usually use LVDS (Low-Voltage DifferentialSignaling) format as the image data output format. LVDS format data usually contains two physical connection signal lines, namely the positive line and the negative line. The image data is first converted from parallel to serial bit data, and then transmitted through the two LVDS signal lines. The FPGA-based driver first receives the LVDS data through the LVDS receiving module, converts it into parallel data, and then time-aligns the LVDS data of multiple channels through data training, byte alignment and channel alignment, thereby achieving accurate image acquisition.

[0003] Existing LVDS training and channel alignment methods usually use mature modules provided by device manufacturers, such as LVDS receiving buffer, DELAY delay module, ISERDES serial-to-parallel conversion module, shift register module and RAM cache. Figure 1 As shown in the figure. In this method, the purpose of the shift register is to achieve channel alignment. However, as the resolution of today's image sensors increases, the number of LVDS data channels also increases. Shift registers with too many channels (such as 32 channels) will occupy a large amount of FPGA cache resources, and will also consume the layout and routing resources of the FPGA internal program, resulting in tight layout and routing. At the same time, the shift register needs to perform data movement operations in the same clock domain, resulting in excessive fan-out of a single clock, which is not conducive to clock stability. Summary of the invention

[0004] In view of this, the invention aims to provide a multi-channel LVDS format data receiving and storage device, which uses the mature cache resource FIFO (First Input First Output) inside the FPGA to realize the channel alignment function of the image data. Compared with the shift register, the advantage of FIFO is that the cache depth is deeper, it supports reading and writing clocks of different frequencies, and the system stability is higher.

[0005] To achieve the above object, the technical solution created by the present invention is implemented as follows: A multi-channel LVDS format data receiving and storage device, comprising: LVDS data conversion module, converting the transmitted multi-channel LVDS format data into multi-channel parallel data; A data signal extraction module, which identifies and extracts a field synchronization signal, a line synchronization signal and a data signal of parallel data of each channel in multi-channel parallel data; A channel data buffer module receives the field synchronization signal, the line synchronization signal and the data signal of each channel, and writes the data signal into the FIFO of the corresponding channel according to the field synchronization signal and the line synchronization signal; A data synthesis module extracts data signals from the FIFO of each channel and outputs the data signals in the FIFO of each channel; The data storage module receives and stores the data signals obtained by the data integration module, and combines the received data signals to obtain a complete image.

[0006] Furthermore, the LVDS data conversion module includes LVDS data conversion sub-modules, and the number of LVDS data conversion sub-modules is consistent with the number of channels of multi-channel parallel data; each LVDS data conversion sub-module includes a delay sub-module and a serial-to-parallel conversion sub-module; wherein: the LVDS format data of the current channel is collected according to the clock, and the delay is increased by the LVDS format data of the current channel using the delay sub-module, so that the LVDS format data of the current channel is synchronized with the clock; and then the LVDS format data of the current channel is converted by the serial-to-parallel conversion sub-module to obtain byte-aligned parallel data of the current channel, and then obtain multi-channel parallel data.

[0007] Furthermore, the data signal extraction module includes data signal extraction sub-modules, and the number of data signal extraction sub-modules is consistent with the number of channels of multi-channel parallel data; in each data signal extraction sub-module, after identifying the start flag and stop flag in the parallel data of the current channel, the field synchronization signal, line synchronization signal and data signal of the parallel data of the current channel are generated.

[0008] Furthermore, the field synchronization signal indicates the data range of a captured image, the line synchronization signal indicates the data range of a line in a captured image, and the data signal indicates the image data at the corresponding position.

[0009] Furthermore, the channel data cache module includes channel data cache sub-modules, and the number of channel data cache sub-modules is consistent with the number of channels of multi-channel parallel data; each data signal extraction sub-module inputs the field synchronization signal, line synchronization signal and data signal of the current channel into the corresponding channel data cache sub-module; each channel data cache sub-module inputs the data signal of the current channel into the corresponding FIFO according to the field synchronization signal and line synchronization signal of the current channel.

[0010] Furthermore, in the data integration module, the information in the FIFO of each channel is read, and when the row and field synchronization signal of the current channel is valid, the data signal in the FIFO of the corresponding channel is read; when the FIFO reading of a channel is completed, the image data packet of the image corresponding to the FIFO of the channel is output, and the reading of the FIFO of the next channel is started at the same time, until the FIFO reading of all channels is completed.

[0011] Furthermore, when reading data in the corresponding channel FIFO, the reading width is 1 pixel to 8 pixels, and the reading length is the image data length corresponding to each channel.

[0012] Furthermore, the data storage module receives and stores the image data packet output by the data integration module.

[0013] Furthermore, in the multi-channel parallel data, the bit width of the parallel data of each channel is not less than 2 bits and not more than 16 bits.

[0014] Compared with the prior art, the invention can achieve the following beneficial effects: The multi-channel LVDS format data receiving and storage device created by the present invention utilizes FIFO for data caching compared to the shift register method. On the one hand, the overall image data receiving process is simplified by simplifying the channel alignment method; on the other hand, the requirement of the shift register for the simultaneous clock domain of the read and write clocks is avoided; secondly, the advantage of FIFO over the shift register is that the cache depth is deeper, it supports reading and writing clocks of different frequencies, and the system stability is higher; at the same time, FIFO is a common chip resource, and the chip manufacturer's optimization of FIFO is more perfect, making the final overall driver more stable and efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments and descriptions of the present invention are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings: Figure 1 A schematic diagram of the structure of an existing LVDS training and channel alignment device; Figure 2 A schematic diagram of the structure of a multi-channel LVDS format data receiving and storage device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the invention more clear, the invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the invention and do not constitute a limitation of the invention.

[0017] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0018] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0019] In the description of the invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances.

[0020] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0021] like Figure 2As shown, the multi-channel LVDS format data receiving and storage device described in the embodiment of the invention includes an LVDS data conversion module, a data signal extraction module, a channel data buffer module, a data synthesis module and a data storage module. Among them, the LVDS data conversion module converts the transmitted multi-channel LVDS format data into multi-channel parallel data, and then transmits the multi-channel parallel data to the data signal extraction module through an interface, wherein the LVDS format data in each channel is serial data, and the bit width of the parallel data of each channel in the multi-channel parallel data is not less than 2 bits and not more than 16 bits; the data signal extraction module identifies and extracts the field synchronization signal, line synchronization signal and data signal of the parallel data of each channel in the multi-channel parallel data; the channel data buffer module receives the field synchronization signal, line synchronization signal and data signal of each channel, and writes the data signal into the FIFO of the corresponding channel according to the field synchronization signal and the line synchronization signal; the data synthesis module extracts the data signal from the FIFO of each channel, and outputs the data signal in the FIFO of each channel; the data storage module receives and stores the data signal obtained by the data synthesis module, and combines the received data signals to obtain a complete image.

[0022] The LVDS data conversion module includes LVDS data conversion submodules, and the number of LVDS data conversion submodules is consistent with the number of channels of multi-channel parallel data; each LVDS data conversion submodule includes a delay submodule and a serial-to-parallel conversion submodule. During the transmission of the signal in the electronic circuit hardware, a certain delay will be generated. Since the clock signal and the data signal are transmitted on different actual physical circuits, it is impossible to achieve consistent transmission delay. At the same time, a certain delay will still be generated during the internal synthesis and layout and routing of the FPGA. The combined effect of the above delays will cause the first valid data of the clock line and the data line to have different delays when the signal is sent from the external chip to the receiving device. At this time, the delay submodule is required to add a certain delay to the data or clock module to achieve the alignment of the first single-bit valid data of the clock and data lines. In addition, before outputting the image data, the image sensor will cyclically output the training data code, which is usually specified in the instruction manual provided by the image sensor manufacturer. In each LVDS data conversion submodule, firstly, the LVDS format data of the current channel is collected by using the clock in the instruction manual. At this time, the training data code collected without data training does not conform to the training data code specified in the manual because of the offset between the clock and the LVDS format data of the current channel. And because the collected training data code jumps over time and is not stable data, it is necessary to use the data training method to adjust the alignment relationship between the LVDS format data of the current channel and the clock by using the delay submodule. In the present invention, the delay submodule is used to increase the delay of the LVDS format data of the current channel transmitted in the form of a single data line, so that the LVDS format data of the current channel is synchronized with the clock, thereby realizing the long-term stable collection of the LVDS format data of the current channel. The serial-to-parallel conversion submodule converts the LVDS format data of the current channel from a serial signal to a parallel signal by means of data bit swapping, and obtains the training data code specified in the manual at the same time. When the training data code specified in the manual is collected for a long time and stably, the data training and byte alignment process of the image is completed, and the byte-aligned parallel data of the current channel is obtained, and then the multi-channel parallel data is obtained.

[0023] The data signal extraction module includes data signal extraction submodules, and the number of data signal extraction submodules is consistent with the number of channels of multi-channel parallel data; in each data signal extraction submodule, after identifying the start flag and the stop flag in the parallel data of the current channel, the image data between the start flag and the stop flag can be determined. With the start flag and the stop flag, a field synchronization signal and a line synchronization signal can be generated to indicate the image data position, as well as the data signal between the field synchronization signal and the line synchronization signal. Different models of image sensors from different manufacturers use different start flags and stop flags. The data signal extraction module needs to rely on the instruction manual provided by the image sensor device manufacturer to determine the image flag that needs to be identified. When the data signal extraction submodule identifies the corresponding start flag, it will generate a corresponding synchronization signal. Since in data transmission, not only image data but also some other redundant data are transmitted, and redundant data is invalid data for the system, the overall transmission method is that image data and invalid data are output in a certain way. The line field synchronization signal indicates that in this series of data, the part where the line field signal is valid is the image data, and the part where the line synchronization signal is invalid is the invalid data. The part where both the line and field synchronization are invalid is also invalid data. Therefore, a complete image sensor data stream needs to include field synchronization signals, line synchronization signals and data signals. The field synchronization signal is used to indicate the corresponding position from the first pixel to the last pixel of an image, and the line synchronization is used to indicate the first to the last pixel of each line. The two synchronization signals together complete the indication of the entire image, and the data signal is used to indicate the image data at the corresponding position. After the data signal extraction submodule extracts the field synchronization signal, line synchronization signal and data signal of the parallel data of the current channel, the data signal extraction submodule will output these three types of signals to the subsequent channel data cache module. The three types of signals output by the data signal extraction module can only ensure that the channel data it processes is aligned. However, the data content between channels cannot be guaranteed to be aligned, so it is necessary to achieve alignment between channels through the channel data cache module.

[0024] The core of the channel data cache module is to implement cache based on the FIFO IP core of the FPGA chip device manufacturer. The channel data cache module receives the field synchronization signal, line synchronization signal and image data sent by the data signal extraction module. Write the valid image data indicated by the line and field synchronization signal into the FIFO module. Specifically, the channel data cache module includes channel data cache submodules, and the number of channel data cache submodules is consistent with the number of channels of multi-channel parallel data; each data signal extraction submodule inputs the field synchronization signal, line synchronization signal and data signal of the current channel into the corresponding channel data cache submodule; each channel data cache submodule inputs the data signal of the current channel into the corresponding FIFO according to the field synchronization signal and line synchronization signal of the current channel.

[0025] In the data integration module, the information in the FIFO of each channel is read, and when the row field synchronization signal of the current channel is valid, the data signal in the FIFO of the corresponding channel is read; after the FIFO reading of a channel is completed, the image data packet of the image corresponding to the FIFO of the channel is output, and the FIFO of the next reading channel is started at the same time, until the FIFO reading of all channels is completed. In the embodiment of the present invention, the data integration module reads the data signal in the FIFO of each channel by row.

[0026] In the data storage module, the image data packet output by the data integration module is received and stored. In the embodiment of the present invention, the RAM module is used as the data storage module to perform row caching of the image data, that is, the data integration module reads the FIFO of the corresponding channel row by row according to the full image, and each time the data integration module reads out an image data packet (which may contain multiple pixels), it writes it into the RAM module. This method can avoid intermediate data caching and reduce intermediate occupancy.

[0027] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the disclosure of the present invention can be performed in parallel, sequentially or in different orders, as long as the desired results of the technical solution disclosed in the present invention can be achieved, and this document does not limit this.

[0028] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-channel LVDS format data receiving and storage device, characterized in that: include: LVDS data conversion module, converting the transmitted multi-channel LVDS format data into multi-channel parallel data; A data signal extraction module, which identifies and extracts a field synchronization signal, a line synchronization signal and a data signal of parallel data of each channel in the multi-channel parallel data; A channel data buffer module receives the field synchronization signal, the line synchronization signal and the data signal of each channel, and writes the data signal into the FIFO of the corresponding channel according to the field synchronization signal and the line synchronization signal; A data synthesis module extracts data signals from the FIFO of each channel and outputs the data signals in the FIFO of each channel; The data storage module receives and stores the data signals obtained by the data integration module, and combines the received data signals to obtain a complete image.

2. The multi-channel LVDS format data receiving and storage device according to claim 1, characterized in that: The LVDS data conversion module includes LVDS data conversion submodules, and the number of the LVDS data conversion submodules is consistent with the number of channels of the multi-channel parallel data; each LVDS data conversion submodule includes a delay submodule and a serial-to-parallel conversion submodule; wherein: the LVDS format data of the current channel is collected according to the clock, and the delay submodule is used to increase the delay of the LVDS format data of the current channel so that the LVDS format data of the current channel is synchronized with the clock; and the serial-to-parallel conversion submodule is used to convert the LVDS format data of the current channel to obtain the byte-aligned parallel data of the current channel, and then obtain the multi-channel parallel data.

3. The multi-channel LVDS format data receiving and storage device according to claim 1, characterized in that: The data signal extraction module includes data signal extraction submodules, and the number of the data signal extraction submodules is consistent with the number of channels of the multi-channel parallel data; In each data signal extraction submodule, after identifying the start flag and the stop flag in the parallel data of the current channel, a field synchronization signal, a line synchronization signal and a data signal of the parallel data of the current channel are generated.

4. The multi-channel LVDS format data receiving and storage device according to any one of claims 1 to 3, characterized in that: The field synchronization signal indicates the data range of a captured image, the line synchronization signal indicates the data range of a line in a captured image, and the data signal indicates image data at a corresponding position.

5. The multi-channel LVDS format data receiving and storage device according to claim 3, characterized in that: The channel data cache module includes channel data cache sub-modules, and the number of the channel data cache sub-modules is consistent with the number of channels of the multi-channel parallel data; each data signal extraction sub-module inputs the field synchronization signal, line synchronization signal and data signal of the current channel into the corresponding channel data cache sub-module; each channel data cache sub-module inputs the data signal of the current channel into the corresponding FIFO according to the field synchronization signal and line synchronization signal of the current channel.

6. The multi-channel LVDS format data receiving and storage device according to claim 1, characterized in that: In the data integration module, the information in the FIFO of each channel is read, and when the row and field synchronization signals of the current channel are valid, the data signals in the FIFO of the corresponding channel are read; When the FIFO reading of one channel is completed, the image data packet of the image corresponding to the FIFO of the channel is output, and the FIFO reading of the next channel is started at the same time, until the FIFO reading of all channels is completed.

7. The multi-channel LVDS format data receiving and storage device according to claim 6, characterized in that: When reading data in the corresponding channel FIFO, the reading width is 1 pixel to 8 pixels, and the reading length is the image data length corresponding to each channel.

8. The multi-channel LVDS format data receiving and storage device according to claim 7, characterized in that: In the data storage module, the image data packet output by the data integration module is received and stored.

9. The multi-channel LVDS format data receiving and storage device according to claim 1, characterized in that: In the multi-channel parallel data, the bit width of the parallel data of each channel is not less than 2 bits and not more than 16 bits.

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