Shallow compression multi-stripe code rate control method and device and electronic equipment

Abstract

The embodiment of the invention provides a shallow compression multi-strip code rate control method and device and electronic equipment, and relates to the technical field of video transmission, and the method comprises the steps: determining the number of divided strips of single-frame video data of a transmission video and the number of divided sub-strips of each strip; allocating a code rate value for each stripe in the frame; in the process of inputting the video data signal into the cache, calculating the complexity of each first sub-band in the first band of the received video data signal; after the video data signal in the to-be-input cache fully occupies the first strip, correspondingly allocating a code rate value to each first sub-strip according to the complexity of each first sub-strip in the first strip; and determining a quantization parameter of each first sub-band in the first band, and correspondingly adjusting a code rate value allocated to the first sub-band according to the quantization parameter of each first sub-band. Through the code rate control method, low-delay and high-image-quality transmission of videos can be ensured.

Description

Technical Field

[0001] The present application relates to the field of video transmission technology, and in particular to a shallow compression multi-strip bit rate control method and device, and an electronic device. Background Art

[0002] The combination of real-time video transmission and encoding and decoding technology is a hot topic in the current video technology field, especially in application scenarios that pursue high quality and low latency. At present, low-latency video transmission usually adopts deep compression coding technology (such as H.264, H.265, AVS series, etc.), which balances quality and transmission efficiency by implementing bit rate control at the frame level. However, in the field of professional video, this deep compression coding still faces many challenges and shortcomings: first, the performance in high-quality video output is limited and it is difficult to meet professional-level requirements; second, the performance in low-latency performance is not satisfactory, and the latency level is high; third, the bit rate fluctuates greatly, which may lead to unstable video quality, further restricting its application effect in high-standard scenarios. Summary of the invention

[0003] In order to solve one of the above technical defects, the embodiments of the present application provide a shallow compression multi-strip bit rate control method and device, and an electronic device.

[0004] An embodiment of the present invention provides a shallow compression multi-strip bit rate control method, the method comprising: Determine the number of stripes into which a single frame of video data of a transmitted video is divided and the number of sub-strips into which each stripe is divided; assigning a bit rate value to each of the slices within the frame; During the process of inputting the video data signal into the buffer, calculating the complexity of each first sub-strip in the first stripe of the received video data signal; After the video data signal in the input buffer fills up the first stripe, a bit rate value is allocated to each of the first sub-strips according to the complexity of each of the first sub-strips in the first stripe; A quantization parameter of each of the first sub-strips in the first stripe is determined, and a bit rate value allocated to the first sub-strip is correspondingly adjusted according to the quantization parameter of each first sub-strip.

[0005] Optionally, the step of allocating a bit rate value to each of the slices in the frame includes: Determine the encoding bit rate and video frame rate of the video to be transmitted; Determining a constant bit rate according to the encoding bit rate, the video frame rate, and the number of stripes divided in the single frame of video data; A code rate value is allocated to each of the slices in a frame according to the constant code rate.

[0006] Optionally, in the process of inputting the video data signal into the buffer, the step of calculating the complexity of each first sub-strip in the first stripe of the received video data signal includes: In the process of inputting the video data signal into the buffer, dividing the first sub-strip in the first stripe of the received video data signal into a plurality of blocks; For each block divided into the first sub-strip, perform Hadamard transform on the block to obtain a DC component coefficient and an AC component coefficient of the block; Calculating the complexity of the block according to the DC component coefficient and the AC component coefficient of the block; The sum of the complexities of each block divided into the first sub-strip is determined as the complexity of the first sub-strip.

[0007] Optionally, after the video data signal to be input into the buffer occupies the first stripe, the step of allocating a bit rate value to each of the first sub-strips in the first stripe according to the complexity of each of the first sub-strips in the first stripe includes: After the video data signal in the to-be-input buffer fills up the first stripe, calculating the total complexity of each first stripe contained in the first stripe; For each first sub-strip in the first stripe, a product of the complexity of the first sub-strip and a coding rate value allocated to the first stripe is calculated, and a quotient of the product and the total complexity is determined as the coding rate value allocated to the first sub-strip.

[0008] Optionally, the step of determining a quantization parameter of each of the first sub-strips in the first stripe, and correspondingly adjusting a bit rate value allocated to the first sub-strip according to the quantization parameter of each first sub-strip includes: Determining a first quantization parameter of a first sub-strip within the first stripe; For each first sub-strip except the first first sub-strip in the first stripe, determining an integral factor and a differential factor corresponding to the first sub-strip according to bit rate values ​​allocated to the first sub-strip and each sub-strip ordered before the first sub-strip and a cumulative pre-allocated bit rate value; Calculating a quantization parameter of the first sub-band according to an integral factor and a differential factor of the first sub-band, the number of pixels included in the first sub-band, and a quantization parameter of a first sub-band that is ranked before the first sub-band; The bit rate value allocated to the first sub-strip is correspondingly adjusted according to the quantization parameter of each first sub-strip in the first stripe.

[0009] The embodiment of the present invention further provides a shallow compression multi-strip bit rate control device, wherein the device comprises: A first determination module is used to determine the number of stripes into which a single frame of video data of a transmitted video is divided and the number of sub-strips into which each stripe is divided; A first allocation module, configured to allocate a bit rate value to each of the stripes in a frame; A complexity calculation module, used for calculating the complexity of each first sub-strip in the first stripe of the received video data signal during the process of the video data signal being input into the cache; A second allocation module, configured to allocate a bit rate value to each of the first sub-strips according to the complexity of each of the first sub-strips in the first stripe after the video data signal in the input buffer fills up the first stripe; The adjustment module is used to determine the quantization parameter of each of the first sub-strips in the first stripe, and adjust the bit rate value allocated to the first sub-strip according to the quantization parameter of each first sub-strip.

[0010] Optionally, the first allocation module includes: The first submodule is used to determine the encoding bit rate and video frame rate of the video to be transmitted; A second submodule is used to determine a constant bit rate according to the encoding bit rate, the video frame rate and the number of strips divided in the single frame of video data; The third submodule is used to allocate a bit rate value to each of the stripes in the frame according to the constant bit rate.

[0011] Optionally, the complexity calculation module includes: A fourth submodule, configured to divide a first sub-strip within a first strip of a received video data signal into a plurality of blocks during the process of inputting the video data signal into a cache; A fifth submodule, configured to perform Hadamard transform on each block divided into the first sub-strip to obtain a DC component coefficient and an AC component coefficient of the block; A sixth submodule, configured to calculate the complexity of the block according to a DC component coefficient and an AC component coefficient of the block; The seventh submodule is configured to determine the sum of the complexities of each block divided into the first sub-strip as the complexity of the first sub-strip.

[0012] Optionally, the second allocation module includes: An eighth submodule, configured to calculate a total complexity of each first stripe contained in the first stripe after the video data signal in the to-be-input buffer fills up the first stripe; A ninth submodule is configured to calculate, for each first sub-strip in the first stripe, a product of the complexity of the first sub-strip and a code rate value allocated to the first stripe, and determine a quotient of the product and the total complexity as the code rate value allocated to the first sub-strip.

[0013] Optionally, the adjustment module includes: A first quantization parameter determination submodule, configured to determine a first quantization parameter of a first sub-strip within the first stripe; a factor determination submodule, configured to determine, for each first sub-strip except a first first sub-strip in the first sub-strip, an integral factor and a differential factor corresponding to the first sub-strip according to a bit rate value allocated to the first sub-strip and each sub-strip arranged before the first sub-strip and a cumulative pre-allocated bit rate value; a second quantization parameter determination submodule, configured to calculate a quantization parameter of the first sub-band according to an integral factor and a differential factor of the first sub-band, the number of pixels included in the first sub-band, and a quantization parameter of a first sub-band ranked before the first sub-band; The bit rate adjustment submodule is used to adjust the bit rate value allocated to the first sub-strip according to the quantization parameter of each first sub-strip in the first stripe.

[0014] In another aspect of the implementation of the present invention, an electronic device is provided, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; the memory is used to store computer programs; the processor is used to implement any of the above-mentioned shallow compression multi-band bit rate control methods when executing the program stored in the memory.

[0015] The shallow compression multi-strip bit rate control scheme disclosed in the present application determines the number of stripes into which a single frame of video data of a transmitted video is divided and the number of sub-strips into which each stripe is divided; allocates a bit rate value to each stripe in the frame; during the process of inputting a video data signal into a cache, calculates the complexity of each first sub-strip in a first stripe of a received video data signal; after the video data signal in the input cache fills the first stripe, allocates a bit rate value to each first sub-strip according to the complexity of each first sub-strip in the first stripe; determines a quantization parameter of each first sub-strip in the first stripe, and adjusts the bit rate value allocated to the first sub-strip according to the quantization parameter of each first sub-strip. The shallow compression multi-strip bit rate control scheme disclosed in the present application allocates and controls the bit rates for the stripe and sub-strip levels respectively, based on the characteristic that a shallow compression video frame can be divided into multiple stripes and sub-strips. The stripe level is set to a constant bit rate to facilitate the stable transmission of high-bitrate video. At the same time, the bit rate is reasonably allocated to each sub-strip within the strip according to the complexity of each sub-strip, taking into account both the encoded image quality and low encoding delay, and ensuring low-delay video transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 is a flowchart showing a method for shallow compression multi-strip bit rate control according to an embodiment of the present application; Figure 2 is a schematic diagram showing strip division of a single-frame video according to an embodiment of the present application; Figure 3 It is a structural block diagram showing a shallow compression multi-strip bit rate control device according to an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0018] With the continuous advancement of video transmission technology and the continuous improvement of bandwidth resources, in real-time transmission scenarios, the use of shallow compression coding technology with higher bit rate and better picture quality is gradually becoming an ideal solution to meet the needs of the professional video field. From a technical point of view, the notable feature of shallow compression coding is that it only uses intra-frame coding, that is, each frame of video is independent and has no inter-frame prediction or reference dependency. This independence not only improves the stability of video quality, but also significantly reduces the delay during transmission. In addition, shallow compression coding supports dividing the content within the frame into multiple units (such as strips or sub-strips) that can be independently encoded and decoded, further enhancing flexibility and adaptability. Due to the characteristics of shallow compression coding, its rate control method is essentially different from deep compression technology. The rate control method based on multiple stripes is more in line with the characteristics of shallow compression, which can not only achieve efficient use of transmission bandwidth, but also significantly optimize low-latency transmission performance. This method is particularly suitable for professional video transmission scenarios that require high quality, low latency and strong stability. Therefore, a shallow compression multi-strip rate control scheme suitable for low-latency transmission is proposed in the embodiment of the present application.

[0019] The shallow compression multi-strip bit rate control scheme provided by the embodiment of the present application is described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.

[0020] As attached Figure 1 As shown, the shallow compression multi-strip bit rate control method of the embodiment of the present application includes the following steps: Step 101: Determine the number of stripes into which a single frame of video data of a transmitted video is divided and the number of sub-strips into which each stripe is divided.

[0021] The shallow compression multi-band rate control method provided in the embodiment of the present application can be applied to an electronic device. The electronic device is provided with a storage medium, and the storage medium stores a shallow compression multi-band rate control computer program. When the shallow compression multi-band rate control computer program is executed by a processor, the shallow compression multi-band rate control method process is executed.

[0022] For shallow compression coding, one frame of video data can be divided into M stripes. Each stripe is a unit that can be independently encoded, decoded and transmitted. The number of stripes M is generally set to 4-16. Within each stripe, it can also be divided into N sub-strips. Each sub-strip is the smallest unit that can be used for bit rate control. The coding syntax of each sub-strip carries a quantization parameter QP. By controlling the size of QP, the size of the encoded data of the sub-strip can be controlled, thereby affecting the bit rate of the entire stripe. Among them, due to the different names of various shallow compression formats, sub-strips can also be called macroblock rows or block groups. An exemplary stripe division diagram of a single frame of video is shown in the figure. Figure 2 shown.

[0023] For example, when dividing a frame of video with a 3840x2160 image size into strips and sub-strips, it can be divided into 9 strips (i.e., M=9). The height of each strip is 240 lines, the height of each sub-strip is 16 lines, and each strip contains 15 sub-strips (N=15).

[0024] In actual implementation, the number of stripes into which each frame is divided and the number of sub-strips into which each stripe is divided may be preset by those skilled in the art.

[0025] Step 102: Allocate a bit rate value for each slice in the frame.

[0026] Due to the low latency requirement of video transmission, encoding cannot be performed after a frame of signal (i.e., a frame of video data) has arrived in full, and shallow compression and high bit rate transmission are more sensitive to bit rate fluctuations. Therefore, before encoding each frame of video, the same bit rate value is pre-assigned to each strip according to the CBR (Constant Bit Rate) principle.

[0027] An optional way to assign a bit rate value to each stripe in a frame may be: determining the encoding bit rate and video frame rate of the video to be transmitted; determining a constant bit rate based on the encoding bit rate, the video frame rate, and the number of stripes divided in a single frame of video data; and assigning a bit rate value to each stripe in the frame according to the constant bit rate.

[0028] Specifically, the number of bits allocated to each stripe can be calculated as follows:

[0029] Among them, bitrate is the encoding bitrate set for the video, fps is the video frame rate, and N is the number of strips in one frame of video.

[0030] Step 103: When the video data signal is input into the buffer, the complexity of each first sub-strip in the first stripe of the received video data signal is calculated.

[0031] In this step, the complexity of each sub-strip in the stripe is calculated along with the row-level signal input. In an optional process of video data signal input buffering, a method of calculating the complexity of each first sub-strip in the first stripe of the received video data signal may include the following sub-steps: Sub-step 1: during the process of video data signal inputting into a buffer, a first sub-strip in a first stripe of the received video data signal is divided into a plurality of blocks.

[0032] In actual division, the height and width of each sub-strip may be limited to multiples of 2, and each sub-strip may be regarded as a combination of several 2x2 blocks.

[0033] Sub-step 2: For each block divided into the first sub-strip, perform Hadamard transform on the block to obtain a DC component and an AC component of the block.

[0034] Perform a 2x2 Hadamard transform on each 2x2 block, and the transformation matrix is:

[0035] After the transformation, each 2x2 block obtains 1 DC coefficient (i.e., DC component coefficient) and 15 AC coefficients (i.e., AC component coefficients). The complexity of each 2x2 block is calculated as follows:

[0036] Where abs is the absolute value, DC prev is the DC coefficient after Hadamard transform of the previous 2x2 block. If this block is the first block of the strip, DC prev =0.

[0037] Sub-step 3: Calculate the complexity of the block based on the DC component coefficient and AC component coefficient of the block.

[0038] Sub-step 4: Determine the complexity of the first sub-band as the sum of the complexities of each block divided into the first sub-band.

[0039] Assuming that the number of 2x2 blocks contained in a sub-strip is L, the complexity of a sub-strip can be calculated as follows:

[0040] By repeating the above sub-steps 1 to 4, the complexity of each sub-strip in the first stripe can be calculated.

[0041] Step 104: after the video data signal in the input buffer fills up the first stripe, a bit rate value is allocated to each first sub-strip according to the complexity of each first sub-strip in the first stripe.

[0042] Since the sub-strip complexity is calculated synchronously with the signal input, when the video data signal input is enough for one stripe, the complexity of each sub-strip has been calculated. In other words, when the video data signal input is enough for one stripe, the bit rate value of the sub-strip is allocated according to the sub-strip complexity.

[0043] Optionally, after the video data signal in the input buffer fills up the first stripe, a method of allocating a bit rate value to each first sub-strip according to the complexity of each first sub-strip in the first stripe may include the following sub-steps: Sub-step 1: after the video data signal in the input buffer fills up the first stripe, calculate the total complexity of each first stripe contained in the first stripe; Sub-step 2: for each first sub-strip in the first stripe, calculate the product of the complexity of the first sub-strip and the code rate value allocated to the first stripe, and determine the quotient of the product and the total complexity as the code rate value allocated to the first sub-strip.

[0044] A feasible calculation formula for the number of bits allocated to the x-th sub-strip is as follows:

[0045] Step 105: Determine the quantization parameter of each first sub-strip in the first stripe, and adjust the bit rate value allocated to the first sub-strip according to the quantization parameter of each first sub-strip.

[0046] In this step, the quantization parameter, ie, QP, of each sub-slice is adjusted to achieve bit rate control within the slice.

[0047] A method of optionally determining a quantization parameter of each first sub-strip in a first stripe, and adjusting a code rate value allocated to a first sub-strip code according to the quantization parameter of each first sub-strip, comprises the following sub-steps: Sub-step 1: Determine a first quantization parameter of a first sub-slice in a first slice.

[0048] In this step, the quantization parameter QP of the first sub-strip in each strip is first determined. If the complexity calculated for the strip differs from the complexity of the strip at the same position in the previous frame of video by a certain threshold (indicating that the video has switched scenes), or the currently transmitted video data is the first frame of video, the quantization parameter QP of the first sub-strip takes a default initial QP based on an empirical value. Otherwise, the quantization parameter QP of the first sub-strip is set to the average value of the quantization parameters QP of all sub-strips in the strip at the same position in the previous frame of video. Sub-step 2: For each first sub-strip in the first strip except the first first sub-strip, determine the integral factor and differential factor corresponding to the first sub-strip based on the bit rate values ​​allocated to the first sub-strip and the sub-strips sorted before the first sub-strip and the accumulated pre-allocated bit rate values.

[0049] When determining the quantization parameter QP of the second sub-strip to the Nth sub-strip in each strip during the encoding process, a method of jointly determining the QP of the xth (2≤x≤N) sub-strip by integration + differentiation is proposed in the embodiment of the present application. The specific method is: Set acc_target x-1 The accumulative pre-allocated bit number (i.e., the accumulative pre-allocated bit rate value) of the 1st to the x-1th sub-strip. x-1 is the actual number of coded bits for the 1st to the x-1th sub-strip (i.e., the bit rate value allocated to the sub-strip), then the integration factor is:

[0050] Set a budget x-1 The number of pre-allocated bits for the x-1th sub-strip, actual x-1 is the actual number of coded bits of the x-1th sub-strip, then the differential factor is:

[0051] Sub-step 3: Calculate the quantization parameter of the first sub-band according to the integral factor and the differential factor of the first sub-band, the number of pixels included in the first sub-band, and the quantization parameter of the first sub-band that is ranked before the first sub-band.

[0052] Quantization parameter QP of the xth sub-slice x It can be calculated by the following formula:

[0053] Among them, QP x-1is the quantization parameter of the x-1th sub-strip, subslicesize is the number of pixels contained in each sub-strip, a is the integral coefficient, b is the differential coefficient, and round means rounding. The integral coefficient a and the differential coefficient b can be obtained by fitting multiple experimental data or using machine learning methods according to the different characteristics of various shallow compression formats.

[0054] Sub-step 4: adjusting the bit rate value allocated to the first sub-strip according to the quantization parameter of each first sub-strip in the first stripe.

[0055] The shallow compression multi-strip bit rate control method provided by the present application performs the shallow compression multi-strip bit rate control method after determining the number of stripes into which a single frame of video data of a transmitted video is divided and the number of sub-strips into which each stripe is divided. The method generally includes the following steps: assigning a bit rate value to each stripe in a frame according to the CBR principle; calculating the complexity of each sub-strip in the stripe along with the line-level signal input; after the video data signal input is sufficient for one stripe, assigning a bit rate value to the sub-strip according to the complexity of the sub-strip; and adjusting the QP of the sub-strip to achieve bit rate control within the stripe.

[0056] The shallow compression multi-strip bit rate control method provided in the embodiment of the present application, based on the characteristic that a shallow compression video frame can be divided into multiple strips and sub-strips, performs bit rate allocation and control on the stripe and sub-strip levels respectively, and sets the stripe level to a constant bit rate to facilitate stable transmission of high-bit rate video. At the same time, the bit rate is reasonably allocated to each sub-strip within the strip according to the complexity of each sub-strip, taking into account both the encoded image quality and low encoding delay, and ensuring low-delay transmission of video.

[0057] Figure 3 A structural block diagram of a shallow compression multi-strip bit rate control device for implementing an embodiment of the present application.

[0058] The shallow compression multi-strip bit rate control device provided in the embodiment of the present application includes the following functional modules: A first determination module 301 is used to determine the number of stripes into which a single frame of video data of a transmitted video is divided and the number of sub-strips into which each stripe is divided; A first allocation module 302, configured to allocate a bit rate value to each of the slices in a frame; The complexity calculation module 303 is used to calculate the complexity of each first sub-strip in the first stripe of the received video data signal during the process of the video data signal being input into the cache; A second allocation module 304 is configured to allocate a bit rate value to each of the first sub-strips according to the complexity of each of the first sub-strips in the first stripe after the video data signal in the input buffer fills up the first stripe; The adjustment module 305 is configured to determine a quantization parameter of each of the first sub-strips in the first stripe, and adjust a bit rate value allocated to the first sub-strip according to the quantization parameter of each first sub-strip.

[0059] Optionally, the first allocation module includes: The first submodule is used to determine the encoding bit rate and video frame rate of the video to be transmitted; A second submodule is used to determine a constant bit rate according to the encoding bit rate, the video frame rate and the number of strips divided in the single frame of video data; The third submodule is used to allocate a bit rate value to each of the stripes in the frame according to the constant bit rate.

[0060] Optionally, the complexity calculation module includes: A fourth submodule, configured to divide a first sub-strip within a first strip of a received video data signal into a plurality of blocks during the process of inputting the video data signal into a cache; A fifth submodule, configured to perform Hadamard transform on each block divided into the first sub-strip to obtain a DC component coefficient and an AC component coefficient of the block; A sixth submodule, configured to calculate the complexity of the block according to a DC component coefficient and an AC component coefficient of the block; The seventh submodule is configured to determine the sum of the complexities of each block divided into the first sub-strip as the complexity of the first sub-strip.

[0061] Optionally, the second allocation module includes: An eighth submodule, configured to calculate a total complexity of each first stripe contained in the first stripe after the video data signal in the to-be-input buffer fills up the first stripe; A ninth submodule is configured to calculate, for each first sub-strip in the first stripe, a product of the complexity of the first sub-strip and a code rate value allocated to the first stripe, and determine a quotient of the product and the total complexity as the code rate value allocated to the first sub-strip.

[0062] Optionally, the adjustment module includes: A first quantization parameter determination submodule, configured to determine a first quantization parameter of a first sub-strip in the first stripe; a factor determination submodule, configured to determine, for each first sub-strip except a first first sub-strip in the first sub-strip, an integral factor and a differential factor corresponding to the first sub-strip according to a bit rate value allocated to the first sub-strip and each sub-strip arranged before the first sub-strip and a cumulative pre-allocated bit rate value; a second quantization parameter determination submodule, configured to calculate a quantization parameter of the first sub-band according to an integral factor and a differential factor of the first sub-band, the number of pixels included in the first sub-band, and a quantization parameter of a first sub-band ranked before the first sub-band; The bit rate adjustment submodule is used to adjust the bit rate value allocated to the first sub-strip according to the quantization parameter of each first sub-strip in the first stripe.

[0063] The shallow compression multi-strip rate control device provided in the embodiment of the present application determines the number of stripes into which the single frame of video data of the transmitted video is divided and the number of sub-strips into which each stripe is divided; allocates a rate value for each stripe in the frame; during the process of inputting the video data signal into the cache, calculates the complexity of each first sub-strip in the first stripe of the received video data signal; after the video data signal in the input cache fills the first stripe, allocates a rate value for each first sub-strip according to the complexity of each first sub-strip in the first stripe; determines the quantization parameter of each first sub-strip in the first stripe, and adjusts the rate value allocated to the first sub-strip according to the quantization parameter of each first sub-strip. The device allocates and controls the rate for the stripe and sub-strip levels respectively according to the characteristics that the shallow compression video frame can be divided into multiple stripes and sub-strips. The stripe level is set to a constant rate to facilitate the stable transmission of high-rate video. At the same time, the rate is reasonably allocated to each sub-strip within the stripe according to the complexity of each sub-strip, taking into account the quality of the encoded image and low encoding delay, and can ensure low-delay transmission of the video.

[0064] An embodiment of the present invention further provides an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus.

[0065] Memory, used to store computer programs; The processor is used to implement the shallow compression multi-strip bit rate control method shown in the above method embodiment when executing the program stored in the memory.

[0066] The communication bus mentioned in the above terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0067] The communication interface is used for communication between the above terminal and other devices.

[0068] The memory may include a random access memory (RAM) or a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0069] In another embodiment provided by the present invention, a computer-readable storage medium is also provided, in which instructions are stored. When the computer-readable storage medium is executed on an electronic device, the electronic device implements the shallow compression multi-band bit rate control method described in any of the above embodiments.

[0070] In another embodiment of the present invention, a computer program product including instructions is provided. When the computer program product is executed on an electronic device, the electronic device implements the shallow compression multi-strip bit rate control method described in any one of the above embodiments.

[0071] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program codes. The scheme in the embodiments of the present application may be implemented in various computer languages, for example, C language, VHDL language, Verilog language, object-oriented programming language Java, and literal scripting language JavaScript, etc.

[0072] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0073] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0074] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0075] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0076] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0077] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0078] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0079] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A shallow compression multi-strip bit rate control method, characterized in that: The method comprises: Determine the number of stripes into which a single frame of video data of a transmitted video is divided and the number of sub-strips into which each stripe is divided; assigning a bit rate value to each of the slices within the frame; During the process of inputting the video data signal into the buffer, calculating the complexity of each first sub-strip in the first stripe of the received video data signal; After the video data signal in the input buffer fills up the first stripe, a bit rate value is allocated to each of the first sub-strips according to the complexity of each of the first sub-strips in the first stripe; A quantization parameter of each of the first sub-strips in the first stripe is determined, and a bit rate value allocated to the first sub-strip is correspondingly adjusted according to the quantization parameter of each first sub-strip.

2. The method according to claim 1, characterized in that The step of allocating a bit rate value to each of the slices in the frame comprises: Determine the encoding bit rate and video frame rate of the video to be transmitted; Determining a constant bit rate according to the encoding bit rate, the video frame rate, and the number of stripes divided in the single frame of video data; A code rate value is allocated to each of the slices in a frame according to the constant code rate.

3. The method according to claim 1, characterized in that In the process of inputting the video data signal into the buffer, the step of calculating the complexity of each first sub-strip in the first stripe of the received video data signal comprises: In the process of inputting the video data signal into the buffer, dividing the first sub-strip in the first stripe of the received video data signal into a plurality of blocks; For each block divided into the first sub-strip, perform Hadamard transform on the block to obtain a DC component coefficient and an AC component coefficient of the block; Calculating the complexity of the block according to the DC component coefficient and the AC component coefficient of the block; The sum of the complexities of each block divided into the first sub-strip is determined as the complexity of the first sub-strip.

4. The method according to claim 1, characterized in that: After the video data signal to be input into the buffer fills up the first stripe, the step of assigning a bit rate value to each of the first sub-strips in the first stripe according to the complexity of each of the first sub-strips in the first stripe includes: After the video data signal in the to-be-input buffer fills up the first stripe, calculating the total complexity of each first stripe contained in the first stripe; For each first sub-strip in the first stripe, a product of the complexity of the first sub-strip and a coding rate value allocated to the first stripe is calculated, and a quotient of the product and the total complexity is determined as the coding rate value allocated to the first sub-strip.

5. The method according to claim 1, characterized in that The step of determining a quantization parameter of each of the first sub-strips in the first stripe, and adjusting a bit rate value allocated to the first sub-strip according to the quantization parameter of each first sub-strip, comprises: Determining a first quantization parameter of a first sub-strip within the first stripe; For each first sub-strip except the first first sub-strip in the first stripe, determining an integral factor and a differential factor corresponding to the first sub-strip according to bit rate values ​​allocated to the first sub-strip and each sub-strip ordered before the first sub-strip and a cumulative pre-allocated bit rate value; Calculating a quantization parameter of the first sub-band according to an integral factor and a differential factor of the first sub-band, the number of pixels included in the first sub-band, and a quantization parameter of a first sub-band that is ranked before the first sub-band; The bit rate value allocated to the first sub-strip is correspondingly adjusted according to the quantization parameter of each first sub-strip in the first stripe.

6. A shallow compression multi-strip bit rate control device, characterized in that: The device comprises: A first determination module is used to determine the number of stripes into which a single frame of video data of a transmitted video is divided and the number of sub-strips into which each stripe is divided; A first allocation module, configured to allocate a bit rate value to each of the stripes in a frame; A complexity calculation module, used for calculating the complexity of each first sub-strip in the first stripe of the received video data signal during the process of the video data signal being input into the cache; A second allocation module, configured to allocate a bit rate value to each of the first sub-strips according to the complexity of each of the first sub-strips in the first stripe after the video data signal in the input buffer fills up the first stripe; The adjustment module is used to determine the quantization parameter of each of the first sub-strips in the first stripe, and adjust the bit rate value allocated to the first sub-strip according to the quantization parameter of each first sub-strip.

7. The device according to claim 6, characterized in that The first allocation module comprises: The first submodule is used to determine the encoding bit rate and video frame rate of the video to be transmitted; A second submodule is used to determine a constant bit rate according to the encoding bit rate, the video frame rate and the number of strips divided in the single frame of video data; The third submodule is used to allocate a bit rate value to each of the stripes in the frame according to the constant bit rate.

8. The device according to claim 6, characterized in that The complexity calculation module comprises: A fourth submodule, configured to divide a first sub-strip within a first strip of a received video data signal into a plurality of blocks during the process of inputting the video data signal into a cache; A fifth submodule, configured to perform Hadamard transform on each block divided into the first sub-strip to obtain a DC component coefficient and an AC component coefficient of the block; A sixth submodule, configured to calculate the complexity of the block according to a DC component coefficient and an AC component coefficient of the block; The seventh submodule is configured to determine the sum of the complexities of each block divided into the first sub-strip as the complexity of the first sub-strip.

9. The device according to claim 6, characterized in that The second allocation module comprises: An eighth submodule, configured to calculate a total complexity of each first stripe contained in the first stripe after the video data signal in the to-be-input buffer fills up the first stripe; A ninth submodule is configured to calculate, for each first sub-strip in the first stripe, a product of the complexity of the first sub-strip and a code rate value allocated to the first stripe, and determine a quotient of the product and the total complexity as the code rate value allocated to the first sub-strip.

10. The device according to claim 6, characterized in that The adjustment module comprises: A first quantization parameter determination submodule, configured to determine a first quantization parameter of a first sub-strip in the first stripe; a factor determination submodule, configured to determine, for each first sub-strip except a first first sub-strip in the first sub-strip, an integral factor and a differential factor corresponding to the first sub-strip according to a bit rate value allocated to the first sub-strip and each sub-strip arranged before the first sub-strip and a cumulative pre-allocated bit rate value; a second quantization parameter determination submodule, configured to calculate a quantization parameter of the first sub-band according to an integral factor and a differential factor of the first sub-band, the number of pixels included in the first sub-band, and a quantization parameter of a first sub-band ranked before the first sub-band; The bit rate adjustment submodule is used to adjust the bit rate value allocated to the first sub-strip according to the quantization parameter of each first sub-strip in the first stripe.

11. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; The processor is used to implement the shallow compression multi-strip bit rate control method as described in any one of claims 1 to 5 when executing the program stored in the memory.

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