Circuit Board and its Manufacturing Method

Abstract

A circuit board includes a first circuit layer, a second circuit layer, a third circuit layer, a first differential line group, a second differential line group, a third differential line group, and a fourth differential line group. The first and third differential line groups are disposed between the first and second circuit layers. The second and fourth differential line groups are disposed between the first and third circuit layers. A first distance exists between the first differential line group and the first circuit layer, a second distance exists between the second differential line group and the first circuit layer, a third distance exists between the third differential line group and the first circuit layer, and a fourth distance exists between the fourth differential line group and the first circuit layer, wherein the first distance is less than the third distance, and the second distance is less than the fourth distance. The conductive structure of the differential lines is composed of graphene, and the insulating structure of the differential lines is composed of graphene oxide. Therefore, the circuit board of this invention can reduce signal loss and possesses a certain degree of heat resistance in high-temperature environments.

Description

Technical Field

[0001] This invention relates to a circuit board and a method for manufacturing the same, and more particularly to a circuit board formed from graphene, graphene oxide, and liquid metal and a method for manufacturing the same. Background Technology

[0002] In the field of high-frequency transmission line technology, traditional circuit boards typically use via structures to achieve signal shielding, while common transmission line structures include microstrip and stripline structures. However, via structures can lead to impedance discontinuities, and the electromagnetic shielding structures in microstrip and stripline lines cannot achieve omnidirectional shielding against electromagnetic interference (EMI).

[0003] Furthermore, the roughness of the conductor structure on the circuit board also affects the signal shielding effect. High conductor roughness, coupled with the skin effect of electrons, further increases conductor loss, thus impacting signal shielding effectiveness. Therefore, there is an urgent need to develop a fully shielded circuit board and its manufacturing method to overcome these shortcomings. Summary of the Invention

[0004] At least one embodiment of the present invention provides a circuit board and a method for manufacturing the same. The conductive structure of the differential lines of the present invention is composed of graphene, and the insulating structure of the differential lines is composed of graphene oxide. Graphene has high conductivity, high thermal conductivity, and low roughness, thus reducing signal loss. Graphene oxide is an insulator, which also reduces the impact of roughness on high-frequency signals. The liquid metal-coated (three-dimensional surround) differential lines of the present invention provide each transmission line with an individual shielding structure, achieving omnidirectional signal shielding.

[0005] The circuit board provided in at least one embodiment of the present invention includes a first circuit layer, a second circuit layer, a third circuit layer, a first differential line group, a second differential line group, a third differential line group, and a fourth differential line group. The first circuit layer is disposed between the second and third circuit layers. The first differential line group is disposed between the first and second circuit layers. The second differential line group is disposed between the first and third circuit layers. The third differential line group is disposed between the first and second circuit layers. The fourth differential line group is disposed between the first and third circuit layers. The first differential line group has a first orthographic projection on the first circuit layer, the second differential line group has a second orthographic projection on the first circuit layer, the third differential line group has a third orthographic projection on the first circuit layer, and the fourth differential line group has a fourth orthographic projection on the first circuit layer, wherein the first and third orthographic projections are separate, and the second and fourth orthographic projections are separate. The first differential line group has a first distance from the first line layer, the second differential line group has a second distance from the first line layer, the third differential line group has a third distance from the first line layer, and the fourth differential line group has a fourth distance from the first line layer, wherein the first distance is less than the third distance and the second distance is less than the fourth distance.

[0006] In at least one embodiment of the present invention, each of the first differential line group, the second differential line group, the third differential line group, and the fourth differential line group comprises two differential lines.

[0007] In at least one embodiment of the present invention, the circuit board further includes a liquid metal structure. The liquid metal structure covers each differential line, wherein the liquid metal structure is distributed between the first circuit layer, the second circuit layer, and the third circuit layer.

[0008] In at least one embodiment of the present invention, each differential line includes a conductive structure and an insulating structure. The conductive structure is composed of graphene. The insulating structure surrounds the conductive structure, wherein the insulating structure is composed of graphene oxide.

[0009] In at least one embodiment of the present invention, the circuit board further includes a first insulating layer, a first adhesive layer, a second insulating layer, and a second adhesive layer. The first insulating layer is disposed between a first circuit layer and a second circuit layer, wherein the first insulating layer surrounds a liquid metal structure. The first adhesive layer is disposed between the first insulating layer and the second circuit layer. The second insulating layer is disposed between the first circuit layer and a third circuit layer, wherein the second insulating layer surrounds a liquid metal structure. The second adhesive layer is disposed between the second insulating layer and the third circuit layer.

[0010] The method for manufacturing a circuit board according to at least one embodiment of the present invention includes the following steps: A first circuit layer is provided. A first patterned insulating layer is formed on a first surface of the first circuit layer, wherein the first patterned insulating layer includes a plurality of first grooves. A second patterned insulating layer is formed on a second surface of the first circuit layer, wherein the second patterned insulating layer includes a plurality of second grooves, wherein one of the plurality of first grooves is connected to another of the plurality of second grooves. A first liquid metal layer is formed on a portion of the first patterned insulating layer. A second liquid metal layer is formed on a portion of the second patterned insulating layer. A first differential line group is formed on a portion of the first liquid metal layer. A second differential line group is formed on a portion of the second liquid metal layer. A third patterned insulating layer is formed, wherein the third patterned insulating layer includes a plurality of third grooves, and the plurality of first grooves are connected to the plurality of third grooves. A fourth patterned insulating layer is formed, wherein the fourth patterned insulating layer includes a plurality of fourth grooves, and the plurality of second grooves are connected to the plurality of fourth grooves. A third liquid metal layer is formed on the first differential line group. A fourth liquid metal layer is formed on the second differential line group. A second circuit layer is formed on the first differential line group. A third circuit layer is formed on the second differential line group. After forming the second and third circuit layers, liquid metal material is filled into multiple first, second, third, and fourth grooves. The holes in the second circuit layer are sealed.

[0011] In at least one embodiment of the present invention, the step of forming the first differential line group includes the following steps: forming a conductive structure on a first liquid metal layer, wherein the conductive structure is composed of graphene; forming an insulating structure on and around the conductive structure, wherein the insulating structure is composed of graphene oxide.

[0012] In at least one embodiment of the present invention, the method for manufacturing the circuit board further includes the following steps: forming a third differential line group on a portion of a third liquid metal layer; forming a fourth differential line group on a portion of a fourth liquid metal layer; forming a fifth patterned insulating layer, wherein the fifth patterned insulating layer includes a plurality of fifth grooves, and the plurality of third grooves are connected to the plurality of fifth grooves; forming a sixth patterned insulating layer, wherein the sixth patterned insulating layer includes a plurality of sixth grooves, and the plurality of fourth grooves are connected to the plurality of sixth grooves; forming a fifth liquid metal layer on the third differential line group; forming a sixth liquid metal layer on the fourth differential line group, wherein the liquid metal material further fills the plurality of fifth and sixth grooves.

[0013] In at least one embodiment of the present invention, the first, second, third and fourth liquid metal layers are formed by sputtering.

[0014] In at least one embodiment of the present invention, the step of sealing the holes in the second circuit layer is performed in an environment of room temperature and vacuum.

[0015] The circuit board of this invention possesses a certain degree of heat resistance in high-temperature environments. Due to the properties of liquid metal, it can undergo a phase change reaction at higher temperatures. Since graphene and graphene oxide materials serve as the transmission line conductor and insulating layer, respectively, the circuit board of this invention is designed for use in high-temperature environments. Attached Figure Description

[0016] The various aspects of this application can be best understood by reading in conjunction with the accompanying drawings and the following detailed description. It should be understood that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity, the dimensions of the various features can be arbitrarily increased or decreased.

[0017] Figures 1 to 12 This is a cross-sectional schematic diagram of a circuit board at various stages of the manufacturing process according to at least one embodiment of the present invention. Detailed Implementation

[0018] In the following text, to clearly present the technical features of this application, the dimensions (e.g., length, width, thickness, and depth) of the elements (e.g., insulating layers, wiring layers, and vias) in the accompanying drawings will be enlarged proportionally, and the number of some elements may be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings or the dimensions and shapes presented by the elements, but should cover dimensions, shapes, and deviations from both due to actual manufacturing processes and / or tolerances. For example, a flat surface shown in the drawings may have rough and / or non-linear characteristics, and an acute angle shown in the drawings may be rounded. Therefore, the elements presented in the accompanying drawings are primarily for illustrative purposes and are not intended to precisely depict the actual shape of the elements, nor are they intended to limit the claims of this application.

[0019] In addition, spatial relative terms such as "below," "below," "lower than," "above," "above," and other similar terms are used here for the convenience of describing the relationship between one element or feature and another element or feature in the figure. Spatial relative terms cover not only the orientation depicted in the figure but also other orientations of the device during use or operation. That is, when the orientation of the device differs from that in the figure (rotated 90 degrees or in other orientations), the spatial relative terms used in this disclosure can also be interpreted accordingly.

[0020] It will be understood that although terms such as “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0021] The terms "approximately," "approximately," "essentially," or "substantially" used herein can be chosen to select a more acceptable range of deviations or standard deviations based on optical, etching, mechanical, measurement, coating, or other properties, rather than applying a single standard deviation to all properties. It should be noted that the accompanying drawings in this case label a first direction D1 and a second direction D2 to illustrate the arrangement of the components in the drawing; the first direction D1 and the second direction D2 are substantially perpendicular to each other.

[0022] Figures 1 to 12 This is a cross-sectional schematic diagram of the circuit board 100a of at least one embodiment of the present invention at various stages of the manufacturing process, wherein... Figure 12 The circuit board 100a is shown in the diagram. Please refer to it. Figure 1 The first circuit layer 110 has a first surface s1 and a second surface s2. A first insulating layer 111 is formed on the first surface s1, and a second insulating layer 112 is formed on the second surface s2. In other words, the first circuit layer 110 is sandwiched between the first insulating layer 111 and the second insulating layer 112. The first circuit layer 110, the first insulating layer 111, and the second insulating layer 112 are stacked along a first direction D1.

[0023] In this embodiment, the first circuit layer 110 is formed by etching a metal layer (e.g., the copper foil of a copper foil substrate), therefore the first circuit layer 110 is formed using a subtractive method. Figure 1 As shown, the first circuit layer 110 has a through-hole H1. In this embodiment, the first insulating layer 111 and the second insulating layer 112 are photosensitive insulating materials, such as photo-imageable dielectric (PID). In this embodiment, the first insulating layer 111 and the second insulating layer 112 are formed on opposite sides of the first circuit layer 110 by bonding.

[0024] Please refer to Figure 2 The first insulating layer 111 and the second insulating layer 112 are formed into a first patterned insulating layer 111a and a second patterned insulating layer 112a through exposure and development processes, such that the first patterned insulating layer 111a is disposed on the first surface s1 of the first circuit layer 110, and the second patterned insulating layer 112a is disposed on the second surface s2 of the first circuit layer 110. The first patterned insulating layer 111a includes a plurality of first grooves R1, and the second patterned insulating layer 112a includes a plurality of second grooves R2, wherein one of the plurality of first grooves R1 is connected to one of the plurality of second grooves R2 through a through hole H1, such as... Figure 2 As shown.

[0025] Please refer to Figure 3A first liquid metal layer 113 is formed on a portion of a first patterned insulating layer 111a, and a second liquid metal layer 114 is formed on a portion of a second patterned insulating layer 112a, wherein the first patterned insulating layer 111a and the second patterned insulating layer 112a are located between the first liquid metal layer 113 and the second liquid metal layer 114. In this embodiment, the first liquid metal layer 113 and the second liquid metal layer 114 are formed by sputtering. Figure 3 In this embodiment, the first liquid metal layer 113 and the second liquid metal layer 114 are in a solid state.

[0026] In some embodiments, the first liquid metal layer 113 and the second liquid metal layer 114 are composed of liquid metals such as silver (Ag, melting point 961.8°C), gallium (Ga, melting point 29.76°C), rubidium (Rb, melting point 38.89°C), cesium (Cs, melting point 28.44°C), mercury (Hg, melting point -38.86°C), francium (Fr, melting point 27°C), or alloys thereof. This invention utilizes the phase transition properties of liquid metals (i.e., the transition between solid and liquid states) to allow the liquid metal to encapsulate subsequently formed differential lines.

[0027] Still referencing Figure 3 An insulating layer 115 is formed on a first liquid metal layer 113, and a conductive layer 117 is formed on the insulating layer 115. Similarly, an insulating layer 116 is formed on a second liquid metal layer 114, and a conductive layer 118 is formed on the insulating layer 116. It is worth noting that, as... Figure 3 As shown, the width of the insulating layer 115 is greater than the width of the conductive layer 117, and the width of the insulating layer 116 is greater than the width of the conductive layer 118.

[0028] Please refer to Figure 4 Insulating layer 119 covers conductive layer 117, such that insulating layer 119 and insulating layer 115 surround conductive layer 117. Similarly, insulating layer 120 covers conductive layer 118, such that insulating layer 120 and insulating layer 116 surround conductive layer 118. Furthermore, Figure 4 The insulating layers 119 and 120 can both be U-shaped.

[0029] In some embodiments, conductive layers 117 and 118 are composed of graphene. Graphene has high conductivity; therefore, conductive layers 117 and 118 are conductive structures with conductive properties. It should be noted that the "graphene" material referred to herein includes graphene fibers, graphene films, and graphene aerogels. Due to the high conductivity, high thermal conductivity, and low roughness of graphene, signal loss can be reduced. In this embodiment, the heat resistance temperature of graphene is approximately 400°C. In this embodiment, conductive layers 117 and 118 are formed by deposition.

[0030] In some embodiments, insulating layers 119 and 115 are composed of graphene oxide (GO), and insulating layers 120 and 116 are also composed of graphene oxide. Since graphene oxide is an insulator, it is understood that insulating layers 119 and 115 together form an insulating structure, and insulating layers 120 and 116 together form an insulating structure. Furthermore, due to its structural properties, graphene oxide can reduce the impact of roughness on high-frequency signals, thereby reducing signal loss. In this embodiment, the heat resistance temperature of graphene oxide is approximately 400°C. In this embodiment, insulating layers 115, 116, 119, and 120 are formed by deposition.

[0031] Figure 4 The diagram illustrates two conductive layers 117, two insulating layers 115, and two insulating layers 119 (i.e., two conductive structures and two insulating structures), which may be referred to as the "first differential line group DL1". In other words, the first differential line group DL1 contains two differential lines, wherein... Figure 4 The conductive layer 117 shown is a partial cross-section of the aforementioned differential lines. For example... Figure 4 As shown, the first differential line group DL1 is disposed on a portion of the first liquid metal layer 113.

[0032] Figure 4 The diagram illustrates two conductive layers 118, two insulating layers 116, and two insulating layers 120 (i.e., two conductive structures and two insulating structures), which can be referred to as the "second differential line group DL2". In other words, the second differential line group DL2 contains two differential lines, wherein... Figure 4 The conductive layer 118 shown is a partial cross-section of the aforementioned differential lines. For example... Figure 4 As shown, the second differential line group DL2 is disposed on a portion of the second liquid metal layer 114.

[0033] Please refer to Figure 5A third insulating layer 121 is formed on and covers the insulating layer 119. The third insulating layer 121 also covers a plurality of first grooves R1, such that the plurality of first grooves R1 are embedded in the first patterned insulating layer 111a to form cavities. A fourth insulating layer 122 is formed on and covers the insulating layer 120. The fourth insulating layer 122 also covers a plurality of second grooves R2, such that the plurality of second grooves R2 are embedded in the second patterned insulating layer 112a to form cavities. In some embodiments, the materials of the third insulating layer 121 and the fourth insulating layer 122 are the same as or similar to the materials of the first insulating layer 111 and the second insulating layer 112. In this embodiment, the third insulating layer 121 and the fourth insulating layer 122 are formed by bonding.

[0034] Please refer to Figure 6 The third insulating layer 121 and the fourth insulating layer 122 are formed into a third patterned insulating layer 121a and a fourth patterned insulating layer 122a through exposure and development processes. The third patterned insulating layer 121a includes a plurality of third grooves R3 and a plurality of first grooves R1 (see reference). Figure 5 The fourth patterned insulating layer 122a includes multiple fourth grooves R4 and multiple second grooves R2 (see reference). Figure 5 Multiple fourth grooves R4 are connected respectively. It is worth noting that the third patterned insulating layer 121a exposes the first differential line group DL1, and the fourth patterned insulating layer 122a exposes the second differential line group DL2.

[0035] Please refer to Figure 7 The third liquid metal layer 123 is formed on the first differential line group DL1 and covers a portion of the third patterned insulating layer 121a (e.g., Figure 7 (As shown on the right side of the diagram). A fourth liquid metal layer 124 is formed on the second differential line group DL2 and covers a portion of the fourth patterned insulating layer 122a (as shown on the right side of the diagram). Figure 7 (As shown on the right side of the diagram). The first differential line group DL1 and the second differential line group DL2 are located between the third liquid metal layer 123 and the fourth liquid metal layer 124. The materials and formation methods of the third liquid metal layer 123 and the fourth liquid metal layer 124 are the same as or similar to those of the first liquid metal layer 113 and the second liquid metal layer 114.

[0036] Still referencing Figure 7 An insulating layer 125 is formed on a portion of the third liquid metal layer 123, and a conductive layer 127 is formed on the insulating layer 125. Similarly, an insulating layer 126 is formed on a portion of the fourth liquid metal layer 124, and a conductive layer 128 is formed on the insulating layer 126. It is worth noting that, as... Figure 7As shown, the width of the insulating layer 125 is greater than the width of the conductive layer 127, and the width of the insulating layer 126 is greater than the width of the conductive layer 128.

[0037] Please refer to Figure 8 Insulating layer 129 covers conductive layer 127, such that insulating layer 129 and insulating layer 125 surround conductive layer 127. Similarly, insulating layer 130 covers conductive layer 128, such that insulating layer 130 and insulating layer 126 surround conductive layer 128. Furthermore, Figure 8 The insulating layers 129 and 130 can both be U-shaped. The conductive layers 127 and 128 are composed of graphene. In this embodiment, the conductive layers 127 and 128 are formed by deposition. The insulating layers 125, 126, 129, and 130 are composed of graphene oxide. In this embodiment, the insulating layers 125, 126, 129, and 130 are formed by deposition.

[0038] Figure 8 The diagram shows two conductive layers 127, two insulating layers 125, and two insulating layers 129 (i.e., two conductive structures and two insulating structures), which can be referred to as the "third differential line group DL3". In other words, the third differential line group DL3 contains two differential lines, wherein... Figure 8 The conductive layer 127 shown is a partial cross-section of the aforementioned differential lines. For example... Figure 8 As shown, the third differential line group DL3 is disposed on a portion of the third liquid metal layer 123.

[0039] Figure 8 The diagram shows two conductive layers 128, two insulating layers 126, and two insulating layers 130 (i.e., two conductive structures and two insulating structures), which can be referred to as the "fourth differential line group DL4". In other words, the fourth differential line group DL4 contains two differential lines, where... Figure 8 The conductive layer 128 shown is a partial cross-section of the aforementioned differential lines. For example... Figure 8 As shown, the fourth differential line group DL4 is disposed on a portion of the fourth liquid metal layer 124.

[0040] Please refer to Figure 9A fifth insulating layer 131 is formed on and covers the insulating layer 129. The fifth insulating layer 131 also covers a plurality of third grooves R3, such that the plurality of third grooves R3 are embedded in the third patterned insulating layer 121a to form cavities. A sixth insulating layer 132 is formed on and covers the insulating layer 130. The sixth insulating layer 132 also covers a plurality of fourth grooves R4, such that the plurality of fourth grooves R4 are embedded in the fourth patterned insulating layer 122a to form cavities. In some embodiments, the materials of the fifth insulating layer 131 and the sixth insulating layer 132 are the same as or similar to the materials of the first insulating layer 111 and the second insulating layer 112. In this embodiment, the fifth insulating layer 131 and the sixth insulating layer 132 are formed by bonding.

[0041] Please refer to Figure 10 The fifth insulating layer 131 and the sixth insulating layer 132 are formed into a fifth patterned insulating layer 131a and a sixth patterned insulating layer 132a through exposure and development processes. It is worth noting that the fifth patterned insulating layer 131a exposes the third differential line group DL3, and the sixth patterned insulating layer 132a exposes the fourth differential line group DL4.

[0042] The fifth patterned insulating layer 131a includes a plurality of fifth grooves R5 and a plurality of third grooves R3 (see reference). Figure 9 The sixth patterned insulating layer 132a comprises multiple sixth grooves R6 and multiple fourth grooves R4 (see reference). Figure 9 ( ) are respectively connected to multiple sixth grooves R6. In this embodiment, the first groove R1 (please refer to Figure 2 ), third groove R3 (please refer to) Figure 6 ) and the fifth groove R5 (please refer to) Figure 10 ) are aligned with each other, and the second groove R2 (please refer to Figure 2 ), fourth groove R4 (please refer to) Figure 6 ) and the sixth groove R6 (please refer to) Figure 10 Align them with each other.

[0043] It should be noted that the first patterned insulating layer 111a, the third patterned insulating layer 121a and the fifth patterned insulating layer 131a can be collectively referred to as insulating layer IN1, and the second patterned insulating layer 112a, the fourth patterned insulating layer 122a and the sixth patterned insulating layer 132a can be collectively referred to as insulating layer IN2.

[0044] Please refer to Figure 11A fifth liquid metal layer 133 is formed on the third differential line group DL3, and a sixth liquid metal layer 134 is formed on the fourth differential line group DL4, wherein the third differential line group DL3 and the fourth differential line group DL4 are located between the fifth liquid metal layer 133 and the sixth liquid metal layer 134. The materials and formation methods of the fifth liquid metal layer 133 and the sixth liquid metal layer 134 are the same as or similar to those of the first liquid metal layer 113 and the second liquid metal layer 114.

[0045] Then, the second circuit layer 137 is disposed on the fifth patterned insulating layer 131a and the fifth liquid metal layer 133 through the adhesive layer 135, such that multiple grooves (e.g., the first groove R1, the third groove R3, and the fifth groove R5) are embedded in the patterned insulating layer (e.g., Figure 10 A cavity is formed in the insulating layer IN1. The third circuit layer 138 is disposed on the sixth patterned insulating layer 132a and the sixth liquid metal layer 134 via the adhesive layer 136, such that multiple grooves (e.g., the second groove R2, the fourth groove R4, and the sixth groove R6) are embedded in the patterned insulating layer (e.g., IN1). Figure 10 A cavity is formed within the insulating layer IN2. In this embodiment, the second circuit layer 137 and the third circuit layer 138 are formed by bonding. In some embodiments, the adhesive layer 135 and the adhesive layer 136 are made of epoxy resin or other polymer adhesives. In some embodiments, the heat resistance temperature of the adhesive layer 135 and the adhesive layer 136 is 180°C to 320°C.

[0046] It is worth noting that the second circuit layer 137 has at least one through-hole H2, wherein the through-hole H2 connects to the fifth recess R5 (see reference). Figure 10 Through-hole H2 is for subsequent liquid metal material 139 (please refer to...). Figure 12 The filling hole. The aforementioned grooves (e.g., first groove R1 to sixth groove R6) are used to fill subsequent liquid metal material 139 (see reference). Figure 12 ).

[0047] Please refer to Figure 11 and Figure 12 Liquid metal material 139 is formulated to have specific flowability, specific viscosity, or a molten state in a processing environment. Liquid metal material 139 is injected into multiple grooves under pressure (pressure designed according to required parameters) in a pressurized environment, and then cooled and shaped. Optionally, post-processing steps (e.g., infrared heating or sintering) can be used during the injection of liquid metal material 139 to densify the liquid metal material (the material containing the liquid metal layer), thereby improving reliability.

[0048] In detail, liquid metal material 139 is filled into multiple first grooves R1, second groove R2, third groove R3, fourth groove R4, fifth groove R5, and sixth groove R6 through the through hole H2, thereby forming a... Figure 12 The circuit board 100a is then cooled and shaped. More specifically, due to... Figure 11 The circuit board 100 is placed in a pressurized environment (and optionally, a post-processing step), therefore, the first liquid metal layer 113, the second liquid metal layer 114, the third liquid metal layer 123, the fourth liquid metal layer 124, the fifth liquid metal layer 133, and the sixth liquid metal layer 134 have specific fluidity, specific viscosity, or are in a molten state. Figure 11 The multiple grooves are interconnected.

[0049] Then, through the height difference of multiple grooves (e.g., the first groove R1 to the sixth groove R6), the liquid metal material 139 flows and fills these grooves, such as... Figure 12 As shown. In this embodiment, the materials of the first liquid metal layer 113 to the sixth liquid metal layer 134 are the same as the material of the liquid metal material 139.

[0050] Understandably, after the liquid metal material 139 is formed in multiple grooves, it is cooled to solidify. Therefore, the liquid metal material 139, together with the original first to sixth liquid metal layers 113, forms a liquid metal structure. This liquid metal structure covers each differential line, and is distributed between the first circuit layer 110, the second circuit layer 137, and the third circuit layer 138. It should be understood that the term "cover" in this document means covering at least three planes, such as six planes, of a three-dimensional structure. Insulating layer IN1 and insulating layer IN2 (see reference) Figure 10 ) Surrounding the liquid metal structure.

[0051] Please refer to Figure 12 After filling the plurality of grooves with the liquid metal material 139, the through-hole H2 in the second circuit layer 137 is sealed using a sealant 140. In some embodiments, the step of sealing the through-hole H2 in the second circuit layer 137 is performed at room temperature and under vacuum.

[0052] Because each differential line is covered by a liquid metal structure, each differential line group has an individual shielding structure, thereby reducing signal loss. Furthermore, the liquid metal structure connects the first circuit layer 110, the second circuit layer 137, and the third circuit layer 138, grounding the liquid metal structure and thus improving the structure of the circuit board 100a, further reducing signal loss.

[0053] Please refer to this again. Figure 12Circuit board 100a includes a first circuit layer 110, a second circuit layer 137, a third circuit layer 138, a first differential line group DL1, a second differential line group DL2, a third differential line group DL3, and a fourth differential line group DL4. The first circuit layer 110 is disposed between the second circuit layer 137 and the third circuit layer 138. The first differential line group DL1 is disposed between the first circuit layer 110 and the second circuit layer 137. The second differential line group DL2 is disposed between the first circuit layer 110 and the third circuit layer 138. The third differential line group DL3 is disposed between the first circuit layer 110 and the second circuit layer 137. The fourth differential line group DL4 is disposed between the first circuit layer 110 and the third circuit layer 138.

[0054] like Figure 12 As shown, the first differential line group DL1 is arranged along the first horizontal line HL1, the second differential line group DL2 is arranged along the second horizontal line HL2, the third differential line group DL3 is arranged along the third horizontal line HL3, and the fourth differential line group DL4 is arranged along the fourth horizontal line HL4. The first horizontal line HL1, the second horizontal line HL2, the third horizontal line HL3, and the fourth horizontal line HL4 extend in a direction parallel to the second direction D2, and are separated from each other. The third horizontal line HL3 is higher than the first horizontal line HL1, the first horizontal line HL1 is higher than the second horizontal line HL2, and the second horizontal line HL2 is higher than the fourth horizontal line HL4.

[0055] In other words, the first differential line group DL1 to the fourth differential line group DL4 have a height difference, so that each differential line group is not on the same plane, which can avoid signal interference between differential lines (transmission lines). Figure 12 As shown, the first differential line group DL1 to the fourth differential line group DL4 have a mirror-symmetrical structure with the first line layer 110 as the axis of symmetry. Each of the first differential line groups DL1 to the fourth differential line group DL4 may have different functions, such as different transmission frequencies. In some embodiments, the thickness of the conductive structure (e.g., conductive layer 117, conductive layer 118, conductive layer 127, and conductive layer 128) of each of the first differential line groups DL1 to the fourth differential line group DL4 may be different.

[0056] Please refer to Figure 12The first differential line group DL1 has a first orthographic projection (not shown) on the first line layer 110, the second differential line group DL2 has a second orthographic projection (not shown) on the first line layer 110, the third differential line group DL3 has a third orthographic projection (not shown) on the first line layer 110, and the fourth differential line group DL4 has a fourth orthographic projection (not shown) on the first line layer 110, wherein the first orthographic projection and the third orthographic projection are separate, and the second orthographic projection and the fourth orthographic projection are separate.

[0057] Understandably, the term "orthogonal projection" in this document refers to the projection of the first differential line group DL1 to the fourth differential line group DL4 onto the first surface s1 or the second surface s2 of the first circuit layer 110 along a direction parallel to the first direction D1. This is analogous to a virtual beam of light projecting the first differential line group DL1 to the fourth differential line group DL4 onto the first surface s1 or the second surface s2 of the first circuit layer 110 along a direction parallel to the first direction D1.

[0058] like Figure 12 As shown, the first differential line group DL1 has a first distance d1 with respect to the first line layer 110, the second differential line group DL2 has a second distance d2 with respect to the first line layer 110, the third differential line group DL3 has a third distance d3 with respect to the first line layer 110, and the fourth differential line group DL4 has a fourth distance d4 with respect to the first line layer 110, wherein the first distance d1 is less than the third distance d3, and the second distance d2 is less than the fourth distance d4. In some embodiments, the first distance d1 is substantially equal to the second distance d2, and the third distance d3 is substantially equal to the fourth distance d4.

[0059] In summary, the conductive structure of the differential lines in this invention is composed of graphene, and the insulating structure is composed of graphene oxide. Graphene possesses high conductivity, high thermal conductivity, and low roughness, thus reducing signal loss. Graphene oxide, being an insulator, also reduces the impact of roughness on high-frequency signals. The liquid metal-coated (three-dimensional surround) differential lines of this invention provide each transmission line with an individual shielding structure, achieving omnidirectional signal shielding.

[0060] The foregoing overview of the features of various embodiments enables those skilled in the art to better understand the nature of this application. Those skilled in the art should understand that this application can be readily used as the basis for designing or modifying other processes and structures to achieve the same objectives and / or realize the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this application, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this application.

[0061]

Explanation of symbols

[0062] 100, 100a: Circuit board

[0063] 110: First Line Layer

[0064] 111: First insulating layer

[0065] 111a: First patterned insulating layer

[0066] 112: Second insulating layer

[0067] 112a: Second patterned insulating layer

[0068] 113: First liquid metal layer

[0069] 114: Second liquid metal layer

[0070] 115: Insulation layer

[0071] 116: Insulation layer

[0072] 117: Conductive layer

[0073] 118: Conductive layer

[0074] 119: Insulation layer

[0075] 120: Insulation layer

[0076] 121: Third Insulation Layer

[0077] 121a: Third patterned insulating layer

[0078] 122: Fourth Insulation Layer

[0079] 122a: Fourth patterned insulating layer

[0080] 123: Third liquid metal layer

[0081] 124: Fourth liquid metal layer

[0082] 125: Insulation layer

[0083] 126: Insulation layer

[0084] 127: Conductive layer

[0085] 128: Conductive layer

[0086] 129: Insulation layer

[0087] 130: Insulation layer

[0088] 131: Fifth Insulation Layer

[0089] 131a: Fifth patterned insulating layer

[0090] 132: Sixth Insulation Layer

[0091] 132a: Sixth patterned insulating layer

[0092] 133: Fifth liquid metal layer

[0093] 134: The Sixth Liquid Metal Layer

[0094] 135: Adhesive layer

[0095] 136: Adhesive layer

[0096] 137: Second Line Layer

[0097] 138: Third Line Layer

[0098] 139: Liquid Metal Materials

[0099] 140: Seals

[0100] d1: First distance

[0101] d2: Second distance

[0102] d3: Third distance

[0103] d4: Fourth distance

[0104] s1: First surface

[0105] s2: Second surface

[0106] DL1: First differential line group

[0107] DL2: Second differential line group

[0108] DL3: Third Differential Line Group

[0109] DL4: Fourth Differential Line Group

[0110] D1: First Direction

[0111] D2: Second Direction

[0112] HL1: First horizontal line

[0113] HL2: Second horizontal line

[0114] HL3: Third horizontal line

[0115] HL4: Fourth Horizontal Line

[0116] R1: First groove

[0117] R2: Second groove

[0118] R3: Third Groove

[0119] R4: Fourth Groove

[0120] R5: Fifth Groove

[0121] R6: Sixth Groove

[0122] IN1: Insulating layer

[0123] IN2: Insulating layer

[0124] H1, H2: Through holes.

Claims

1. A circuit board, characterized in that, Include: First line layer; Second line layer; A third line layer, wherein the first line layer is disposed between the second line layer and the third line layer; The first differential line group is disposed between the first line layer and the second line layer; The second differential line group is disposed between the first line layer and the third line layer; The third differential line group is located between the first line layer and the second line layer; The fourth differential line group is disposed between the first line layer and the third line layer; The first differential line group has a first orthographic projection on the first line layer, the second differential line group has a second orthographic projection on the first line layer, the third differential line group has a third orthographic projection on the first line layer, and the fourth differential line group has a fourth orthographic projection on the first line layer, wherein the first orthographic projection is separate from the third orthographic projection, and the second orthographic projection is separate from the fourth orthographic projection. The first differential line group has a first distance from the first line layer, the second differential line group has a second distance from the first line layer, the third differential line group has a third distance from the first line layer, and the fourth differential line group has a fourth distance from the first line layer, wherein the first distance is less than the third distance, and the second distance is less than the fourth distance. Each of the first differential line group, the second differential line group, the third differential line group, and the fourth differential line group comprises two differential lines; and A liquid metal structure covers each of the differential lines, wherein the liquid metal structure is distributed between the first circuit layer, the second circuit layer, and the third circuit layer.

2. The circuit board of claim 1, wherein each of the differential lines comprises: A conductive structure, wherein the conductive structure is composed of graphene; and An insulating structure surrounding the conductive structure, wherein the insulating structure is composed of graphene oxide.

3. The circuit board according to claim 1, wherein, Further includes: A first insulating layer is disposed between the first circuit layer and the second circuit layer, wherein the first insulating layer surrounds the liquid metal structure; A first adhesive layer is disposed between the first insulating layer and the second circuit layer; A second insulating layer is disposed between the first circuit layer and the third circuit layer, wherein the second insulating layer surrounds the liquid metal structure; and The second adhesive layer is disposed between the second insulating layer and the third circuit layer.

4. A method for manufacturing a circuit board, characterized in that, Include: Provide the first line layer; A first patterned insulating layer is formed on a first surface of the first circuit layer, wherein the first patterned insulating layer includes a plurality of first grooves; A second patterned insulating layer is formed on the second surface of the first circuit layer, wherein the second patterned insulating layer includes a plurality of second grooves, wherein one of the plurality of first grooves communicates with one of the plurality of second grooves; A first liquid metal layer is formed on a portion of the first patterned insulating layer; A second liquid metal layer is formed on a portion of the second patterned insulating layer; A first differential line group is formed on a portion of the first liquid metal layer, wherein the first differential line group comprises two differential lines; A second differential line group is formed on a portion of the second liquid metal layer, wherein the second differential line group comprises two differential lines; A third patterned insulating layer is formed, wherein the third patterned insulating layer includes a plurality of third grooves, and the plurality of first grooves are connected to the plurality of third grooves; A fourth patterned insulating layer is formed, wherein the fourth patterned insulating layer includes a plurality of fourth grooves, and the plurality of second grooves are connected to the plurality of fourth grooves; A third liquid metal layer is formed on the first differential line group; A fourth liquid metal layer is formed on the second differential line group; A second line layer is formed on the first differential line group; A third line layer is formed on the second differential line group; After forming the second and third circuit layers, liquid metal material is filled into the plurality of first, second, third, and fourth grooves, wherein the liquid metal material forms a liquid metal structure with the first, second, third, and fourth liquid metal layers, the liquid metal structure covering each differential line, and wherein the liquid metal structure is distributed between the first, second, and third circuit layers; and Seal the holes in the second circuit layer.

5. The method for manufacturing a circuit board according to claim 4, wherein the step of forming the first differential line group comprises: A conductive structure is formed on the first liquid metal layer, wherein the conductive structure is composed of graphene; and An insulating structure is formed on and around the conductive structure, wherein the insulating structure is composed of graphene oxide.

6. The method for manufacturing a circuit board according to claim 4, wherein, Also includes: A third differential line group is formed on a portion of the third liquid metal layer; A fourth differential line group is formed on a portion of the fourth liquid metal layer; A fifth patterned insulating layer is formed, wherein the fifth patterned insulating layer includes a plurality of fifth grooves, and the plurality of third grooves are connected to the plurality of fifth grooves; A sixth patterned insulating layer is formed, wherein the sixth patterned insulating layer includes a plurality of sixth grooves, and the plurality of fourth grooves are connected to the plurality of sixth grooves; A fifth liquid metal layer is formed on the third differential line group; and A sixth liquid metal layer is formed on the fourth differential line group, wherein the liquid metal material is also filled in the plurality of fifth and sixth grooves.

7. The method for manufacturing a circuit board according to claim 4, wherein the first, second, third and fourth liquid metal layers are formed by sputtering.

8. The method for manufacturing a circuit board according to claim 4, wherein the step of sealing the holes in the second circuit layer is performed at room temperature and in a vacuum environment.

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