Wiring board

Abstract

Provided is a wiring board including a via conductor that is relatively strong and suppresses signal transmission loss. A wiring board according to an embodiment includes: a first build-up portion including a first insulating layer, a first conductor layer (12), and a first via conductor (13) filling a first via opening (11a); and a second laminated portion including second insulating layers and second conductor layers, the second insulating layers and the second conductor layers being alternately laminated. The minimum value of the wiring width of the wiring included in the first conductor layer is smaller than the minimum value of the wiring width of the wiring included in the second conductor layer, and the minimum value of the inter-wiring distance is smaller than the minimum value of the inter-wiring distance of the wiring included in the second conductor layer. The first layer includes a first portion (121a) having a substantially smooth surface and a second portion (122a), the first portion and the second portion being electrically connected, and a portion of the first portion being located closer to the center side of the first via opening than the second portion.

Description

Technical Field

[0001] The present invention relates to a wiring substrate. Background Art

[0002] Patent Document 1 discloses a printed wiring board including a first conductor layer, an insulating layer formed on the first conductor layer, and a second conductor layer formed on the insulating layer. The first conductor layer and the second conductor layer are connected by via conductors that fill through holes that penetrate the insulating layer in the thickness direction.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2015-126103

[0004] In the printed wiring board disclosed in Patent Document 1, the inner wall of the through hole filled with the via conductor has a complex uneven surface. It is believed that the surface of the via conductor in contact with the inner wall of the through hole has a large roughness, which may increase the transmission loss of high-frequency signals. Summary of the invention

[0005] The wiring substrate of the present invention has a first surface and a second surface on the opposite side to the first surface, and the wiring substrate has: a first build-up portion, which includes a first insulating layer and a first conductor layer, a first via opening penetrating the first insulating layer, and a first via conductor filling the first via opening, the first insulating layer and the first conductor layer being alternately stacked; and a second build-up portion, which includes a second insulating layer and a second conductor layer, the second insulating layer and the second conductor layer being alternately stacked. The first build-up portion is located on the first surface side of the second build-up portion, and is combined with the second build-up portion, the minimum value of the wiring width of the wiring included in the first conductor layer is smaller than the minimum value of the wiring width of the wiring included in the second conductor layer, the minimum value of the wiring distance between the wiring included in the first conductor layer is smaller than the minimum value of the wiring distance between the wiring included in the second conductor layer, the first conductor layer and the first via conductor have a first layer and a second layer formed on the first layer, the first layer covering the inner wall surface of the first via opening includes a first portion and a second portion having a substantially smooth surface, the first portion is electrically connected to the second portion, and a portion of the first portion is located closer to the center of the first via opening than the second portion.

[0006] According to an embodiment of the present invention, a portion of the first portion of the first layer covering the inner wall surface of the first via opening is located closer to the center side of the first via opening than the second portion. Therefore, it is considered that the first layer is relatively strong and is difficult to break. In addition, the first layer includes the first portion and the second portion having a substantially smooth surface, so that the transmission loss when transmitting a high-frequency signal to the first via conductor can be suppressed to a relatively small level. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a cross-sectional view showing an example of a wiring substrate according to an embodiment of the present invention.

[0008] Figure 2A An example of a wiring substrate according to an embodiment of the present invention is shown. Figure 1 A partial enlarged view of .

[0009] Figure 2B An example of a wiring substrate according to an embodiment of the present invention is shown. Figure 2A A partial enlarged view of .

[0010] Figure 3A This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0011] Figure 3B This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0012] Figure 3C This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0013] Figure 3D This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0014] Figure 3E This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0015] Figure 3F This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0016] Figure 3G This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0017] Figure 3H This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0018] Fig. 3I This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0019] Figure 3J This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0020] Figure 3K This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0021] Figure 3L This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0022] Figure 3M This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0023] Description of symbols

[0024] 1: wiring substrate; 10: first build-up portion; 20: second build-up portion; 30: third build-up portion; 11: insulating layer (first insulating layer); 21: insulating layer (second insulating layer); 211: insulating layer (third insulating layer); 12: conductor layer (first conductor layer); 22: conductor layer (second conductor layer); 212: conductor layer (third conductor layer); 13: via conductor (first via conductor); 23: via conductor; 33: via conductor; 12a: first layer; 12b: second layer; 12aa: lower layer; 12ab: upper layer; 12p: conductor pad; 32p: conductor pad; FW: fine wiring;

[0025] E1, E2: electronic components; GS: supporting substrate; EA1, EA2: component mounting areas; 10F, 20F, 30F: one surface; 10B, 20B, 30B: the other surface; 1F: first surface; 1B: second surface. DETAILED DESCRIPTION

[0026] A wiring substrate according to one embodiment will be described with reference to the drawings. Figure 1 1 is a cross-sectional view showing a wiring substrate 1 as an example of a wiring substrate according to an embodiment. The wiring substrate 1 is merely an example of a wiring substrate according to this embodiment. The stacked structure of the wiring substrate according to this embodiment and the number of conductor layers and insulating layers are not limited to Figure 1 The stacked structure of the wiring substrate 1 and the number of conductor layers and insulating layers included in the wiring substrate 1 are shown. In addition, the referenced drawings are not intended to show the exact ratio of each component, but are depicted in a manner that makes it easy to understand the characteristics of the present invention.

[0027] The wiring substrate 1 of the embodiment has a stacked structure including a first stacked portion 10 and a second stacked portion 20 respectively composed of a conductor layer and an insulating layer, and the conductor layer and the insulating layer are alternately stacked. The first stacked portion 10 has a face 10F and another face 10B on the side opposite to the face 10F as two surfaces perpendicular to its thickness direction (stacking direction). The second stacked portion 20 has a face 20F and another face 20B on the side opposite to the face 20F as two surfaces perpendicular to its thickness direction (stacking direction). The wiring substrate 1 has two surfaces perpendicular to its thickness direction (the first face 1F and the second face 1B on the side opposite to the first face 1F). The wiring substrate 1 of the present embodiment is preferably a coreless wiring substrate that does not include a core layer.

[0028] exist Figure 1 In the example shown, the wiring substrate 1 further includes a third build-up portion 30 composed of an insulating layer and a conductor layer on the side opposite to the first build-up portion 10 of the second build-up portion 20. The third build-up portion 30 has one surface 30F and another surface 30B on the side opposite to the one surface 30F as two surfaces perpendicular to its thickness direction (stacking direction). In the example shown in the figure, one surface 10F of the first build-up portion 10 constitutes the first surface 1F, and the other surface 30B of the third build-up portion 30 constitutes the second surface 1B. In addition, in the case where the wiring substrate 1 does not have the third build-up portion 30, the second surface 1B can be constituted by the other surface 20B of the second build-up portion 20.

[0029] The first build-up portion 10 includes relatively fine wiring and can have a relatively high-density circuit wiring. Figure 1 In the example of , the first build-up portion 10 includes an insulating layer 11 (first insulating layer 11) and a conductive layer 12 (first conductive layer 12), and the insulating layer 11 (first insulating layer 11) and the conductive layer 12 (first conductive layer 12) are alternately stacked. The conductive layers 12 facing each other with the first insulating layer 11 interposed therebetween are connected to each other by via-hole conductors 13 (first via-hole conductors 13).

[0030] As shown in the figure, the via conductor 13 is formed into a tapered shape that decreases from the other surface 10B of the first laminated part 10 toward the one surface 10F. In addition, here, for convenience, the term "reduced diameter" is used, but the shape of the via conductor 13 is not necessarily limited to a circle. "Reduced diameter" only means that the diameter of the via conductor 13 (the distance between the two longest points on the outer circumference in the horizontal cross section) becomes smaller. In addition, the via diameter of the via conductor 13 (the diameter of the contact surface of the via conductor 13 with the conductor layer 12 on the other surface 10B side) can be about 10μm.

[0031] One surface 10F of the first build-up part 10 is composed of the surface of the first conductor layer 12 and the surface of the first insulating layer 11 exposed from the pattern of the first conductor layer 12. The first conductor layer 12 is patterned to have a predetermined conductor pattern. In the example shown in the figure, the first conductor layer 12 constituting the one surface 10F is formed into a pattern having a plurality of conductor pads 12p. In addition, as shown in the figure, the conductor layer 12 constituting the other surface 10B of the first build-up part 10 and in contact with the second build-up part 20 may have a thickness different from that of the other conductor layers 12 of the first build-up part 10.

[0032] The conductor pad 12p constitutes the outermost surface (first surface 1F) of the wiring substrate 1 and constitutes a component mounting surface of the wiring substrate 1 to which external electronic components can be connected. The component mounting surface of the wiring substrate 1 may have a plurality of component mounting areas. For example, Figure 1 As shown in the example, two component mounting areas (EA1, EA2) can be formed corresponding to the areas where the electronic components E1 and E2 should be mounted. In the mounting of the external electronic components on the wiring substrate 1 in the illustrated example, the exposed conductor pads 12p can be electrically and mechanically connected to the external electronic components via conductive bonding materials such as solder (not shown) between the connection pads of the external electronic components. At this time, a plating layer (not shown) such as a nickel layer and a tin layer can also be pre-formed on the surface of the conductor pads 12p. In the case of forming multiple component mounting areas, a conductor pattern that can electrically connect the conductor pads 12p located in adjacent component mounting areas can also be formed in the conductor layer 12 in the first laminated part 10. Multiple electronic components mounted during the use of the wiring substrate 1 can be electrically connected to each other via the first laminated part 10 in a short path. As a result, there is a situation where the degree of freedom of circuit design via multiple electronic components that can be mounted during the use of the wiring substrate 1 is increased.

[0033] Examples of the electronic components E1 and E2 that can be mounted on the wiring substrate 1 include electronic components such as active components such as semiconductor integrated circuit devices and transistors. Specifically, for example, they may be integrated circuits such as logic chips in which logic circuits are assembled, processing devices such as MPUs (Micro Processor Units), and memory elements such as HBMs (High Bandwidth Memory).

[0034] The first insulating layer 11 of the first buildup portion 10 can be formed of insulating resin such as epoxy resin or phenolic resin. The first insulating layer 11 can include any one of fluororesin, liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), polyester resin (PE), and modified polyimide resin (MPI).

[0035] Examples of the conductor constituting the first conductor layer 12 and the first via-hole conductor 13 include copper, nickel, and the like, and copper is preferably used. Figure 1 In the example shown, the first conductor layer 12 and the first via-hole conductor 13 are shown as a single layer, but the first conductor layer 12 and the via-hole conductor 13 can be configured in a multi-layer structure. Figure 2A and Figure 2B As described in detail, the first conductor layer 12 and the first via-hole conductor 13 can have a multilayer structure including a metal film layer (preferably a sputtered film layer) and a plated film layer (preferably an electroplated film layer).

[0036] The first conductor layer 12 can have high-density wiring, i.e., fine wiring FW, which has a relatively small wiring width and a relatively small distance between wirings (the shortest distance between adjacent wirings). The fine wiring FW can have the smallest pattern width and the smallest distance between patterns among the wirings constituting the wiring substrate 1. In the example shown in the figure, four of the plurality of first conductor layers 12 included in the first build-up portion 10 have fine wiring FW as high-density wiring. However, the number of first conductor layers 12 having fine wiring FW included in the first build-up portion 10 is not limited.

[0037] The fine wiring FW included in the first build-up part 10 has a wiring width and a wiring distance that are smaller than the wiring width and wiring distance of the wiring included in the conductor layer 22 (second conductor layer 22) in the second build-up part 20 described later. Specifically, for example, the minimum value of the wiring width of the fine wiring FW can be 3 μm or less, and the minimum value of the wiring distance between adjacent wirings can be 3 μm or less. By providing the first build-up part 10 with the fine wiring FW, wiring with more appropriate characteristics corresponding to the electrical signal that can be transmitted by the wiring in the first build-up part 10 is sometimes provided. In addition, it is considered that the density of the wiring in the first build-up part 10 is sometimes increased, and the degree of freedom of wiring design is increased. In addition, from the same point of view, the aspect ratio of the fine wiring FW is, for example, greater than 2.0 and less than 4.0.

[0038] The thickness of the first conductor layer 12 including the fine wiring FW in the first build-up portion 10 may be, for example, 7 μm or less. The thickness of the first insulating layer 11 in the first build-up portion 10 may be, for example, about 7.5 to 10 μm. In this case, the first insulating layer 11 preferably does not include a core material (reinforcement material) made of glass fiber, aramid fiber, or the like.

[0039] like Figure 1As shown, the first laminated part 10 is in contact with one surface 20F of the second laminated part 20. That is, the other surface 10B of the first laminated part 10, which is composed of the surfaces of the insulating layer 11 and the conductive layer 12 of the first laminated part 10, is opposite to the one surface 20F of the second laminated part 20. The second laminated part 20 has an insulating layer 21 (second insulating layer 21) and a conductive layer 22 (second conductive layer 22) in the same manner as the first laminated part 10, and the insulating layer 21 (second insulating layer 21) and the conductive layer 22 (second conductive layer 22) are alternately stacked. A via conductor 23 is formed in the second insulating layer 21 and penetrates the second insulating layer 21. Each conductive layer 22 is patterned to have a predetermined conductive pattern. As shown in FIG. Figure 1 As shown, the second build-up part 20 does not include a core layer.

[0040] like Figure 1 As shown, in the wiring substrate 1, a third build-up part 30 may be further laminated on the other side 20B of the second build-up part 20. The other side 20B, which is composed of the surface of the second conductor layer 22 of the second build-up part 20 and the surface of the second insulating layer 21 exposed from the pattern of the second conductor layer 22, faces one side 30F of the third build-up part 30. The third build-up part 30 includes an insulating layer 211 (third insulating layer 211) and a conductor layer 212 (third conductor layer 212). A via conductor 33 is formed in the insulating layer 211, and the via conductor 33 penetrates the insulating layer 211 and connects the conductor layer 212 and the conductor layer 22 constituting the other side 20B of the second build-up part 20.

[0041] exist Figure 1 In the example of the third laminated part 30, the third laminated part 30 further includes a solder resist layer 31 covering the surface of the insulating layer 211 and the conductive layer 212. The solder resist layer 31 is formed using, for example, a photosensitive polyimide resin or epoxy resin. An opening 31a is formed in the solder resist layer 31, and a conductive pad 32p of the conductive layer 212 is exposed from the opening 31a.

[0042] The insulating layer 21 constituting the second laminated portion 20 can be formed using the same insulating resin as the insulating layer 11. Each insulating layer 11, 21 can contain the same insulating resin in each laminated portion, or can contain different insulating resins from each other. Each insulating layer 21 can also contain a core material (reinforcement material) composed of glass fiber or aramid fiber. In the example shown in the figure, the insulating layer 211 of the third laminated portion 30 contains a core material 21b composed of glass fiber. Each insulating layer 21, 211 can also contain an inorganic filler composed of microparticles such as silica (SiO2), alumina or mullite.

[0043] The conductor layer 22 of the second build-up portion 20, the conductor layer 212 of the third build-up portion 30, and the via-hole conductors 23 and 33 can be formed using any metal such as copper or nickel, similarly to the conductor layer 12 and the via-hole conductor 13. Figure 1 As shown, each via-hole conductor 23 included in second build-up portion 20 and each via-hole conductor 33 included in third build-up portion 30 are formed into a tapered shape with a diameter decreasing from second surface 1B side toward first surface 1F side of wiring substrate 1 , similarly to via-hole conductor 13 of first build-up portion 10 .

[0044] The wiring width and the distance between wirings included in the second conductor layer 22 of the second build-up portion 20 and the third conductor layer 212 of the third build-up portion 30 are larger than the wiring width and the distance between wirings included in the first conductor layer 12 of the first build-up portion 10. The thickness of the second conductor layer 22 is formed thicker than the thickness of the first conductor layer 12, for example, about 10 μm or more. The second conductor layer 22 of the second build-up portion 20 does not include a fine wiring pattern of the same degree as the fine wiring FW of the first build-up portion 10. For example, the minimum value of the wiring width of the wiring included in the second conductor layer 22 is about 4 μm, and the minimum value of the distance between wirings is about 6 μm. In addition, the aspect ratio of the wiring included in the second conductor layer 22 is sometimes substantially the same as the aspect ratio of the fine wiring FW of the conductor layer 12, for example, about 2.0 or more and 4.0 or less. The via hole diameter of the via hole conductor 23 (the diameter of the contact surface of the via hole conductor 23 that contacts the conductor layer 22 on the other surface 20B side) is approximately 50 μm.

[0045] In the wiring substrate 1 shown in the figure, for example, the insulating layer 211 and the conductor layer 212 of the third build-up portion 30 are both formed thicker than the insulating layer 21 and the conductor layer 22 in the second build-up portion 20. For example, the thickness of the insulating layer 211 is about 100 μm or more and about 200 μm or less. In addition, the thickness of the conductor layer 212 is about 20 μm. In addition, the via diameter of the via conductor 33 formed in the insulating layer 211 (the diameter of the contact surface of the via conductor 33 that contacts the conductor layer 212 on the other surface 30B side) is about 100 μm.

[0046] Similar to the first conductor layer 12 and the first via conductor 13, the conductor layers 22, 212 and the via conductors 23, 33 may be composed of a multilayer structure, for example, a multilayer structure including a metal film layer (preferably a sputtered film layer or a chemically plated film layer) and a plated film layer (preferably an electroplated film layer). The second build-up portion 20 and the third build-up portion 30 do not include a fine wiring pattern like the fine wiring FW of the first build-up portion 10. In this case, the metal film layer in the multilayer structure constituting the conductor layer 22 and the via conductor 23 and the conductor layer 212 and the via conductor 33 may be a chemically plated film layer formed of a chemically plated film, in particular, a chemically plated copper film layer, and the plated film layer may be an electroplated film layer formed of an electroplated film, in particular, an electroplated copper film layer.

[0047] In addition, when the wiring substrate 1 itself is mounted on an external element such as an external wiring substrate (for example, a motherboard of any electrical device), the second surface 1B of the wiring substrate 1 on the side opposite to the component mounting surface of the wiring substrate 1 can be a connection surface connected to the external element. The conductor pad 32p can be connected to any substrate, electrical component, or mechanical component.

[0048] exist Figure 1 Referring to the enlarged view of the area IIA surrounded by the single-point dashed line, Figure 2A and in Figure 2A The enlarged view of the area IIB surrounded by the single-dot dash line is Figure 2B , the first conductor layer 12 in the first build-up portion 10 and the first via-hole conductor 13 formed integrally with the first conductor layer 12 are described in detail. Figure 2A and Figure 2B In, relative to Figure 1 , the vertical direction (thickness direction of the wiring substrate 1) is reversed, one surface 10F is located on the lower side of the paper, and the other surface 10B is located on the upper side of the paper. Figure 2A and Figure 2B In the description of the wiring substrate 1 , one surface 10F side is referred to as “lower” or “lower side”, and the other surface 10B side is referred to as “upper” or “upper side”.

[0049] like Figure 2A As shown in the figure, a via opening 11a penetrating the first insulating layer 11 is formed in the first insulating layer 11. The first via-hole conductor 13 connecting the first conductor layers 12 opposed to each other across the first insulating layer 11 is formed by filling the via opening 11a with a conductor. Specifically, as shown in the figure, the first layer 12a, which may be a metal film layer formed by sputtering, and the second layer 12b, which may be a plated film layer, which constitute the first conductor layer 12, fill the via opening 11a to constitute the first via-hole conductor 13. The first conductor layer 12 and the first via-hole conductor 13 are formed integrally. In addition, the via opening 11a formed in the first insulating layer 11 is also referred to as the first via opening 11a.

[0050] The first layer 12a covers the entire area of ​​the inner wall surface of the via opening 11a, and can function as a power supply layer when the second layer 12b is formed by electroplating. In the illustrated example, the first layer 12a has a double-layer structure including a lower layer 12aa and an upper layer 12ab. The lower layer 12aa can be, for example, a sputtered film layer of a copper alloy formed by sputtering using an alloy containing copper (for example, an alloy containing copper, silicon and aluminum) as a target. The upper layer 12ab can be, for example, a sputtered film layer of copper formed by sputtering using copper as a target. By having a structure in which the first layer 12a covering the inner wall surface of the via opening 11a includes the lower layer 12aa and the upper layer 12ab, sometimes the tightness between the inner wall surface of the via opening 11a and the first layer 12a (that is, the tightness between the inner wall surface of the via opening 11a and the first via conductor 13) is improved. In particular, when lower layer 12 aa is a sputtered film layer of copper alloy as described above, the inner wall surface of via opening 11 a and lower layer 12 aa can have relatively good adhesion.

[0051] The via opening 11a can be formed by irradiating a laser beam at a position of the first insulating layer 11 where the first via conductor 13 is to be formed, for example, from the upper surface of the insulating layer 11. The diameter of the formed via opening 11a is large on the laser irradiation side and small on the side opposite to the laser irradiation side (the inner side). Therefore, the via opening 11a can be formed in such a way that the diameter on the upper side is large and the diameter on the lower side is small. Figure 2A As shown, the inner wall surface of the via opening 11a is inclined from the upper side to the lower side of the insulating layer 11. The angle (inclination angle) θ of the inner wall surface of the via opening 11a on the side opposite to the via opening 11a (in the insulating layer 11) relative to the upper surface of the conductive layer 12 can be, for example, greater than 70° and less than 90°.

[0052] In addition, for example, the via opening 11a can be formed so that the aspect ratio of the via conductor 13 (the height from the upper surface of the lower conductor layer 12 to which the via conductor 13 is connected to the lower surface of the upper conductor layer / the diameter of the via conductor 13 on the upper surface of the lower conductor layer 12) is greater than about 0.5 and less than about 1.0.

[0053] In detail, as described later in the description of the manufacturing method of the wiring substrate, after the first insulating layer 11 is perforated with a via opening 11a by laser irradiation, the inner wall of the via opening 11a is desmeared. The desmearing is performed by a dry process. In the case where the first insulating layer 11 contains an inorganic filler, due to the desmearing, the filler particles exposed from the inner wall of the via opening 11a are formed to have a flat portion along the inner wall surface. Specifically, the portion of the filler particles protruding from the surface of the insulating resin constituting the first insulating layer 11 to the inner side of the via opening 11a is removed by the desmearing, and the inner wall surface can be roughly smoothly formed by the surface of the resin and the flat portion of the filler particles. That is, the entire inner wall surface of the via opening 11a can be relatively smoothly formed into a surface having a predetermined angle relative to the bottom surface of the via opening 11a (the upper surface of the conductor layer 12). Even in the case where the first insulating layer 11 contains an inorganic filler, the inner wall surface of the via opening 11a can be formed to be relatively smooth with a relatively small roughness. Since the inner wall surface of the via hole opening 11a is formed relatively smoothly, the surface of the first via hole conductor 13 in contact with the inner wall surface of the via hole opening 11a is also formed relatively smoothly. Therefore, the transmission loss of the signal transmitted through the first via hole conductor 13 can be suppressed to be relatively small.

[0054] like Figure 2B As shown, the first layer 12a constituting the via conductor 13 has a first portion 121a and a second portion 122a. Specifically, the lower layer 12aa constituting the first layer 12a has a lower layer first portion 121aa and a lower layer second portion 122aa, and the upper layer 12ab has an upper layer first portion 121ab and an upper layer second portion 122ab. The first portion 121a in the first layer 12a includes the lower layer first portion 121aa and the upper layer first portion 121ab. The second portion 122a in the first layer 12a includes the lower layer second portion 122aa and the upper layer second portion 122ab. The first portion 121a and the second portion 122a can be formed simultaneously when the first layer 12a is formed.

[0055] More specifically, as shown in the figure, the first portion 121a is a portion including the front end portion 121t and extending toward the bottom surface side of the via opening 11a, and the second portion 122a is a portion including the front end portion 122t and extending toward the opposite side of the bottom surface of the via opening 11a. The first portion 121a and the second portion 122a are continuous and electrically connected at the rear end portion 122e of the second portion 122a. The lower first portion 121aa includes the lower front end portion 121ta, and is continuous with the lower second portion 122aa at the lower rear end portion 122ea of ​​the lower second portion 122aa.

[0056] A portion of the first portion 121a is formed at a position closer to the center 11ac of the via opening 11a than the second portion 122a. Specifically, as shown in the figure, the front end portion 121t included in the first portion 121a is formed at a position closer to the center 11ac of the via opening 11a than the rear end portion 122e of the second portion 122a. In addition, in the lower layer 12aa, the lower layer front end portion 121ta is formed at a position closer to the center 11ac of the via opening 11a than the lower layer rear end portion 122ea. It is believed that the strength of the first layer 12a is relatively strong and the first layer 12a is difficult to break due to the structure in which a portion of the first portion 121a is formed at a position closer to the center 11ac of the via opening 11a than the second portion 122a.

[0057] The first layer 12a is formed along the inner wall surface of the via opening 11a. As described above, the inner wall surface of the via opening 11a is composed of the surface of the resin constituting the first insulating layer 11 and the flat part of the filler particles, and can be formed to have a relatively small roughness and be roughly smooth. Therefore, the surface of the first layer 12a (the surface in contact with the inner wall surface and the surface in contact with the second layer 12b) formed in contact with the inner wall surface of the via opening 11a also has a roughly smooth surface. That is, the first part 121a and the second part 122a of the first layer 12a have a roughly smooth surface. It should be noted that here, "roughly smooth surface" means that any continuous range of the surface of the first layer 12a covering the inner wall surface of the via opening 11a, excluding the front end 121t, 122t and the rear end 122e, is relatively smooth. It is believed that by making the first layer 12a have a roughly smooth surface, the transmission loss when the high-frequency signal is transmitted using the first via conductor 13 can be suppressed to a relatively small level.

[0058] As shown in the figure, the first layer 12a covering the inner wall surface of the via opening 11a may have a substantially stepped shape. In addition, the "substantially stepped shape" in the description of this specification means that as the outline of the cross-sectional shape of the first layer 12a, a plurality of portions extending substantially vertically relative to the bottom surface of the via opening 11a (the upper surface of the conductor layer 12) exist at different positions in the extending direction of the bottom surface of the via opening 11a. In this way, by making the first layer 12a in the first via conductor 13 have a substantially stepped shape, the adhesion between the first layer 12a and the second layer 12b can be improved by utilizing the anchoring effect relative to the second layer 12b formed on the first layer 12a. In addition, the lower layer 12aa and the upper layer 12ab constituting the first layer 12a each have a substantially stepped shape. In addition, on the inner wall surface of the via opening 11a constituted by the surface of the resin constituting the first insulating layer 11 and the flat portion of the filler particles, a step is sometimes formed at the boundary between the surface of the resin and the flat portion of the filler particles.

[0059] The upper surface of the first conductor layer 12 may be a polished surface with relatively small roughness and high flatness. By making the surface of the conductor layer 12 a polished surface with relatively small roughness, good high-frequency transmission characteristics may be obtained in the first build-up portion 10 .

[0060] Next, refer to Figure 3A to Figure 3M , to manufacture Figure 1 The manufacturing method of the wiring substrate of the embodiment is described by taking the case of the wiring substrate 1 shown in FIG. 1 as an example. In addition, each structural element formed in the manufacturing method described below can be used in any other embodiment unless otherwise specified. Figure 1 The wiring substrate 1 is formed of the materials exemplified as the materials of the corresponding structural elements in the description of the wiring substrate 1. In the following description of the manufacturing method of the wiring substrate 1, the side close to the supporting substrate GS is referred to as "lower" or "lower side", and the side away from the supporting substrate GS is referred to as "upper" or "upper side". Therefore, the surface facing the supporting substrate GS side of each element constituting the wiring substrate 1 is also referred to as the "lower surface", and the surface facing the side opposite to the supporting substrate GS is also referred to as the "upper surface". The wiring substrate 1 can be formed by manufacturing a first build-up portion 10 on the supporting substrate GS, manufacturing a second build-up portion 20 on the first build-up portion 10, and manufacturing a third build-up portion 30 on the second build-up portion 20 (refer to Figure 1 ).

[0061] First, if Figure 3A As shown, a support substrate GS having good surface flatness, such as a glass substrate, is prepared. On the surfaces of both sides of the support substrate GS, a metal film layer 121 is formed via an adhesive layer AL containing an azobenzene-based polymer adhesive that can be attached or detached by light irradiation. The metal film layer 121 is, for example, a metal film (preferably a copper film) layer formed by chemical plating or sputtering. The metal film layer 121 can be composed of a relatively thin metal foil.

[0062] Then, if Figure 3B As shown, a conductor layer 12 having a plurality of conductor pads 12p including a metal film layer 121 and a plated film layer 122 is formed on a support substrate GS via an adhesive layer AL. In forming the conductor layer 12, for example, a plating resist is formed on the metal film layer 121, and an opening corresponding to a formation area of ​​a pattern of the conductor pad 12p is formed on the plating resist, for example, by photolithography. Next, the plated film layer 122 is formed in the opening by electroplating using the metal film layer 121 as a seed layer. After the plated film layer 122 is formed, the plating resist is removed, and the metal film layer 121 exposed by removing the plating resist is etched to form a Figure 2B Status shown.

[0063] Then, if Figure 3CAs shown, an insulating layer 11 covering a conductor layer 12 is stacked. As the insulating layer 11, for example, an insulating resin such as an epoxy resin or a phenolic resin can be used. Fluororesin, liquid crystal polymer (LCP), polyvinyl fluoride resin (PTFE), polyester resin (PE), and modified polyimide resin (MPI) can also be used. The insulating layer 11 can be formed by hot pressing these resins formed into a film onto the conductor layer 12. A protective film PF is formed on the insulating layer 11 to completely cover the upper surface of the insulating layer 11. The protective film PF is, for example, a film made of polyethylene terephthalate (PET). A release agent may be present between the protective film PF and the upper surface of the insulating layer 11.

[0064] Next, the via conductor 13 (see Figure 1 ) is formed at a formation position by irradiation with, for example, a carbon dioxide laser, an excimer laser, or the like. A via opening 11a is formed that penetrates the protective film PF and the insulating layer 11. The via opening 11a can be formed in a shape that tapers from the upper surface of the insulating layer 11 toward the bottom surface (the upper surface of the conductor layer 12). The via opening 11a can be formed, for example, so that the angle θ of the inner wall surface opposite to the via opening 11a (in the insulating layer 11) relative to the upper surface of the conductor layer 12 is greater than 70° and less than 90°. After the via opening 11a is formed by laser, the inner surface (bottom surface and inner wall surface) of the via opening 11a can be desmeared. The desmearing treatment is preferably implemented by dry desmearing treatment using a plasma gas (for example, containing tetrafluoromethane). The desmearing treatment can also be performed while protecting the surface of the insulating layer 11 in a state where the protective film PF is formed on the surface of the insulating layer 11.

[0065] In addition, Figure 3C And the following references Figure 3F to Figure 3M In the figure, the laminate formed on one surface of the support substrate GS is shown, and the laminate that can be formed on the surface on the opposite side is omitted. However, the surface on the opposite side may also be formed with the same form and number of laminates, or with a conductor layer and an insulating layer of a form and number different from those on one surface, or may not be formed.

[0066] As in Figure 3C The enlarged view of the area D surrounded by the single-point dashed line in Figure 3DAs shown, by adjusting the processing conditions (gas content, gas concentration, processing temperature, processing time, pressure, etc.) in the desmear treatment using plasma gas, the inner wall surface of the via opening 11a can be smoothed. Specifically, in the case where the insulating layer 11 contains inorganic fillers, the protruding parts of the filler particles protruding from the inner wall surface of the via opening 11a can be selectively removed by the desmear treatment using plasma gas. A flat portion is formed on the filler particles. As a result, the surface of the inner wall surface of the via opening 11a composed of the resin contained in the insulating layer 11 and the surface composed of the flat portion of the filler particles can constitute an inner wall surface that is substantially the same and substantially smooth.

[0067] When the inner wall surface of the via opening 11a is formed roughly smoothly with respect to the surface composed of the resin and the surface composed of the flat portion of the filler particles, a step may be formed at the boundary between the surface of the resin and the flat portion of the filler particles depending on the processing conditions in the desmear treatment. After the desmear treatment in the via opening 11a, the protective film PF is removed from the upper surface of the insulating layer 11.

[0068] Then, if Figure 3E As shown, a conductor layer 12 (see FIG. 1 ) is formed on the inner wall surface of the via opening 11a and the upper surface of the insulating layer 11 by sputtering. Figure 3G ) is formed. Specifically, first, by sputtering, a lower layer 12aa is formed on the upper surface of the insulating layer 11, the inner wall surface of the via opening 11a, and the upper surface of the conductor layer 12 constituting the bottom surface of the via opening 11a. The lower layer 12aa can be formed, for example, by sputtering using an alloy containing copper (for example, an alloy containing copper, silicon, and aluminum) as a target. At this time, the lower layer 12aa can be formed simultaneously in a range where the lower layer 12aa is to be formed in a manner having a substantially step-like shape on the inner wall surface. By forming a step at the boundary between the surface of the resin in the inner wall surface of the via opening 11a and the flat portion of the filler particles, it is sometimes possible to relatively easily form the lower layer 12aa having a substantially step-like shape.

[0069] Next, the upper layer 12ab is formed by sputtering in a manner covering the lower layer 12aa. The upper layer 12ab is formed, for example, by sputtering using copper as a target. At this time, in the case where the lower layer 12aa has a substantially stepped shape, the upper layer 12ab can be formed along the substantially stepped shape of the lower layer 12aa. The surface of the formed upper layer 12ab reflects the surface of the substantially smooth inner wall surface of the via opening 11a, and has a substantially smooth surface.

[0070] like Figure 3F As shown in FIG. 1 , a plating resist R1 having an opening R11 corresponding to a conductor pattern to be formed is provided on the metal film (first layer) 12a. Figure 3F to Figure 3J In order to facilitate observation, Figure 3E The first layer 12a of the two-layer structure shown is shown as a single layer.

[0071] like Figure 3G As shown, by electroplating the first layer 12a as a power supply layer, the second layer 12b as a plated film layer is formed in the opening of the opening R11 of the plating resist R1. Then, after removing the plating resist R1, the portion of the first layer 12a not covered by the second layer 12b is removed by etching or the like. As a result, the conductor layer 12 composed of the first layer 12a and the second layer 12b having fine wiring FW is formed. In addition, the interior of the via opening 11a is completely filled with the second layer 12b as a plated film, thereby forming a via conductor 13.

[0072] Then, if Figure 3H As shown, a desired number of insulating layers 11 and conductive layers 12 and via-hole conductors 13 penetrating the insulating layers are formed on conductive layers 12 and insulating layers 11 by the same method as the above-mentioned method of forming insulating layers 11, conductive layers 12 and via-hole conductors 13.

[0073] Then, if Fig. 3I As shown, a first build-up portion 10 is formed on the upper side of the conductor layer 12 (see Figure 1 ) of the outermost insulating layer 11 of the insulating layer 11. Then, by laser processing, the via conductor 13 (refer to Figure 1 ) is formed in the insulating layer 11 at a position corresponding to the formation position of the via hole 13 to form a via hole opening 11a.

[0074] Then, if Figure 3J As shown, the conductor layer 12 constituting the other surface 10B is formed simultaneously with the via conductor 13 filling the via opening 11a by using any conductor pattern forming method such as the semi-additive method. The formation of the first build-up portion 10 on the support substrate GS is completed.

[0075] Then, if Figure 3K As shown, the second laminated part 20 is formed on the conductor layer 12 and the insulating layer 11 constituting the other surface 10B of the first laminated part 10. The insulating layer 21 can be formed by thermocompression bonding of a film-like resin. The conductor layer 22 can be formed by any conductor pattern forming method such as a semi-additive method. The desired number of insulating layers 21 and conductor layers 22 and the via conductors 23 penetrating the insulating layers 21 are formed. In addition, Figure 3K to Figure 3M In the Figure 1 Likewise shown as a single layer.

[0076] like Figure 3LAs shown, the third build-up part 30 is formed on the insulating layer 21 and the conductor layer 22 constituting the other surface 20B of the second build-up part 20. The via conductor 33 penetrating the insulating layer 211, the conductor layer 212 and the insulating layer 211 is formed by the same method as the method of forming the insulating layer 21, the conductor layer 22 and the via conductor 23. As the insulating resin forming the insulating layer 211, a prepreg containing an insulating resin such as epoxy resin, BT resin impregnated in a reinforcing material (core material) composed of glass fiber can be used. Next, a solder resist layer 31 is formed by forming a photosensitive epoxy resin or polyimide resin layer on the surface of the insulating layer 211 and the conductor layer 212. Then, openings 31a that define the conductor pads 32p are formed respectively by photolithography technology.

[0077] Then, if Figure 3M As shown, the support substrate GS is removed. The lower surface of the conductor pad 12p and the lower surface of the insulating layer 11 are exposed. In the removal of the support substrate GS, after the adhesive layer AL is irradiated with, for example, laser light to soften it, the support substrate GS is peeled off from the conductor pad 12p and the insulating layer 11. In addition, the adhesive layer AL that may remain on the surface of the conductor pad 12p and the insulating layer 11 can be removed by cleaning. Completion Figure 1 The wiring substrate 1 is shown.

[0078] The wiring substrate of the embodiment is not limited to the structure, shape, and material illustrated in the drawings and in this specification. As described above, each buildup portion included in the wiring substrate of the embodiment can have any number of insulating layers and conductive layers. In addition, the manufacturing method of the wiring substrate of the embodiment is not limited to the structure, shape, and material illustrated in the drawings. Figure 3A to Figure 3M The conditions, order, etc. of the described method can be changed arbitrarily. In addition, a specific step can be omitted, and other steps can be added. For example, a plating layer including a nickel layer and a tin layer can be formed on the surface of the conductor pad 12p exposed after the support substrate GS is removed.

Claims

1. A wiring substrate comprising a first surface and a second surface opposite to the first surface, The wiring substrate has: a first build-up portion including a first insulating layer and a first conductor layer, a first via opening penetrating the first insulating layer, and a first via conductor filling the first via opening, wherein the first insulating layer and the first conductor layer are alternately stacked; and The second build-up portion includes a second insulating layer and a second conductive layer, wherein the second insulating layer and the second conductive layer are alternately stacked. in, The first laminated portion is located on the first surface side of the second laminated portion and is bonded to the second laminated portion. The minimum value of the wiring width of the wiring included in the first conductor layer is smaller than the minimum value of the wiring width of the wiring included in the second conductor layer, The minimum value of the distance between wirings included in the first conductor layer is smaller than the minimum value of the distance between wirings included in the second conductor layer. The first conductor layer and the first via conductor have a first layer and a second layer formed on the first layer, The first layer covering the inner wall surface of the first via opening includes a first portion and a second portion having a substantially smooth surface, The first part is electrically connected to the second part, A portion of the first portion is located closer to the center of the first via opening than the second portion.

2. The wiring substrate according to claim 1, wherein: The aspect ratio of the wiring included in the first conductive layer is greater than or equal to 2.0 and less than or equal to 4.

0.

3. The wiring substrate according to claim 1, wherein The minimum value of the wiring width of the wiring included in the first conductor layer is 3 μm or less, and the minimum value of the distance between wirings included in the first conductor layer is 3 μm or less.

4. The wiring substrate according to claim 1, wherein: The front end portion included in the first portion is located closer to the center of the first via opening than the rear end portion of the second portion.

5. The wiring substrate according to claim 1, wherein The first portion and the second portion are formed simultaneously.

6. The wiring substrate according to claim 1, wherein The first layer formed on the inner wall surface has a substantially step-like cross-section.

7. The wiring substrate according to claim 1, wherein: The first layer includes a lower layer covering the inner wall surface and an upper layer on the lower layer, The lower layer includes a lower layer first portion included in the first portion and a lower layer second portion included in the second portion.

8. The wiring substrate according to claim 7, wherein: The lower front end portion of the lower first portion is located closer to the center of the first via opening than the lower rear end portion of the lower second portion.

9. The wiring substrate according to claim 7, wherein: The lower layer has a substantially stepped shape in cross section.

10. The wiring substrate according to claim 1, wherein The first insulating layer comprises resin and filler particles, The filler particles have a flat portion, The inner wall surface is composed of the resin and the flat portion.

11. The wiring substrate according to claim 10, wherein: A step is formed between the resin forming the inner wall surface and the flat portion.

12. The wiring substrate according to claim 10, wherein: The flat portion of the filler particle is formed by removing a protruding portion protruding from a surface of the resin during formation of the first via opening.

13. The wiring substrate according to claim 1, wherein The first via opening has a shape with a diameter decreasing from the second surface toward the first surface.

14. The wiring substrate according to claim 1, wherein The thickness of the first conductor layer is less than 7 μm, The second conductor layer has a thickness of 10 μm or more.

15. The wiring substrate according to claim 1, wherein The second build-up portion includes a third build-up portion including a third insulating layer and a third conductive layer on the second-surface side of the second build-up portion.

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