Semiconductor device, manufacturing method thereof, and memory system

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and a storage system, and the semiconductor device comprises a plurality of channel structures which are arranged in an array manner along a first direction and a second direction and extend along a third direction, the first direction intersects with the second direction, and the third direction intersects with the first direction and the second direction; the multiple conductive shielding structures are arranged in the second direction, and the conductive shielding structures are located between the adjacent channel structures in the second direction; the gate lines extend along the first direction and the third direction and are positioned between the adjacent channel structures; at least part of the shielding structure leading-out wire extends in the second direction, and the shielding structure leading-out wire is connected with the at least two conductive shielding structures.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and a storage system. Background Art

[0002] Dynamic random access memory is an important memory. The storage unit of dynamic random access memory mainly includes a storage capacitor and a transistor connected in series with the storage capacitor. The storage capacitor is used to store data, and the transistor is used to control the storage of data in the storage capacitor.

[0003] At present, the manufacturing process of dynamic random access memory is relatively difficult. How to reduce the manufacturing difficulty of dynamic random access memory is a technical problem that needs to be solved. Summary of the invention

[0004] The purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, and a storage system to reduce the difficulty of manufacturing the semiconductor device.

[0005] In a first aspect, the present application provides a semiconductor device, comprising:

[0006] A plurality of channel structures are arranged in an array along a first direction and a second direction and extend along a third direction, wherein the first direction intersects with the second direction, and the third direction intersects with the first direction and the second direction;

[0007] A plurality of conductive shielding structures are arranged along the second direction, wherein the conductive shielding structures are located between adjacent channel structures in the second direction;

[0008] a gate line extending along the first direction and the third direction, wherein the gate line is located between adjacent channel structures; and

[0009] The shielding structure leads out a conductive line, at least a portion of which extends along the second direction and is connected to at least two of the conductive shielding structures.

[0010] In some embodiments of the semiconductor device, the semiconductor device further comprises: a plurality of bit lines extending along the second direction and arranged along the first direction and respectively connected to one end of the plurality of channel structures in the third direction;

[0011] A plurality of bit line lead contacts, respectively connected to the plurality of bit lines; and

[0012] The shielding structure lead-out contact is connected to the shielding structure lead-out wire, is located on the same side of the channel structure as the bit line lead-out contact in the third direction, and is located on at least one side of the bit line in the second direction.

[0013] In the semiconductor device of some embodiments, the plurality of bit lines and the shielding structure lead wires are located on the same side of the channel structure in the third direction, and the shielding structure lead wires are located on at least one side of the bit lines in the first direction.

[0014] In some embodiments of the semiconductor device, the semiconductor device further comprises: a redundant channel structure extending along the third direction and disconnected from the plurality of bit lines; and the shielding structure lead wire is disposed adjacent to the redundant channel structure.

[0015] In the semiconductor device of some embodiments, in the first direction, the shielding structure lead wire is spaced apart from the redundant channel structure.

[0016] In the semiconductor device of some embodiments, the shielding structure lead-out conductive line contacts the redundant channel structure.

[0017] In some embodiments of the semiconductor device, the semiconductor device further comprises: a plurality of gate line lead contacts, located on both sides of the bit line in the first direction and respectively connected to the plurality of gate lines;

[0018] Wherein, in the second direction, a plurality of bit line lead-out contacts and the shielding structure lead-out contacts are respectively located on both sides of the gate line.

[0019] In the semiconductor device of some embodiments, the semiconductor device further comprises: a capacitor connected to the other end of the channel structure in the third direction;

[0020] Wherein, in the third direction, the capacitor and the shielding structure lead wires are located on both sides of the channel structure.

[0021] In the semiconductor device of some embodiments, the shielding structure leads out a conductive line extending along the second direction; or,

[0022] The shielding structure lead wire includes a first wire segment extending along the second direction and a second wire segment extending along the first direction, wherein the first wire segment is connected to the second wire segment and contacts a plurality of conductive shielding structures.

[0023] In a second aspect, the present application provides a method for manufacturing a semiconductor device, comprising:

[0024] A groove is formed in the semiconductor layer, the groove is sunken from the first surface of the semiconductor layer to the second surface, the remaining semiconductor layer includes a plurality of channel structures arranged in an array along the first direction and the second direction and extending along the third direction, the first surface and the second surface are arranged opposite to each other in the third direction, the first direction intersects with the second direction, and the third direction intersects with the first direction and the second direction;

[0025] forming a plurality of conductive shielding structures arranged along the second direction in the semiconductor layer, wherein the conductive shielding structures are located between adjacent channel structures in the second direction;

[0026] forming a gate line extending along the first direction and the third direction in the semiconductor layer, wherein the gate line is located between adjacent channel structures; and

[0027] A shielding structure lead-out wire is formed, at least a portion of which extends along the second direction and is connected to at least two of the conductive shielding structures.

[0028] In the method for manufacturing a semiconductor device in some embodiments, the method further includes: forming a plurality of bit lines extending along the second direction and arranged along the first direction, the plurality of bit lines being respectively connected to one end of the plurality of channel structures in the third direction;

[0029] forming a plurality of bit line extraction contacts respectively connected to the plurality of bit lines; and

[0030] A shielding structure lead contact connected to the shielding structure lead wire is formed, the shielding structure lead contact and the bit line lead contact are located on the same side of the plurality of channel structures in the third direction, and the shielding structure lead contact is located on at least one side of the bit line in the second direction.

[0031] In some embodiments of the semiconductor device manufacturing method, the forming of a plurality of bit lines extending along the second direction and arranged along the first direction includes: in the third direction, the plurality of bit lines and the shielding structure lead-out wires are located on the same side of a plurality of the channel structures, and in the first direction, the shielding structure lead-out wires are located on at least one side of the bit lines.

[0032] In the method for manufacturing a semiconductor device in some embodiments, the method further comprises: causing the remaining semiconductor layer to further comprise a redundant channel structure extending along the third direction;

[0033] The forming of a plurality of bit lines extending along the second direction and arranged along the first direction comprises: forming a plurality of the bit lines disconnected from the redundant channel structure;

[0034] The forming of the shielding structure lead-out conductor includes: forming the shielding structure lead-out conductor disposed adjacent to the redundant channel structure.

[0035] In the method for manufacturing a semiconductor device in some embodiments, the method further includes: filling a dielectric layer in the groove;

[0036] Thinning the second surface of the semiconductor layer to expose the dielectric layer and form a thinned third surface; and

[0037] Removing a portion of the dielectric layer and / or a portion of the semiconductor layer adjacent to the redundant channel structure to form a lead wire accommodating groove, wherein the lead wire accommodating groove exposes a plurality of the conductive shielding structures, and at least a portion of the lead wire accommodating groove extends along the third direction, and the lead wire accommodating groove is sunken from the third surface to the first surface;

[0038] The forming of the shielding structure lead wire comprises: forming a shielding structure lead wire in the lead wire receiving groove so as to contact with a plurality of the conductive shielding structures.

[0039] In the method for manufacturing a semiconductor device in some embodiments, forming a groove in the semiconductor layer includes:

[0040] forming a first groove extending along the second direction and the third direction in the semiconductor layer, and the remaining semiconductor layer includes a semiconductor line;

[0041] Forming a plurality of second grooves and a plurality of third grooves in the semiconductor layer, the grooves extending along the third direction and the first direction and arranged along the second direction, wherein the second grooves and the third grooves intersect the semiconductor line, and the size of the second grooves along the first direction is smaller than the size of the third grooves along the first direction;

[0042] The forming of a plurality of conductive shielding structures arranged along the second direction in the semiconductor layer comprises: filling a conductive layer in a plurality of the second grooves and a plurality of the third grooves; and

[0043] The conductive layer in the plurality of the third grooves is removed, and at least a portion of the conductive layer remaining in the plurality of the second grooves forms a plurality of the conductive shielding structures.

[0044] In the method for manufacturing a semiconductor device in some embodiments, the method further includes: expanding the size of the third groove along the third direction and the second direction to form a plurality of fourth grooves;

[0045] The forming of the gate lines extending along the first direction in the semiconductor layer comprises: forming a plurality of the gate lines extending along the first direction and arranged along the second direction in a plurality of the fourth grooves respectively;

[0046] The method further includes: forming a plurality of gate line lead-out contacts, wherein the plurality of gate line lead-out contacts are located on both sides of the bit line in the first direction and are respectively connected to the plurality of gate lines.

[0047] In the method for manufacturing a semiconductor device in some embodiments, the method further includes: forming a capacitor connected to the other end of the plurality of channel structures in the third direction;

[0048] The forming of the shielding structure lead-out wire comprises: forming the shielding structure lead-out wire on a side of the channel structure away from the capacitor in the third direction.

[0049] In the method for manufacturing a semiconductor device in some embodiments, the forming of the shielding structure lead wire comprises: forming the shielding structure lead wire extending along the second direction and contacting a plurality of the conductive shielding structures; or,

[0050] The forming of the shielding structure lead wire includes: making the shielding structure lead wire include a first wire segment extending along the second direction and a second wire segment extending along the first direction, wherein the first wire segment is connected to the second wire segment and contacts the plurality of the conductive shielding structures.

[0051] In a third aspect, the present application further provides a storage system, the storage system comprising:

[0052] A memory, comprising the semiconductor device as described in any of the above embodiments; and

[0053] The controller is connected to the memory and is used to control the memory.

[0054] The beneficial effects of some embodiments of the present application include: the gate line extends along a first direction, and at least a portion of the shielding structure lead-out wire extends along a second direction, and the first direction intersects with the second direction. Therefore, the extension direction of at least a portion of the shielding structure lead-out wire intersects with the extension direction of the gate line. When the shielding structure lead-out contact is used to lead out the shielding structure lead-out wire, the process window of the shielding structure lead-out contact will not be limited by the spacing between adjacent gate lines in the second direction, which can reduce the manufacturing difficulty of the semiconductor device. Moreover, a plurality of conductive shielding structures are arranged at intervals along the second direction, and a shielding structure lead-out wire is connected to at least two conductive shielding structures. With this design, the number of shielding structure lead-out wires in the semiconductor device is relatively small, further reducing the manufacturing difficulty of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present application;

[0056] Figure 2A Schematic diagram of a semiconductor layer, a first insulating layer and a mask layer in some embodiments of the present application;

[0057] Figure 2B For along Figure 2A Schematic diagram of the cross-sectional structure taken along the A-A' tangent line;

[0058] Figure 2C A schematic diagram of a planar structure of forming semiconductor lines and a first dielectric layer in a semiconductor layer in some embodiments of the present application;

[0059] Figure 2D For along Figure 2C Schematic diagram of the cross-sectional structure taken along the B-B' tangent line;

[0060] Figure 2E It is a schematic plan view of a structure in which a second groove and a third groove are formed in a semiconductor layer in some embodiments of the present application;

[0061] Figure 2F For along Figure 2E Schematic diagram of the cross-sectional structure taken along the C-C' tangent line;

[0062] Figure 2G It is a schematic diagram of a planar structure in which a conductive layer is formed in the second groove and the third groove in some embodiments of the present application;

[0063] Figure 2H For along Figure 2G Schematic diagram of the cross-sectional structure taken along the D-D' tangent line;

[0064] Fig.2I It is a schematic plan view of forming a conductive shielding structure in the second groove and forming a protective layer and a first insulating filling portion in some embodiments of the present application;

[0065] Figure 2J For along Fig.2I Schematic diagram of the cross-sectional structure taken along the E-E' tangent line;

[0066] Figure 2K This is a schematic plan view of the structure of expanding the third groove to form a fourth groove in some embodiments of the present application;

[0067] Figure 2L For along Figure 2K A schematic diagram of the cross-sectional structure taken along the F1-F1' tangent line;

[0068] Figure 2MFor along Figure 2K A schematic diagram of the cross-sectional structure taken along the F2-F2' tangent line;

[0069] Figure 3A A schematic diagram of a planar structure for forming an initial gate layer in some embodiments of the present application;

[0070] Figure 3B For along Figure 3A Schematic diagram of the cross-sectional structure taken along the G-G' tangent line;

[0071] Figure 3C It is a schematic diagram of a planar structure of forming a gate line and a second insulating filling portion in some embodiments of the present application;

[0072] Figure 3D For along Figure 3C Schematic diagram of the cross-sectional structure taken along the H-H' tangent line;

[0073] Figure 3E A schematic diagram of a planar structure in which the second surface is thinned to form a third surface in some embodiments of the present application;

[0074] Figure 3F For along Figure 3E Schematic diagram of the cross-sectional structure taken along the I-I' tangent line;

[0075] Figure 4A is a schematic plan view of forming a second mask pattern on a third surface in some embodiments of the present application;

[0076] Figure 4B For along Figure 4A A schematic diagram of the cross-sectional structure taken along the J1-J1' tangent line;

[0077] Figure 4C For along Figure 4A A schematic diagram of the cross-sectional structure taken along the J2-J2' tangent line;

[0078] Figure 5A It is a schematic diagram of a planar structure of forming a lead wire receiving groove in some embodiments of the present application;

[0079] Figure 5B For along Figure 5A Schematic diagram of the cross-sectional structure taken along the K1-K1' tangent line;

[0080] Figure 5C For along Figure 5A Schematic diagram of the cross-sectional structure taken along the K2-K2' tangent line;

[0081] Figure 5D It is a schematic diagram of a planar structure of a lead-out wire of a shielding structure formed in a lead-out wire accommodating groove in some embodiments of the present application;

[0082] Figure 5E For along Figure 5D Schematic diagram of the cross-sectional structure taken along the M-M' tangent line;

[0083] Fig. 6A A schematic diagram of a planar structure for forming a bit line in some embodiments of the present application;

[0084] Figure 6B For along Fig. 6A Schematic diagram of the cross-sectional structure taken along the N-N' tangent line;

[0085] Fig. 7A It is a schematic diagram of a planar structure for forming a bit line lead-out contact, a shielding structure lead-out contact, and a gate line lead-out contact in some embodiments of the present application;

[0086] Figure 7B Schematic diagram of the planar structure of the gate line, the conductive shielding structure, the channel structure and the redundant channel structure in some embodiments of the present application;

[0087] Figure 7C For along Fig. 7A A schematic diagram of the cross-sectional structure taken along the O1-O1' tangent line;

[0088] Fig.7D For along Fig. 7A Schematic diagram of the cross-sectional structure taken along the O2-O2' tangent line;

[0089] Fig. 8A Schematic diagrams of plan views of forming a second mask pattern on a third surface in some other embodiments of the present application;

[0090] Figure 8B For along Fig. 8A A schematic diagram of the cross-sectional structure taken along the P1-P1' tangent line;

[0091] Figure 8C For along Fig. 8A A schematic diagram of the cross-sectional structure taken along the P2-P2' tangent line;

[0092] Fig.8D It is a schematic diagram of a planar structure of forming shielding structure lead-out conductors, bit line lead-out contacts, shielding structure lead-out contacts and gate line lead-out contacts in other embodiments of the present application;

[0093] Fig. 8E For along Fig.8D Schematic diagram of the cross-sectional structure taken along the Q-Q' tangent line;

[0094] Fig. 9 A block diagram of a storage system according to some embodiments of the present application;

[0095] Fig.10A block diagram of a storage system according to some other embodiments of the present application;

[0096] Fig.11 A block diagram of an electronic device according to some embodiments of the present application.

[0097] Reference numerals:

[0098] x, first direction; y, second direction; z, third direction;

[0099] 11, semiconductor layer; 11a, first surface; 11b, second surface; 111, semiconductor line; 11c1, storage area; 11c2, peripheral area; 11d, first groove; 11e, second groove; 11f, third groove; 11g, fourth groove; 11h, third surface; 112, columnar semiconductor structure; 113, channel structure; 114, redundant channel structure; 1151, first electrode; 1152, second electrode;

[0100] 121, first insulating layer; 122, first dielectric layer; 1231, first isolation layer; 1232, second isolation layer; 1233, protective layer; 1234, first insulating filling portion; 1235, insulating padding portion; 1235a, insulating padding top surface; 1235b, insulating padding bottom surface; 1236, gate insulating layer; 1237, second insulating filling portion; 1238, third isolation layer; 1239, fourth isolation layer;

[0101] 131, first mask layer; 131a, first mask pattern; 132a, second mask opening; 132b, second mask pattern; 133a, third mask opening; 133b, third mask pattern;

[0102] 141, conductive layer; 142, conductive shielding structure; 142a, conductive shielding bottom surface; 142b, conductive shielding top surface;

[0103] 151, initial gate layer; 1511, first initial conductive layer; 1512, second initial conductive layer; 152, gate line; 152a, top surface of gate line; 152b, bottom surface of gate line;

[0104] 161, connection contact; 162, capacitor; 163, first electrode; 164, second electrode;

[0105] 171, lead wire receiving groove; 1711, first lead wire receiving groove; 1712, second lead wire receiving groove; 172, shielding structure lead wire; 1721, first wire segment; 1722, second wire segment;

[0106] 181, bit line; 182, bit line receiving groove;

[0107] 191, bit line lead-out contact; 192, shield structure lead-out contact; 193, gate line lead-out contact;

[0108] 100, semiconductor device; 200, memory; 300, controller; 400, storage system; 500, electronic device; host, 600. DETAILED DESCRIPTION

[0109] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0110] Please refer to Figure 1 As shown, it is a schematic flow chart of a method for manufacturing a semiconductor device in some embodiments of the present application. The method for manufacturing a semiconductor device comprises the following steps:

[0111] Step S101: forming a groove in the semiconductor layer, the groove being sunken from the first surface to the second surface of the semiconductor layer, the remaining semiconductor layer comprising a plurality of channel structures arranged in an array along the first direction and the second direction and extending along the third direction, the first surface and the second surface being arranged opposite to each other in the third direction, the first direction intersecting with the second direction, and the third direction intersecting with the first direction and the second direction;

[0112] Step S102: forming a plurality of conductive shielding structures arranged along a second direction in the semiconductor layer, wherein the conductive shielding structures are located between adjacent channel structures in the second direction;

[0113] Step S103: forming a gate line extending along a first direction in the semiconductor layer, and the gate line is located between adjacent channel structures;

[0114] Step S104: forming a shielding structure lead-out wire, wherein at least a portion of the shielding structure lead-out wire extends along the second direction and is connected to at least two conductive shielding structures.

[0115] In some embodiments of the present application, a gate line extending along a first direction is formed in a semiconductor layer, and a shielding structure lead-out wire is also formed, at least a portion of the shielding structure lead-out wire extends along a second direction, and the first direction intersects with the second direction. Therefore, the extension direction of at least a portion of the shielding structure lead-out wire intersects with the extension direction of the gate line. When the shielding structure lead-out contact is used to lead out the shielding structure lead-out wire, the process window of the shielding structure lead-out contact will not be limited by the spacing between adjacent gate lines in the second direction, which can reduce the manufacturing difficulty of the semiconductor device. Moreover, a plurality of conductive shielding structures are arranged at intervals along the second direction, and a shielding structure lead-out wire is connected to at least two conductive shielding structures. With this design, the number of shielding structure lead-out wires in the semiconductor device is relatively small, further reducing the manufacturing difficulty of the semiconductor device.

[0116] The manufacturing process of the semiconductor device is described in detail below.

[0117] First, execute the above step S101, refer to Figures 2A to 2M As shown, a groove is formed in the semiconductor layer 11, and the groove is sunken from the first surface 11a of the semiconductor layer 11 to the second surface 11b. The remaining semiconductor layer 11 includes a plurality of channel structures 113 arranged in an array along the first direction x and the second direction y and extending along the third direction z. The first surface 11a and the second surface 11b are arranged opposite to each other in the third direction z, the first direction x intersects with the second direction y, and the third direction z intersects with the first direction x and the second direction y.

[0118] In some embodiments, reference Figure 2A and Figure 2B As shown, before forming a groove in the semiconductor layer 11, the manufacturing method of the semiconductor device includes: providing a semiconductor layer 11, the semiconductor layer 11 includes a first surface 11a and a second surface 11b opposite to each other in a third direction z; and forming a first insulating layer 121 on the first surface 11a of the semiconductor layer 11.

[0119] The semiconductor layer 11 has adjacent storage areas 11c1 and peripheral areas 11c2, and the peripheral area 11c2 is located at least on one side of the storage area 11c1 in the first direction x. The storage area 11c1 is used to form a storage element. The material of the semiconductor layer 11 includes but is not limited to single-element semiconductor materials such as single crystal silicon. Specifically, the semiconductor layer 11 includes a silicon wafer.

[0120] During the processing of the semiconductor layer 11, the first insulating layer 121 protects the semiconductor layer 11. The material of the first insulating layer 121 includes, but is not limited to, insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. Specifically, the material of the first insulating layer 121 includes silicon oxide to ensure that it can better adhere to the semiconductor layer 11.

[0121] Any two of the first direction x, the second direction y, and the third direction z are perpendicular to each other, but the present invention is not limited thereto.

[0122] In some embodiments, please refer to FIG. 2A to FIG. 2D As shown, before forming a groove in the semiconductor layer 11, the method for manufacturing a semiconductor device includes: forming a first mask layer 131 on a surface of the first insulating layer 121 away from the semiconductor layer 11; and patterning the first mask layer 131 to form a first mask pattern 131a.

[0123] After the first mask layer 131 is patterned, a first mask pattern 131a is formed. The semiconductor layer 11 can be patterned using the first mask pattern 131a as a mask. The material of the first mask layer 131 may include at least one of an inorganic insulating material and an organic insulating material. The inorganic insulating material includes but is not limited to silicon nitride. The organic insulating material includes but is not limited to photoresist. Specifically, the material of the first mask layer 131 includes silicon nitride.

[0124] In some embodiments, please refer to Figure 2C and Figure 2D As shown, forming grooves in the semiconductor layer 11 includes: forming a plurality of first grooves 11 d in the semiconductor layer 11 , and the remaining semiconductor layer 11 includes a plurality of semiconductor lines 111 .

[0125] Specifically, a portion of the semiconductor layer 11 is removed through an etching process, and the remaining semiconductor layer 11 includes a plurality of semiconductor wires 111 .

[0126] The plurality of first grooves 11d are arranged at intervals along the first direction x. The plurality of first grooves 11d are sunken from the first surface 11a to the second surface 11b and extend along the second direction y.

[0127] A plurality of semiconductor wires 111 are arranged at intervals along a first direction x, and a first groove 11d is provided between two adjacent semiconductor wires 111. A plurality of semiconductor wires 111 are provided in a storage area 11c1 and a peripheral area 11c2. Each semiconductor wire 111 extends along a second direction y and a third direction z. Each semiconductor wire 111 includes a first end face and a second end face opposite to each other in the second direction y. The first end faces of two adjacent semiconductor wires 111 are staggered. The second end faces of two adjacent semiconductor wires 111 are staggered.

[0128] In some embodiments, please refer to Figure 2C and Figure 2D As shown, after forming a plurality of semiconductor lines 111 , the method for manufacturing a semiconductor device further includes: forming a first dielectric layer 122 in the first groove 11 d .

[0129] In some embodiments of the present application, adjacent semiconductor lines 111 are isolated from each other by a first dielectric layer 122. The material of the first dielectric layer 122 includes at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0130] In some embodiments, before forming the first dielectric layer 122 in the first groove 11 d , the method for manufacturing a semiconductor device further includes: forming a second insulating layer (not shown) on the sidewalls of the plurality of semiconductor lines 111 .

[0131] In some embodiments of the present application, the second insulating layer repairs the sidewalls of the semiconductor line 111. Exemplarily, the sidewalls of the semiconductor line 111 are oxidized at a high temperature to form the second insulating layer, but the present invention is not limited thereto.

[0132] In some embodiments, reference Figure 2E and Figure 2F As shown, forming grooves in the semiconductor layer 11 also includes: forming a plurality of second grooves 11e and a plurality of third grooves 11f extending along the third direction z and the first direction x and arranged along the second direction y in the semiconductor layer 11, the second grooves 11e and the third grooves 11f intersecting with the semiconductor lines 111 to form a columnar semiconductor structure 112, and the size of the second grooves 11e along the first direction x is smaller than the size of the third grooves 11f along the first direction x.

[0133] In the second direction y, the plurality of second grooves 11e and the plurality of third grooves 11f are alternately arranged in a one-to-one manner. In the second direction y, the size of the second groove 11e is the same as the size of the third groove 11f. In the third direction z, the size of the second groove 11e is also the same as the size of the third groove 11f. In the first direction x, the size of the second groove 11e is smaller than the size of the third groove 11f.

[0134] In some embodiments, reference Figure 2G and 2H As shown, after forming multiple second grooves 11e and multiple third grooves 11f, the manufacturing method of the semiconductor device also includes: forming a first isolation layer 1231 in the multiple second grooves 11e, and forming a second isolation layer 1232 in the multiple third grooves 11f, the first isolation layer 1231 and the second isolation layer 1232 are located on the side walls of the columnar semiconductor structure 112.

[0135] In some embodiments, a first isolation layer 1231 and a second isolation layer 1232 may be formed in the plurality of second grooves 11e and the plurality of third grooves 11f respectively by a thin film deposition process. In other embodiments, the sidewalls of the columnar semiconductor structure 112 may also be oxidized under heating conditions to form the first isolation layer 1231 and the second isolation layer 1232. The materials of the first isolation layer 1231 and the second isolation layer 1232 include, but are not limited to, insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0136] Next, please refer to Figure 2G to Figure 2J As shown, the above step 102 is performed to form a plurality of conductive shielding structures 142 arranged along the second direction y in the semiconductor layer 11 .

[0137] In some embodiments, forming a plurality of conductive shielding structures 142 arranged along the second direction y in the semiconductor layer 11 includes: filling a conductive layer 141 in a plurality of second grooves 11e and a plurality of third grooves 11f; and removing the conductive layer 141 in the plurality of third grooves 11f, and at least a portion of the conductive layer 141 remaining in the plurality of second grooves 11e forms a plurality of conductive shielding structures 142.

[0138] It should be noted that in some related technologies, a sacrificial layer needs to be formed in the third groove and a conductive layer needs to be formed in the second groove. The sacrificial layer and the conductive layer are formed by different materials and different steps. In some embodiments of the present application, a conductive layer 141 is filled in the third groove 11f and the second groove 11e at the same time. At least a portion of the conductive layer 141 remaining in the second groove 11e forms a conductive shielding structure 142, and the conductive layer 141 in the third groove 11f is used as a sacrificial layer, which is conducive to simplifying the manufacturing process of the semiconductor device.

[0139] In some embodiments, the material of the conductive layer 141 includes at least one of a metal material and a non-metal conductive material. The metal material includes but is not limited to copper, tungsten, aluminum, etc. The non-metal conductive material includes but is not limited to titanium nitride.

[0140] In some embodiments, after filling the conductive layer 141 in the multiple second grooves 11e and the multiple third grooves 11f, and before removing the conductive layer 141 in the multiple third grooves 11f, the manufacturing method of the semiconductor device also includes: forming a protective layer 1233, the protective layer 1233 covers the conductive layer 141 in the multiple third grooves 11f.

[0141] In some embodiments of the present application, in the process of removing part of the conductive layer 141 in the second groove 11e, the protective layer 1233 protects the conductive layer 141 in the third groove 11f. The material of the protective layer 1233 includes but is not limited to silicon oxide, silicon nitride or silicon oxynitride. Specifically, the material of the protective layer 1233 includes silicon nitride.

[0142] In some embodiments, please refer to Fig.2I and Figure 2J As shown, after forming the protection layer 1233, forming a plurality of conductive shielding structures 142 arranged along the second direction y in the semiconductor layer 11 further includes: removing a portion of the conductive layer 141 in the plurality of second grooves 11e, and the remaining conductive layer 141 in the plurality of second grooves 11e constitutes a conductive shielding structure 142. The conductive shielding structure 142 includes a conductive shielding top surface 142b and a conductive shielding bottom surface 142a opposite to each other in the third direction z, and the conductive shielding bottom surface 142a contacts the bottom of the second groove 11e.

[0143] In some embodiments of the present application, a portion of the conductive layer 141 in the plurality of second grooves 11e is removed so that the conductive shielding top surfaces 142b of the plurality of conductive shielding structures 142 are flush or substantially flush. In this way, the size of the conductive shielding structure 142 in the third direction z is controllable, and can better play a shielding role.

[0144] In some embodiments, the conductive shield bottom surface 142a comprises a curved surface, and the conductive shield top surface 142b comprises a flat surface.

[0145] In some embodiments, please refer to Fig.2I and Figure 2J As shown, after forming a plurality of conductive shielding structures 142 arranged along the second direction y in the semiconductor layer 11, the method for manufacturing a semiconductor device further includes: forming a first insulating filling portion 1234 filling the second groove 11e on the conductive shielding structure 142 in the second groove 11e. The material of the first insulating filling portion 1234 includes but is not limited to at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0146] In some embodiments, please refer to Figure 2K , Figure 2L as well as Figure 2M As shown, the method for manufacturing a semiconductor device further includes: after forming the first insulating filling portion 1234 , removing the protection layer 1233 .

[0147] In some embodiments, please refer to Figure 2K , Figure 2L as well as Figure 2MAs shown, after removing the protective layer 1233, the manufacturing method of the semiconductor device also includes: removing the conductive layer 141 in the plurality of third grooves 11f; expanding the dimensions of the third grooves 11f along the third direction z and the second direction y to form a plurality of fourth grooves 11g, and the remaining columnar semiconductor structure 112 in the storage area 11c1 includes a plurality of channel structures 113.

[0148] In some embodiments of the present application, the third groove 11f is expanded to form a fourth groove 11g. The fourth groove 11g provides an accommodating space for forming a gate line 152 described below.

[0149] It should be noted that, while forming the fourth groove 11g, the remaining columnar semiconductor structure 112 includes a plurality of channel structures 113, and the plurality of channel structures 113 need to be connected to the bit line 181 described below. The plurality of channel structures 113 are arranged in an array along the first direction x and the second direction y, and extend along the third direction z. The plurality of channel structures 113 are located in the storage area 11c1.

[0150] In some embodiments, the method for manufacturing a semiconductor device further includes: the remaining columnar semiconductor structure 112 further includes a plurality of redundant channel structures 114 located in the peripheral region 11c2. The plurality of redundant channel structures 114 are used to improve the process yield of the plurality of channel structures 113, and the plurality of redundant channel structures 114 are not connected to the bit line 181. The plurality of redundant channel structures 114 are located in the peripheral region 11c2.

[0151] In some embodiments, in the first direction x, the plurality of redundant channel structures 114 are located on at least one side of the plurality of channel structures 113. Specifically, in the first direction x, the plurality of redundant channel structures 114 are located on one side of the plurality of channel structures 113.

[0152] In some other embodiments, the plurality of redundant channel structures 114 may also be located on both sides of the plurality of channel structures 113 in the first direction x. In some other embodiments, the plurality of redundant channel structures 113 may also be located on both sides of the plurality of redundant channel structures 114 in the first direction x.

[0153] Next, refer to FIG. 3A to FIG. 3D As shown, the above step S103 is performed: a gate line 152 extending along the first direction x is formed in the semiconductor layer 11 , and the gate line 152 is located between adjacent channel structures 113 .

[0154] In some embodiments, reference Figure 3A and Figure 3BAs shown, before forming the gate line 152 extending along the first direction x in the semiconductor layer 11, the method for manufacturing the semiconductor device further includes: forming an insulating pad 1235 at the bottom of the fourth groove 11g. The insulating pad 1235 includes an insulating pad top surface 1235a and an insulating pad bottom surface 1235b opposite to each other in the third direction z, and the insulating pad bottom surface 1235b contacts the groove wall of the fourth groove 11g.

[0155] In some embodiments of the present application, the insulating pad portion 1235 serves to isolate the gate line 152 from the semiconductor layer 11. The size of the insulating pad portion 1235 in the third direction z can be adjusted to adjust the size of the gate line 152 in the third direction z. The insulating pad top surface 1235a includes a plane, which is convenient for adjusting the size of the gate line 152 in the third direction z. The insulating pad bottom surface 1235b includes a curved surface. The material of the insulating pad portion 1235 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0156] In some embodiments, in the third direction z, the conductive shielding bottom surface 142a is located between the insulating pad top surface 1235a and the insulating pad bottom surface 1235b, so that the insulating pad top surface 1235a is located above the conductive shielding bottom surface 142a, which is beneficial for the gate voltage transmitted by the gate line 152 to affect the channel structure 113. The area covered by the conductive shielding structure 142 ensures that the conductive shielding structure 142 can better play a shielding role.

[0157] In some embodiments, please refer to Figure 3A and Figure 3B As shown, after forming the insulating pad 1235, the method for manufacturing a semiconductor device further includes: forming a gate insulating layer 1236 on the groove wall of the fourth groove 11g. The gate insulating layer 1236 serves to isolate the gate line 152 from the channel structure 113 and the redundant channel structure 114. The material of the gate insulating layer 1236 includes but is not limited to insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0158] In some embodiments, reference Figure 3C and Figure 3D As shown, forming the gate lines 152 extending along the first direction x in the semiconductor layer 11 includes: forming a plurality of gate lines 152 extending along the first direction x and arranged along the second direction y in a plurality of fourth grooves 11 g respectively.

[0159] Specifically, refer to FIG. 3A to FIG. 3DAs shown, a gate line 152 extending along a first direction x is formed in the semiconductor layer 11, including: forming an initial gate layer 151 covering the gate insulating layer 1236 and the insulating pad 1235 in the fourth groove 11g; and removing part of the initial gate layer 151, and the remaining initial gate layer 151 constitutes a plurality of gate lines 152.

[0160] In some embodiments, reference Figure 3A and Figure 3B As shown, the initial gate layer 151 includes a first initial conductive layer 1511 and a second initial conductive layer 1512. Part of the first initial conductive layer 1511 is located on the groove wall of the fourth groove 11g, and the second initial conductive layer 1512 covers the first initial conductive layer 1511. The fourth groove 11g formed by the initial gate layer 151 still has a gap, that is, the initial gate layer 151 does not fill the fourth groove 11g. The materials of the first initial conductive layer 1511 and the second initial conductive layer 1512 include at least one of a metal material and a non-metal material. The metal material includes but is not limited to copper, tungsten, aluminum, etc. The non-metal conductive material includes but is not limited to titanium nitride.

[0161] In some embodiments, removing part of the initial gate layer 151 includes: removing the initial gate layer 151 outside the fourth groove 11g and removing part of the initial gate layer 151 in the fourth groove 11g to form two disconnected gate lines 152 in each fourth groove 11g.

[0162] Reference Figure 3D As shown, the gate line 152 includes a gate line top surface 152a and a gate line bottom surface 152b opposite to each other in the third direction z. The gate line bottom surface 152b contacts the insulating pad top surface 1235a. The gate line top surface 152a and the gate line bottom surface 152b both include planes, so that the size of the gate line 152 in the third direction z is more controllable, and the uniformity of the size of the plurality of gate lines 152 is easier to control.

[0163] In some embodiments, the gate line top surface 152a is flush or substantially flush with the conductive shielding top surface 142b, or, in the third direction z, the gate line top surface 152a is located between the conductive shielding top surface 142b and the conductive shielding bottom surface 142a. With this design, the gate voltage transmitted by the gate line 152 acts on the channel structure 113 in the area covered by the conductive shielding structure 142, ensuring that the conductive shielding structure 142 can better play a shielding role.

[0164] In some embodiments, please refer to Figure 3C and Figure 3DAs shown, after forming a plurality of gate lines 152, the method for manufacturing a semiconductor device further includes: forming a second insulating filling portion 1237 covering the plurality of gate lines 152 and filling the fourth groove 11g. The material of the second insulating filling portion 1237 is the same as that of the first insulating filling portion 1234. The material of the second insulating filling portion 1237 includes but is not limited to at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0165] In some embodiments, please refer to Figure 3E and Figure 3F As shown, the manufacturing method of the semiconductor device also includes: doping the ends of the multiple channel structures 113 away from the second surface 11b to form multiple first electrodes 163; forming multiple connecting contacts 161 respectively connected to the multiple first electrodes 163; forming multiple capacitors 162 connected to the multiple connecting contacts 161; and forming a third isolation layer 1238 between the multiple capacitors 162.

[0166] In some embodiments, please refer to Figure 3E and Figure 3F As shown, the method for manufacturing a semiconductor device also includes: flipping the semiconductor layer 11 so that the second surface 11b of the semiconductor layer 11 faces upward and the first surface 11a faces downward, thinning the second surface 11b of the semiconductor layer 11 to expose the first dielectric layer 122, and forming a thinned third surface 11h.

[0167] In some embodiments, please refer to FIG. 4A to FIG. 4C As shown, before forming the shielding structure lead wire 172, the manufacturing method of the semiconductor device also includes: forming a second mask layer covering the third surface 11h; forming a second mask opening 132a on the second mask layer, and the remaining second mask layer forms a second mask pattern 132b, and the second mask opening 132a exposes the first dielectric layer 122 and the semiconductor layer 11 adjacent to the redundant channel structure 114.

[0168] Finally, please refer to FIG. 5A to FIG. 5E As shown, the above step S104 is performed to form a shielding structure lead-out wire 172 , at least a portion of which extends along the second direction y and is connected to at least two conductive shielding structures 142 .

[0169] In some embodiments, please refer to FIG. 5A to FIG. 5CAs shown, forming the shielding structure lead wire 172 includes: removing the portion of the first dielectric layer 122 adjacent to the redundant channel structure 114, forming a lead wire accommodating groove 171 overlapping the first dielectric layer 122, the lead wire accommodating groove 171 being sunken from the third surface 11h to the first surface 11a, the lead wire accommodating groove 171 exposing multiple conductive shielding structures 142, and at least a portion of the lead wire accommodating groove 171 extending along the second direction y.

[0170] It should be noted that in order to expose the multiple conductive shielding structures 142 , in addition to removing the first dielectric layer 122 adjacent to the redundant channel structure 114 , the first isolation layer 1231 covering the conductive shielding bottom surface 142 a of the conductive shielding structure 142 also needs to be removed.

[0171] In some embodiments, at least a portion of the lead wire accommodating groove 171 also extends along the second direction y, which is beneficial for one lead wire accommodating groove 171 to expose multiple conductive shielding structures 142. On the basis of at least a portion of the lead wire accommodating groove 171 extending along the second direction y, a portion of the lead wire accommodating groove 171 can also extend along the first direction x.

[0172] Specifically, the lead wire accommodating groove 171 includes two first lead wire accommodating grooves 1711 extending along the second direction y and a second lead wire accommodating groove 1712 extending along the first direction x. The second lead wire accommodating groove 1712 is located on one side of the two first lead wire accommodating grooves 1711 and is connected to the two first lead wire accommodating grooves 1711. The lead wire accommodating groove 171 is arranged around a plurality of redundant channel structures 114.

[0173] In some embodiments, please refer to Figure 5D and Figure 5E As shown, forming the shielding structure lead wire 172 also includes: forming a shielding structure lead wire 172 in the lead wire accommodating groove 171 to contact multiple conductive shielding structures 142, and the shielding structure lead wire 172 is adjacent to the redundant channel structure 114 in the first direction x and is arranged at intervals.

[0174] In some embodiments, at least a portion of the shielding structure lead-out wire 172 extends along the second direction y, so that one shielding structure lead-out wire 172 is connected to a plurality of conductive shielding structures 142 , thereby reducing the number of shielding structure lead-out wires 172 .

[0175] Specifically, the shielding structure lead wire 172 includes two first wire segments 1721 extending along the second direction y and a second wire segment 1722 extending along the first direction x, so as to reduce the impedance of the shielding structure lead wire 172. The first wire segment 1721 is connected to the second wire segment 1722 and contacts the plurality of conductive shielding structures 142. The first wire segment 1721 is located in the first lead wire receiving groove 1711. The second wire segment 1722 is located in the second lead wire receiving groove 1712.

[0176] In some embodiments, the shielding structure lead wire 172 includes a first shielding structure lead layer (not shown) and a second shielding structure lead layer (not shown). The first shielding structure lead layer contacts the groove wall of the lead wire receiving groove 171, and the second shielding structure lead layer covers the first shielding structure lead layer and fills the lead wire receiving groove 171. The material of the shielding structure lead wire 172 includes at least one of a metal material and a non-metallic conductive material. The metal material includes but is not limited to copper, tungsten, aluminum, etc. The non-metallic conductive material includes but is not limited to titanium nitride.

[0177] In some embodiments, reference Fig. 6A and Figure 6B As shown, after forming the shielding structure lead wire 172, the manufacturing method of the semiconductor device also includes removing the second mask pattern 132b; forming a third mask layer covering the third surface 11h and the shielding structure lead wire 172; forming a third mask opening on the third mask layer, and the remaining third mask layer constitutes a third mask pattern 133b, and the third mask opening exposes the first dielectric layer 122 and the semiconductor layer 11 adjacent to the channel structure 113.

[0178] In some embodiments, please refer to Fig. 6A and Figure 6B As shown, the manufacturing method of the semiconductor device also includes: doping one end of the plurality of channel pillars away from the first electrode 163 to form a second electrode 164; forming a plurality of bit lines 181 extending along the second direction y and arranged along the first direction x, and the plurality of bit lines 181 are respectively connected to one end of the plurality of channel structures 113 in the third direction z.

[0179] In some embodiments, forming a plurality of bit lines 181 extending along the second direction y and arranged along the first direction x includes: forming a bit line accommodating groove 182, the bit line accommodating groove 182 being recessed from the third surface 11h to the first surface 11a, the bit line accommodating groove 182 extending along the second direction y and overlapping with the plurality of channel structures 113; and forming a plurality of bit lines 181 in the bit line accommodating groove 182, the plurality of bit lines 181 being connected to one end of the plurality of channel structures 113 and being disconnected from the plurality of redundant channel structures 114.

[0180] In some embodiments, forming the bit line receiving groove 182 includes removing the semiconductor layer 11 on the third surface 11 h overlapping the channel structure 113 .

[0181] In some embodiments, reference Fig. 7A and Figure 7C As shown, the method for manufacturing a semiconductor device further includes: forming a plurality of bit line lead contacts 191 , wherein the plurality of bit line lead contacts 191 are respectively connected to the plurality of bit lines 181 .

[0182] In some embodiments, reference Fig. 7A As shown, the manufacturing method of the semiconductor device also includes: forming a shielding structure lead-out contact 192 connected to the shielding structure lead-out wire 172, the shielding structure lead-out contact 192 and the bit line lead-out contact 191 are located on the same side of the multiple channel structures 113 in the third direction z, and the shielding structure lead-out contact 192 is located on at least one side of the bit line 181 in the second direction y.

[0183] In some embodiments, reference Fig. 7A and Figure 7B As shown, a plurality of gate line lead contacts 193 are formed. The plurality of gate line lead contacts 193 are located on both sides of the bit line 181 in the first direction x and are respectively connected to the plurality of gate lines 152 .

[0184] In some embodiments, the gate line lead-out contact 193 , the bit line lead-out contact 191 , and the shielding structure lead-out contact 192 are formed simultaneously to simplify the manufacturing process of the semiconductor device.

[0185] In other embodiments, please refer to Fig. 8A , Figure 8B as well as Figure 8C As shown, forming the shielding structure lead-out wire 172 includes: removing the portion of the semiconductor layer 11 adjacent to the redundant channel structure 114, forming a lead-out wire accommodating groove 171 overlapping the redundant channel structure 114, the lead-out wire accommodating groove 171 being sunken from the third surface 11h to the first surface 11a, the lead-out wire accommodating groove 171 exposing a plurality of conductive shielding structures 142, and at least a portion of the lead-out wire accommodating groove 171 extending along the second direction y.

[0186] It should be noted that, as mentioned above, in order to expose the multiple conductive shielding structures 142 , in addition to removing the first dielectric layer 122 adjacent to the redundant channel structure 114 , the first isolation layer 1231 covering the conductive shielding bottom surface 142 a of the conductive shielding structure 142 also needs to be removed.

[0187] Specifically, the lead wire receiving groove 171 contacts a row of redundant channel structures 114 arranged along the second direction y.

[0188] In other embodiments, please refer to Fig.8D and Fig. 8E As shown, forming the shielding structure lead wire 172 further includes: forming the shielding structure lead wire 172 in the lead wire receiving groove 171 to contact the plurality of conductive shielding structures 142 , and the shielding structure lead wire 172 contacts the redundant channel structure 114 .

[0189] In some other embodiments, portions of the first dielectric layer 122 and the semiconductor layer 11 adjacent to the redundant channel structure 114 can be removed to form a lead wire accommodating groove 171 overlapping the redundant channel structure 114 and the first dielectric layer 122, the lead wire accommodating groove 171 being recessed from the third surface 11h toward the first surface 11a, the lead wire accommodating groove 171 exposing a plurality of conductive shielding structures 142, and at least a portion of the lead wire accommodating groove 171 extending along the second direction y.

[0190] The present application also provides a semiconductor device obtained by the manufacturing method of the semiconductor device. 7A to 7D as well as Fig.8D and Fig. 8E Semiconductor devices according to some embodiments of the present application are described in detail.

[0191] Reference 7A to 7D as well as Fig.8D and Fig. 8E As shown, the semiconductor device 100 includes multiple channel structures 113, multiple conductive shielding structures 142, multiple gate lines 152, shielding structure lead wires 172, multiple bit lines 181, capacitors 162, multiple bit line lead contacts 191, shielding structure lead contacts 192, redundant channel structures 114 and multiple gate line lead contacts 193.

[0192] Reference Figure 7B As shown, a plurality of channel structures 113 are arranged in an array along a first direction x and a second direction y, and extend along a third direction z. The first direction x intersects with the second direction y, and the third direction z intersects with the first direction x and the second direction y. Specifically, any two of the first direction x, the second direction y, and the third direction z are perpendicular to each other, but are not limited thereto.

[0193] Reference Figure 7C As shown, the channel structure 113 is in contact with the first electrode 163 and the second electrode 164 at opposite ends in the third direction z, respectively. One of the first electrode 163 and the second electrode 164 is a source, and the other of the first electrode 163 and the second electrode 164 is a drain. One end of the channel structure 113 is connected to the bit line 181 through the second electrode 164. The first electrode 163 is connected to the capacitor 162 through the connection contact 161, so that the other end of the channel structure 113 in the third direction z is connected to the capacitor 162 through the first electrode 163.

[0194] Reference Figure 7B As shown, in some embodiments, in the first direction x, the plurality of redundant channel structures 114 are located on at least one side of the plurality of channel structures 113. The redundant channel structures 114 extend along the third direction z and are disconnected from the plurality of bit lines 181. Specifically, in the first direction x, the plurality of redundant channel structures 114 are located on both sides of the plurality of channel structures 113. In other embodiments, in the first direction x, the plurality of channel structures 113 may also be located on both sides of the plurality of redundant channel structures 114.

[0195] Reference Figure 7B and Figure 7C As shown, a plurality of conductive shielding structures 142 extend along the first direction x and the third direction z, and are arranged at intervals along the second direction y. In the second direction y, the conductive shielding structure 142 is located between two adjacent rows of channel structures 113 to shield the coupling effect between two adjacent channel structures 113 in the second direction y. Parts of the plurality of conductive shielding structures 142 are also located between adjacent redundant channel structures 114 in the second direction y. A first isolation layer 1231 is provided between the conductive shielding structure 142 and the sidewall of the redundant channel structure 114. A first isolation layer 1231 is also provided between the conductive shielding structure 142 and the sidewall of the channel structure 113.

[0196] The conductive shielding structure 142 includes a conductive shielding top surface 142b and a conductive shielding bottom surface 142a which are opposite to each other in the third direction z. The conductive shielding top surface 142b is arranged near the first electrode 163, and the conductive shielding bottom surface 142a is arranged near the second electrode 164. The conductive shielding bottom surface 142a includes a curved surface, and the conductive shielding top surface 142b includes a flat surface. The conductive shielding top surface 142b contacts the first insulating filling portion 1234. The first insulating filling portion 1234 protects the conductive shielding structure 142.

[0197] Reference Figure 7B As shown, a plurality of gate lines 152 extend along the first direction x and the third direction z, and are arranged along the second direction y. In the second direction y, each gate line 152 is located between two adjacent rows of channel structures 113. In the second direction y, a portion of each gate line 152 is also located between two adjacent redundant channel structures 114. In the second direction y, two disconnected gate lines 152 are arranged between two adjacent conductive shielding structures 142.

[0198] Reference Figure 7CAs shown, the gate line 152 includes a gate line top surface 152a and a gate line bottom surface 152b opposite to each other in the third direction z, the gate line top surface 152a is arranged close to the first electrode 163, and the gate line bottom surface 152b is arranged close to the second electrode 164. The gate line top surface 152a and the gate line bottom surface 152b both include planes, so that the size of the gate line 152 in the third direction z is more controllable, and the uniformity of the size of the plurality of gate lines 152 is easier to control.

[0199] The gate line bottom surface 152b contacts the insulating pad portion 1235, and the gate line top surface 152a of the gate line 152 contacts the second insulating filling portion 1237. The insulating pad portion 1235 includes an insulating pad top surface 1235a and an insulating pad bottom surface 1235b opposite to each other in the third direction z, and the insulating pad top surface 1235a contacts the gate line bottom surface 152b.

[0200] In some embodiments, in the third direction z, the conductive shielding bottom surface 142a is located between the insulating pad top surface 1235a and the insulating pad bottom surface 1235b, so that the insulating pad top surface 1235a is located above the insulating pad top surface 1235a, which is beneficial for the gate voltage transmitted by the gate line 152 to affect the channel structure 113. The area covered by the conductive shielding structure 142 ensures that the conductive shielding structure 142 can better play a shielding role.

[0201] In some embodiments, the gate line top surface 152a is flush or substantially flush with the conductive shielding top surface 142b, or, in the third direction z, the gate line top surface 152a is located between the conductive shielding top surface 142b and the conductive shielding bottom surface 142a. With this design, the gate voltage transmitted by the gate line 152 acts on the channel structure 113 in the area covered by the conductive shielding structure 142, ensuring that the conductive shielding structure 142 can better play a shielding role.

[0202] Reference Fig. 7A and Fig.8D As shown, at least part of the shielding structure lead wire 172 extends along the second direction y and is connected to at least two conductive shielding structures 142. With this design, the extension direction of at least part of the shielding structure lead wire 172 intersects with the extension direction of the gate line 152. When the shielding structure lead contact 192 is used to lead out the shielding structure lead wire 172, the process window of the shielding structure lead contact 192 will not be limited by the spacing between adjacent gate lines 152 in the second direction y, which can reduce the manufacturing difficulty of the semiconductor device. Moreover, a plurality of conductive shielding structures 142 are arranged at intervals along the second direction y, and a shielding structure lead wire 172 is connected to at least two conductive shielding structures 142. With this design, the number of shielding structure lead wires 172 in the semiconductor device is small, further reducing the manufacturing difficulty of the semiconductor device.

[0203] In some embodiments, the shielding structure lead wire 172 and the plurality of bit lines 181 are located on the same side of the channel structure 113 in the third direction z, and the shielding structure lead wire 172 is located on at least one side of the bit line 181 in the first direction x. Meanwhile, in the third direction z, the capacitor 162 and the shielding structure lead wire 172 are located on both sides of the channel structure 113.

[0204] In some other embodiments, the shielding structure lead wire 172 and the capacitor 162 may also be located on the same side of the channel structure 113. Meanwhile, in the third direction z, the bit line 181 and the shielding structure lead wire 172 are located on both sides of the channel structure 113.

[0205] In some embodiments, the shielding structure lead-out conductor 172 is arranged adjacent to the redundant channel structure 114, so that the shielding structure lead-out conductor 172 is arranged in the area where the redundant channel structure 114 is arranged, thereby improving the area where the shielding structure lead-out conductor 172 is arranged where the bit line 181 is located, thereby reducing the layout area of ​​the bit line 181.

[0206] In other embodiments, reference Fig. 7A As shown, in the first direction x, the shielding structure lead-out conductive line 172 is disposed spaced apart from the redundant channel structure 114. Therefore, the shielding structure lead-out conductive line 172 is disposed in a region adjacent to and spaced apart from the redundant channel structure 114.

[0207] In other embodiments, reference Fig.8D and Fig. 8E As shown, the shielding structure lead-out conductive line 172 contacts the redundant channel structure 114. Therefore, in the third direction z, the shielding structure lead-out conductive line 172 is disposed in a region overlapping with the redundant channel structure 114.

[0208] In some embodiments, reference Fig. 7A and Fig.7D As shown, the shielding structure lead wire 172 includes a first wire segment 1721 extending along the second direction y and a second wire segment 1722 extending along the first direction x. The first wire segment 1721 is connected to the second wire segment 1722 and contacts the plurality of conductive shielding structures 142 .

[0209] Specifically, the shielding structure lead wire 172 includes two first wire segments 1721 extending along the second direction y and a second wire segment 1722 extending along the first direction x. The first wire segment 1721 is connected to the second wire segment 1722 and contacts the plurality of conductive shielding structures 142 .

[0210] In other embodiments, reference Fig.8DAs shown, the shielding structure lead-out wire 172 is in a straight line shape, and the shielding structure lead-out wire 172 extends along the second direction y.

[0211] Reference Fig. 7A and Figure 7C As shown, the plurality of bit lines 181 extend along the second direction y and are arranged along the first direction x, and are respectively connected to one end of the plurality of channel structures 113 in the third direction z. In the first direction x, the shielding structure lead wire 172 is located on at least one side of the plurality of bit lines 181. Specifically, in the first direction x, one shielding structure lead wire 172 is located on one side of the plurality of bit lines 181.

[0212] Reference Fig. 7A As shown, a plurality of bit line lead contacts 191 are respectively connected to a plurality of bit lines 181. A shielding structure lead contact 192 is connected to a shielding structure lead conductor 172. In the third direction z, the shielding structure lead contact 192 and the bit line lead contact 191 are located on the same side of the channel structure 113, and in the second direction y, are located on at least one side of the bit line 181. In the second direction y, a plurality of bit line lead contacts 191 and the shielding structure lead contact 192 are respectively located on both sides of the gate line 152.

[0213] It should be noted that the shielding structure leads out the contact 192 to load the ground potential or the fixed voltage, and transmits the ground potential and the fixed voltage to the conductive shielding structure 142, which can improve the coupling effect of the gate line transmitting the gate voltage on the adjacent channel structures.

[0214] Reference Fig. 7A and Figure 7B As shown, a plurality of gate line lead contacts 193 are located on both sides of the bit line 181 in the first direction x, and are respectively connected to a plurality of gate lines 152 .

[0215] In some embodiments, multiple bit line lead contacts 191, multiple gate line lead contacts 193, and shield structure lead contacts 192 all penetrate the fourth isolation layer 1239, and the fourth isolation layer 1239 covers multiple bit lines 181 and shield structure lead wires 172. With this design, multiple bit line lead contacts 191, multiple gate line lead contacts 193, and shield structure lead contacts 192 are formed simultaneously, reducing the number of masks required for manufacturing semiconductor devices and simplifying the manufacturing process of semiconductor devices.

[0216] In addition, see Fig. 9 and Fig.10 As shown, based on the same inventive concept, the present application further provides a storage system 400, which includes a memory 200 and a controller 300. The controller 300 is connected to the memory 200 and is used to control the memory 200. The memory 200 includes the semiconductor device 100 of any of the above embodiments.

[0217] Among them, the storage system 400 can be applied to and packaged into different types of electronic products, such as mobile phones (such as mobile phones), desktop computers, tablet computers, laptops, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0218] In some embodiments, reference Fig. 9 As shown, the storage system 400 includes a memory 200 and a controller 300. The storage system 400 may be integrated into a three-dimensional memory card.

[0219] Among them, the three-dimensional memory card includes any one of PC card (PCMCIA, Personal Computer Three-Dimensional Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, three-dimensional memory, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0220] In other embodiments, reference Fig.10 As shown, the storage system 400 includes a plurality of memories 200 and a controller 300. The storage system 400 is integrated into a solid state drive (SSD).

[0221] In some embodiments, in the storage system 400, the controller 300 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0222] In other embodiments, in the storage system 400, the controller 300 is configured to operate in a high duty cycle environment SSD or eMMC, which is used for data storage in mobile devices such as smart phones, tablets, laptops, and enterprise storage arrays.

[0223] In some embodiments, the controller 300 may be configured to manage data stored in the memory 200 and communicate with an external device (e.g., a host). In some embodiments, the controller 300 may also be configured to control operations of the memory 200, such as read, erase, and program operations. In some embodiments, the controller 300 may also be configured to manage various functions regarding data stored or to be stored in the memory 200, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 300 is also configured to process error correction codes for data read from or written to the memory 200.

[0224] Of course, the controller 300 may also perform any other suitable functions, such as formatting the memory 200; for example, the controller 300 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0225] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0226] Please refer to Fig.11 Some embodiments of the present application further provide an electronic device 500. The electronic device 500 may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0227] The electronic device 500 may include the above-mentioned storage system 400 and a host 600 , and the host 600 includes at least one of a central processing unit (CPU) and a cache.

[0228] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: A plurality of channel structures are arranged in an array along a first direction and a second direction and extend along a third direction, wherein the first direction intersects with the second direction, and the third direction intersects with the first direction and the second direction; A plurality of conductive shielding structures are arranged along the second direction, wherein the conductive shielding structures are located between adjacent channel structures in the second direction; a gate line extending along the first direction and the third direction, wherein the gate line is located between adjacent channel structures; as well as The shielding structure leads out a conductive line, at least a portion of which extends along the second direction and is connected to at least two of the conductive shielding structures.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: a plurality of bit lines extending along the second direction and arranged along the first direction and respectively connected to one end of the plurality of channel structures in the third direction; A plurality of bit line lead contacts, respectively connected to the plurality of bit lines; and The shielding structure lead-out contact is connected to the shielding structure lead-out wire, is located on the same side of the channel structure as the bit line lead-out contact in the third direction, and is located on at least one side of the bit line in the second direction.

3. The semiconductor device according to claim 2, characterized in that In the third direction, the plurality of bit lines and the shielding structure lead-out conductive line are located on the same side of the channel structure, and in the first direction, the shielding structure lead-out conductive line is located on at least one side of the bit line.

4. The semiconductor device according to claim 2, characterized in that The semiconductor device further comprises: a redundant channel structure extending along the third direction and disconnected from the plurality of bit lines; and the shielding structure lead wire is arranged adjacent to the redundant channel structure.

5. The semiconductor device according to claim 4, characterized in that In the first direction, the shielding structure lead wire is spaced apart from the redundant channel structure.

6. The semiconductor device according to claim 4 or 5, characterized in that: The shielding structure leads out a conductive line which contacts the redundant channel structure.

7. The semiconductor device according to claim 2, characterized in that The semiconductor device further comprises: a plurality of gate line lead contacts, located on both sides of the bit line in the first direction and respectively connected to the plurality of gate lines; Wherein, in the second direction, a plurality of bit line lead-out contacts and the shielding structure lead-out contacts are respectively located on both sides of the gate line.

8. The semiconductor device according to claim 1, wherein: The semiconductor device further includes: a capacitor connected to the other end of the channel structure in the third direction; Wherein, in the third direction, the capacitor and the shielding structure lead wires are located on both sides of the channel structure.

9. The semiconductor device according to claim 1, wherein: The shielding structure leads out a conductive wire extending along the second direction; or, The shielding structure lead wire includes a first wire segment extending along the second direction and a second wire segment extending along the first direction, wherein the first wire segment is connected to the second wire segment and contacts a plurality of conductive shielding structures.

10. A method for manufacturing a semiconductor device, characterized in that: include: A groove is formed in the semiconductor layer, the groove is sunken from the first surface of the semiconductor layer to the second surface, the remaining semiconductor layer includes a plurality of channel structures arranged in an array along the first direction and the second direction and extending along the third direction, the first surface and the second surface are arranged opposite to each other in the third direction, the first direction intersects with the second direction, and the third direction intersects with the first direction and the second direction; forming a plurality of conductive shielding structures arranged along the second direction in the semiconductor layer, wherein the conductive shielding structures are located between adjacent channel structures in the second direction; forming a gate line extending along the first direction and the third direction in the semiconductor layer, wherein the gate line is located between adjacent channel structures; as well as A shielding structure lead-out wire is formed, at least a portion of which extends along the second direction and is connected to at least two of the conductive shielding structures.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that: The method further includes: forming a plurality of bit lines extending along the second direction and arranged along the first direction, wherein the plurality of bit lines are respectively connected to one end of the plurality of channel structures in the third direction; forming a plurality of bit line extraction contacts respectively connected to the plurality of bit lines; and A shielding structure lead contact connected to the shielding structure lead wire is formed, the shielding structure lead contact and the bit line lead contact are located on the same side of the plurality of channel structures in the third direction, and the shielding structure lead contact is located on at least one side of the bit line in the second direction.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that: The forming of a plurality of bit lines extending along the second direction and arranged along the first direction includes: in the third direction, the plurality of bit lines and the shielding structure lead wires are located on the same side of the plurality of channel structures, and in the first direction, the shielding structure lead wires are located on at least one side of the bit lines.

13. The method for manufacturing a semiconductor device according to claim 11, characterized in that: The method further comprises: causing the remaining semiconductor layer to further comprise a redundant channel structure extending along the third direction; The forming of a plurality of bit lines extending along the second direction and arranged along the first direction comprises: forming a plurality of the bit lines disconnected from the redundant channel structure; The forming of the shielding structure lead-out conductor includes: forming the shielding structure lead-out conductor disposed adjacent to the redundant channel structure.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that: The method further comprises: filling a dielectric layer in the groove; Thinning the second surface of the semiconductor layer to expose the dielectric layer and form a thinned third surface; and Removing a portion of the dielectric layer and / or a portion of the semiconductor layer adjacent to the redundant channel structure to form a lead wire accommodating groove, wherein the lead wire accommodating groove exposes a plurality of the conductive shielding structures, and at least a portion of the lead wire accommodating groove extends along the third direction, and the lead wire accommodating groove is sunken from the third surface to the first surface; The forming of the shielding structure lead wire comprises: forming a shielding structure lead wire in the lead wire receiving groove so as to contact with a plurality of the conductive shielding structures.

15. The method for manufacturing a semiconductor device according to claim 13, characterized in that: The forming a groove in the semiconductor layer comprises: forming a first groove extending along the second direction and the third direction in the semiconductor layer, and the remaining semiconductor layer includes a semiconductor line; Forming a plurality of second grooves and a plurality of third grooves in the semiconductor layer, the grooves extending along the third direction and the first direction and arranged along the second direction, wherein the second grooves and the third grooves intersect the semiconductor line, and the size of the second grooves along the first direction is smaller than the size of the third grooves along the first direction; The forming of a plurality of conductive shielding structures arranged along the second direction in the semiconductor layer comprises: filling a conductive layer in a plurality of the second grooves and a plurality of the third grooves; and The conductive layer in the plurality of the third grooves is removed, and at least a portion of the conductive layer remaining in the plurality of the second grooves forms a plurality of the conductive shielding structures.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that: The method further includes: expanding the dimensions of the third groove along the third direction and the second direction to form a plurality of fourth grooves; The forming of the gate lines extending along the first direction in the semiconductor layer comprises: forming a plurality of the gate lines extending along the first direction and arranged along the second direction in a plurality of the fourth grooves respectively; The method further includes: forming a plurality of gate line lead-out contacts, wherein the plurality of gate line lead-out contacts are located on both sides of the bit line in the first direction and are respectively connected to the plurality of gate lines.

17. The method for manufacturing a semiconductor device according to claim 10, characterized in that: The method further includes: forming a capacitor connected to the other end of the plurality of channel structures in the third direction; The forming of the shielding structure lead-out wire comprises: forming the shielding structure lead-out wire on a side of the channel structure away from the capacitor in the third direction.

18. The method for manufacturing a semiconductor device according to claim 10, characterized in that: The forming of the shielding structure lead wire comprises: forming the shielding structure lead wire extending along the second direction and contacting with a plurality of the conductive shielding structures; or, The forming of the shielding structure lead wire includes: making the shielding structure lead wire include a first wire segment extending along the second direction and a second wire segment extending along the first direction, wherein the first wire segment is connected to the second wire segment and contacts the plurality of the conductive shielding structures.

19. A storage system, characterized in that: The storage system comprises: A memory, comprising the semiconductor device according to any one of claims 1 to 9; and The controller is connected to the memory and is used to control the memory.

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