Semiconductor device and preparation method thereof, and storage system

Abstract

The invention provides a semiconductor device and a preparation method thereof, and a storage system, the semiconductor device comprises a plurality of semiconductor columns arranged along a first direction and a second direction, each semiconductor column comprises a first end in a third direction and a bit line located at the first end of the semiconductor column, and the bit lines extend along the second direction and are connected with the semiconductor columns. The protection layer at least covers the side walls of the two sides of the bit line in the first direction, and the plane shared by the first direction and the second direction intersects with the third direction; according to the semiconductor device, the preparation method thereof and the storage system provided by the invention, the bit line is protected in the manufacturing process of the semiconductor device through the arrangement of the protection layer, the protection effect on the bit line in the formation of the semiconductor device is improved, and the device performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a semiconductor device and a manufacturing method thereof, and a storage system. Background Art

[0002] With the widespread application of 3D DRAM (Dynamic Random Access Memory) technology, the performance requirements of semiconductor devices used in 3D DRAM are constantly increasing, and the difficulty of the manufacturing process is increasing accordingly. The manufacturing yield and product performance of semiconductor devices need to be improved.

[0003] Therefore, there is an urgent need for a semiconductor device and a manufacturing method thereof, and a storage system to solve the above technical problems. Summary of the invention

[0004] In view of this, the present application provides a semiconductor device and a manufacturing method and a storage system thereof, which are capable of protecting a bit line during the preparation of the semiconductor device and thus improving the device performance of the semiconductor device.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] The present application provides a method for preparing a semiconductor device, comprising:

[0007] forming a plurality of pre-semiconductor pillars arranged along a first direction and a second direction and a first insulating material layer filled between two adjacent pre-semiconductor pillars in the first direction;

[0008] Removing a portion of the first insulating material layer to form a first groove, wherein the first groove is located between the pre-semiconductor pillars and close to a first end of the pre-semiconductor pillar in a third direction, the first groove extends along the second direction, and a plane common to the first direction and the second direction intersects the third direction;

[0009] forming a bit line at the first end of the pre-semiconductor column, and forming a semiconductor column at the other part of the pre-semiconductor column;

[0010] A second insulating layer is formed to cover at least the sidewall of the bit line along the first direction, wherein the material of the second insulating layer is different from that of the first insulating material layer.

[0011] In some embodiments, after the step of “forming a second insulating layer that at least covers the sidewalls of the bit line along the first direction”, the method further includes:

[0012] forming a third insulating layer covering the second insulating layer on a side of the second insulating layer away from the bit line in the third direction;

[0013] Wherein, a material of the third insulating layer is different from a material of the second insulating layer.

[0014] In some embodiments, the step of forming the third insulating layer further includes:

[0015] An air gap is formed in the first groove.

[0016] In some embodiments, after the step of “forming a second insulating layer that at least covers the sidewalls of the bit line along the first direction”, the method further includes:

[0017] The second insulating layer is patterned to expose the bottom of the first groove.

[0018] In some embodiments, after patterning the second insulating layer, the method further includes:

[0019] A second groove is formed in the first insulating material layer, and the first groove is connected to the second groove.

[0020] In some embodiments, after the second groove is formed, the method further includes:

[0021] An air gap is formed in the second groove.

[0022] In some embodiments, the step of “forming a bit line at the first end of the pre-semiconductor column and forming a semiconductor column at the other portion of the pre-semiconductor column” includes:

[0023] Metallization is performed on the first end of the pre-semiconductor column to form the bit line and semiconductor columns located at other portions of the pre-semiconductor column.

[0024] The present application also provides a semiconductor device, comprising:

[0025] A plurality of semiconductor columns arranged along a first direction and a second direction, wherein the semiconductor columns include a first end in a third direction, and a plane common to the first direction and the second direction intersects the third direction;

[0026] A bit line, located at the first end of the semiconductor column, extending along the second direction and connected to the semiconductor column;

[0027] The protection layer at least covers the side walls of the bit line on both sides in the first direction.

[0028] In some embodiments, the semiconductor device further comprises:

[0029] A first insulating layer, located between two adjacent semiconductor pillars along the first direction;

[0030] Wherein, the material of the protection layer is different from that of the first insulating layer.

[0031] In some embodiments, the semiconductor device further comprises:

[0032] A covering layer covers the protection layer, wherein the covering layer includes an air gap, and the air gap is located between two adjacent bit lines.

[0033] In some embodiments, the protection layer includes a first subsegment extending along the third direction, and the first subsegment covers a portion of the semiconductor pillar and sidewalls of the bit line on both sides in the first direction.

[0034] In some embodiments, the air gap is farther away from one end of the bit line in the third direction than one end of the protection layer in the third direction farther away from the bit line.

[0035] In some embodiments, the protective layer also includes a second sub-segment and a third sub-segment connected to the first sub-segment, the second sub-segment and the third sub-segment extend along the first direction respectively, the second sub-segment covers an end of the first insulating layer close to the protective layer in the third direction, and the third sub-segment covers an end of the bit line away from the semiconductor column in the third direction.

[0036] In some embodiments, the air gap is farther from one end of the bit line in the third direction, and is closer to the bit line than the end of the protection layer is farther from the bit line in the third direction.

[0037] In some embodiments, the bit line includes a metal silicide layer.

[0038] The present application also provides a storage system, the storage system comprising a memory and a controller, the controller being coupled to the memory and configured to control the memory to store data;

[0039] Wherein, the memory includes any of the semiconductor devices described above.

[0040] The semiconductor device and its preparation method and storage system provided in the present application protect the bit line during the manufacturing process of the semiconductor device by setting a protective layer, thereby improving the protection effect of the bit line during the formation of the semiconductor device and improving the device performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in some embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figures 1A to 1H is a flowchart of steps of a method for preparing a semiconductor device in some embodiments;

[0043] Figure 2 This is a first step flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0044] 3A to 3H It is a structural schematic diagram corresponding to each process in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0045] Figure 4 is a second step flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0046] Figure 5 yes Figure 4 A step flow chart of step S500 in the step flow chart provided;

[0047] Figure 6 yes Figure 5 A step flow chart of step S510 in the step flow chart provided;

[0048] Figure 7 is a flowchart of the third step of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0049] Figure 8 yes Figure 7 A step flow chart of step S500 in the step flow chart provided;

[0050] Fig. 9 yes Figure 8 A step flow chart of step S520 in the step flow chart provided;

[0051] Fig.10 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0052] Fig.11 yes Fig.10 A first cross-sectional view of the semiconductor device along the AA' section;

[0053] Fig.12 yes Fig.10 A second cross-sectional view of the semiconductor device along the AA' section;

[0054] Fig.13 It is a schematic diagram of the structure of the storage system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in some embodiments of the present application to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0056] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0057] The present application may repeat reference numerals and / or reference letters in different embodiments. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0058] like Figures 1A to 1H As shown, in some embodiments of the semiconductor device preparation method, a plurality of pre-semiconductor pillars 112' are arranged along a first direction X' and a second direction Y', a protective layer 103' is first formed at the first end of the pre-semiconductor pillar 112' in the third direction Z', and then a bit line 102' is formed. To ensure that the bit line 102' can be formed at the first end of the pre-semiconductor pillar 112' in the third direction Z', a portion of the second insulating layer 115' located at the first end of the pre-semiconductor pillar 112' and a portion located at the side wall of the pre-semiconductor pillar 112' are removed during the process of forming the protective layer 103', the side wall portion of the bit line 102' in the first direction X' is exposed, and a covering layer 107' is formed to cover the protective layer 103', the covering layer 107' has an air gap between two adjacent bit lines 102', thereby reducing the coupling between the two adjacent bit lines 102'.

[0059] See also Figure 2 , an embodiment of the present application provides a method for preparing a semiconductor device, comprising:

[0060] Step S100 : forming a plurality of pre-semiconductor pillars 112 arranged along a first direction X and a second direction Y and forming a first insulating material layer 113 filled between two adjacent pre-semiconductor pillars 112 in the first direction X.

[0061] Step S200: remove part of the first insulating material layer 113 to form a first groove 114, wherein the first groove 114 is located between the pre-semiconductor columns 112 and close to the first end of the pre-semiconductor column 112 in the third direction Z, and the first groove 114 extends along the second direction Y, and a plane shared by the first direction X and the second direction Y intersects with the third direction Z.

[0062] Step S300 : forming a bit line 102 at the first end of the pre-semiconductor column 112 , and forming a semiconductor column 101 at the other portion of the pre-semiconductor column 112 .

[0063] Step S400 : forming a second insulating layer 115 that at least covers the bit line 102 along the first direction X, wherein the material of the second insulating layer 115 is different from that of the first insulating material layer 113 .

[0064] In some embodiments, see Figure 3A The plurality of pre-semiconductor pillars 112 arranged along the first direction X and the second direction Y are arranged in an array on a plane shared by the first direction X and the second direction Y. Each of the pre-semiconductor pillars 112 extends along a third direction Z. The plane shared by the first direction X and the second direction Y intersects with the third direction Z.

[0065] In some embodiments, the first direction X, the second direction Y and the third direction Z are perpendicular to each other. It can be understood that the vertical in the present application refers to vertical within a certain angle error range, for example, 85° to 95° can be interpreted as vertical.

[0066] In some embodiments, the first insulating material layer 113 can be formed by filling between two adjacent pre-semiconductor pillars 112 in the first direction X through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0067] In some embodiments, the material of the first insulating material layer 113 may be selected from at least one of silicon oxide, silicon nitride, and doped silicon oxide. For example, the material of the first insulating material layer 113 may be selected from silicon oxide.

[0068] In some embodiments, the first groove 114 may be formed by dry etching. For example, the first groove 114 may be formed by plasma bombarding the first insulating material layer 113 .

[0069] In some embodiments, see Figure 3B The first groove 114 exposes the sidewall of the first end of the pre-semiconductor column 112 in the first direction X, so that a bit line is formed at the first end of the pre-semiconductor column 112 in a subsequent process.

[0070] In some embodiments, see Figure 3B The pre-semiconductor column 112 includes a first portion 112 a located at the first end, and the first portion 112 a of the pre-semiconductor column 112 has a first height H1 in the third direction Z. The pre-semiconductor column 112 also includes a second portion 112 b, and the second portion 112 b of the pre-semiconductor column 112 is located in the third direction Z on a side of the first portion of the pre-semiconductor column 112 away from the first groove 114.

[0071] In some embodiments, the material of the pre-semiconductor column 112 may include semiconductor materials such as single crystal silicon, polycrystalline silicon, amorphous silicon, etc. The first portion 112a of the pre-semiconductor column 112 may be formed by doping the semiconductor material with P-type doping ions or N-type doping ions by ion implantation or the like, the P-type doping ions may include boron, aluminum, gallium, etc., and the N-type doping ions may include phosphorus, arsenic, antimony, etc.

[0072] In some embodiments, see Figure 3B The first groove 114 has a first depth D1 in the third direction Z, and the first height H1 is greater than or equal to the first depth D1.

[0073] In some embodiments, see Figure 3C , step S300 includes:

[0074] Step S310 : performing metallization on the first end of the pre-semiconductor pillar 112 to form the bit line 102 and the semiconductor pillar 101 located at other portions of the pre-semiconductor pillar 112 .

[0075] In some embodiments, step S310 may include:

[0076] Step S311 : forming a first metal material layer covering the first end of the pre-semiconductor pillar 112 and the first groove 114 .

[0077] The material of the first metal material layer may include at least one of nickel, cobalt, and titanium. For example, the material of the first metal material layer may be nickel.

[0078] In some embodiments, the first metal material layer may be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0079] Step S312 : performing heat treatment on the first end of the pre-semiconductor column 112 and the first metal material layer to form the bit line 102 , and the other part of the pre-semiconductor column 112 forms the semiconductor column 101 .

[0080] In some embodiments, the heat treatment may be an annealing treatment, and by controlling the temperature of the annealing treatment, the metal atoms of the first metal material layer react only with the material of the first portion of the first end of the pre-semiconductor column 112 to form the bit line 102, and the other portion of the pre-semiconductor column 112 forms the semiconductor column 101. Figure 3B and Figure 3C , the bit line 102 has a second height H2 in the third direction Z, the first height H1 is greater than the second height H2, after the bit line 102 is formed, the remaining height of the first portion 112a of the pre-semiconductor column 112 in the third direction Z is the difference between the first height H1 and the second height H2, the remaining portion of the first portion 112a of the pre-semiconductor column 112 after the bit line 102 is formed can become the first portion 101a of the semiconductor column 101, and the first portion 101a of the semiconductor column 101 can be the source or drain of the transistor in the semiconductor device. The second portion 112b of the pre-semiconductor column 112 can become the second portion 101b of the semiconductor column 101, and the second portion 101b of the semiconductor column 101 can be the channel of the transistor in the semiconductor device.

[0081] In some embodiments, the bit line 102 may be formed by one annealing process or by multiple annealing processes. When the bit line 102 is formed by multiple annealing processes, taking two annealing processes as an example, step S312 may include:

[0082] Step S312 a : performing a first annealing process on the first metal material layer and the first end of the pre-semiconductor column 112 to form a pre-metal silicide layer on the first end of the pre-semiconductor column 112 .

[0083] Step S312b: removing the remaining first metal material layer which has not formed the pre-metal silicide layer after the first annealing treatment.

[0084] In some embodiments, the remaining first metal material layer can be removed by a process such as wet etching.

[0085] Step S312 c : performing a second annealing treatment on the pre-metal silicide layer to form the bit line 102 , and forming the semiconductor column 101 in the other part of the pre-semiconductor column 112 where the bit line 102 is not formed.

[0086] The annealing temperature during the first annealing treatment is lower than the annealing temperature during the second annealing treatment. When the first metal material layer is subjected to the first annealing treatment, the annealing temperature causes the metal atoms of the first metal material layer to react with the material in the first portion, thereby forming the pre-metal silicide layer, while the first metal material layer does not react with the material of the first insulating material layer 113 at the bottom of the first groove 114. When the pre-metal silicide layer is subjected to the second annealing treatment, the annealing temperature is conducive to the phase transition of the pre-metal silicide layer, and the formed bit line 102 is more stable and has a lower resistance.

[0087] In some embodiments, see Figure 3B and Figure 3C The pre-semiconductor column 112 further includes a third portion 112c, which is located on a side of the second portion 112b of the pre-semiconductor column 112 away from the first portion 112a of the semiconductor column 101 in the third direction Z. The third portion 112c of the pre-semiconductor column 112 may be formed by doping a semiconductor material with P-type doping ions or N-type doping ions by ion implantation or the like. The P-type doping ions may include boron, aluminum, gallium, etc., and the N-type doping ions may include phosphorus, arsenic, antimony, etc. The third portion 112c of the pre-semiconductor column 112 may become the third portion 101c of the semiconductor column 101. The third portion 101c of the semiconductor column 101 may be the source or drain of the transistor of the semiconductor device. When the first portion 101a of the semiconductor column 101 is one of the source and drain of the transistor, the second portion 101b of the semiconductor column 101 becomes the other of the source and drain of the transistor.

[0088] The material of the second insulating layer 115 is different from that of the first insulating material layer 113, so as to avoid mutual interference in the processing of the first insulating material layer 113 and the second insulating layer 115 in the subsequent process. For example, the material of the second insulating layer 115 is different from that of the first insulating material layer 113, and the two have different sensitivities to different etching processes, so as to avoid excessive etching of the first insulating material layer 113 when the second insulating layer 115 is subsequently patterned by an etching process.

[0089] The material of the second insulating layer 115 may be selected from at least one of silicon oxide, silicon nitride, and doped silicon oxide. For example, when the material of the first insulating material layer 113 is selected from silicon oxide, the material of the second insulating layer 115 may be selected from silicon nitride.

[0090] In some embodiments, the second insulating layer 115 may be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0091] In some embodiments, see Figure 3D The second insulating layer 115 includes a first insulating portion 115a, a second insulating portion 115b and a third insulating portion 115c, wherein the first insulating portion 115a covers the sidewall of the bit line 102 in the first direction X and a portion of the sidewall of the first end of the semiconductor pillar 101 in the first direction X. The second insulating portion 115b covers the bottom of the first groove 114, and the third insulating portion 115c covers a side of the bit line 102 away from the semiconductor pillar 101 in the third direction Z.

[0092] In some embodiments, the bit line 102 and the semiconductor column 101 have an interface 104 in the third direction Z, and the first insulating portion covers the interface 104 in the first direction X to protect the interface 104 and prevent the interface 104 from being damaged in subsequent processes and causing problems such as collapse of the bit line 102, thereby improving the product quality and device performance of the formed semiconductor device.

[0093] In some embodiments, see Figure 4 and Figure 7 , after step S400, further comprising:

[0094] Step S500 : forming a third insulating layer 116 in the third direction Z to cover the bit line 102 .

[0095] In some embodiments, the material of the third insulating layer 116 is different from the material of the second insulating layer 115. The material of the third insulating layer 116 can be the same as the material of the first insulating material layer 113.

[0096] In some embodiments, the third insulating layer 116 may be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0097] In some embodiments, see Figure 3E , Figures 4 to 6 , step S500 may include:

[0098] Step S510 : forming a third insulating layer 116 covering the second insulating layer 115 on a side of the second insulating layer 115 away from the bit line 102 in the third direction Z.

[0099] In some embodiments, see Figure 3E and Figure 6 , step S510 further includes:

[0100] Step S511 : forming an air gap 108 in the first groove 114 .

[0101] When the third insulating layer 116 is formed by deposition or the like, the air gap 108 is formed when the third insulating layer 116 is deposited in the first groove 114 .

[0102] When the third insulating layer 116 is formed directly after the second insulating layer 115 is formed, the first insulating material layer 113 forms the first insulating layer 105 after the first groove 114 is formed.

[0103] In some embodiments, see Figure 3F and Figure 7 , after step S400 and before step S500, further comprising:

[0104] Step S600 : patterning the second insulating layer 115 to expose the bottom of the first groove 114 .

[0105] In some embodiments, when patterning the second insulating layer 115, the second insulating portion and the third insulating portion of the second insulating layer 115 are removed, and at least a portion of the first insulating portion is retained to form a protective layer 103 (eg, Figure 5 shown).

[0106] In some embodiments, see Figure 3G and Figure 7, after step S600, further comprising:

[0107] S700 : forming a second groove 117 in the first insulating material layer 113 , wherein the first groove 114 is connected to the second groove 117 .

[0108] The second groove 117 can be formed by an etching process, such as a dry etching process or a wet etching process. The second groove 117 is formed and the first insulating portion of the second insulating layer 115 is retained by taking advantage of the fact that the material of the first insulating layer 105 is different from the material of the second insulating layer 115 and the different tolerances to different etching processes.

[0109] After the second groove 117 is formed, the first insulating material layer 113 forms a first insulating layer 105 .

[0110] In some embodiments, after step S700, see Figure 3H , Figures 7 to 9 , step S500 may include:

[0111] Step S520 : forming a third insulating layer 116 covering the bit line 102 in the third direction Z and covering the first insulating portion of the second insulating layer 115 in the first direction X.

[0112] In some embodiments, see Figure 3H and Fig. 9 , step S520 further includes:

[0113] Step S521 : forming an air gap 108 in the second groove 117 .

[0114] When the third insulating layer 116 is formed by deposition or the like, the air gap 108 is formed when the third insulating layer 116 is deposited in the first groove 114 and the second groove 117 .

[0115] By forming the second groove 117, the depth of the groove extending along the second direction Y, which is located between the semiconductor pillars 101 and close to the first end of the semiconductor pillar 101 in the third direction Z, is further deepened, which is beneficial to making the depth of the formed air gap 108 deeper than the depth of the air gap 108 formed directly in the first groove 114, and is more beneficial to using the air gap 108 to reduce the coupling between the adjacent bit lines 102 in the first direction X, thereby improving the product performance of the formed semiconductor device.

[0116] The method for preparing a semiconductor device provided in the present application forms a second insulating layer 115 and utilizes the second insulating layer 115 to protect the bit line 102 in subsequent processes, thereby improving the protection effect of the bit line 102 during the formation of the semiconductor device and improving the device performance of the semiconductor device.

[0117] See also Figures 10 to 12 The present application also provides a semiconductor device 100, including:

[0118] A plurality of semiconductor pillars 101 arranged along a first direction X and a second direction Y, wherein the semiconductor pillars 101 include a first end 118 in a third direction Z, and a plane common to the first direction X and the second direction Y intersects the third direction Z;

[0119] The bit line 102 is located at the first end 118 of the semiconductor column 101 and extends along the second direction Y and is connected to the semiconductor column 101;

[0120] The protection layer 103 at least covers the sidewalls of the bit line 102 on both sides in the first direction X.

[0121] In some embodiments, the first direction X, the second direction Y and the third direction Z are perpendicular to each other. It can be understood that the vertical in the present application refers to vertical within a certain angle error range, for example, 85° to 95° can be interpreted as vertical.

[0122] See also Fig.11 and Fig.12In some embodiments, the semiconductor column 101 includes a first portion 101a, a second portion 101b and a third portion 101c, the first portion 101a of the semiconductor column 101 is located at the first end 118 of the semiconductor column 101, the semiconductor column 101 includes a second end 119 opposite to the first end 118 of the semiconductor column 101 in a third direction Z, the third portion 101c of the semiconductor column 101 is located at the second end 119 of the semiconductor column 101 in the third direction Z, and the second portion 101b of the semiconductor column 101 is located between the first portion 101a of the semiconductor column 101 and the third portion 101c of the semiconductor column 101 in the third direction Z. The material of the semiconductor column 101 includes semiconductor materials such as single crystal silicon, polycrystalline silicon, and amorphous silicon. The first portion 101a of the semiconductor column 101 and the third portion 101c of the semiconductor column 101 are doped portions formed by doping the semiconductor material with P-type doping ions or N-type doping ions by ion implantation or the like. The P-type doping ions may include boron, aluminum, gallium, etc., and the N-type doping ions may include phosphorus, arsenic, antimony, etc. The first portion 101a of the semiconductor column 101 may be one of the source and the drain, for example, the source; the third portion 101c of the semiconductor column 101 may be the other of the source and the drain, for example, the drain; the second portion 101b of the semiconductor column 101 is a channel located between the source and the drain in the third direction Z.

[0123] In some embodiments, the bit line 102 includes a metal silicide layer. The metal silicide layer includes metal silicide, which may be selected from at least one of nickel silicon compound, titanium silicon compound, and cobalt silicon compound. For example, the metal silicide may be selected from nickel silicon compound (NiSi).

[0124] See also Fig.11 and Fig.12 In some embodiments, an interface 104 is provided between the first end 118 of the semiconductor pillar 101 and the bit line 102. The protection layer 103 covers the sidewalls of the bit line 102 on both sides in the first direction X, and the protection layer 103 also covers part of the sidewalls of the first end 118 of the semiconductor pillar 101 on both sides in the first direction X, so as to protect the bit line 102 and the interface 104 between the bit line 102 and the semiconductor pillar 101, and avoid the problem of the bit line 102 collapsing due to damage to the interface 104 during the manufacturing process, thereby improving the product quality and device performance of the formed semiconductor device 100.

[0125] In some embodiments, when the semiconductor device 100 is formed by the semiconductor device manufacturing method as described above, the protective layer 103 is formed by the second insulating layer 115 (such as FIG. 3E to FIG. 3H shown) is formed.

[0126] See also Figures 10 to 12 In some embodiments, the semiconductor device 100 further includes:

[0127] A first insulating layer 105 is located between two adjacent semiconductor pillars 101 along the first direction X;

[0128] The material of the protection layer 103 is different from that of the first insulating layer 105 .

[0129] In some embodiments, the material of the first insulating layer 105 can be selected from at least one of silicon oxide, silicon nitride, and doped silicon oxide. For example, the material of the first insulating layer 105 can be selected from silicon oxide. The material of the protective layer 103 can be selected from at least one of silicon oxide, silicon nitride, and doped silicon oxide that is different from the material of the first insulating layer 105. For example, when the material of the first insulating layer 105 is selected from silicon oxide, the material of the second insulating layer 115 can be selected from silicon nitride.

[0130] See also Fig.11 In some embodiments, the protection layer 103 includes a first sub-segment 106 extending along the third direction Z, and the first sub-segment 106 covers part of the sidewalls of the semiconductor pillar 101 and the bit line 102 on both sides in the first direction X. That is, an end of the first sub-segment 106 away from the semiconductor pillar 101 in the third direction Z does not exceed a side of the bit line 102 away from the semiconductor pillar 101 in the third direction Z, and an end of the first sub-segment 106 close to the semiconductor pillar 101 in the third direction Z exceeds an interface 104 between the bit line 102 and the semiconductor pillar 101 in the third direction Z.

[0131] See also Fig.11 In some embodiments, one end of the first sub-segment 106 away from the semiconductor column 101 in the third direction Z is flush with a side of the bit line 102 away from the semiconductor column 101 in the third direction Z, so that the protection layer 103 can fully protect the side wall of the bit line 102 in the first direction X.

[0132] See also Fig.11 In some embodiments, the protective layer 103 may be composed of the first sub-segment 106 .

[0133] See also Fig.11and Fig.12 In some embodiments, the semiconductor device 100 further includes:

[0134] The covering layer 107 covers the protection layer 103 . The covering layer 107 includes an air gap 108 , and the air gap 108 is located between two adjacent bit lines 102 .

[0135] In some embodiments, when the semiconductor device 100 is formed by the semiconductor device manufacturing method as described above, the capping layer 107 is formed by the third insulating layer 116 (eg, Figure 3E and Figure 3H shown) is formed.

[0136] In some embodiments, the material of the capping layer 107 is different from the material of the protective layer 103. The material of the capping layer 107 may be the same as the material of the first insulating layer 105. The material of the capping layer 107 may be selected from at least one of silicon oxide, silicon nitride, and doped silicon oxide, for example, the material of the capping layer 107 may be selected from silicon oxide.

[0137] See also Fig.11 In some embodiments, the covering layer 107 is in direct contact with the first insulating layer 105 , and the air gap 108 is away from one end of the bit line 102 in the third direction Z, and is away from the bit line 102 relative to one end of the protective layer 103 in the third direction Z that is away from the bit line 102 .

[0138] See also Fig.12 In some embodiments, the protective layer 103 also includes a second sub-segment 109 and a third sub-segment 110 connected to the first sub-segment 106, the second sub-segment 109 and the third sub-segment 110 extend along the first direction X respectively, the second sub-segment 109 covers an end of the first insulating layer 105 close to the protective layer 103 in the third direction Z, and the third sub-segment 110 covers an end of the bit line 102 away from the semiconductor pillar 101 in the third direction Z.

[0139] See also Fig.12 In some embodiments, the protection layer 103 is spaced between the first insulating layer 105 and the covering layer 107, and the air gap 108 is located at one end of the bit line 102 in the third direction Z away from the bit line 102, and is close to the bit line 102 relative to the end of the protection layer 103 in the third direction Z away from the bit line 102.

[0140] When the air gap 108 is away from one end of the bit line 102 in the third direction Z, and is away from the bit line 102 relative to the end of the protective layer 103 away from the bit line 102 in the third direction Z, the air gap 108 has a first air gap depth in the third direction Z; when the air gap 108 is away from one end of the bit line 102 in the third direction Z, and is close to the bit line 102 relative to the end of the protective layer 103 away from the bit line 102 in the third direction Z, the air gap 108 has a second air gap depth in the third direction Z, and the first air gap depth is greater than the second air gap depth. A larger air gap depth is more conducive to reducing the coupling between the adjacent bit lines 102 in the first direction X, and improving the device performance of the semiconductor device 100.

[0141] In some embodiments, the semiconductor device 100 may include a single-gate transistor, a multi-gate transistor, a ring-gate transistor, etc., which are not specifically limited herein. The semiconductor device 100 further includes a gate 111, and the gate 111 contacts at least one side wall of the channel of the semiconductor column 101. For example, Figure 4 As shown, the semiconductor device 100 includes a single-gate transistor, the gate 111 is arranged along the second direction Y, and the gate 111 contacts a side wall of the second portion of the semiconductor pillar 101 on one side in the second direction Y.

[0142] The semiconductor device 100 provided in the present application protects the bit line 102 during the manufacturing process of the semiconductor device 100 by setting the protection layer 103, thereby improving the protection effect of the bit line 102 during the formation of the semiconductor device 100 and improving the device performance of the semiconductor device 100.

[0143] See also Fig.13 , the present application also provides a storage system 10, the storage system 10 includes a memory 11 and a controller 12, the controller 12 is coupled to the memory 11, and is used to control the memory 11 to store data;

[0144] The memory 11 includes the semiconductor device 100 in any one of the above embodiments.

[0145] In some embodiments, the semiconductor device 100 is the memory 11. Alternatively, the semiconductor device 100 may be a part of the memory 11. For example, the memory 11 includes a memory chip and a peripheral circuit chip, the peripheral circuit chip is electrically connected to the memory chip, and the peripheral circuit chip can store data in the memory chip or read data from the memory chip. The memory chip and / or the peripheral circuit chip may include the semiconductor device 100 in any of the above embodiments.

[0146] Specifically, the memory 11 may be a three-dimensional memory (eg, a 3D DRAM memory). It is understood that the memory provided by the embodiment of the present application has the same beneficial effects as the semiconductor device 100 provided by the embodiment of the present application.

[0147] The storage system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. The controller may be configured to control operations of the semiconductor package structure, such as read, erase, and program operations.

[0148] In some embodiments, the controller 12 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0149] In some embodiments, the controller 12 is designed to operate in a solid state drive (SSD) or an embedded multi media card (eMMC), which is used as data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0150] The present application provides a semiconductor device, a preparation method thereof, and a storage system. The semiconductor device includes a plurality of semiconductor columns arranged along a first direction and a second direction. The semiconductor column includes a first end in a third direction, a bit line located at the first end of the semiconductor column, the bit line extends along the second direction and is connected to the semiconductor column, a protective layer covers at least the side walls of the bit line on both sides in the first direction, and a plane shared by the first direction and the second direction intersects with the third direction. The semiconductor device, the preparation method thereof, and the storage system provided by the present application protect the bit line in the process of the semiconductor device through the provision of the protective layer, thereby improving the protection effect of the bit line in the formation of the semiconductor device and improving the device performance of the semiconductor device.

[0151] The semiconductor device and its preparation method and storage system provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: forming a plurality of pre-semiconductor pillars arranged along a first direction and a second direction and a first insulating material layer filled between two adjacent pre-semiconductor pillars in the first direction; Removing a portion of the first insulating material layer to form a first groove, wherein the first groove is located between the pre-semiconductor pillars and close to a first end of the pre-semiconductor pillar in a third direction, the first groove extends along the second direction, and a plane common to the first direction and the second direction intersects the third direction; forming a bit line at the first end of the pre-semiconductor column, and forming a semiconductor column at the other part of the pre-semiconductor column; A second insulating layer is formed to cover at least the sidewall of the bit line along the first direction, wherein the material of the second insulating layer is different from that of the first insulating material layer.

2. The method for preparing a semiconductor device according to claim 1, wherein: After the step of "forming a second insulating layer that at least covers the sidewalls of the bit line along the first direction", the method further includes: forming a third insulating layer covering the second insulating layer on a side of the second insulating layer away from the bit line in the third direction; Wherein, a material of the third insulating layer is different from a material of the second insulating layer.

3. The method for preparing a semiconductor device according to claim 2, wherein: The step of forming the third insulating layer further includes: An air gap is formed in the first groove.

4. The method for preparing a semiconductor device according to claim 1, wherein: After the step of "forming a second insulating layer that at least covers the sidewalls of the bit line along the first direction", the method further includes: The second insulating layer is patterned to expose the bottom of the first groove.

5. The method for preparing a semiconductor device according to claim 4, characterized in that: After patterning the second insulating layer, the method further includes: A second groove is formed in the first insulating material layer, and the first groove is connected to the second groove.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: After the second groove is formed, the method further comprises: An air gap is formed in the second groove.

7. The method for preparing a semiconductor device according to claim 1, wherein: The step of "forming a bit line at the first end of the pre-semiconductor column and forming a semiconductor column at the other part of the pre-semiconductor column" includes: Metallization is performed on the first end of the pre-semiconductor pillar to form the bit line and semiconductor pillars located at other portions of the pre-semiconductor pillar.

8. A semiconductor device, characterized in that: include: A plurality of semiconductor columns arranged along a first direction and a second direction, wherein the semiconductor columns include a first end in a third direction, and a plane common to the first direction and the second direction intersects the third direction; A bit line, located at the first end of the semiconductor column, extending along the second direction and connected to the semiconductor column; The protection layer at least covers the side walls of the bit line on both sides in the first direction.

9. The semiconductor device according to claim 8, characterized in that The semiconductor device further comprises: A first insulating layer, located between two adjacent semiconductor pillars along the first direction; Wherein, the material of the protection layer is different from that of the first insulating layer.

10. The semiconductor device according to claim 9, wherein: The semiconductor device further comprises: A covering layer covers the protection layer, wherein the covering layer includes an air gap, and the air gap is located between two adjacent bit lines.

11. The semiconductor device according to claim 10, wherein: The protection layer includes a first sub-segment extending along the third direction, and the first sub-segment covers a portion of the semiconductor pillar and side walls of both sides of the bit line in the first direction.

12. The semiconductor device according to claim 11, wherein The air gap is away from one end of the bit line in the third direction, and is away from the bit line relative to one end of the protection layer in the third direction away from the bit line.

13. The semiconductor device according to claim 11, wherein The protective layer also includes a second sub-segment and a third sub-segment connected to the first sub-segment, the second sub-segment and the third sub-segment respectively extend along the first direction, the second sub-segment covers an end of the first insulating layer close to the protective layer in the third direction, and the third sub-segment covers an end of the bit line away from the semiconductor column in the third direction.

14. The semiconductor device according to claim 13, wherein: The air gap is away from one end of the bit line in the third direction, and is closer to the bit line than one end of the protection layer is away from the bit line in the third direction.

15. The semiconductor device according to claim 8, wherein The bit line includes a metal silicide layer.

16. A storage system, characterized in that: The storage system includes a memory and a controller, wherein the controller is coupled to the memory and is used to control the memory to store data; Wherein, the memory comprises the semiconductor device as claimed in any one of claims 8 to 15.

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