Semiconductor structure, manufacturing method thereof and memory system

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a storage system. In one embodiment, a method of fabricating a semiconductor structure includes forming a conductive structure extending in a second direction within a memory region and forming an isolation structure extending in the second direction through the memory region and a non-memory region, where the conductive structure is located at a first sidewall of a semiconductor pillar and the isolation structure is located at a second sidewall of the semiconductor pillar. A part of the isolation structure is located at a second side wall, opposite to the first side wall, of the semiconductor column; and forming a lead-out structure connected with the isolation structure in the non-storage area.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a method for manufacturing the semiconductor structure, and a storage system. Background Art

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices and cloud storage, the requirements for the storage density of semiconductor structures such as three-dimensional semiconductor memory devices are getting higher and higher. However, as the storage density of semiconductor structures increases, the number of storage cells and wiring lead-out structures increases, the size decreases, and the spatial density increases, which makes the coupling phenomenon between adjacent components more and more serious. In addition, the wiring lead-out space of the isolation structure used to isolate adjacent components such as adjacent storage cells will also be subject to certain restrictions. Summary of the invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies proposed in the above background technology section or other deficiencies in the prior art.

[0004] The present application provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a semiconductor layer, the semiconductor layer includes a plurality of storage areas and at least one non-storage area, the storage area and the non-storage area both extend along a first direction and are arranged along a second direction, the storage area includes a plurality of semiconductor pillars extending along a third direction, and the first direction, the second direction and the third direction are perpendicular to each other. The method includes: forming a conductive structure in the storage area and extending along the second direction, and forming an isolation structure extending through the storage area and the non-storage area along the second direction, wherein the conductive structure is located at a first side wall of the semiconductor pillar, and a portion of the isolation structure is located at a second side wall of the semiconductor pillar opposite to the first side wall; and forming a lead-out structure connected to the isolation structure in the non-storage area.

[0005] In one embodiment, a conductive structure is formed within a storage area and extending along a second direction, and an isolation structure is formed extending along the second direction through the storage area and a non-storage area, including: forming a plurality of initial semiconductor pillars extending along a first direction in the storage area; forming a third trench within the storage area, passing through the initial semiconductor pillars and extending along the second direction, and forming a fourth trench extending along the second direction through the initial semiconductor pillars and the non-storage area, wherein the third trench and the fourth trench divide the initial semiconductor pillar into a plurality of semiconductor pillars, and the width of the third trench is greater than the width of the fourth trench; and forming a conductive structure in the third trench, and forming an isolation structure in the fourth trench.

[0006] In one embodiment, a conductive structure extending along a second direction is formed in a storage area, and an isolation structure extending along the second direction through the storage area and the non-storage area is formed, including: forming a plurality of initial semiconductor pillars extending along a first direction in the storage area; forming third and fourth trenches alternately arranged along the first direction and extending along the second direction through the initial semiconductor pillars and the non-storage area, wherein the third trench and the fourth trench divide the initial semiconductor pillars into a plurality of semiconductor pillars, and the width of the third trench is greater than the width of the fourth trench; forming an initial conductive structure in the third trench, and forming an isolation structure in the fourth trench; and removing at least a portion of the initial conductive structure located in the non-storage area to form a conductive structure.

[0007] In one embodiment, a plurality of initial semiconductor pillars extending along a first direction are formed in a storage area, including: forming a plurality of first trenches extending along the first direction in the storage area, and forming second trenches extending along the first direction in a non-storage area, wherein the width of the second trenches is greater than the width of the first trenches; and forming a filling dielectric layer in the first trenches and the second trenches, wherein the semiconductor layer that is not removed in the storage area forms the initial semiconductor pillars.

[0008] In one embodiment, a third trench is formed in a storage area, passes through an initial semiconductor column and extends along a second direction, and a fourth trench is formed extending along the second direction through the initial semiconductor column and a non-storage area, including: an initial third trench is formed in the storage area, passes through an initial semiconductor column and extends along the second direction, and a fourth trench is formed extending along the second direction through the initial semiconductor column and a non-storage area; a first sacrificial layer and a second sacrificial layer are formed in the initial third trench and the fourth trench, respectively; a portion of the second sacrificial layer is removed along a third direction, and a protective layer is formed in the removed space; and the first sacrificial layer is removed, and the width and depth of the initial third trench are increased to form a third trench.

[0009] In one embodiment, a conductive structure is formed in the third trench and an isolation structure is formed in the fourth trench, including: forming a first dielectric layer in the third trench; removing a portion of the first dielectric layer along a third direction to form a first gap; forming a gate dielectric layer on the sidewall of the first gap; forming a conductive layer on the inner side of the gate dielectric layer; removing a portion of the conductive layer along the third direction to form a second gap; forming a third gap along the third direction through the conductive layer to expose the first dielectric layer, wherein the conductive layer that is not removed forms a conductive structure; forming a second dielectric layer in the second gap and the third gap; removing the protective layer and the remaining second sacrificial layer to form a fourth gap; and forming an isolation structure in the fourth gap.

[0010] In one embodiment, the method further includes: forming a contact structure connected to the conductive structure.

[0011] In one embodiment, the isolation structure includes a first isolation structure located at the second side wall of the semiconductor column and a second isolation structure located in the non-storage area, forming a contact structure connected to the conductive structure, including: etching back a portion of the first isolation structure along a third direction and forming a third dielectric layer in the etched back space; and forming a contact structure on a side of the conductive structure corresponding to the third dielectric layer.

[0012] In one embodiment, forming a lead-out structure connected to the isolation structure in the non-storage region includes: forming a lead-out hole extending along a third direction to the isolation structure in the non-storage region; and forming the lead-out structure in the lead-out hole.

[0013] In one embodiment, forming a lead-out structure connected to an isolation structure in a non-storage area includes: forming a lead-out groove in the non-storage area extending along a third direction to the isolation structure and extending along the first direction; and forming the lead-out structure in the lead-out groove.

[0014] On the other hand, the present application provides a semiconductor structure. The semiconductor structure includes: a semiconductor layer, including multiple storage areas and at least one non-storage area, the storage area and the non-storage area both extend along the first direction and are arranged along the second direction, the storage area includes multiple semiconductor pillars extending along the third direction, and the first direction, the second direction and the third direction are perpendicular to each other; a conductive structure, located at the first side wall of the semiconductor pillar and extending along the second direction in the storage area; an isolation structure, extending through the storage area and the non-storage area along the second direction, and a part of the isolation structure is located at the second side wall of the semiconductor pillar opposite to the first side wall; and a lead-out structure, arranged in the non-storage area and connected to the isolation structure.

[0015] In one embodiment, the semiconductor structure also includes: a gate dielectric layer located between the conductive structure and the semiconductor pillar, wherein the conductive structure includes a first conductive layer located on the inner side of the gate dielectric layer and a second conductive layer located on the inner side of the first conductive layer; and a second dielectric layer located on the inner side of the second conductive layer.

[0016] In one embodiment, the material of the isolation structure includes metal, and the semiconductor structure further includes: a third dielectric layer located on one side of the isolation structure and connected to the isolation structure.

[0017] In one embodiment, the semiconductor structure further includes: a contact structure located on a side of the conductive structure corresponding to the third dielectric layer and connected to the conductive structure.

[0018] In one embodiment, the lead-out structure includes: a plurality of sub-lead-out structures connected to the isolation structure and arranged along the first direction.

[0019] In one embodiment, the lead-out structure extends along a first direction.

[0020] In one embodiment, the semiconductor structure further includes a source and a drain respectively disposed at two ends of the semiconductor column.

[0021] On the other hand, the present application provides a storage system, which includes at least one three-dimensional memory, each three-dimensional memory including the semiconductor structure as described above; and a controller coupled to the semiconductor structure for controlling the three-dimensional memory to store data.

[0022] In one or more embodiments of the present application, by configuring the isolation structure to extend along the second direction through the storage area and the non-storage area, and forming a lead-out structure connected to the isolation structure in the non-storage area, the isolation structures of multiple storage areas can be connected to the lead-out structure via the non-storage area, which is beneficial for reducing the lead-out space of the isolation structure and reducing the difficulty of leading out the isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Other features, purposes and advantages of the present application will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0024] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0025] Figures 2 to 17 is a process step diagram for forming a conductive structure and an isolation structure according to an exemplary embodiment of the present application;

[0026] Figures 18 to 35 is a process step diagram for forming a conductive structure and an isolation structure according to another exemplary embodiment of the present application;

[0027] Fig.36 is a process step diagram for forming a contact structure according to an exemplary embodiment of the present application;

[0028] Fig.37 is a process step diagram of forming a contact structure according to another exemplary embodiment of the present application;

[0029] Fig.38 is a process step diagram for forming a lead-out structure according to an exemplary embodiment of the present application;

[0030] Fig.39 is a process step diagram for forming a lead-out structure according to another exemplary embodiment of the present application;

[0031] Fig.40 is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of the present application; and

[0032] Fig.41Aand Fig.41B is a schematic diagram of a storage system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and do not limit the scope of the present application in any way.

[0034] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first groove discussed in this application may also be referred to as the second groove, the third groove, the first direction may also be referred to as the second direction, the third direction, and vice versa.

[0035] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0036] In addition, in this document, when describing that one part is located "on" another part, for example, the meaning of "on", "above" and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" does not absolutely mean being above based on the direction of gravity, nor does it only mean the meaning of "on something" or "above something", but also includes the meaning of "on something" or "over something" with no intervening features or layers in between (i.e., directly on something).

[0037] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0038] This document is described with reference to schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and sizes shown, but include various equivalent structures that can achieve the same functions and shape and size deviations caused by, for example, manufacturing. The positions shown in the drawings are schematic in nature and are not intended to limit the positions of the components.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0040] As used in this article, the term "layer" refers to a material portion including an area with a height. A layer can be an area of ​​a uniform or non-uniform continuous structure, whose height is less than the height of the continuous structure. For example, a layer can be located between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above it and / or below it. A layer can include multiple layers.

[0041] In addition, in the present application, when “connected” or “coupled” is used, it may indicate that the corresponding components are in direct contact or indirect contact, unless otherwise clearly defined or can be inferred from the context.

[0042] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0043] Figure 1 is a flow chart of a method 1000 of fabricating a semiconductor structure according to an exemplary embodiment of the present application.

[0044] like Figure 1As shown, the method 1000 for manufacturing a semiconductor structure may include: S1100, forming a conductive structure in a storage area and extending along a second direction, and forming an isolation structure extending through the storage area and the non-storage area along the second direction, wherein the conductive structure is located at a first sidewall of the semiconductor column, and a portion of the isolation structure is located at a second sidewall of the semiconductor column opposite to the first sidewall; and S1200, forming a lead-out structure connected to the isolation structure in the non-storage area. Steps S1100 and S1200 will be described in detail below.

[0045] In the exemplary embodiment of the present application, Figure 2 As shown, the semiconductor layer 1100 may include a plurality of storage areas A and at least one non-storage area B. The storage areas A and the non-storage areas B may both extend along the first direction Y and be arranged along the second direction X. The storage area A may include a plurality of semiconductor pillars (not shown) extending along the third direction Z, wherein the first direction Y, the second direction X, and the third direction Z may be perpendicular to each other. The storage area A may be used to form a storage array including a plurality of storage cells (including the conductive structure 1400 formed below), and the non-storage area B may be used to form a wiring lead-out structure (including the lead-out structure 1800 formed below). Exemplarily, the non-storage area B may be located between two adjacent storage areas A, or may be located on one side of the plurality of storage areas A.

[0046] Although the present application only exemplifies that the non-storage area B is located between two adjacent storage areas A, it should be understood that the present application does not specifically limit the position of the non-storage area B. In actual processes, the position of the non-storage area B can be reasonably set according to actual needs, such as the non-storage area B can also be set on one side of multiple storage areas A, and the present application does not make specific restrictions on this.

[0047] In the exemplary embodiment of the present application, Fig.16 and Fig.17 (or Fig.34 and Fig.35 ), a conductive structure 1400 may be formed in the storage area A and extending along the second direction X, and an isolation structure 1500 may be formed extending through the storage area A and the non-storage area B along the second direction X, wherein the conductive structure 1400 may be located at a first side wall of the semiconductor column 1210, and a portion of the isolation structure 1500 may be located at a second side wall of the semiconductor column 1210 opposite to the first side wall.

[0048] In an exemplary embodiment of the present application, Figures 2 to 17 As shown, a process step diagram for forming a conductive structure 1400 and an isolation structure 1500 is shown.

[0049] For example, Figure 2 As shown, a first dielectric layer 1110 and a second dielectric layer 1120 stacked in sequence may be formed on the surface of the semiconductor layer 1100 .

[0050] The material of the semiconductor layer 1100 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The material of the first dielectric layer 1110 may include an oxide such as silicon oxide. The material of the second dielectric layer 1120 may include a nitride such as silicon nitride.

[0051] In an exemplary embodiment, the first dielectric layer 1110 and the second dielectric layer 1120 may be deposited by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In another exemplary embodiment, the first dielectric layer 1110 may be formed by oxidizing the surface of the semiconductor layer 1100 by, for example, an oxidation process.

[0052] Figure 3 and Figure 4 is a schematic diagram of a structure for forming an initial semiconductor column 1200 according to an exemplary embodiment of the present application, wherein: Figure 4 for Figure 3 Cross-sectional view along CC direction.

[0053] For example, Figure 3 and Figure 4 As shown, a plurality of initial semiconductor pillars 1200 extending along the first direction Y may be formed in the storage region A. For example, a plurality of first trenches 100 extending along the first direction Y may be formed in the storage region A, and a second trench 200 extending along the first direction Y may be formed in the non-storage region B, wherein the width of the second trench 200 may be greater than the width of the first trench 100; and a filling dielectric layer 1130 may be formed in the first trench 100 and the second trench 200, wherein the semiconductor layer 1100 not removed in the storage region A forms the initial semiconductor pillars 1200.

[0054] Exemplarily, the second dielectric layer 1120, the first dielectric layer 1110 and the semiconductor layer 1100 may be etched by an etching process to form the first trench 100, the second trench 200 and the initial semiconductor pillar 1200. For example, the second dielectric layer 1120 and the first dielectric layer 1110 may be etched by a photolithography process to form a patterned mask, wherein the second dielectric layer 1120 may be used as a bottom anti-reflection layer of the photolithography, and the first dielectric layer 1110 may be used as a hard mask; then, the semiconductor layer 1100 is etched by one or more dry etching and / or wet etching processes with the patterned mask as a mask to form the first trench 100 and the second trench 200 in the semiconductor layer 1100, wherein the semiconductor layer 1100 that is not removed in the storage area A may form the initial semiconductor pillar 1200.

[0055] In the present application, the initial semiconductor pillar 1200 may be formed by etching the semiconductor layer 1100. Therefore, the initial semiconductor pillar 1200 may have the same material as the semiconductor layer 1100, such as single crystal silicon. In addition, since the non-storage area B is mainly used to form the lead-out structure described below, the width of the second trench 200 may be greater than the width of the first trench 100, so as to provide a larger space for the subsequent formation of the lead-out structure.

[0056] For example, the filling dielectric layer 1130 may be deposited in the first trench 100 and the second trench 200 by a thin film deposition process, so that adjacent initial semiconductor pillars 1200 are isolated by the filling dielectric layer 1130. In addition, a planarization process such as a mechanical grinding process may be performed to remove the filling dielectric layer 1130 on the surface of the second dielectric layer 1120.

[0057] In the exemplary embodiment of the present application, Figures 5 to 12 As shown, a third trench 310 ( Fig.11 or Fig.12 ), and forming a fourth trench 400 ( Figure 6 or Figure 7 ), wherein the third trench 310 and the fourth trench 400 can divide the initial semiconductor column 1200 into a plurality of semiconductor columns 1210, and the width of the third trench 310 can be greater than the width of the fourth trench 400.

[0058] Figure 6 and Figure 7 is a schematic diagram of a structure for forming an initial third trench 300, a fourth trench 400 and a semiconductor pillar 1210 according to an exemplary embodiment of the present application, wherein: Figure 7 for Figure 6 Cross-sectional view along DD direction.

[0059] For example, Figure 6 and Figure 7 As shown, an initial third trench 300 may be formed in the storage region A, passing through the initial semiconductor pillar 1200 and extending along the second direction X, and a fourth trench 400 may be formed extending through the initial semiconductor pillar 1200 and the non-storage region B along the second direction X. In other words, the initial third trench 300 may be formed in the storage region A, passing through the initial semiconductor pillar 1200 and extending along the second direction X, that is, the initial third trench 300 may be located in the storage region A. The fourth trench 400 may be formed in the storage region A and the non-storage region B, extending through the initial semiconductor pillar 1200 and the non-storage region B along the second direction X, that is, the fourth trench 400 may be located in the storage region A and the non-storage region B.

[0060] For example, Figure 5 As shown, a patterned mask H may be formed on the surface of the filling dielectric layer 1130 and the second dielectric layer 1120, and the filling dielectric layer 1130, the second dielectric layer 1120, the first dielectric layer 1110 and the semiconductor layer 1100 may be etched with the patterned mask H as a mask to form an initial third trench 300 located in the storage area A and a fourth trench 400 extending through the storage area A and the non-storage area B. For example, the initial third trench 300 and the fourth trench 400 may be formed by etching using one or more dry etching and / or wet etching processes. The initial third trench 300 and the fourth trench 400 may divide the initial semiconductor pillar 1200 into a plurality of semiconductor pillars 1210. The present application forms the semiconductor pillars 1210 by etching the semiconductor layer 1100, so the semiconductor pillars 1210 may have the same material as the semiconductor layer 1100 and may extend along the third direction Z in the semiconductor layer 1100.

[0061] In the present application, by setting the initial third trench 300 and the fourth trench 400 to pass through the initial semiconductor column 1200, it is helpful to divide the initial semiconductor column 1200 into multiple semiconductor columns 1210. By setting the fourth trench 400 to extend through the storage area A and the non-storage area B, the isolation structure subsequently formed in the fourth trench 400 can extend through the storage area A and the non-storage area B, and then the isolation structures of multiple storage areas A can be connected to the lead-out structure through the non-storage area B, which is helpful to simplify the circuit layout of the storage area A and reduce the process difficulty of the storage area A.

[0062] Figure 8 and Fig. 9 is a schematic diagram of a structure for forming a first sacrificial layer 1310 and a second sacrificial layer 1320 according to an exemplary embodiment of the present application, wherein: Fig. 9 for Figure 8 Cross-sectional view along DD direction.

[0063] For example, Figure 8 and Fig. 9 As shown, a first sacrificial layer 1310 and a second sacrificial layer 1320 may be formed in the initial third trench 300 and the fourth trench 400, respectively. For example, the first sacrificial layer 1310 and the second sacrificial layer 1320 may be formed by depositing dielectric materials such as silicon oxide, carbon materials, etc., by one or more thin film deposition processes.

[0064] For example, Fig.10 As shown, part of the second sacrificial layer 1320 may be removed along the third direction Z, and a protective layer 1330 may be formed in the removed space. For example, a photolithography process, one or more dry etching and / or wet etching processes may be used to remove part of the second sacrificial layer 1320; then one or more thin film deposition processes may be used to form the protective layer 1330 in the removed space to cover and protect the remaining second sacrificial layer 1320. The material of the protective layer 1330 may include, but is not limited to, dielectric materials such as silicon nitride.

[0065] Fig.11 and Fig.12 is a schematic diagram of a structure for forming a third trench 310 according to an exemplary embodiment of the present application, wherein: Fig.12 for Fig.11 Cross-sectional view along DD direction.

[0066] For example, Fig.11 and Fig.12 As shown, the first sacrificial layer 1310 may be removed, and the width and depth of the initial third trench 300 may be increased to form the third trench 310. For example, the first sacrificial layer 1310 may be removed by using a photolithography process, one or more dry etching and / or wet etching processes, etc. Exemplarily, in the process of removing the first sacrificial layer 1310, the initial third trench 300 may be enlarged and deepened to form a third trench 310 having a width and a depth greater than the initial third trench 300.

[0067] In the exemplary embodiment of the present application, Figures 13 to 17 As shown, a conductive structure 1400 may be formed in the third trench 310 , and an isolation structure 1500 may be formed in the fourth trench 400 .

[0068] For example, Fig.13As shown, a first dielectric layer 1610 may be formed in the third trench 310; a portion of the first dielectric layer 1610 may be removed along the third direction Z to form a first gap 500. For example, one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof, may be used to deposit and form the first dielectric layer 1610. The material of the first dielectric layer 1610 includes but is not limited to silicon oxide. Exemplarily, before forming the first dielectric layer 1610, a dielectric layer 1620 may be deposited on the sidewall of the third trench 310 to partially fill the third trench 310. Exemplarily, a portion of the first dielectric layer 1610 may be removed along the third direction Z so that the remaining first dielectric layer 1610 covers the bottom surface of the third trench 310.

[0069] For example, Fig.14 As shown, a gate dielectric layer 1630 may be formed on the sidewall of the first gap 500 ; and a conductive layer 1410 may be formed inside the gate dielectric layer 1630 .

[0070] By way of example, the gate dielectric layer 1630 may be a portion of the continuous dielectric layer 1620 formed on the sidewalls of the semiconductor pillars 1210 extending along the second direction X. The material of the gate dielectric layer 1630 may include, but is not limited to, oxides such as silicon oxide. By way of example, a wet oxidation and / or dry oxidation process, such as an in-situ steam oxidation process, may be performed to form the gate dielectric layer 1630 on the sidewalls of the third trench 310.

[0071] Then, a conductive layer 1410 may be formed inside the gate dielectric layer 1630 in the third trench 310. For example, the conductive layer 1410 may be formed by depositing one or more conductive materials such as metals and / or metal compounds such as metal tungsten W and titanium nitride TiN inside the gate dielectric layer 1630 through one or more thin film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof to form the conductive layer 1410. For example, TiN and W may be deposited sequentially to form the conductive layer 1410. For example, a planarization process such as a chemical mechanical polishing process may be performed to remove excess conductive material on the surface of the second dielectric layer 1120.

[0072] For example, Fig.15 As shown, part of the conductive layer 1410 can be removed along the third direction Z to form a second gap (not shown); a third gap (not shown) is formed along the third direction Z through the conductive layer 1410 to expose the first dielectric layer 1610, wherein the conductive layer 1410 that is not removed forms a conductive structure 1400; and a second dielectric layer 1640 is formed in the second gap and the third gap.

[0073] For example, a back-etching process may be used to remove part of the conductive layer 1410 along the third direction Z, so that the upper end of the conductive layer 1410 is below the top surface of the semiconductor pillar 1210. In addition, since the gate dielectric layer 1630 is not back-etched, the upper end of the conductive layer 1410 is below the upper end of the gate dielectric layer 1630. In this way, the back-etched conductive layer 1410 may extend along the second direction X, and its portion corresponding to the semiconductor pillar 1210 may be used as a gate electrode, and together with the corresponding gate dielectric layer 1630, it may constitute a gate structure; and its remaining portion may be used as a gate electrode for connecting the gate structure to the contact structure 1700 ( Fig.36 or Fig.37 ) connected word lines.

[0074] For example, the third gap may be formed by an etching process such as punch-down etching, dry etching and / or wet etching to form two disconnected conductive structures 1400 in the third trench 310. For example, a bottom punch-down etching process may be used to disconnect the conductive structure 1400 at the bottom of the third trench 310 until the first dielectric layer 1610 is exposed.

[0075] For example, one or more thin film deposition processes may be used to deposit the second dielectric layer 1640 in the second gap and the third gap. In other words, the second dielectric layer 1640 may be deposited in the remaining space of the third trench 310. The material of the second dielectric layer 1640 includes, but is not limited to, silicon oxide.

[0076] For example, Fig.16 As shown, a through hole 700 penetrating the gate dielectric layer 1630 and the conductive structure 1400 along the third direction Z may be formed to separate the annular gate dielectric layer 1630 and the conductive structure 1400 in the third trench 310 into at least two parts. For example, two through holes 700 with a certain interval may be formed in each of the annular gate dielectric layer 1630 and the conductive structure 1400 to separate the annular gate dielectric layer 1630 and the conductive structure 1400 into two parts. In other words, the two through holes 700 separate the annular gate dielectric layer 1630 into two parts, and separate the conductive structure 1400 into two parts.

[0077] It should be understood that the present application does not specifically limit the size and / or position of the through hole 700, and the size and / or position of the through hole 700 can be arbitrarily set according to the actual process to separate the gate dielectric layer 1630 and the conductive structure 1400 in the third trench 310 into two parts.

[0078] Fig.16 and Fig.17 is a schematic diagram of a structure for forming an isolation structure 1500 according to an exemplary embodiment of the present application, wherein: Fig.17 for Fig.16Cross-sectional view along DD direction.

[0079] For example, Fig.16 and Fig.17 As shown, the protective layer 1330 and the remaining second sacrificial layer 1320 may be removed to form a fourth gap 600; and an isolation structure 1500 may be formed in the fourth gap 600. For example, the fourth gap 600 may be formed by a photolithography process, one or more dry etching and / or wet etching processes, and the isolation structure 1500 may be formed by one or more thin film deposition processes. Exemplarily, the material of the isolation structure 1500 may include, but is not limited to, metal materials such as tungsten and copper. Exemplarily, as Fig.17 As shown, an etch-back process may be used to remove a portion of the isolation structure 1500 along the third direction Z, and a dielectric material may be filled in the removed space.

[0080] In another exemplary embodiment of the present application, Figures 18 to 35 As shown, a process step diagram for forming a conductive structure 1400 and an isolation structure 1500 is shown.

[0081] For example, Fig.18 As shown, a first dielectric layer 1110 and a second dielectric layer 1120 stacked in sequence may be formed on the surface of the semiconductor layer 1100 .

[0082] The material of the semiconductor layer 1100 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The material of the first dielectric layer 1110 may include an oxide such as silicon oxide. The material of the second dielectric layer 1120 may include a nitride such as silicon nitride.

[0083] Fig.19 and Fig. 20 is a schematic diagram of a structure for forming an initial semiconductor column 1200 according to an exemplary embodiment of the present application, wherein: Fig. 20 for Fig.19 Cross-sectional view along CC direction.

[0084] For example, Fig.19 and Fig. 20 As shown, a plurality of initial semiconductor pillars 1200 extending along the first direction Y may be formed in the storage region A. For example, a plurality of first trenches 100 extending along the first direction Y may be formed in the storage region A, and a second trench 200 extending along the first direction Y may be formed in the non-storage region B, wherein the width of the second trench 200 may be greater than the width of the first trench 100; and a filling dielectric layer 1130 may be formed in the first trench 100 and the second trench 200, wherein the semiconductor layer 1100 not removed in the storage region A forms the initial semiconductor pillars 1200.

[0085] In the exemplary embodiment of the present application, Figures 21 to 28 As shown, third trenches 310 (which are alternately arranged along the first direction Y and extend along the second direction X through the initial semiconductor pillars 1200 and the non-storage area B) may be formed. Fig. 27 or Fig.28 ) and the fourth groove 400 ( Fig. 22 or Fig.23 ). The third trench 310 and the fourth trench 400 may divide the initial semiconductor pillar 1200 into a plurality of semiconductor pillars 1210 , and the width of the third trench 310 may be greater than the width of the fourth trench 400 .

[0086] Fig. 22 and Fig.23 is a schematic diagram of a structure for forming an initial third trench 300, a fourth trench 400 and a semiconductor pillar 1210 according to an exemplary embodiment of the present application, wherein: Fig.23 for Fig. 22 Cross-sectional view along DD direction.

[0087] For example, Fig. 22 and Fig.23 As shown, initial third trenches 300 and fourth trenches 400 may be formed which are alternately arranged along the first direction Y and extend along the second direction X through the initial semiconductor pillars 1200 and the non-storage area B. In other words, initial third trenches 300 and fourth trenches 400 may be formed in the storage area A and the non-storage area B along the second direction X and extend through the initial semiconductor pillars 1200 and the non-storage area B, that is, the initial third trenches 300 and the fourth trenches 400 may both pass through the storage area A and the non-storage area B.

[0088] For example, Fig.21 As shown, a patterned mask H may be formed on the surface of the filling dielectric layer 1130 and the second dielectric layer 1120, and the filling dielectric layer 1130, the second dielectric layer 1120, the first dielectric layer 1110 and the semiconductor layer 1100 may be etched with the patterned mask H as a mask to form initial third trenches 300 and fourth trenches 400 that are alternately arranged along the first direction Y and extend along the second direction X through the initial semiconductor pillars 1200 and the non-storage area B. For example, the initial third trenches 300 and the fourth trenches 400 may be formed by etching using one or more dry etching and / or wet etching processes. The initial third trenches 300 and the fourth trenches 400 may divide the initial semiconductor pillars 1200 into a plurality of semiconductor pillars 1210. In the present application, the semiconductor pillars 1210 are formed by etching the semiconductor layer 1100, so the semiconductor pillars 1210 may have the same material as the semiconductor layer 1100 and may extend along the third direction Z in the semiconductor layer 1100.

[0089] Fig.24 and Fig.25is a schematic diagram of a structure for forming a first sacrificial layer 1310 and a second sacrificial layer 1320 according to an exemplary embodiment of the present application, wherein: Fig.25 for Fig.24 Cross-sectional view along DD direction.

[0090] For example, Fig.24 and Fig.25 As shown, a first sacrificial layer 1310 and a second sacrificial layer 1320 may be formed in the initial third trench 300 and the fourth trench 400, respectively. For example, the first sacrificial layer 1310 and the second sacrificial layer 1320 may be formed by depositing dielectric materials such as silicon oxide, carbon materials, etc., by one or more thin film deposition processes.

[0091] For example, Fig.26 As shown, part of the second sacrificial layer 1320 may be removed along the third direction Z, and a protective layer 1330 may be formed in the removed space. For example, a photolithography process, one or more dry etching and / or wet etching processes may be used to remove part of the second sacrificial layer 1320; then one or more thin film deposition processes may be used to form the protective layer 1330 in the removed space to cover and protect the remaining second sacrificial layer 1320. The material of the protective layer 1330 may include, but is not limited to, dielectric materials such as silicon nitride.

[0092] Fig. 27 and Fig.28 is a schematic diagram of a structure for forming a third trench 310 according to an exemplary embodiment of the present application, wherein: Fig.28 for Fig. 27 Cross-sectional view along DD direction.

[0093] For example, Fig. 27 and Fig.28 As shown, the first sacrificial layer 1310 may be removed, and the width and depth of the initial third trench 300 may be increased to form the third trench 310. For example, the first sacrificial layer 1310 may be removed by using a photolithography process, one or more dry etching and / or wet etching processes, etc. Exemplarily, in the process of removing the first sacrificial layer 1310, the initial third trench 300 may be enlarged and deepened to form a third trench 310 having a width and a depth greater than the initial third trench 300.

[0094] In the exemplary embodiment of the present application, Figure 29 to Figure 33 As shown, an initial conductive structure 1420 may be formed in the third trench 310 , and an isolation structure 1500 may be formed in the fourth trench 400 .

[0095] For example, Fig.29As shown, a first dielectric layer 1610 may be formed in the third trench 310; a portion of the first dielectric layer 1610 may be removed along the third direction Z to form a first gap 500. For example, one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof, may be used to deposit and form the first dielectric layer 1610. The material of the first dielectric layer 1610 includes but is not limited to silicon oxide. Exemplarily, before forming the first dielectric layer 1610, a dielectric layer 1620 may be deposited on the sidewall of the third trench 310 to partially fill the third trench 310. Exemplarily, a portion of the first dielectric layer 1610 may be removed along the third direction Z so that the remaining first dielectric layer 1610 covers the bottom surface of the third trench 310.

[0096] For example, Fig.30 As shown, a gate dielectric layer 1630 may be formed on the sidewall of the first gap 500 ; and a conductive layer 1410 may be formed inside the gate dielectric layer 1630 .

[0097] By way of example, the gate dielectric layer 1630 may be a portion of the continuous dielectric layer 1620 formed on the sidewalls of the semiconductor pillars 1210 extending along the second direction X. The material of the gate dielectric layer 1630 may include, but is not limited to, oxides such as silicon oxide. By way of example, a wet oxidation and / or dry oxidation process, such as an in-situ steam oxidation process, may be performed to form the gate dielectric layer 1630 on the sidewalls of the third trench 310.

[0098] Then, a conductive layer 1410 may be formed inside the gate dielectric layer 1630 in the third trench 310. For example, the conductive layer 1410 may be formed by depositing one or more conductive materials such as metals and / or metal compounds such as metal tungsten W and titanium nitride TiN inside the gate dielectric layer 1630 through one or more thin film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof to form the conductive layer 1410. For example, TiN and W may be deposited sequentially to form the conductive layer 1410. For example, a planarization process such as a chemical mechanical polishing process may be performed to remove excess conductive material on the surface of the second dielectric layer 1120.

[0099] For example, Fig.31 As shown, part of the conductive layer 1410 can be removed along the third direction Z to form a second gap (not shown); a third gap (not shown) is formed along the third direction Z through the conductive layer 1410 to expose the first dielectric layer 1610, wherein the conductive layer 1410 that is not removed forms an initial conductive structure 1420; and a second dielectric layer 1640 is formed in the second gap and the third gap.

[0100] For example, a back-etching process may be used to remove part of the conductive layer 1410 along the third direction Z, so that the upper end of the conductive layer 1410 is below the top surface of the semiconductor pillar 1210. In addition, since the gate dielectric layer 1630 is not back-etched, the upper end of the conductive layer 1410 is below the upper end of the gate dielectric layer 1630. In this way, the back-etched conductive layer 1410 may extend along the second direction X, and its portion corresponding to the semiconductor pillar 1210 may be used as a gate electrode, and together with the corresponding gate dielectric layer 1630, it may constitute a gate structure; and its remaining portion may be used as a gate electrode for connecting the gate structure to the contact structure 1700 ( Fig.36 or Fig.37 ) connected word lines.

[0101] By way of example, the third gap may be formed by an etching process such as punch-down etching, dry etching and / or wet etching to form two disconnected initial conductive structures 1420 in the third trench 310. By way of example, a bottom punch-down etching process may be used to disconnect the initial conductive structure 1420 at the bottom of the third trench 310 until the first dielectric layer 1610 is exposed. By way of example, one or more thin film deposition processes may be used to deposit and form the second dielectric layer 1640 in the second gap and the third gap. In other words, the second dielectric layer 1640 may be deposited and formed in the remaining space of the third trench 310. The material of the second dielectric layer 1640 includes, but is not limited to, silicon oxide.

[0102] Fig.32 and Fig.33 is a schematic diagram of a structure for forming an isolation structure 1500 according to an exemplary embodiment of the present application, wherein: Fig.33 for Fig.32 Cross-sectional view along DD direction.

[0103] For example, Fig.32 and Fig.33 As shown, the protective layer 1330 and the remaining second sacrificial layer 1320 may be removed to form a fourth gap 600; and an isolation structure 1500 may be formed in the fourth gap 600. For example, the fourth gap 600 may be formed by a photolithography process, one or more dry etching and / or wet etching processes, and the isolation structure 1500 may be formed by one or more thin film deposition processes. Exemplarily, the material of the isolation structure 1500 may include, but is not limited to, metal materials such as tungsten and copper. Exemplarily, as Fig.33 As shown, an etch-back process may be used to remove a portion of the isolation structure 1500 along the third direction Z, and a dielectric material may be filled in the removed space.

[0104] For example, Fig.32As shown, a through hole 700 penetrating the gate dielectric layer 1630 and the initial conductive structure 1420 along the third direction Z may be formed to separate the annular gate dielectric layer 1630 and the initial conductive structure 1420 in the third trench 310 into at least two parts. For example, two through holes 700 with a certain interval may be formed in each of the annular gate dielectric layer 1630 and the initial conductive structure 1420 to separate the annular gate dielectric layer 1630 and the initial conductive structure 1420 into two parts. In other words, the two through holes 700 separate the annular gate dielectric layer 1630 into two parts, and separate the initial conductive structure 1420 into two parts.

[0105] It should be understood that the present application does not specifically limit the size and / or position of the through hole 700, and the size and / or position of the through hole 700 can be arbitrarily set according to the actual process to separate the gate dielectric layer 1630 and the initial conductive structure 1420 in the third trench 310 into two parts.

[0106] Fig.34 and Fig.35 is a schematic structural diagram of forming a conductive structure 1400 according to an exemplary embodiment of the present application, wherein: Fig.35 for Fig.34 Cross-sectional view along DD direction.

[0107] For example, Fig.34 and Fig.35 As shown, at least a portion of the initial conductive structure 1420 located in the non-storage region B may be removed to form the conductive structure 1400. In other words, the non-storage region B may not be provided with the conductive structure 1400, or the conductive structure 1400 in the non-storage region B may be discontinuous.

[0108] Fig.36 and Fig.37 They are two schematic diagrams of forming a contact structure 1700 according to an exemplary embodiment of the present application. It should be understood that in the present application, Fig.36 or Fig.37 The contact structure 1700 shown may be in Fig.17 or Fig.35 The semiconductor structure shown is formed on the basis of

[0109] In the exemplary embodiment of the present application, Fig.36 or Fig.37 As shown, the isolation structure 1500 may include a first isolation structure 1510 located at the second sidewall of the semiconductor pillar 1210 and a second isolation structure (not shown) located in the non-memory region B.

[0110] Forming the contact structure 1700 connected to the conductive structure 1400 may include: etching back a portion of the first isolation structure 1510 along the third direction Z, and forming a third dielectric layer 1650 in the etched back space; and forming the contact structure 1700 on one side of the conductive structure 1400 corresponding to the third dielectric layer 1650. In an exemplary embodiment of the present application, Fig.36 As shown, a contact structure 1700 connected to an end of the conductive structure 1400 away from the first dielectric layer 1610 may be formed. In another exemplary embodiment of the present application, as Fig.37 As shown, a contact structure 1700 connected to an end of the conductive structure 1400 close to the first dielectric layer 1610 may be formed.

[0111] The present application sets a contact structure 1700 to connect with the conductive structure 1400, so as to realize the connection between the word line (the portion of the conductive structure 1400 extending along the second direction X) and the contact structure 1700, thereby facilitating the transmission of electrical signals between the gate structure and the peripheral circuit through the contact structure 1700 and the word line. The present application can reduce the electrical connection between the contact structure 1700 and the first isolation structure 1510 by etching back part of the first isolation structure 1510.

[0112] For example, the contact structure 1700 may be formed by a combination of one or more dry etching and / or wet etching processes, and one or more thin film deposition processes, etc. The material of the contact structure 1700 may include, but is not limited to, metal materials such as tungsten and copper.

[0113] Fig.38 and Fig.39 They are two schematic diagrams of forming the lead-out structure 1800 according to the exemplary embodiments of the present application. It should be understood that in the present application, Fig.38 or Fig.39 The lead-out structure 1800 shown may be Fig.36 or Fig.37 The semiconductor structure shown is formed on the basis of

[0114] In the exemplary embodiment of the present application, Fig.38 or Fig.39 As shown, a lead-out structure 1800 connected to the isolation structure 1500 may be formed in the non-memory region B.

[0115] Exemplarily, the isolation structure 1500 may include a first isolation structure 1510 located at the second sidewall of the semiconductor pillar 1210 and a second isolation structure 1520 located in the non-storage region B. A lead-out structure 1800 connected to the isolation structure 1500 may be formed in the non-storage region B, which may include: a lead-out structure 1800 connected to the second isolation structure 1520 may be formed in the non-storage region B.

[0116] In an exemplary embodiment of the present application, Fig.38 As shown, forming a lead-out structure 1800 connected to the isolation structure 1500 in the non-storage area B may include: forming a lead-out hole 1810 in the non-storage area B extending along a third direction Z to the second isolation structure 1520; and forming the lead-out structure 1800 in the lead-out hole 1810.

[0117] By way of example, a dielectric layer may be formed on the surface of the non-storage area B, and a plurality of lead holes 1810 extending along the third direction Z to the second isolation structure 1520 may be formed in the dielectric layer, wherein the plurality of lead holes 1810 may be arranged along the first direction Y. Then, a conductive material may be filled in the lead holes 1810 to form a lead structure 1800. By way of example, the lead structure 1800 and the contact structure 1700 may be located on the same side of the conductive structure 1400; of course, the lead structure 1800 and the contact structure 1700 may also be located on opposite sides of the conductive structure 1400.

[0118] For example, a dielectric layer may be formed on the surface of the non-storage area B by one or more thin film deposition processes. The lead-out hole 1810 may be formed by etching by one or more dry etching and / or wet etching processes.

[0119] In another exemplary embodiment of the present application, Fig.39 As shown, a lead-out structure 1800 connected to the isolation structure 1500 is formed in the non-storage area B, which may include: forming a lead-out groove 1820 in the non-storage area B extending along the third direction Z to the second isolation structure 1520 and extending along the first direction Y; and forming the lead-out structure 1800 in the lead-out groove 1820.

[0120] By way of example, a dielectric layer may be formed on the surface of the non-storage area B, and a lead-out groove 1820 may be formed in the dielectric layer, extending along the third direction Z to the second isolation structure 1520 and extending along the first direction Y. Then, a conductive material may be filled in the lead-out groove 1820 to form a lead-out structure 1800. By way of example, the lead-out structure 1800 and the contact structure 1700 may be located on the same side of the conductive structure 1400; of course, the lead-out structure 1800 and the contact structure 1700 may also be located on opposite sides of the conductive structure 1400.

[0121] For example, a dielectric layer may be formed on the surface of the non-storage area B by one or more thin film deposition processes. The lead-out groove 1820 may be formed by etching by one or more dry etching and / or wet etching processes.

[0122] In the present application, the lead-out structure 1800 may be grounded or a certain fixed potential may be applied to the lead-out structure 1800. The isolation structures 1500 of multiple storage areas may be connected together and connected to the lead-out structure 1800 of the non-storage area B, so that the isolation structure 1500 may electrically insulate the adjacent semiconductor pillars 1210 and reduce the coupling phenomenon between the adjacent semiconductor pillars 1210. In addition, this arrangement of the present application may also reduce the number of lead-out structures 1800, reduce the lead-out space of the isolation structure 1500, and reduce the lead-out difficulty of the isolation structure 1500.

[0123] As described above, the present application provides two processes for forming the conductive structure 1400 and the isolation structure 1500, two processes for forming the contact structure 1700, and two processes for forming the lead-out structure 1800. Specifically, Figures 2 to 17 A process for forming a conductive structure 1400 and an isolation structure 1500 is shown. Figures 18 to 35 Another process for forming the conductive structure 1400 and the isolation structure 1500 is shown; Fig.36 and Fig.37 Two processes for forming the contact structure 1700 are shown respectively; and Fig.38 and Fig.39 Two processes for forming the lead-out structure 1800 are shown respectively.

[0124] It should be understood that in the method 1000 for manufacturing a semiconductor structure provided in the present application, the process of forming the conductive structure 1400 and the isolation structure 1500, the process of forming the contact structure 1700, and the process of forming the lead-out structure 1800 can be combined with each other, that is, the present application provides at least eight exemplary embodiments above to introduce the method 1000 for manufacturing a semiconductor structure.

[0125] Fig.38 and Fig.39 They are respectively schematic structural diagrams of semiconductor structures according to exemplary embodiments of the present application.

[0126] The semiconductor structure may include a semiconductor layer 1100 ( Fig.37 ), a conductive structure 1400, an isolation structure 1500 and a lead-out structure 1800.

[0127] The semiconductor layer 1100 may include a plurality of storage areas A and at least one non-storage area B. The storage areas A and the non-storage areas B may both extend along a first direction Y and be arranged along a second direction X. The storage area A may include a plurality of semiconductor pillars 1210 extending along a third direction Z, wherein the first direction Y, the second direction X, and the third direction Z may be perpendicular to each other. The storage area A may be used to form a storage array (including a conductive structure 1400) including a plurality of storage cells, and the non-storage area B may be used to form a wiring lead-out structure (including a lead-out structure 1800). Exemplarily, the non-storage area B may be located between two adjacent storage areas A, or may be located on one side of the plurality of storage areas A.

[0128] Although the present application only exemplifies that the non-storage area B is located between two adjacent storage areas A, it should be understood that the present application does not specifically limit the position of the non-storage area B. In actual processes, the position of the non-storage area B can be reasonably set according to actual needs, such as the non-storage area B can also be set on one side of multiple storage areas A, and the present application does not make specific restrictions on this.

[0129] The semiconductor pillar 1210 may have the same material as the semiconductor layer 1100 and may extend in the semiconductor layer 1100 along the third direction Z. The conductive structure 1400 may be located at a first sidewall of the semiconductor pillar 1210 and extend in the second direction X within the storage region A.

[0130] Exemplarily, the semiconductor structure further includes a gate dielectric layer 1630 located between the conductive structure 1400 and the semiconductor pillar 1210. The conductive structure 1400 may include a first conductive layer located inside the gate dielectric layer 1630 and a second conductive layer located inside the first conductive layer. The material of the first conductive layer may include but is not limited to titanium nitride TiN. The material of the second conductive layer may include but is not limited to metal tungsten W. The material of the gate dielectric layer 1630 may include but is not limited to oxides such as silicon oxide. The portion of the conductive structure 1400 corresponding to the semiconductor pillar 1210 may serve as a gate electrode. The conductive structure 1400 and the corresponding gate dielectric layer 1630 may together constitute a gate structure.

[0131] The isolation structure 1500 may extend through the storage area A and the non-storage area B along the second direction X, and a portion of the isolation structure 1500 is located at the second sidewall of the semiconductor pillar 1210, which is opposite to the first sidewall. The material of the isolation structure 1500 may include, but is not limited to, metal materials such as tungsten and copper. For example, the isolation structure 1500 may include a first isolation structure 1510 located at the second sidewall of the semiconductor pillar 1210 and a second isolation structure 1520 located in the non-storage area B.

[0132] By way of example, the semiconductor structure may further include a third dielectric layer 1650 and a contact structure 1700. The third dielectric layer 1650 may be located on one side of the isolation structure 1500 and connected to the isolation structure 1500. The contact structure 1700 may be located on one side of the conductive structure 1400 corresponding to the third dielectric layer 1650 and connected to the conductive structure 1400. By way of example, the third dielectric layer 1650 may be located on one side of the first isolation structure 1510 and connected to the first isolation structure 1510.

[0133] The present application provides a contact structure 1700 connected to the conductive structure 1400, so as to realize the connection between the word line (the portion of the conductive structure 1400 extending along the second direction X) and the contact structure 1700, thereby facilitating the transmission of electrical signals between the gate structure and the peripheral circuit through the contact structure 1700 and the word line. The present application provides a third dielectric layer 1650, so as to reduce the electrical connection between the contact structure 1700 and the first isolation structure 1510.

[0134] The lead-out structure 1800 may be disposed in the non-storage region B and connected to the isolation structure 1500. In an exemplary embodiment of the present application, Fig.38 As shown, the lead-out structure 1800 may include a plurality of sub-lead-out structures. Each sub-lead-out structure may be connected to the isolation structure 1500 and arranged along the first direction Y. In another exemplary embodiment of the present application, Fig.39 As shown, the lead-out structure 1800 may extend along the first direction Y. For example, the lead-out structure 1800 may be connected to the second isolation structure 1520. For example, the lead-out structure 1800 and the contact structure 1700 may be located on the same side of the conductive structure 1400; of course, the lead-out structure 1800 and the contact structure 1700 may also be located on opposite sides of the conductive structure 1400.

[0135] In the present application, the lead-out structure 1800 may be grounded or a certain fixed potential may be applied to the lead-out structure 1800. The isolation structures 1500 of multiple storage areas may be connected together and connected to the lead-out structure 1800 of the non-storage area B, so that the isolation structure 1500 may electrically insulate the adjacent semiconductor pillars 1210 and reduce the coupling phenomenon between the adjacent semiconductor pillars 1210. In addition, this arrangement of the present application may also reduce the number of lead-out structures 1800, reduce the lead-out space of the isolation structure 1500, and reduce the lead-out difficulty of the isolation structure 1500.

[0136] Exemplarily, the semiconductor structure may further include a second dielectric layer 1640 ( Fig.35 The material of the second dielectric layer 1640 may include, but is not limited to, silicon oxide. The second dielectric layer 1640 may be used to separate adjacent conductive structures 1400.

[0137] Exemplarily, the semiconductor structure may further include a source and a drain respectively disposed at both ends of the semiconductor column 1210. Exemplarily, the source and the drain at both ends of the semiconductor column 1210 may be connected to the capacitor and the bit line, respectively. Exemplarily. The capacitor may be coupled to the drain of the semiconductor column 1210 to be charged or discharged through the drain. The bit line may be coupled to the source region of the semiconductor column 1210 and serve as a path for charging or discharging the capacitor. The word line (the portion of the conductive structure 1400 extending along the second direction X) may be coupled to the gate electrode (the portion of the conductive structure 1400 corresponding to the semiconductor column 1210) to turn on or off the transistor (including the semiconductor column 1210, the conductive structure 1400, and the portion of the gate dielectric layer 1630 corresponding to the semiconductor column).

[0138] Since the contents and structures involved in the method 1000 for manufacturing a semiconductor structure described above may be fully or partially applicable to the semiconductor structure described herein, the contents related or similar thereto will not be described in detail herein.

[0139] Although the exemplary structure and method of making the semiconductor structure are described herein, it is understood that one or more features may be omitted, replaced or added from the method of making the semiconductor structure. In addition, the illustrated layers and materials thereof are merely exemplary.

[0140] Fig.40 is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application.

[0141] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device having the storage system 12 located therein). Fig.40 As shown, the system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to or from the three-dimensional memory 14.

[0142] The three-dimensional memory 14 may include a semiconductor structure described in any embodiment of the present application. According to some embodiments, the controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media card (eMMC) used as a data storage device for mobile devices, and an enterprise storage array, and the mobile device is a smart phone, a tablet computer, a laptop computer, etc. The controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction code (ECC) related to data read from or written to the three-dimensional memory 14. Any other appropriate function may also be performed by the controller 16, for example, formatting the three-dimensional memory 14. The controller 16 may communicate with an external device (e.g., a host 18) according to a specific communication protocol. For example, the controller 16 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0143] The controller 16 and the one or more three-dimensional memories 14 may be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 may be implemented and packaged into different types of final electronic products. Fig.41AIn one example shown in FIG, the controller 16 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a computer that connects the memory card 22 to a host (e.g., Fig.40 The host 18 in the memory card connector 24 is coupled. Fig.41B In another example shown in FIG. 1 , the controller 16 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Fig.40 In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than the storage capacity and / or operating speed of the memory card 22.

[0144] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The semiconductor layer includes a plurality of storage areas and at least one non-storage area, the storage areas and the non-storage areas both extend along a first direction and are arranged along a second direction, the storage area includes a plurality of semiconductor pillars extending along a third direction, the first direction, the second direction and the third direction are perpendicular to each other, and the method includes: forming a conductive structure in the storage area and extending along the second direction, and forming an isolation structure extending through the storage area and the non-storage area along the second direction, wherein the conductive structure is located at a first sidewall of the semiconductor pillar, and a portion of the isolation structure is located at a second sidewall of the semiconductor pillar opposite to the first sidewall; and A lead-out structure connected to the isolation structure is formed in the non-storage area.

2. The method according to claim 1, characterized in that A conductive structure is formed in the storage area and extends along the second direction, and an isolation structure is formed extending through the storage area and the non-storage area along the second direction, including: forming a plurality of initial semiconductor pillars extending along the first direction in the storage area; forming a third trench in the storage area, passing through the initial semiconductor pillar and extending along the second direction, and forming a fourth trench extending along the second direction passing through the initial semiconductor pillar and the non-storage area, wherein the third trench and the fourth trench divide the initial semiconductor pillar into a plurality of semiconductor pillars, and a width of the third trench is greater than a width of the fourth trench; and The conductive structure is formed in the third trench, and the isolation structure is formed in the fourth trench.

3. The method according to claim 1, characterized in that forming a conductive structure extending along the second direction in the storage area, and forming an isolation structure extending through the storage area and the non-storage area along the second direction, including: forming a plurality of initial semiconductor pillars extending along the first direction in the storage area; forming third trenches and fourth trenches alternately arranged along the first direction and extending through the initial semiconductor pillars and the non-storage area along the second direction, wherein the third trenches and the fourth trenches divide the initial semiconductor pillars into a plurality of semiconductor pillars, and the width of the third trenches is greater than the width of the fourth trenches; forming an initial conductive structure in the third trench, and forming the isolation structure in the fourth trench; and At least a portion of the initial conductive structure located in the non-storage area is removed to form the conductive structure.

4. The method according to claim 2 or 3, characterized in that: A plurality of initial semiconductor pillars extending along the first direction are formed in the storage area, comprising: forming a plurality of first trenches extending along the first direction in the storage area, and forming a second trench extending along the first direction in the non-storage area, wherein the width of the second trench is greater than the width of the first trench; and A filling dielectric layer is formed in the first trench and the second trench, wherein the semiconductor layer in the storage area that has not been removed forms an initial semiconductor column.

5. The method according to claim 2, characterized in that: forming a third trench in the storage area, passing through the initial semiconductor column and extending along the second direction, and forming a fourth trench extending through the initial semiconductor column and the non-storage area along the second direction, comprising: forming an initial third trench in the storage area, passing through the initial semiconductor column and extending along the second direction, and forming a fourth trench extending along the second direction passing through the initial semiconductor column and the non-storage area; forming a first sacrificial layer and a second sacrificial layer in the initial third trench and the fourth trench respectively; removing a portion of the second sacrificial layer along a third direction, and forming a protective layer in the removed space; and The first sacrificial layer is removed, and the width and depth of the initial third trench are increased to form the third trench.

6. The method according to claim 5, characterized in that The conductive structure is formed in the third trench, and the isolation structure is formed in the fourth trench, including: forming a first dielectric layer in the third trench; removing a portion of the first dielectric layer along the third direction to form a first gap; forming a gate dielectric layer on a sidewall of the first gap; forming a conductive layer inside the gate dielectric layer; removing part of the conductive layer along the third direction to form a second gap; forming a third gap along the third direction through the conductive layer to expose the first dielectric layer, wherein the conductive layer that is not removed forms the conductive structure; forming a second dielectric layer in the second gap and the third gap; removing the protective layer and the remaining second sacrificial layer to form a fourth gap; and The isolation structure is formed in the fourth gap.

7. The method according to claim 1, characterized in that The method further comprises: A contact structure connected to the conductive structure is formed.

8. The method according to claim 7, characterized in that The isolation structure includes a first isolation structure located at the second sidewall of the semiconductor column and a second isolation structure located in the non-storage area, forming a contact structure connected to the conductive structure, including: Carving back a portion of the first isolation structure along the third direction, and forming a third dielectric layer in the etched-back space; and The contact structure is formed on a side of the conductive structure corresponding to the third dielectric layer.

9. The method according to claim 1, characterized in that: A lead-out structure connected to the isolation structure is formed in the non-storage area, comprising: forming a lead-out hole in the non-storage area extending along the third direction to the isolation structure; and A lead-out structure is formed in the lead-out hole.

10. The method according to claim 1, characterized in that A lead-out structure connected to the isolation structure is formed in the non-storage area, comprising: forming a lead-out groove in the non-storage area, the lead-out groove extending along the third direction to the isolation structure and extending along the first direction; and A lead-out structure is formed in the lead-out groove.

11. A semiconductor structure, characterized in that: include: A semiconductor layer, comprising a plurality of storage areas and at least one non-storage area, wherein the storage areas and the non-storage areas both extend along a first direction and are arranged along a second direction, wherein the storage area comprises a plurality of semiconductor pillars extending along a third direction, wherein the first direction, the second direction and the third direction are perpendicular to each other; a conductive structure, located at a first side wall of the semiconductor column and extending along the second direction in the storage area; an isolation structure extending through the storage area and the non-storage area along the second direction, and a portion of the isolation structure is located at a second sidewall of the semiconductor column opposite to the first sidewall; as well as A lead-out structure is arranged in the non-storage area and connected to the isolation structure.

12. The semiconductor structure according to claim 11, characterized in that: The semiconductor structure further comprises: a gate dielectric layer located between the conductive structure and the semiconductor pillar, wherein the conductive structure comprises a first conductive layer located inside the gate dielectric layer and a second conductive layer located inside the first conductive layer; and The second dielectric layer is located inside the second conductive layer.

13. The semiconductor structure according to claim 11, characterized in that: The material of the isolation structure includes metal, and the semiconductor structure further includes: The third dielectric layer is located at one side of the isolation structure and connected to the isolation structure.

14. The semiconductor structure according to claim 13, characterized in that: The semiconductor structure further comprises: The contact structure is located on a side of the conductive structure corresponding to the third dielectric layer and is connected to the conductive structure.

15. The semiconductor structure according to claim 11, characterized in that The lead-out structure comprises: A plurality of sub-lead-out structures are connected to the isolation structure and arranged along the first direction.

16. The semiconductor structure according to claim 11, characterized in that The lead-out structure extends along the first direction.

17. The semiconductor structure according to claim 11, characterized in that The semiconductor structure further includes a source and a drain respectively disposed at two ends of the semiconductor column.

18. A storage system, characterized in that: include: At least one three-dimensional memory, each of the three-dimensional memory comprising a semiconductor structure as claimed in any one of claims 11 to 17; as well as The controller is coupled to the semiconductor structure and is used for controlling the three-dimensional memory to store data.

Images