Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention belongs to the field of semiconductors, and particularly relates to a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method of the semiconductor structure comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a front surface and a back surface which are oppositely arranged; forming a to-be-patterned functional layer with first stress on the front surface of the semiconductor substrate; a stress adjusting layer with second stress is formed on the back face of the semiconductor substrate, and the first stress and the second stress are stress of the same type, the semiconductor substrate is in a flat plate shape or an arch shape with the edge bent towards one side deviating from the to-be-patterned functional layer under the action of the to-be-patterned functional layer and the stress adjusting layer, and the bending degree of the arch shape meets set parameters; and after the stress adjusting layer is formed, performing patterning processing on the functional layer to be patterned. According to the scheme, the yield of the semiconductor structure can be improved.

Description

Technical Field

[0001] The present disclosure belongs to the field of semiconductors, and in particular relates to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] As semiconductor structures such as DRAM (Dynamic Random Access Memory) chips develop towards smaller sizes, in order to make smaller structures, a method of transferring patterns downward layer by layer is usually used to achieve smaller sizes. The stress generated in these manufacturing processes will cause large bending deformations of semiconductor substrates such as wafers, which in turn causes distortion of the final device, leading to device failure, low yield and other problems. Summary of the invention

[0003] The embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and a semiconductor structure to improve product yield.

[0004] A first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

[0005] Providing a semiconductor substrate, wherein the semiconductor substrate has a front side and a back side that are oppositely disposed;

[0006] forming a functional layer to be patterned having a first stress on the front surface of the semiconductor substrate;

[0007] A stress adjustment layer having a second stress is formed on the back side of the semiconductor substrate, wherein the first stress and the second stress are of the same type, so that the semiconductor substrate is in a flat plate shape or an arch shape with an edge bent away from the functional layer to be patterned under the action of the functional layer to be patterned and the stress adjustment layer, and the bending degree of the arch shape meets the set parameters;

[0008] After forming the stress adjustment layer, the functional layer to be patterned is patterned.

[0009] In an exemplary embodiment of the present disclosure, the first stress and the second stress are both compressive stresses, and the first stress is greater than or equal to the second stress.

[0010] In an exemplary embodiment of the present disclosure, the step of forming a stress adjustment layer having a second stress on the back side of the semiconductor substrate includes:

[0011] forming a patterned regulating film layer on the back side of the semiconductor substrate, wherein the patterned regulating film layer has a plurality of strip-shaped regulating structures arranged at intervals;

[0012] A compressive stress regulating film layer is formed, wherein the compressive stress regulating film layer has a filling portion and a covering portion, wherein the filling portion is filled between adjacent strip regulating structures, and the covering portion covers the patterned regulating film layer and a side of the filling portion away from the semiconductor substrate.

[0013] In an exemplary embodiment of the present disclosure, the step of patterning the functional layer to be patterned includes:

[0014] forming a photoresist pattern layer on a side of the functional layer to be patterned away from the semiconductor substrate, wherein the photoresist pattern layer comprises a plurality of photoresist mask strips arranged at intervals;

[0015] Performing patterning processing on the functional layer to be patterned based on the photoresist pattern layer;

[0016] Wherein, the extending direction of the photoresist mask strip is perpendicular to the extending direction of the strip-shaped adjustment structure.

[0017] In an exemplary embodiment of the present disclosure, the compressive stress regulating film layer comprises a compressive stress silicon oxide film; and / or

[0018] The compressive stress adjustment film layer includes a compressive stress polysilicon film.

[0019] In an exemplary embodiment of the present disclosure, the step of forming a stress adjustment layer having a second stress on the back side of the semiconductor substrate further includes:

[0020] An anti-stripping adjustment film layer is formed on the back side of the semiconductor substrate, the anti-stripping adjustment film layer is located on the side of the patterned adjustment film layer close to the semiconductor substrate, and the thermal expansion coefficient of the anti-stripping adjustment film layer is between the thermal expansion coefficient of the semiconductor substrate and the thermal expansion coefficient of the patterned adjustment film layer.

[0021] In an exemplary embodiment of the present disclosure, the area between the adjacent strip-shaped adjustment structures in the patterned adjustment film layer is a hollow area, and in the hollow area, the filling portion is in contact with the anti-peeling adjustment film layer.

[0022] In an exemplary embodiment of the present disclosure, the semiconductor substrate includes a silicon wafer, the anti-stripping adjustment film layer includes an anti-stripping silicon oxide film, and the patterned adjustment film layer includes a patterned silicon nitride film.

[0023] In an exemplary embodiment of the present disclosure, the step of forming an anti-peeling adjustment film layer includes:

[0024] Performing oxidation treatment on the back side of the silicon wafer by using a thermal oxidation process to form the anti-stripping silicon oxide film; or

[0025] A silicon oxide material is deposited on the back side of the silicon wafer by using a deposition process to form the anti-stripping silicon oxide film.

[0026] In an exemplary embodiment of the present disclosure, the functional layer to be patterned includes a compressive stress silicon oxide film; and / or

[0027] The functional layer to be patterned includes a compressive stress polysilicon film.

[0028] In an exemplary embodiment of the present disclosure, during the process of patterning the functional layer to be patterned, the manufacturing method further includes:

[0029] Based on the stress variation of the film layer on the front surface of the semiconductor substrate, the stress adjustment layer is thinned or removed so that the semiconductor substrate is kept in the flat plate shape or the arch shape.

[0030] In an exemplary embodiment of the present disclosure, the functional layer to be patterned includes at least one hard mask functional film layer having a first stress, and the step of patterning the functional layer to be patterned includes:

[0031] Performing patterning on the hard mask functional film layer to form a hard mask pattern layer;

[0032] performing patterning processing on a structure located under the hard mask pattern layer based on the hard mask pattern layer, and then removing the hard mask pattern layer;

[0033] Wherein, after removing the hard mask pattern layer, the stress adjustment layer is thinned or removed.

[0034] In an exemplary embodiment of the present disclosure, the hard mask functional film layer has N layers and is stacked, and the step of patterning the functional layer to be patterned includes:

[0035] Performing patterning on the n-th hard mask functional film layer to form an n-th hard mask pattern layer, where 1<n≤N, and N and n are both integers;

[0036] performing patterning processing on the n-1th hard mask functional film layer based on the nth hard mask pattern layer to form an n-1th hard mask pattern layer;

[0037] removing the nth hard mask pattern layer;

[0038] Wherein, after each hard mask pattern layer is removed, the stress adjustment layer is thinned to keep the semiconductor substrate in the flat plate shape or the arch shape.

[0039] In an exemplary embodiment of the present disclosure, the functional layer to be patterned further includes a target device functional film layer, which is located on a side of the first hard mask functional film layer close to the semiconductor substrate; wherein,

[0040] After forming the first hard mask pattern layer, patterning the target device functional film layer based on the first hard mask pattern layer to form a target device pattern layer;

[0041] The first hard mask pattern layer is removed.

[0042] In an exemplary embodiment of the present disclosure, before the step of forming a stress adjustment layer on the back side of the semiconductor substrate, the manufacturing method further includes:

[0043] forming a protective film layer on a side of the functional layer to be patterned away from the semiconductor substrate;

[0044] After forming the protective film layer, turning over the semiconductor substrate so that the back side of the semiconductor substrate faces upward;

[0045] Wherein, after forming the stress adjustment layer and before patterning the functional layer to be patterned, the manufacturing method further includes:

[0046] The semiconductor substrate is turned over so that the front side of the semiconductor substrate faces upward.

[0047] In an exemplary embodiment of the present disclosure, the protection film layer includes an amorphous carbon film layer.

[0048] In an exemplary embodiment of the present disclosure, before patterning the functional layer to be patterned, the manufacturing method further includes:

[0049] Performing patterning on the amorphous carbon film layer to form an amorphous carbon pattern layer;

[0050] Wherein, the amorphous carbon pattern layer is used as a mask to perform patterning on the functional layer to be patterned.

[0051] In an exemplary embodiment of the present disclosure, the step of patterning the functional layer to be patterned includes:

[0052] Patterning the functional layer to be patterned by using a self-aligned M-patterning process or a reverse self-aligned M-patterning process;

[0053] Here, M is an even number greater than or equal to 2.

[0054] A second aspect of the present disclosure provides a semiconductor structure manufactured using any of the aforementioned manufacturing methods.

[0055] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: before patterning the functional layer to be patterned on the front side of the semiconductor substrate, a stress adjustment layer is first formed on the back side of the semiconductor substrate, and the stress adjustment layer has the same type of stress as the functional layer to be patterned. Since the stress adjustment layer has the same type of stress as the functional layer to be patterned, the stress generated by the stress adjustment layer on the semiconductor substrate is opposite to the stress generated by the functional layer to be patterned on the semiconductor substrate. In this way, the bending deformation of the semiconductor substrate can be adjusted or improved, so that the semiconductor substrate is in a flat shape or an arch shape with a bending degree that meets the set parameters under the action of the functional layer to be patterned and the stress adjustment layer, that is, the bending deformation degree of the semiconductor substrate is reduced, so that the functional layer to be patterned is in a flat state or a tensioned state to a certain extent before the patterning process, thereby reducing the bending degree of the pattern layer generated after the functional layer to be patterned is patterned, ensuring the performance of the generated pattern layer, and then improving the yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0057] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is shown.

[0058] Figures 2 to 18 A structural schematic diagram corresponding to each step in the method for manufacturing a semiconductor structure shown in an embodiment of the present disclosure is shown.

[0059] Fig.19 It is a schematic structural diagram showing that the semiconductor substrate in the semiconductor structure shown in an embodiment of the present disclosure is in an arch shape.

[0060] Description of reference numerals:

[0061] 10. semiconductor substrate; 101. front side; 102. back side;

[0062] 20, functional layer to be patterned; 201, target device functional film layer; 2011, target device strip; 202, first hard mask functional film layer; 2021, first hard mask strip; 203, second hard mask functional film layer; 2031, second hard mask strip;

[0063] 30. protective film layer; 301. protective mask strip;

[0064] 40, stress adjustment layer; 401, anti-peeling adjustment film layer; 402, adjustment film layer to be patterned; 4021, strip adjustment structure; 403, compressive stress adjustment film layer; 4031, filling part; 4032, covering part;

[0065] 50. A first photoresist mask strip;

[0066] 60. sacrificial material layer; 601. sacrificial mask strip;

[0067] 70. A second photoresist mask strip;

[0068] 80, intermediate film; 801, gap wall;

[0069] 90, top film; 901, auxiliary mask strip;

[0070] X, first direction; Y, second direction. DETAILED DESCRIPTION

[0071] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0072] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0073] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0074] As DRAM chips develop towards smaller sizes, in order to make smaller structures, the embodiments of the present disclosure use a self-aligned M-repetitive patterning process or a reverse self-aligned M-repetitive patterning process to pattern the functional layer to be patterned on the front side of the semiconductor substrate, where M is an even number greater than or equal to 2.

[0075] It should be understood that M is not limited to being equal to 2 or equal to 4, but may also be equal to 6, 8, etc., depending on the specific circumstances.

[0076] Among them, the above-mentioned self-aligned M-weight patterning processes all require the use of a method of transferring the patterned structure downward layer by layer to achieve a smaller size, but often the stacking of multiple film layers will produce extremely large stress, causing a large bend in the semiconductor substrate. In the process of transferring the patterned structure downward, the film layers will be removed layer by layer, the stress will change, and the patterned structure will be deformed under the action of stress. The deformed patterned structure continues to be transferred downward, resulting in distortion of the final required functional structure and failure of the device function.

[0077] In order to improve the bending deformation of the semiconductor substrate, an annealing process can be used to release stress. However, during the patterning process, the annealing process has the following two problems:

[0078] 1. Stress cannot be released by bending, and some materials may even undergo crystal phase changes, resulting in greater stress.

[0079] 2. It affects the peripheral circuits. The peripheral circuits experience more thermal budget (heat accumulation), which affects the performance of the semiconductor structure.

[0080] Based on this, combined Figures 1 to 18 As shown, the present disclosure provides a method for manufacturing a semiconductor structure, which may include:

[0081] Step S100, providing a semiconductor substrate 10, wherein the semiconductor substrate 10 has a front surface 101 and a back surface 102 disposed opposite to each other. For example, the semiconductor substrate 10 may include a silicon wafer, but is not limited thereto, and may also include other semiconductor materials;

[0082] Step S110 , forming a functional layer 20 to be patterned having a first stress on the front surface 101 of the semiconductor substrate 10 ;

[0083] Step S120, forming a stress adjustment layer 40 having a second stress on the back side 102 of the semiconductor substrate 10, wherein the first stress and the second stress are the same type of stress, so that the semiconductor substrate 10 is in a flat plate shape or an arch shape with an edge bent toward a side away from the functional layer 20 to be patterned under the action of the functional layer 20 to be patterned and the stress adjustment layer 40, and the curvature of the arch shape meets the set parameters;

[0084] Step S130 , after forming the stress adjustment layer 40 , patterning the functional layer 20 to be patterned.

[0085] In the present embodiment, before patterning the functional layer 20 to be patterned on the front side 101 of the semiconductor substrate 10, a stress adjustment layer 40 is first formed on the back side 102 of the semiconductor substrate 10. The stress adjustment layer 40 has the same type of stress as the functional layer 20 to be patterned. Since the stress adjustment layer 40 has the same type of stress as the functional layer 20 to be patterned, the stress generated by the stress adjustment layer 40 on the semiconductor substrate 10 is opposite to the stress generated by the functional layer 20 to be patterned on the semiconductor substrate 10. In this way, the bending deformation of the semiconductor substrate 10 can be adjusted or improved, so that the semiconductor substrate 10 is in a flat plate shape or an arch shape with a bending degree that meets the set parameters under the action of the functional layer 20 to be patterned and the stress adjustment layer 40, that is, the bending deformation degree of the semiconductor substrate 10 is reduced, so that the functional layer 20 to be patterned is in a flat state or a tensioned state to a certain extent before the patterning process, thereby reducing the bending degree of the pattern layer generated after the functional layer 20 to be patterned is patterned, ensuring the performance of the generated pattern layer, and then improving the yield of the semiconductor structure.

[0086] In addition, since the stress adjustment layer 40 has the same type of stress as the functional layer 20 to be patterned, it is convenient to balance the stress on both sides of the front side 101 and the back side 102 of the semiconductor substrate 10 when patterning the functional layer 20 to be patterned.

[0087] Specifically, in the process of patterning the patterned functional layer 20, the manufacturing method of this embodiment may further include:

[0088] Based on the stress change of the film layer on the front side 101 of the semiconductor substrate 10, the stress adjustment layer 40 is thinned or removed so that the stress of the film layer on the front side 101 and the back side 102 of the semiconductor substrate 10 always remains within a certain stress range, thereby keeping the semiconductor substrate 10 in a flat plate shape or the arch shape mentioned above, and making the film layer on the front side 101 of the semiconductor substrate 10 in a flat state or a tensioned state, so as to ensure that the structure generated by the patterning is pulled straighter, so that the structure generated by the patterning can achieve a straight transfer effect when it is transferred between layers, thereby avoiding or improving the distortion of the final patterned structure.

[0089] It should be noted that the flat plate shape mentioned in this embodiment means that the front side 101 and the back side 102 of the semiconductor substrate 10 are parallel planes to each other, and the semiconductor substrate 10 has no bending deformation or the bending deformation is very small and can be ignored.

[0090] In this embodiment, the semiconductor substrate 10 can always maintain an arch shape that meets set requirements, which has a certain tensioning effect on the film layer of the front side 101 of the semiconductor substrate 10 to reduce distortion and other conditions during the patterning process.

[0091] refer to Fig.19 As shown, when the semiconductor substrate 10 is in an arch shape, the aforementioned setting parameters may include: the vertical distance H between the edge of the semiconductor substrate 10 and its center is less than or equal to 30 μm, so as to prevent the front surface 101 film layer of the semiconductor substrate 10 from being subjected to excessive tension and being broken.

[0092] Furthermore, the setting parameters may also include: the vertical distance H between the edge of the semiconductor substrate 10 and its center is greater than or equal to 15 μm, so as to avoid the situation where the tension force on the front surface 101 of the semiconductor substrate 10 is too small, resulting in distortion during the patterning process.

[0093] Based on the foregoing, when the semiconductor substrate 10 is in an arch shape, the vertical distance H between the edge of the semiconductor substrate 10 and its center needs to be greater than or equal to 15μm and less than or equal to 30μm, such as 15μm, 20μm, 25μm, 30μm, etc., so as to ensure that the bending degree of the semiconductor substrate 10 is moderate, thereby ensuring that the front side 101 film layer of the semiconductor substrate 10 is subjected to a moderate tension force, avoiding breakage or distortion of the patterned structure during the patterning process, and ensuring product yield.

[0094] In one embodiment of the present disclosure, in step S100, the back surface 102 of the semiconductor substrate 10 may be supported on an operating platform so that the front surface 101 of the semiconductor substrate 10 is away from the operating platform, that is, the front surface 101 of the semiconductor substrate 10 is facing upward. Then, step S110 is performed to form a functional layer 20 to be patterned on the front surface 101 of the semiconductor substrate 10.

[0095] The functional layer 20 to be patterned in this embodiment may be a stacked structure including multiple film layers, but is not limited thereto, and may also be a single-layer structure.

[0096] For example, if the final target pattern needs to be formed in the semiconductor substrate 10, at this time, the functional layer 20 to be patterned can be regarded as a mask layer to be patterned, wherein the functional layer 20 to be patterned may include at least one hard mask functional film layer having a first stress. When patterning the functional layer 20 to be patterned, the hard mask functional film layer can be patterned first to form a hard mask pattern layer, and then the semiconductor substrate 10 is patterned based on the hard mask pattern layer to form a target pattern in the front side 101 of the semiconductor substrate 10, and then the hard mask pattern layer is removed.

[0097] If the target pattern finally formed needs to be protruded on the front side 101 of the semiconductor substrate 10, at this time, the functional layer 20 to be patterned may include a target device functional film layer 201 and at least one mask functional film layer having a first stress, which are sequentially formed on the front side 101 of the semiconductor substrate 10. When the functional layer 20 to be patterned is patterned, the hard mask functional film layer may be patterned first to form a hard mask pattern layer, and then the target device functional film layer 201 may be patterned based on the hard mask pattern layer to form a target device pattern layer, and then the hard mask pattern layer may be removed.

[0098] It should be noted that the target device pattern layer may be a signal line pattern layer (i.e., a word line pattern layer including multiple word lines or a bit line pattern layer including multiple bit lines), but is not limited to this. It may also be an electrode pattern layer for a capacitor (the electrode pattern layer may include multiple electrodes), etc., depending on the specific situation, which will not be described in detail here.

[0099] In addition, the target device functional film layer 201 may be a single-layer structure, but is not limited thereto, and may also be a stacked structure including multiple film layers, which will not be described in detail herein.

[0100] It should be noted that when the hard mask functional film layer in the to-be-patterned functional layer 20 has multiple layers, when the to-be-patterned functional layer 20 is patterned, the mask functional film layers may be patterned one by one in sequence.

[0101] For example, when the functional layer 20 to be patterned includes at least one hard mask functional film layer having a first stress, step S130 may specifically include:

[0102] Step S1301, patterning the hard mask functional film layer to form a hard mask pattern layer;

[0103] In step S1302, a structure located below the hard mask pattern layer is patterned based on the hard mask pattern layer, and then the hard mask pattern layer is removed. It should be noted that the structure of this lower layer can be understood as a lower hard mask functional film layer, or as a target device functional film layer 201, or as a semiconductor substrate 10, etc., depending on the specific circumstances.

[0104] Among them, after removing the hard mask pattern layer with the first stress, the stress adjustment layer 40 can be thinned or removed so that the stress of the film layer on the front side 101 and the back side 102 of the semiconductor substrate 10 always maintains a certain stress range, so that the semiconductor substrate 10 is maintained in a flat shape or the arch shape mentioned above, so that the patterned film layer on the front side 101 of the semiconductor substrate 10 is in a flat state or a tensioned state, so as to ensure that the structure of the patterned film layer is pulled straighter, so that the patterned structure can achieve a straight transfer effect when it is transferred between layers, thereby avoiding or improving the distortion of the final patterned structure.

[0105] Optionally, the hard mask functional film layer may have N layers and be stacked, and step S130 may specifically include:

[0106] Step S1303, patterning the n-th hard mask functional film layer to form an n-th hard mask pattern layer, where 1<n≤N, and N and n are both integers;

[0107] Step S1304, patterning the n-1th hard mask functional film layer based on the nth hard mask pattern layer to form an n-1th hard mask pattern layer;

[0108] Step S1305, removing the nth hard mask pattern layer;

[0109] After each hard mask pattern layer is removed, the stress adjustment layer 40 is thinned to keep the semiconductor substrate 10 in a flat plate shape or an arch shape.

[0110] Optionally, the functional layer 20 to be patterned may also include a target device functional film layer 201, which is located on the side of the first hard mask functional film layer close to the semiconductor substrate 10; wherein, after forming the first hard mask pattern layer, the target device functional film layer 201 is patterned based on the first hard mask pattern layer to form a target device pattern layer; thereafter, the first hard mask pattern layer is removed.

[0111] Furthermore, after the step of removing the first hard mask pattern layer, the stress adjustment layer 40 may be completely removed to facilitate subsequent processes, but is not limited thereto, and a certain thickness of the stress adjustment layer 40 may also be retained according to subsequent processes.

[0112] For example, step S130 may further include:

[0113] Step S1306, forming a photoresist pattern layer on the side of the to-be-patterned functional layer 20 away from the semiconductor substrate 10, the photoresist pattern layer may include a plurality of spaced photoresist mask strips, for example, a photoresist material film may be first formed on the side of the to-be-patterned functional layer 20 away from the semiconductor substrate 10, and then the photoresist material film may be subjected to photolithography processes such as exposure, development, and baking to form the photoresist pattern layer;

[0114] Step S1307, patterning the functional layer 20 to be patterned based on the photoresist pattern layer. Specifically, the topmost film layer (for example, the topmost hard mask functional film layer) in the functional layer 20 to be patterned can be patterned first to form a topmost patterned film layer. Thereafter, the topmost patterned film layer formed is used as a mask to pattern the next layer, that is, patterning the underlying film layers layer by layer to achieve a downward transfer of the pattern to the target layer layer by layer. It should be noted that the topmost film layer refers to the film layer in the functional layer 20 to be patterned that is farthest from the semiconductor substrate 10 when the functional layer 20 to be patterned is a stacked structure.

[0115] In one embodiment of the present disclosure, after step S110 and before step S120, the method for manufacturing a semiconductor structure may further include:

[0116] Step S112, forming a protective film layer 30 on a side of the to-be-patterned functional layer 20 away from the semiconductor substrate 10;

[0117] Step S114, after forming the protective film layer 30, flip the semiconductor substrate 10 so that the back side 102 of the semiconductor substrate 10 faces upward, so as to facilitate the subsequent formation of the stress adjustment layer 40 on the back side 102 of the semiconductor substrate 10. At this time, the protective film layer 30 is supported on the operating platform to isolate the functional layer 20 to be patterned from the operating platform to avoid contamination or wear of the functional layer 20 to be patterned.

[0118] It should be understood that after step S120 and before step S130, the manufacturing method further includes: step S122, flipping the semiconductor substrate 10 so that the front side 101 of the semiconductor substrate 10 faces upward, so as to facilitate the subsequent patterning of the functional layer 20 to be patterned on the front side 101 of the semiconductor substrate 10.

[0119] Before step S130, the manufacturing method also includes: step S124, removing the protective film layer 30, but is not limited to this, and the protective film layer 30 may not be removed. For example: before step S130, the manufacturing method also includes: step S126, patterning the protective film layer 30 to form a protective pattern layer, and then, based on the protective pattern layer as a mask, patterning the patterned functional layer 20.

[0120] For example, the protective film layer 30 may include an amorphous carbon film layer. This amorphous carbon film layer has a relatively large hardness. On the one hand, it can provide good protection for the functional layer 20 to be patterned. On the other hand, after the amorphous film layer is patterned, the amorphous carbon pattern layer formed has good collimation. The amorphous carbon pattern layer is used as a mask to pattern the functional layer 20 to be patterned, which can also ensure the accuracy of the pattern of the functional layer 20 to be patterned after the subsequent patterning.

[0121] That is, in step S126 , the method may specifically include: patterning the amorphous carbon film layer to form an amorphous carbon pattern layer, and subsequently patterning the functional layer 20 to be patterned based on the amorphous carbon pattern layer as a mask.

[0122] In this embodiment, the first stress of the functional layer 20 to be patterned and the second stress of the stress adjustment layer 40 are both compressive stresses, and the first stress is greater than or equal to the second stress. That is to say, the compressive stress of the functional layer 20 to be patterned may be greater than or equal to the compressive stress of the stress adjustment layer 40. This ensures that the semiconductor substrate 10 is in a flat plate shape or an arch shape with a bending degree that meets the set parameters under the action of the functional layer 20 to be patterned and the stress adjustment layer 40.

[0123] Taking the example that both the functional layer 20 to be patterned and the stress adjustment layer 40 have compressive stress, the implementation step S120 may include:

[0124] Step S1201, forming a patterned adjustment film layer on the back surface 102 of the semiconductor substrate 10, wherein the patterned adjustment film layer has a plurality of strip-shaped adjustment structures 4021 arranged at intervals;

[0125] Step S1202 , forming a compressive stress regulating film layer 403 , the compressive stress regulating film layer 403 having a filling portion 4031 and a covering portion 4032 , the filling portion 4031 is filled between adjacent strip regulating structures 4021 , and the covering portion 4032 covers the patterned regulating film layer and a side of the filling portion 4031 away from the semiconductor substrate 10 .

[0126] In the present embodiment, a patterned adjustment film layer is first formed, and then a compressive stress adjustment film layer 403 is formed. Part of the compressive stress adjustment film layer 403 can be filled between adjacent strip adjustment structures 4021. Due to the structural effect of the compressive stress adjustment film layer 403, the strip adjustment structure 4021 of the patterned adjustment film layer will be squeezed. This design can appropriately reduce the thickness of the stress adjustment layer 40 while offsetting at least part of the stress formed by the functional layer 20 to be patterned to achieve stress adjustment on both sides of the semiconductor substrate 10.

[0127] For example, the extension direction of the strip-shaped adjustment structure 4021 in the patterned adjustment film layer may be perpendicular to the extension direction of the photoresist mask strip in the aforementioned photoresist pattern layer. For example, the extension direction of the photoresist mask strip in the photoresist pattern layer may be a first direction X, and the extension direction of the strip-shaped adjustment structure 4021 in the patterned adjustment film layer may be a second direction Y, and the first direction X and the second direction Y are perpendicular to each other.

[0128] When the photoresist pattern layer is used as a mask to pattern the functional layer 20 to be patterned, the pattern of the photoresist pattern layer can be first transferred to the hard mask functional film layer located at the top layer in the functional layer 20 to be patterned, so as to form a hard mask pattern layer, and the hard mask pattern layer includes a plurality of hard mask strips extending in the first direction X. By designing the extension direction of the strip-shaped adjustment structure 4021 in the patterned adjustment film layer to be perpendicular to the extension direction of the photoresist mask strip, the strip-shaped adjustment structure 4021 in the patterned adjustment film layer is perpendicular to the extension direction of the photoresist mask strip. A larger stress is generated on the side, so that the functional layer 20 to be patterned on the front side 101 of the semiconductor substrate 10 is subjected to a tensioning force in the first direction X, so as to ensure that in the process of patterning the functional layer 20 to be patterned to form a hard mask strip, the formed hard mask strip is in a straightened state due to the tensioning force in the first direction X, thereby reducing or improving the distortion of the hard mask strip, and then achieving a straight transmission effect when the patterned structure is transferred between layers, thereby avoiding or improving the distortion of the final patterned structure.

[0129] In the present embodiment, the compressive stress regulating film layer 403 includes a compressive stress silicon oxide film, and the material of the compressive stress silicon oxide film is silicon dioxide (SiO2); but not limited to this, the compressive stress regulating film layer 403 may also include a compressive stress polycrystalline silicon film, wherein the step of forming the compressive stress regulating film layer 403 may include: using plasma enhanced chemical vapor deposition (abbreviated as: PEVCD) to deposit polycrystalline silicon material. Compared with other deposition processes such as physical vapor deposition (abbreviated as PVD), the polycrystalline silicon film deposited by the PEVCD process in the present embodiment can have a larger compressive stress, that is, a compressive stress polycrystalline silicon film is formed.

[0130] In addition, it should be understood that the compressive stress adjustment film may also include a compressive stress silicon oxide film and a compressive stress polysilicon film at the same time, depending on the specific situation. No further explanation is given here. This embodiment is mainly described by taking the compressive stress adjustment film layer 403 including a compressive stress silicon oxide film as an example.

[0131] By way of example, step S120 may specifically include: step S1200, forming an anti-stripping adjustment film layer 401 on the back side 102 of the semiconductor substrate 10, the anti-stripping adjustment film layer 401 being located on the side of the patterned adjustment film layer close to the semiconductor substrate 10, that is, first forming the anti-stripping adjustment film layer 401 on the back side 102 of the semiconductor substrate 10, and then forming the patterned adjustment film layer, wherein the thermal expansion coefficient of the anti-stripping adjustment film layer 401 is between the thermal expansion coefficient of the semiconductor substrate 10 and the thermal expansion coefficient of the patterned adjustment film layer.

[0132] In the present embodiment, an anti-peeling adjustment film layer 401 is formed before forming a patterned adjustment film layer. This can avoid the situation where the stress adjustment layer 40 is peeled off from the back side 102 of the semiconductor substrate 10 due to a large difference in thermal expansion coefficient between the semiconductor substrate 10 and the patterned adjustment film layer, thereby improving the structural stability between the stress adjustment layer 40 and the semiconductor substrate 10 during the semiconductor structure manufacturing process.

[0133] Optionally, when the semiconductor substrate 10 includes a silicon wafer, the anti-stripping adjustment film layer 401 may include an anti-stripping silicon oxide film, that is, the material of the anti-stripping adjustment film layer 401 may be silicon oxide (SiO2), and the patterned adjustment film layer may include a patterned silicon nitride film, that is, the material of the patterned adjustment film layer may be silicon nitride (Si3N4).

[0134] For example, step S1200 specifically includes: using a thermal oxidation process to oxidize the back side 102 of the silicon wafer to form an anti-stripping silicon oxide film. The anti-stripping silicon oxide film formed by thermal oxidation has good structural density, but is not limited to this. A deposition process can also be used to deposit silicon oxide material on the back side 102 of the silicon wafer to form an anti-stripping silicon oxide film. This method makes it easy to control the thickness of the anti-stripping silicon oxide film.

[0135] In one embodiment of the present disclosure, the area between adjacent strip-shaped adjustment structures 4021 in the patterned adjustment film layer is a hollow area, and in the hollow area, the filling portion 4031 of the compressive stress adjustment film layer 403 is in contact with the anti-peeling adjustment film layer 401. This design can generate a larger compressive stress, so as to appropriately reduce the thickness of the stress adjustment layer 40 while ensuring that the compressive stress on both sides of the semiconductor substrate 10 is maintained within a certain compressive stress range.

[0136] When the material of the anti-peeling adjustment film layer 401 and the material of the compressive stress adjustment film layer 403 are both silicon oxide, the filling portion 4031 of the compressive stress adjustment film layer 403 contacts the anti-peeling adjustment film layer 401 at the hollow area to ensure that the stress adjustment layer 40 has good stability.

[0137] For example, when the first stress of the functional layer 20 to be patterned is compressive stress, the functional layer 20 to be patterned includes a compressive stress silicon oxide film; and / or, the functional layer 20 to be patterned includes a compressive stress polysilicon film, and this compressive stress polysilicon film can be formed by plasma enhanced chemical vapor deposition, wherein the compressive stress silicon oxide film in the functional layer 20 to be patterned and the compressive stress polysilicon film formed by plasma enhanced chemical vapor deposition can be used as a hard mask functional film layer.

[0138] Based on the above-mentioned embodiment contents, combined with Figures 2 to 18 Taking the reverse self-aligned double patterning process for patterning the to-be-patterned functional layer 20 on the front surface 101 of the semiconductor substrate 10 as an example, the manufacturing method of the semiconductor structure of the embodiment of the present disclosure is described in detail. Specifically, the manufacturing method may include the following steps:

[0139] Step S200, providing a semiconductor substrate 10, and supporting the back side 102 of the semiconductor substrate 10 on an operating platform (not shown in the figure). For example, the semiconductor substrate 10 can be understood as a wafer;

[0140] Step S201, forming a target device functional film layer 201 and a first hard mask functional film layer 202 and a second hard mask functional film layer 203 having a first stress on the front surface 101 of the semiconductor substrate 10 in sequence to form a functional layer 20 to be patterned. For example, the target device functional film layer 201 may be a stacked structure, which may include a BPSG (boron phospho-silicate glass) film, a SiCN (silicon carbon nitride) film, a SiO2 film, a SiCN film, etc. deposited in sequence. The first hard mask functional film layer 202 may be a Poly (polycrystalline silicon) film deposited by plasma enhanced chemical vapor deposition, and the second hard mask may be a deposited SiO2 film;

[0141] Step S202, forming a protective film layer 30 on a side of the functional layer 20 to be patterned away from the semiconductor substrate 10, such as Figure 2 As shown, for example, the protective film layer 30 may be a deposited amorphous carbon film layer;

[0142] Step S203, turning over the semiconductor substrate 10 so that the back side 102 of the semiconductor substrate 10 faces upward, and at this time, the protective film layer 30 is in contact with the operating platform;

[0143] Step S204, forming an anti-peeling adjustment film layer 401, a patterned adjustment film layer 402 and a first photoresist pattern layer on the back side 102 of the semiconductor substrate 10 in sequence, referring to Figure 3As shown, the first photoresist pattern layer may include a plurality of first photoresist mask strips 50 extending in the second direction Y, and the plurality of first photoresist mask strips 50 are arranged at intervals in the first direction X. For example, when the semiconductor substrate 10 is a wafer, the anti-stripping adjustment film layer 401 may be a silicon oxide film, and the to-be-patterned adjustment film layer 402 may be a Si3N4 film;

[0144] Step S205, patterning the to-be-patterned adjustment film layer 402 based on the first photoresist pattern layer to form a patterned adjustment film layer, referring to Figure 4 As shown, the pattern of the patterned adjustment film layer is the same as the pattern of the first photoresist pattern layer, that is, the patterned adjustment film layer may include a plurality of strip-shaped adjustment structures 4021 extending in the second direction Y;

[0145] Step S206, removing the first photoresist pattern layer and forming a compressive stress adjustment film layer 403, referring to Figure 5 As shown, a stress adjustment layer 40 is formed, wherein the filling portion 4031 of the compressive stress adjustment film layer 403 is filled between adjacent strip-shaped adjustment structures 4021, and the covering portion 4032 of the compressive stress adjustment film layer 403 covers the patterned adjustment film layer and the side of the filling portion 4031 away from the semiconductor substrate 10. For example, the compressive stress adjustment film layer 403 can be a SiO2 film, wherein the compressive stress adjustment film layer 403 can be formed by first depositing a certain thickness of SiO2 material, and then performing a CMP (Chemical Mechanical Polishing) process to form the compressive stress adjustment film layer 403;

[0146] Step S207, turning over the semiconductor substrate 10 so that the front surface 101 of the semiconductor substrate 10 faces upward, and at this time, the compressive stress regulating film layer 403 is in contact with the operating platform;

[0147] Step S208, at least one sacrificial material layer 60 and a second photoresist pattern layer are sequentially formed on the side of the protective film layer 30 away from the semiconductor substrate 10, and the second photoresist pattern layer is formed on the protective film layer 30. Figure 6 and Figure 7 As shown, the second photoresist pattern layer may include a plurality of second photoresist mask strips 70 extending in the first direction X. For example, the sacrificial material layer 60 may include a SOC (spin-on carbon) film and a SiON (silicon oxynitride) film deposited in sequence. It should be noted that the number of layers of the sacrificial material layer 60 may be determined according to the actual pattern to be processed later, which will not be described in detail herein.

[0148] Step S209, patterning the sacrificial material layer 60 based on the second photoresist pattern layer to form a sacrificial pattern film layer, the pattern of the sacrificial pattern film layer is the same as the pattern of the second photoresist pattern layer, that is: Figure 8As shown, the sacrificial pattern film layer may include a plurality of sacrificial mask strips 601 extending in a first direction X;

[0149] Step S210, removing the second photoresist pattern layer, and forming an intermediate film 80 covering the surface and side surfaces of the sacrificial mask strip 601, such as Fig. 9 As shown, due to the geometric effect of the sidewalls of the sacrificial mask strip 601, the intermediate film 80 deposited on both sides of the sacrificial mask strip 601 will remain, that is, spacers 801 are formed on both sides of the sacrificial mask strip 601. For example, the intermediate film 80 can be a SiO2 film. Specifically, an atomic layer deposition technology can be used to deposit a film with a relatively uniform thickness on the surface and side of the sacrificial mask strip 601.

[0150] Step S211, forming a top film 90 covering the middle film 80 and filling the remaining gaps between the sacrificial mask strips 601, refer to Fig.10 As shown, for example, the top film 90 may be a SOC film;

[0151] Step S212, removing the portion of the top film 90 that is higher than the middle film 80, so as to form auxiliary mask strips 901 that fill the remaining gaps between the sacrificial mask strips 601, as shown in FIG. Fig.11 As shown;

[0152] Step S213, removing the spacer 801 to form a target mask pattern layer, such as Fig.12 As shown, the target mask pattern includes sacrificial mask strips 601 and auxiliary mask strips 901 that are alternately and spaced apart;

[0153] Step S214, patterning the protective film layer 30 based on the target mask pattern layer to form a protective pattern layer, wherein Fig.13 As shown, the protection pattern layer has the same pattern as the target mask pattern layer, and the protection pattern layer includes a plurality of protection mask strips 301 extending in a first direction X;

[0154] Step S215, removing the target mask pattern layer, and patterning the second hard mask functional film layer 203 based on the protection pattern layer to form a second hard mask pattern layer, wherein Fig.14 As shown, the second hard mask pattern layer has the same pattern as the protection pattern layer, and the second hard mask pattern layer includes a plurality of second hard mask strips 2031 extending in the first direction X;

[0155] Step S216, removing the protective pattern layer, and patterning the first hard mask functional film layer 202 based on the second hard mask pattern layer to form a first hard mask pattern layer, wherein: Fig.15As shown, the first hard mask pattern layer has the same pattern as the second hard mask pattern layer, and the first hard mask pattern layer includes a plurality of first hard mask strips 2021 extending in a first direction X;

[0156] Step S217, removing the second hard mask pattern layer, and then reducing the thickness of the stress adjustment layer 40, such as Fig.16 As shown, for example, the thickness of the stress adjustment layer 40 can be directly thinned using the operating platform, for example: the compressive stress adjustment film layer 403 can be directly thinned using the operating platform to ensure that the stress of the front and back surfaces 102 of the semiconductor substrate 10 always maintains a certain stress range;

[0157] Step S218, after reducing the thickness of the stress adjustment layer 40, patterning the target device functional film layer 201 based on the first hard mask pattern layer to form a target device pattern layer, referring to Fig.17 As shown, the target device pattern layer has the same pattern as the first hard mask pattern layer, and the target device pattern layer includes a plurality of target device strips 2011 extending in a first direction X;

[0158] Step S219, removing the first hard mask pattern layer, and then thinning the thickness of the stress adjustment layer 40 again, referring to Fig.18 As shown, the stress on the front and back surfaces 102 of the semiconductor substrate 10 is ensured to always maintain a certain stress range.

[0159] It should be noted that the present embodiment is not limited to the use of a reverse self-aligned double patterning process to pattern the functional layer 20 to be patterned on the front side 101 of the semiconductor substrate 10. The present embodiment may also use a reverse self-aligned quadruple patterning process to pattern the functional layer 20 to be patterned on the front side 101 of the semiconductor substrate 10. The difference between the reverse self-aligned double patterning process and the reverse self-aligned double patterning process is that after step S213 and before step S214, the patterning process mentioned in steps S210 to S213 may be repeated to achieve a doubling of the spatial graphic density based on the target mask pattern layer.

[0160] It should be understood that when step S210 is performed for the second time, since there is no second photoresist pattern layer, the second step S210 does not include the specific operation of removing the second photoresist pattern layer.

[0161] In addition, the present embodiment may also use a self-aligned double or quadruple patterning process to pattern the functional layer 20 to be patterned on the front side 101 of the semiconductor substrate 10. The difference between the process and the reverse self-aligned double patterning process is that there is no need to form a top film 90. After step S210, the sacrificial mask strip 601 may be directly removed to form a target mask pattern layer with the remaining spacer 801. The aforementioned steps S211 to S213 may be omitted.

[0162] The present disclosure also provides a semiconductor structure, which can be referred to as Fig.18 As shown, this semiconductor structure can be manufactured using the manufacturing method mentioned in any of the above embodiments. Therefore, the semiconductor structure has at least the advantages of small functional structure distortion and high yield of the semiconductor structure. For details, please refer to the above content and will not be repeated here.

[0163] In addition, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the feature. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0164] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0165] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The manufacturing method comprises: Providing a semiconductor substrate, wherein the semiconductor substrate has a front side and a back side that are oppositely disposed; forming a functional layer to be patterned having a first stress on the front surface of the semiconductor substrate; A stress adjustment layer having a second stress is formed on the back side of the semiconductor substrate, wherein the first stress and the second stress are of the same type, so that the semiconductor substrate is in a flat plate shape or an arch shape with an edge bent away from the functional layer to be patterned under the action of the functional layer to be patterned and the stress adjustment layer, and the bending degree of the arch shape meets the set parameters; After forming the stress adjustment layer, the functional layer to be patterned is patterned.

2. The manufacturing method according to claim 1, characterized in that: The first stress and the second stress are both compressive stresses, and the first stress is greater than or equal to the second stress.

3. The manufacturing method according to claim 2, characterized in that: The step of forming a stress adjustment layer having a second stress on the back side of the semiconductor substrate comprises: forming a patterned regulating film layer on the back side of the semiconductor substrate, wherein the patterned regulating film layer has a plurality of strip-shaped regulating structures arranged at intervals; A compressive stress regulating film layer is formed, wherein the compressive stress regulating film layer has a filling portion and a covering portion, wherein the filling portion is filled between adjacent strip regulating structures, and the covering portion covers the patterned regulating film layer and a side of the filling portion away from the semiconductor substrate.

4. The manufacturing method according to claim 3, characterized in that: The step of patterning the functional layer to be patterned comprises: forming a photoresist pattern layer on a side of the functional layer to be patterned away from the semiconductor substrate, wherein the photoresist pattern layer comprises a plurality of photoresist mask strips arranged at intervals; Performing patterning processing on the functional layer to be patterned based on the photoresist pattern layer; Wherein, the extending direction of the photoresist mask strip is perpendicular to the extending direction of the strip-shaped adjustment structure.

5. The manufacturing method according to claim 3, characterized in that: The compressive stress regulating film layer comprises a compressive stress silicon oxide film; and / or The compressive stress adjustment film layer includes a compressive stress polysilicon film.

6. The manufacturing method according to claim 3, characterized in that: The step of forming a stress adjustment layer having a second stress on the back side of the semiconductor substrate further includes: An anti-stripping adjustment film layer is formed on the back side of the semiconductor substrate, the anti-stripping adjustment film layer is located on the side of the patterned adjustment film layer close to the semiconductor substrate, and the thermal expansion coefficient of the anti-stripping adjustment film layer is between the thermal expansion coefficient of the semiconductor substrate and the thermal expansion coefficient of the patterned adjustment film layer.

7. The manufacturing method according to claim 6, characterized in that: The area between the adjacent strip-shaped adjustment structures in the patterned adjustment film layer is a hollow area, and in the hollow area, the filling part is in contact with the anti-peeling adjustment film layer.

8. The manufacturing method according to claim 6 or 7, characterized in that: The semiconductor substrate comprises a silicon wafer, the anti-stripping adjustment film layer comprises an anti-stripping silicon oxide film, and the patterned adjustment film layer comprises a patterned silicon nitride film.

9. The manufacturing method according to claim 8, characterized in that: The step of forming the anti-peeling adjustment film layer comprises: Performing oxidation treatment on the back side of the silicon wafer by using a thermal oxidation process to form the anti-stripping silicon oxide film; or A silicon oxide material is deposited on the back side of the silicon wafer by a deposition process to form the anti-stripping silicon oxide film.

10. The manufacturing method according to claim 2, characterized in that: The functional layer to be patterned includes a compressive stress silicon oxide film; and / or The functional layer to be patterned includes a compressive stress polysilicon film.

11. The manufacturing method according to claim 1, characterized in that: In the process of patterning the functional layer to be patterned, the manufacturing method further comprises: Based on the stress variation of the film layer on the front surface of the semiconductor substrate, the stress adjustment layer is thinned or removed so that the semiconductor substrate is kept in the flat plate shape or the arch shape.

12. The manufacturing method according to claim 11, characterized in that: The functional layer to be patterned includes at least one hard mask functional film layer having a first stress, and the step of patterning the functional layer to be patterned includes: Performing patterning on the hard mask functional film layer to form a hard mask pattern layer; performing patterning processing on a structure located under the hard mask pattern layer based on the hard mask pattern layer, and then removing the hard mask pattern layer; Wherein, after removing the hard mask pattern layer, the stress adjustment layer is thinned or removed.

13. The manufacturing method according to claim 12, characterized in that: The hard mask functional film layer has N layers and is stacked, and the step of patterning the functional layer to be patterned includes: Performing patterning on the n-th hard mask functional film layer to form an n-th hard mask pattern layer, where 1<n≤N, and N and n are both integers; Performing patterning on the n-1th hard mask functional film layer based on the nth hard mask pattern layer to form an n-1th hard mask pattern layer; removing the nth hard mask pattern layer; Wherein, after each hard mask pattern layer is removed, the stress adjustment layer is thinned to keep the semiconductor substrate in the flat plate shape or the arch shape.

14. The manufacturing method according to claim 13, characterized in that: The functional layer to be patterned also includes a target device functional film layer, which is located on the side of the first hard mask functional film layer close to the semiconductor substrate; wherein, After forming the first hard mask pattern layer, patterning the target device functional film layer based on the first hard mask pattern layer to form a target device pattern layer; The first hard mask pattern layer is removed.

15. The manufacturing method according to claim 1, characterized in that: Before the step of forming a stress adjustment layer on the back side of the semiconductor substrate, the manufacturing method further comprises: forming a protective film layer on a side of the functional layer to be patterned away from the semiconductor substrate; After forming the protective film layer, turning over the semiconductor substrate so that the back side of the semiconductor substrate faces upward; Wherein, after forming the stress adjustment layer and before patterning the functional layer to be patterned, the manufacturing method further includes: The semiconductor substrate is turned over so that the front side of the semiconductor substrate faces upward.

16. The manufacturing method according to claim 15, characterized in that: The protective film layer includes an amorphous carbon film layer.

17. The manufacturing method according to claim 16, characterized in that: Before patterning the functional layer to be patterned, the manufacturing method further includes: Performing patterning on the amorphous carbon film layer to form an amorphous carbon pattern layer; Wherein, the amorphous carbon pattern layer is used as a mask to perform patterning on the functional layer to be patterned.

18. The manufacturing method according to claim 1, characterized in that: The step of patterning the functional layer to be patterned comprises: Patterning the functional layer to be patterned by using a self-aligned M-patterning process or a reverse self-aligned M-patterning process; Here, M is an even number greater than or equal to 2.

19. A semiconductor structure, characterized in that: The method is manufactured by the manufacturing method according to any one of claims 1 to 18.

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