Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes a substrate having an active region and a peripheral region surrounding the active region, a plurality of gate structures disposed in the active region of the substrate, and a fuse element disposed in the peripheral region of the substrate. The fuse element includes a polysilicon portion having a bottom tip directed toward the substrate, a dielectric film disposed between the polysilicon portion and the substrate, and a conductive portion disposed on the polysilicon portion. The invention also discloses a manufacturing method of the semiconductor device. The fuse element is provided with the bottom tip which is favorable for concentrating an electric field, so that a point discharge effect is induced at the bottom tip when an external voltage is applied to the fuse element, and the breakdown voltage required for fusing the fuse element is further reduced.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly, the present disclosure relates to a semiconductor device with a fuse and a manufacturing method thereof. Background Art

[0002] In recent decades, with the continuous improvement of electronic products, the demand for storage capacity has also increased. In order to increase the storage capacity of a memory element (such as a DRAM element), more memory cells are integrated into the memory element. As the degree of integration increases, the manufacturing process of the memory element becomes more complicated, and the process margin (process window) becomes quite narrow. Therefore, the increase in integration may lead to a higher possibility of leakage between multiple memory cells.

[0003] In integrated circuits, fuse elements are widely used features for a variety of purposes, such as improving manufacturing yield or customizing generic integrated circuits. For example, by replacing defective circuits on a chip with duplicate or redundant circuits on the same chip, manufacturing yield can be greatly improved. Integrated circuits designed with multiple fuses that can be selectively blown are economical to manufacture and suitable for different customized uses. Summary of the invention

[0004] An embodiment of the present disclosure provides a semiconductor device, comprising a substrate having an active region and a peripheral region surrounding the active region, a plurality of gate structures disposed in the active region of the substrate, and a fuse element disposed in the peripheral region of the substrate. The fuse element comprises a polysilicon portion having a bottom tip pointing toward the substrate, a dielectric film disposed between the polysilicon portion and the substrate, and a conductive portion disposed on the polysilicon portion.

[0005] In some embodiments, the bottom tip of the polysilicon portion has an angle, and the angle is 90 degrees.

[0006] In some embodiments, the dielectric film has a V-shaped cross-section.

[0007] In some embodiments, a bottom tip of the polysilicon portion is lower than an upper surface of the substrate.

[0008] In some embodiments, the resistance of the conductive portion is lower than the resistance of the polysilicon portion.

[0009] In some embodiments, the polysilicon portion includes a bottom block and a top block, wherein the bottom block is embedded in the substrate and the top block protrudes from the substrate.

[0010] In some embodiments, the gate structure includes a dummy gate structure and an active gate structure, and the dummy gate structure is disposed at an edge of the active region.

[0011] In some embodiments, the semiconductor device further includes an insulating layer disposed between the gate structure and the substrate, wherein the insulating layer has a first portion between the dummy gate structure and the substrate and a second portion between the active gate structure and the substrate, and the thickness of the first portion is greater than the thickness of the second portion.

[0012] In some embodiments, the semiconductor device further includes a contact disposed in a peripheral region of the substrate, wherein the contact includes a dielectric film disposed on the substrate, a polysilicon portion disposed on the dielectric film, and a conductive portion disposed on the polysilicon portion.

[0013] In some embodiments, a cross-section of a polysilicon portion of the fuse element is different than a cross-section of the polysilicon portion of the contact.

[0014] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising forming a plurality of gate structures in an active region of a substrate; forming a mask on the substrate, wherein the mask covers the active region and has an opening to expose a portion of the substrate; etching the portion of the substrate through the opening of the mask to form a recess in a peripheral region of the substrate, wherein the recess has a bottom angle; and forming a fuse element in the recess.

[0015] In some embodiments, etching the portion of the substrate includes using a sodium hydroxide solution as an etchant.

[0016] In some embodiments, etching the portion of the substrate includes using a potassium hydroxide solution as an etchant.

[0017] In some embodiments, the bottom angle of the recess is 90 degrees.

[0018] In some embodiments, the method further includes removing the mask after the recess is formed; and performing an oxidation process to form an oxide layer blanketing the recess and a peripheral area of ​​the substrate.

[0019] In some embodiments, the method further includes forming a polysilicon layer on the oxide layer; forming a conductive layer on the polysilicon layer; and patterning the oxide layer, the polysilicon layer, and the conductive layer to form a fuse element, wherein the fuse element includes a dielectric film on the substrate, a polysilicon portion on the dielectric film, and a conductive portion on the polysilicon portion.

[0020] In some embodiments, the step of forming a polysilicon layer on the oxide layer includes filling the recess with the polysilicon layer so that the polysilicon portion of the fuse element has a bottom tip.

[0021] In some embodiments, patterning the oxide layer, the polysilicon layer, and the conductive layer includes forming contacts at a peripheral region of the substrate.

[0022] In some embodiments, the resistance of the conductive layer is lower than the resistance of the polysilicon layer.

[0023] In some embodiments, the dielectric film of the fuse element has a V-shaped cross-section.

[0024] According to some embodiments of the present disclosure, the fuse element has a bottom tip, which is beneficial for concentrating the electric field so as to induce a tip discharge effect at the bottom tip when an external voltage is applied to the fuse element, thereby reducing the breakdown voltage required to blow (disable) the fuse element. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To make the purpose, features, advantages and embodiments of the present disclosure more clearly understood, the detailed description of the attached drawings is as follows:

[0026] Figures 1 to 8 The following are schematic diagrams of some embodiments of the method for manufacturing a semiconductor device disclosed herein at different manufacturing stages.

[0027] Fig. 9 FIG. 4 is a schematic top view of a peripheral region of a semiconductor device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0028] The following will clearly illustrate the spirit of the present disclosure with the accompanying drawings and detailed descriptions. After understanding the preferred embodiments of the present disclosure, any person skilled in the art can make changes and modifications based on the techniques taught by the present disclosure without departing from the spirit and scope of the present disclosure.

[0029] When an element is referred to as being "on...", it can generally refer to the element being directly on other elements, or there being other elements between the two. Conversely, when an element is referred to as being "directly on" another element, there cannot be other elements between the two. As used herein, the term "and / or" includes any combination of one or more of the listed associated items.

[0030] In addition, relative terms, such as "lower" or "bottom" and "upper" or "top", are used to describe the relationship of one element to another element shown in the accompanying drawings. It is understood that relative terms are used to describe different orientations of the device other than those described in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, the element that would be described as being on the "lower" side of the other elements will be oriented to be on the "upper" side of the other elements. The exemplary term "lower" can include both "lower" and "upper" orientations depending on the specific orientation of the accompanying drawings. Similarly, if the device in the accompanying drawings is turned over, the element that would be described as being "below" or "beneath" other elements will be oriented to be "above" other elements. The exemplary term "lower" or "beneath" can include both "above" and "on".

[0031] Fuse elements can be used to replace defective circuits on a chip with other duplicate or redundant circuits on the same chip, or fuse elements can be selectively blown to suit customized applications. Fuse elements disconnected by a laser beam can be represented as laser fuse elements, while fuse elements disconnected or blown by passing current can be represented as electric fuse elements. The breakdown voltage of the electric fuse element determines the current required to disconnect or blow the electric fuse element. The present disclosure relates to a semiconductor device having an electric fuse element with a reduced breakdown voltage and a method for making the same.

[0032] Reference Figures 1 to 8 , which are schematic diagrams of some embodiments of the semiconductor device manufacturing method disclosed in the present invention at different manufacturing stages. Figure 1 As shown, in step S10, a plurality of grooves 111, 112, 113 are formed in the active region A1, wherein the active region A1 is a region defined in the substrate 100. In some embodiments, the substrate 100 includes a surface 101 and a surface 102 opposite to each other. In some embodiments, the surface 101 is the active surface of the substrate 100, and the surface 102 is the back surface of the substrate 100. In some embodiments, the substrate 100 may be, for example, a silicon substrate. Alternatively, the substrate 100 may be a silicon substrate doped with other semiconductor elements. In some other embodiments, the substrate 100 may include a semiconductor layer, such as silicon / silicon germanium, silicon-on-insulator, or silicon germanium-on-insulator.

[0033] In some embodiments, the active region A1 is disposed on or in the substrate 100. In some embodiments, the active region A1 is disposed on or close to the surface 101 of the substrate 100. In some embodiments, the active region A1 has a surface S1, and the surface S1 of the active region A1 is exposed to the surface 101 of the substrate 100. In some embodiments, the surface S1 of the active region A1 is coplanar with the surface 101 of the substrate 100.

[0034] In some embodiments, the active region A1 may be doped with N-type dopants, such as phosphorus (P), arsenic (As), antimony (Sb), etc. In some other embodiments, the active region A1 may be doped with P-type dopants, such as boron (B) or indium (In), etc. In some embodiments, the substrate 100 may be or include a region that is not ion-implanted. In some embodiments, the doping concentration of the active region A1 is higher than the doping concentration of the substrate 100.

[0035] In some embodiments, the trenches 111 and 112 are disposed at the edge of the active region A1, and the trench 113 is disposed between the trenches 111 and 112. In some embodiments, the trenches 111 and 112 disposed at the edge of the active region A1 have a deeper depth than the trench 113. In some embodiments, the bottom of the trenches 111 and 112 may be above the bottom of the active region A1, adjacent to the bottom of the active region A1, or below the bottom of the active region A1.

[0036] In some embodiments, the formation method of the grooves 111, 112, 113 includes forming a hard mask layer 120 on the surface 101 of the substrate 100. Then, a patterned photoresist layer (not shown) is formed on the hard mask layer 120. The patterned photoresist layer has an opening to expose a portion of the hard mask layer 120. Then, the hard mask layer 120 is etched through the opening of the patterned photoresist layer to remove the portion of the active area A1 that is not protected by the hard mask layer 120 and the patterned photoresist layer. In this way, the grooves 111, 112, 113 can be formed in the active area A1. After the grooves 111, 112, 113 are formed, the patterned photoresist layer can be removed.

[0037] In some embodiments, the hard mask layer 120 may be a single layer structure or a multi-layer structure. For example, the hard mask layer 120 may include a pad oxide layer on the surface 101 of the substrate 100 and a nitride layer on the pad oxide layer. In some embodiments, the thickness of the nitride layer may be greater than the thickness of the pad oxide layer. In some embodiments, the hard mask layer 120 may remain on the surface 101 of the substrate 100 after the grooves 111, 112, 113 are formed.

[0038] Reference Figure 2 In step S12, an insulating layer 130 is formed to blanket the inner walls of the trenches 111, 112, and 113 and the hard mask layer 120. In some embodiments, the material of the insulating layer 130 can be a dielectric material, such as silicon dioxide. In some other embodiments, the material of the insulating layer 130 can be a dielectric material with a high dielectric constant, such as hafnium oxide (HfO 2 ), hafnium silicate (hafniumsilicate, HfSiO 4 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAlO 3 ), zirconium oxide (ZrO 2 ), zirconium silicate (zirconiumsilicate, ZrSiO 4 )、aluminaluminum oxide(Al 2 O 3 ) or a combination thereof.

[0039] The insulating layer 130 may be formed by any suitable deposition process. In some embodiments, the deposition process may be controlled so that the thickness T1 of the insulating layer 130 at the bottom of the trenches 111 and 112 is much greater than the thickness T2 of the insulating layer 130 at the bottom of the trench 113 .

[0040] Reference Figure 3 In step S14, a plurality of gate structures 140 and word lines 150 are formed in the trenches 111, 112, and 113. In some embodiments, forming the gate structure 140 includes depositing a bottom conductive layer 142 at the bottom of the trenches 111, 112, and 113, depositing an intermediate conductive layer 144 on the bottom conductive layer 142, and depositing a top conductive layer 146 on the intermediate conductive layer 144. In some embodiments, the bottom conductive layer 142 may be a metal nitride, such as titanium nitride. The material of the bottom conductive layer 142 may first fill the trenches 111, 112, and 113, and then a portion of the material of the bottom conductive layer 142 may be removed by an etch-back process to form the bottom conductive layer 142 at the bottom of the trenches 111, 112, and 113.

[0041] Similarly, the material of the middle conductive layer 144 can be deposited on the bottom conductive layer 142 and at least partially fill the trenches 111, 112, and 113, and then a back etching process is performed to remove a portion of the material of the middle conductive layer 144 to form the middle conductive layer 144 in the middle of the trenches 111, 112, and 113. In some embodiments, the material of the middle conductive layer 144 can be polysilicon.

[0042] Next, the material of the top conductive layer 146 is deposited. In some embodiments, the material of the top conductive layer 146 may be a metal nitride, such as titanium nitride. The material of the top conductive layer 146 not only completely fills the trenches 111, 112, 113, but also covers the surface 101 of the substrate 100. After the material of the top conductive layer 146 is deposited, a patterning process (not shown) may be performed to remove a portion of the material of the top conductive layer 146 on the surface 101 of the substrate 100. More specifically, after this patterning process, a portion of the material of the top conductive layer 146 is disposed on the top of the trenches 111, 112, 113 and on the middle conductive layer 144. The bottom conductive layer 142, the middle conductive layer 144, and the top conductive layer 146 in the trenches 111, 112, 113 are collectively referred to as the gate structure 140. The portion of the material of the top conductive layer 146 on the surface 101 of the substrate 100 serves as a word line 150, which is a linear structure and connects the corresponding gate structure 140. The insulating layer 130 is disposed between the gate structure 140 and the active region A1 of the substrate 100 , so the insulating layer 130 may also be referred to as a gate dielectric layer.

[0043] In some embodiments, the gate structure 140 at the edge of the active region A1, such as the gate structure 140 filled in the trenches 111 and 112, can have a thicker insulating layer 130 at its bottom. In this way, the gate structure 140 filled in the trenches 111 and 112 and having the thicker insulating layer 130 can be used as an isolation structure. In some embodiments, the gate structure 140 filled in the trenches 111 and 112 is regarded as a dummy gate structure, and the gate structure 140 filled in the trench 113 is regarded as an active gate structure.

[0044] Reference Figure 4In step S16, a first mask 160 is formed to cover the active area A1 of the substrate 100, while the peripheral area A2 of the substrate 100 is not covered by the first mask 160. In some embodiments, the peripheral area A2 is located at the periphery of the substrate 100, and the active area A1 is surrounded by the peripheral area A2. After the first mask 160 is formed on the active area A1 of the substrate 100, one or more etching steps are performed to remove the portion of the hard mask layer 120, the insulating layer 130, and the top conductive layer 146 that are not protected by the first mask 160. After performing the one or more etching steps, the surface 101 of the substrate 100 at the peripheral area A2 is exposed again and is not covered by the first mask 160. After removing the portion of the hard mask layer 120, the insulating layer 130, and the top conductive layer 146, the first mask 160 can be removed.

[0045] Reference Figure 5 In step S18, a second mask 170 is formed on the substrate 100. The second mask 170 is formed on the active area A1 and the peripheral area A2 of the substrate 100. More specifically, the active area A1 of the substrate 100 is completely covered by the second mask 170, and a portion of the peripheral area A2 is exposed to the second mask 170. For example, the second mask 170 is a patterned mask having a plurality of openings 172, and the openings 172 are used to expose a portion of the peripheral area A2 of the substrate 100. In some embodiments, the material of the second mask 170 may be a photoresist.

[0046] Next refer to Figure 6 In step S20, an etching process is performed through the opening 172 to remove a portion of the substrate 100, thereby forming a plurality of recesses 180 on the surface 101 of the substrate 100. In some embodiments, the substrate 100 is single crystal silicon and has a specific lattice arrangement direction, and the etching process is a wet etching process, which has a significantly higher etching rate for the silicon substrate in the direction corresponding to the lattice arrangement. Therefore, the formed recess 180 also has a sidewall 182 and a bottom angle 184 defined by the sidewall 182.

[0047] For example, in some embodiments, the substrate 100 is a single crystal silicon substrate, and its lattice arrangement direction is Si <100> The wet etching process can use sodium hydroxide solution as an etchant. This wet etching process has sufficient chemical strength to etch Si with low density. <100> planar, but in the denser Si <111> The plane has a relatively weak chemical strength. Therefore, the sidewall 182 of the recess 180 is along the Si <111> Alternatively, in some other embodiments, the substrate 100 is a single crystal silicon substrate, and its lattice arrangement direction is Si <111> The corresponding wet etching process uses potassium hydroxide solution as the etchant.

[0048] Since the etching direction of the wet etching is directly related to the lattice arrangement direction of the facets of the substrate 100, the sidewall 182 of the recess 180 formed by the wet etching is relatively smooth. In addition, the bottom angle 184 of the recess 180 has a sharp and sharp profile. In some embodiments, each recess 180 has a V-shaped cross-section, and the angle θ of the bottom angle 184 of the recess 180 is about 90 degrees.

[0049] After the recess 180 is formed in the peripheral area A2 of the substrate 100 , the second mask 170 may be removed.

[0050] Reference Figure 7 In step S22, an oxidation process is performed to form an oxide layer 190 on the peripheral area A2 of the substrate 100. More specifically, the oxide layer 190 is formed by converting the surface of the silicon substrate in the peripheral area A2 of the substrate 100 into oxide. Since the surface roughness of the surface 101 of the substrate 100 and the sidewall 182 of the recess 180 is very smooth, the formed oxide layer 190 can have thin and uniform characteristics. In some embodiments, the oxide layer 190 located in the peripheral area A2 and the insulating layer 130 located in the active area A1 can be bridged together by the hard mask layer 120.

[0051] After the oxide layer 190 is formed on the surface 101 of the substrate 100 and the sidewall 182 of the recess 180, the polysilicon layer 200 is deposited on the oxide layer 190. In some embodiments, the polysilicon layer 200 may be deposited to fill the recess 180. In some embodiments, an etch-back process may be further performed to allow the polysilicon layer 200 to have a flat upper surface.

[0052] A conductive layer 210 is then deposited on the polysilicon layer 200. The material of the conductive layer 210 in the peripheral region A2 can be the same as or different from the material of the top conductive layer 146 in the active region A1. In some embodiments, the material of the conductive layer 210 in the peripheral region A2 can be a low-resistance material, such as metal. In some embodiments, the material of the conductive layer 210 can be tungsten.

[0053] Optionally, a planarization process is performed to make the upper surface of the conductive layer 210 in the peripheral region A2 flush with the upper surface of the top conductive layer 146 in the active region A1. In some other embodiments, the upper surface of the conductive layer 210 in the peripheral region A2 may be higher or lower than the upper surface of the top conductive layer 146 in the active region A1.

[0054] Reference Figure 8In step S24, a planarization process is performed to form a plurality of fuse elements 220 and a plurality of contacts 230 in the peripheral area A2. That is, the fuse elements 220 and the contacts 230 are formed simultaneously, and the cross-section of the fuse elements 220 is different from the cross-section of the contacts 230. Each fuse element 220 includes a dielectric film 222, a polysilicon portion 224 on the dielectric film 222, and a conductive portion 226 on the polysilicon portion 224. Each contact 230 includes a dielectric film 232, a polysilicon portion 234 on the dielectric film 232, and a conductive portion 236 on the polysilicon portion 234. The main difference between the cross-section of the fuse element 220 and the cross-section of the contact 230 is that the polysilicon portion 224 of the fuse element 220 extends further into the substrate 100 and has a bottom tip 224c pointing to the bottom of the substrate 100, and the dielectric film 222 of the fuse element 220 is V-shaped. The bottom tip 224c of the fuse element 220 is lower than the surface 101 of the substrate 100. In contrast, the polysilicon portion 234 of the contact 230 has a rectangular cross-section, and the dielectric film 232 of the contact 230 is flat against the surface 101 of the substrate 100.

[0055] In some embodiments, the contact 230 includes a gate contact, which can be coupled to the word line 150 via a conductive line or other interconnect structure.

[0056] In some embodiments, individual fuse elements 220 may be connected to a main circuit, a redundant circuit, or a duplicate circuit in the substrate 100. In some embodiments, the fuse element 220 connected to a defective main circuit may be blown (disabled) to allow the duplicate circuit to be turned on, which is based on the purpose of repair. In other embodiments, one fuse element 220 is connected to the main circuit, and another fuse element 220 is connected to the redundant circuit, and one of the main circuit or the redundant circuit is selectively blown (disabled) to allow the other of the main circuit or the redundant circuit to operate, which is based on the purpose of customization.

[0057] Each fuse element 220 includes a dielectric film 222 located in the recess 180 of the substrate 100, a polysilicon portion 224 on the dielectric film 222, and a conductive portion 226 on the polysilicon portion 224. The dielectric film 222 is conformally formed on the sidewall 182 of the recess 180, and the conductive portion 226 has a lower resistance than the polysilicon portion 224. The polysilicon portion 224 includes a bottom block 224b and a top block 224t. The bottom block 224b of the polysilicon portion 224 is embedded in the substrate 100 and fills the recess 180. The top block 224t of the polysilicon portion 224 is disposed on the bottom block 224b and protrudes from the surface 101 of the substrate 100. The bottom block 224b has a bottom tip 224c pointing to the bottom of the substrate 100. The angle θ of the bottom tip 224c is approximately 90 degrees. The bottom tip 224c of the bottom block 224b is beneficial to concentrate the electric field, so as to induce a tip discharge effect in the bottom block 224b of the polysilicon portion 224 when an external voltage is applied to the fuse element 220. Therefore, the breakdown voltage required to blow (disable) the fuse element 220 can be reduced accordingly.

[0058] Reference Fig. 9 , which is a top view of the peripheral area of ​​a semiconductor device according to some embodiments of the present disclosure. The fuse element 220 can be connected to the circuit through a wire 250. The wire 250 can be part of an internal connection structure, and the level of the wire 250 can be higher or lower than the fuse element 220.

[0059] According to some embodiments of the present disclosure, the fuse element has a bottom tip, which is beneficial for concentrating the electric field so as to induce a tip discharge effect at the bottom tip when an external voltage is applied to the fuse element, thereby reducing the breakdown voltage required to blow (disable) the fuse element.

[0060] Although the present disclosure has been disclosed as above by way of embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the definition of the attached claims.

[0061]

Explanation of symbols

[0062] 100:Substrate

[0063] 101,102,S1: Surface

[0064] 111,112,113: Grooves

[0065] 120: Hard mask layer

[0066] 130: Insulation layer

[0067] 140: Gate structure

[0068] 142: bottom conductive layer

[0069] 144: Middle conductive layer

[0070] 146: Top conductive layer

[0071] 150: Character line

[0072] 160: First mask

[0073] 170: Second mask

[0074] 172: Opening

[0075] 180: Depression

[0076] 182: Side wall

[0077] 184: Bottom corner

[0078] 190: Oxide layer

[0079] 200: Polysilicon layer

[0080] 210: Conductive layer

[0081] 220: Fuse element

[0082] 222,232: Dielectric film

[0083] 224,234: Polysilicon part

[0084] 224b: Bottom block

[0085] 224t: Top block

[0086] 224c: bottom tip

[0087] 226,236: Conductive part

[0088] 230: Contact

[0089] 250: Wire

[0090] A1: Active area

[0091] A2: Surrounding area

[0092] S10, S12, S14, S16, S18, S20, S22, S24: Steps

[0093] T1, T2: thickness

[0094] θ: angle.

Claims

1. A semiconductor device, characterized in that: Include: a substrate having an active region and a peripheral region surrounding the active region; A plurality of gate structures are disposed in the active region of the substrate; as well as A fuse element is disposed in the peripheral region of the substrate, wherein the fuse element comprises a polysilicon portion having a bottom tip pointing toward the substrate, a dielectric film disposed between the polysilicon portion and the substrate, and a conductive portion disposed on the polysilicon portion. 2 . The semiconductor device according to claim 1 , wherein the bottom tip of the polysilicon portion has an angle, and the angle is 90 degrees.

3. The semiconductor device according to claim 1, wherein the dielectric film has a V-shaped cross section. 4 . The semiconductor device of claim 1 , wherein the bottom tip of the polysilicon portion is lower than an upper surface of the substrate. The semiconductor device according to claim 1 , wherein a resistance of the conductive portion is lower than a resistance of the polysilicon portion. 6 . The semiconductor device according to claim 1 , wherein the polysilicon portion comprises a bottom block and a top block, the bottom block being embedded in the substrate, and the top block being protruding from the substrate. 7 . The semiconductor device according to claim 1 , wherein the plurality of gate structures include a dummy gate structure and an active gate structure, and the dummy gate structure is disposed at an edge of the active region.

8. The semiconductor device according to claim 7, wherein: It also includes an insulating layer disposed between the plurality of gate structures and the substrate, wherein the insulating layer has a first portion between the dummy gate structure and the substrate and a second portion between the active gate structure and the substrate, and the thickness of the first portion is greater than the thickness of the second portion.

9. The semiconductor device according to claim 1, wherein: The invention also comprises a contact element, which is arranged in the peripheral area of ​​the substrate, wherein the contact element comprises a dielectric film arranged on the substrate, a polysilicon portion arranged on the dielectric film, and a conductive portion arranged on the polysilicon portion. 10 . The semiconductor device of claim 9 , wherein a cross-section of the polysilicon portion of the fuse element is different from a cross-section of the polysilicon portion of the contact.

11. A method for manufacturing a semiconductor device, characterized in that: Include: forming a plurality of gate structures in an active region of the substrate; forming a mask on the substrate, wherein the mask covers the active area and has an opening to expose a portion of the substrate; etching the portion of the substrate through the opening of the mask to form a recess in a peripheral region of the substrate, wherein the recess has a bottom angle; as well as A fuse element is formed in the recess.

12. The method of claim 11, wherein etching the portion of the substrate comprises using a sodium hydroxide solution as an etchant.

13. The method of claim 11, wherein etching the portion of the substrate comprises using a potassium hydroxide solution as an etchant. The method according to claim 11 , wherein the bottom angle of the recess is 90 degrees.

15. The method according to claim 11, wherein: Also includes: After the recess is formed, removing the mask; and An oxidation process is performed to form an oxide layer blanketing the recess and the peripheral area of ​​the substrate.

16. The method according to claim 15, wherein: Also includes: forming a polysilicon layer on the oxide layer; forming a conductive layer on the polysilicon layer; and The oxide layer, the polysilicon layer, and the conductive layer are patterned to form the fuse element, wherein the fuse element includes a dielectric film on the substrate, a polysilicon portion on the dielectric film, and a conductive portion on the polysilicon portion. 17 . The method of claim 16 , wherein the step of forming a polysilicon layer on the oxide layer comprises filling the recess with the polysilicon layer such that the polysilicon portion of the fuse element has a bottom tip. 18 . The method of claim 16 , wherein patterning the oxide layer, the polysilicon layer, and the conductive layer comprises forming a contact at the peripheral region of the substrate. The method according to claim 16 , wherein a resistance of the conductive layer is lower than a resistance of the polysilicon layer.

20. The method of claim 16, wherein the dielectric film of the fuse element has a V-shaped cross-section.

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