Three-dimensional memory preparation process based on self-alignment dual imaging

Abstract

The invention provides a three-dimensional memory preparation process based on self-alignment dual imaging, which comprises the following steps: forming a first mesh mask layer on a three-dimensional memory substrate, and transferring a pattern of the first mesh mask layer to the three-dimensional memory substrate through etching to form a circular hole array; forming a second mesh mask layer on the three-dimensional memory substrate, and transferring the pattern of the second mesh mask layer to the three-dimensional memory substrate through etching to form an annular groove array; the annular grooves in the annular groove array are in one-to-one correspondence with the circular holes in the circular hole array, and the circular holes are located in the centers of the corresponding annular grooves; the first net-shaped mask layer comprises a first strip-shaped mask layer and a second strip-shaped mask layer, and the second net-shaped mask layer comprises a third strip-shaped mask layer and a fourth strip-shaped mask layer; the first strip-shaped mask layer, the second strip-shaped mask layer, the third strip-shaped mask layer and the fourth strip-shaped mask layer are prepared through self-alignment dual imaging. The size of the storage unit is reduced, and the storage density is improved.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a three-dimensional memory preparation process based on self-aligned double imaging. Background Art

[0002] Currently, 1S1C memory has become a very likely candidate for the next generation DRAM (Dynamic Random Access Memory) memory, but the ring and circular size miniaturization of 1S1C memory still faces certain difficulties, which limits the further improvement of the density of 1S1C memory and reduces the possibility of its further application. Therefore, it is necessary to study the key ring size and circular size miniaturization process of 1S1C memory.

[0003] Since the diffraction limit of the lithography system is a circular spot, it means that when preparing a ring structure, a circular spot with a diffraction limit is required to form a circle. Therefore, the inner diameter of the ring structure will be much larger than the diffraction limit of the lithography system, and the ring width of the ring structure will directly affect the capacitance of the capacitor in the prepared 1S1C. The wider the ring width, the lower the capacitance. According to the traditional preparation process, the minimum ring width is the diameter of the circular spot with the diffraction limit of the lithography system, which will greatly reduce the capacitance of the storage unit. Therefore, it is necessary to develop a specific preparation process for 1S1C memory to prepare higher density three-dimensional 1S1C memory. Summary of the invention

[0004] The present invention provides a three-dimensional memory preparation process based on self-aligned double imaging, which is used to solve the size miniaturization defect faced by 1S1C memory in the prior art, and realizes the introduction of multiple exposure technology into three-dimensional 1S1C preparation, thereby improving the storage unit density of three-dimensional 1S1C and further improving the overall performance of the memory.

[0005] The present invention provides a three-dimensional memory preparation process based on self-aligned double imaging, comprising:

[0006] Forming a first mesh mask layer on a three-dimensional memory substrate, and transferring the pattern of the first mesh mask layer to the three-dimensional memory substrate by etching to form a circular hole array;

[0007] forming a second mesh mask layer on the three-dimensional memory substrate, and transferring the pattern of the second mesh mask layer to the three-dimensional memory substrate by etching to form an annular groove array;

[0008] The annular grooves in the annular groove array correspond one to one with the circular holes in the circular hole array, and the circular holes are located at the centers of the corresponding annular grooves;

[0009] The first mesh mask layer includes a first strip mask layer and a second strip mask layer, and the second mesh mask layer includes a third strip mask layer and a fourth strip mask layer;

[0010] The first stripe mask layer, the second stripe mask layer, the third stripe mask layer and the fourth stripe mask layer are all prepared by self-aligned double imaging;

[0011] The spacing between all the strip lines in the first strip mask layer and the second strip mask layer is c, and the width of the strip lines is a;

[0012] The spacing between all the strip lines in the third strip mask layer and the fourth strip mask layer is f, and the width of the strip lines is d;

[0013] Among them, a+c=d+f, d<a, f>c.

[0014] According to a three-dimensional memory manufacturing process based on self-aligned double imaging provided by the present invention, the manufacturing process of the first stripe mask layer includes:

[0015] forming a first sacrificial layer, a first hard mask layer, a second sacrificial layer and a second hard mask layer in sequence on the three-dimensional memory substrate;

[0016] Leaving a plurality of parallel first strip photoresists on the second hard mask layer by photolithography, wherein the first strip photoresists have a strip width of a and a spacing of b;

[0017] Using the first strip photoresist as a mask, etching the second hard mask layer and the second sacrificial layer;

[0018] Uniformly depositing a first covering layer, wherein the first covering layer grows uniformly on the surface and the side, and the thickness of the first covering layer is c;

[0019] removing the first covering layer on the surface and retaining the first covering layer on the side;

[0020] Using the first covering layer as a mask, etching the first hard mask layer and the first sacrificial layer;

[0021] A first filling layer is deposited, and the surface is flattened by a planarization technique, and the surface of the first sacrificial layer is exposed, the strip width of the first sacrificial layer is c, and the strip width of the first filling layer is a.

[0022] According to a three-dimensional memory manufacturing process based on self-aligned double imaging provided by the present invention, the thickness c of the first covering layer and the stripe width a and the spacing b are in a relationship of a=b-2c.

[0023] According to a three-dimensional memory manufacturing process based on self-aligned double imaging provided by the present invention, the second stripe mask layer has the same manufacturing process and size as the first stripe mask layer;

[0024] The angle α between the lines in the second strip-shaped mask layer and the lines in the first strip-shaped mask layer in the horizontal direction is greater than 30°.

[0025] According to a three-dimensional memory manufacturing process based on self-aligned double imaging provided by the present invention, the manufacturing process of the first mesh mask layer includes:

[0026] forming a first stripe-shaped mask layer on the three-dimensional memory substrate;

[0027] forming a second stripe-shaped mask layer on the first stripe-shaped mask layer;

[0028] The first sacrificial layer in the first strip mask layer and the second strip mask layer is selectively removed, and the remaining first filling layer constitutes the first mesh mask layer.

[0029] According to a three-dimensional memory manufacturing process based on self-aligned double imaging provided by the present invention, the manufacturing process of the third stripe mask layer is the same as that of the first stripe mask layer;

[0030] In the preparation process of the third strip mask layer, the strip width of the first strip photoresist is d, the spacing is e, the thickness of the first covering layer is f, the final strip width of the first sacrificial layer is f, and the final strip width of the first filling layer is d;

[0031] Among them, d+e=a+b.

[0032] According to a three-dimensional memory manufacturing process based on self-aligned double imaging provided by the present invention, the thickness f of the first covering layer and the stripe width d and the spacing e are in a relationship of d=e-2f.

[0033] According to a three-dimensional memory manufacturing process based on self-aligned double imaging provided by the present invention, the fourth stripe mask layer has the same manufacturing process and size as the third stripe mask layer;

[0034] The angle α between the fourth strip-shaped mask layer and the lines in the third strip-shaped mask layer in the horizontal direction is greater than 30°;

[0035] The lines in the third strip-shaped mask layer and the first strip-shaped mask layer are parallel to each other, and their projection centers coincide with each other in the vertical direction;

[0036] The lines in the fourth strip-shaped mask layer and the second strip-shaped mask layer are parallel to each other, and the projection centers of the lines in the vertical direction coincide with each other.

[0037] According to a three-dimensional memory manufacturing process based on self-aligned double imaging provided by the present invention, the manufacturing process of the second mesh mask layer includes:

[0038] forming the third stripe-shaped mask layer on the three-dimensional memory substrate;

[0039] forming the fourth stripe-shaped mask layer on the third stripe-shaped mask layer;

[0040] The first sacrificial layer in the third strip-shaped mask layer and the fourth strip-shaped mask layer is selectively removed, and the remaining first filling layer constitutes the second mesh mask layer.

[0041] According to a three-dimensional memory manufacturing process based on self-aligned double imaging provided by the present invention, the manufacturing process of the annular groove array includes:

[0042] Depositing a third hard mask layer, a third sacrificial layer and a fourth hard mask layer in sequence on the three-dimensional memory substrate, and forming the second mesh mask layer on the fourth hard mask layer;

[0043] Using the second mesh mask layer as a template, etching the fourth hard mask layer and the third sacrificial layer to form a plurality of circular holes;

[0044] Uniformly depositing a second covering layer, wherein the second covering layer grows uniformly on the surface and the side, and the thickness of the second covering layer is g;

[0045] removing the second covering layer on the surface, retaining the second covering layer on the side, and removing the fourth hard mask layer and the third sacrificial layer remaining on the surface;

[0046] Depositing a second filling layer, and making the surface flat by a planarization technology, and exposing the surface of the second covering layer, wherein the strip ring width of the second covering layer is g;

[0047] The second covering layer is selectively removed, and the third hard mask layer and the three-dimensional memory substrate are etched using the remaining second filling layer as a template to form the annular groove array on the three-dimensional memory substrate, wherein the annular groove has a ring width of g.

[0048] The present invention provides a three-dimensional memory preparation process based on self-aligned double imaging. The structure of the three-dimensional memory is mainly composed of circular through holes and annular grooves. The preparation of the circular through holes and the preparation of the annular grooves both rely on a mesh mask layer, which can prepare a mesh mask layer with a smaller size and a denser mesh, which means that the characteristic size of the storage unit can be reduced and the storage density of the memory can be improved. The use of the self-aligned double imaging process to prepare the three-dimensional memory can continue to miniaturize the size of the storage unit and improve the storage density without using a more advanced lithography system, thereby improving the overall performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 It is a schematic diagram of the process flow of preparing a circular through-hole array in the three-dimensional memory preparation process based on self-aligned double imaging provided by the present invention;

[0051] Figure 2 It is a schematic diagram of the process flow of preparing an annular groove array in the three-dimensional memory preparation process based on self-aligned double imaging provided by the present invention;

[0052] Figure 3 It is a schematic diagram of the process flow of preparing a three-dimensional memory based on self-aligned double imaging provided by the present invention. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] Combine the following Figures 1 to 3 The present invention describes a three-dimensional memory preparation process based on self-aligned double imaging, comprising:

[0055] Forming a first mesh mask layer on a three-dimensional memory substrate, and transferring the pattern of the first mesh mask layer to the three-dimensional memory substrate by etching to form a circular hole array;

[0056] forming a second mesh mask layer on the three-dimensional memory substrate, and transferring the pattern of the second mesh mask layer to the three-dimensional memory substrate by etching to form an annular groove array;

[0057] The annular grooves in the annular groove array correspond one to one with the circular holes in the circular hole array, and the circular holes are located at the centers of the corresponding annular grooves;

[0058] The first mesh mask layer includes a first strip mask layer and a second strip mask layer, and the second mesh mask layer includes a third strip mask layer and a fourth strip mask layer;

[0059] The first stripe mask layer, the second stripe mask layer, the third stripe mask layer and the fourth stripe mask layer are all prepared by self-aligned double imaging;

[0060] The spacing between all the strip lines in the first strip mask layer and the second strip mask layer is c, and the width of the strip lines is a;

[0061] The spacing between all the strip lines in the third strip mask layer and the fourth strip mask layer is f, and the width of the strip lines is d;

[0062] Among them, a+c=d+f, d<a, f>c.

[0063] When it is necessary to use a self-aligned double imaging process to prepare a three-dimensional memory, the order of preparing the annular groove array and the circular hole array can be adjusted according to actual process requirements, and the remaining thin film materials can be grown in the circular holes or annular grooves without affecting the alignment process of the annular groove array and the circular hole array, ensuring that there is a circular hole in the center of each annular groove, and the circular through hole is almost located in the center of the annular groove.

[0064] Although the first mesh mask layer is used to prepare a circular hole array and the second mesh mask layer is used to prepare an annular groove array, in order to ensure that there is a circular hole in the center of each annular groove, it is necessary to ensure that the line period of the first mesh mask layer and the second mesh mask layer is consistent, so a+c=d+f is required. In addition, since the circular hole is located in the center of the ring, it means that the size of the ring needs to be larger than the circular hole, so d<a, f>c is required.

[0065] It is necessary to satisfy d<a, which means that starting from the first layer of photoresist lines, it is necessary to ensure that the photoresist lines used to prepare the ring are narrower than the photoresist lines used to prepare the holes, and f>c, which means that the thickness of the second covering layer deposited on the side wall for preparing the ring is thicker than the first covering layer deposited on the side wall for preparing the hole, so that the inner diameter of the annular groove is larger than the circular hole, so that the circular hole is located in the center of the annular groove.

[0066] The structure of the three-dimensional memory in this embodiment is mainly composed of circular through holes and annular grooves. The preparation of the circular through holes and the preparation of the annular grooves both rely on the mesh mask layer. A mesh mask layer with a smaller size and a denser mesh can be prepared, which means that the characteristic size of the storage unit can be reduced and the storage density of the memory can be improved. The three-dimensional memory is prepared using a self-aligned dual imaging process, and the size of the storage unit can continue to be miniaturized without using a more advanced lithography system, thereby improving the storage density and improving the overall performance of the memory.

[0067] Based on the above embodiments, Figure 1 As shown, the preparation process of the first stripe mask layer in this embodiment includes:

[0068] forming a first sacrificial layer, a first hard mask layer, a second sacrificial layer and a second hard mask layer in sequence on the three-dimensional memory substrate;

[0069] Leaving a plurality of parallel first strip photoresists on the second hard mask layer by photolithography, wherein the first strip photoresists have a strip width of a and a spacing of b;

[0070] Using the first strip photoresist as a mask, etching the second hard mask layer and the second sacrificial layer;

[0071] Uniformly depositing a first covering layer, wherein the first covering layer grows uniformly on the surface and the side, and the thickness of the first covering layer is c;

[0072] removing the first covering layer on the surface and retaining the first covering layer on the side;

[0073] Using the first covering layer as a mask, etching the first hard mask layer and the first sacrificial layer;

[0074] A first filling layer is deposited, and the surface is flattened by a planarization technique, and the surface of the first sacrificial layer is exposed, the strip width of the first sacrificial layer is c, and the strip width of the first filling layer is a.

[0075] Figure 1 1.1 to 1.7 are the process flow charts for preparing the first stripe mask layer, wherein:

[0076] Figure 1 1.1 is to form a first sacrificial layer, a first hard mask layer, a second sacrificial layer and a second hard mask layer on a given three-dimensional memory substrate, and leave parallel first strips of photoresist on the second hard mask layer by photolithography, wherein the strip width is a and the spacing is b;

[0077] Figure 1 1.2 is etching the second hard mask layer and the second sacrificial layer using the first strip photoresist as a mask;

[0078] Figure 1 1.3 in the figure is to uniformly deposit a first covering layer, and the first covering layer grows uniformly on the surface and the side surface;

[0079] 1.4: remove the first covering layer on the surface and keep the first covering layer on the side. The thickness of the first covering layer is c, and a=b-2c;

[0080] Figure 1 1.5 in which the first hard mask layer and the first sacrificial layer are etched using the first covering layer as a mask;

[0081] Figure 1 1.6 in the figure means depositing a first filling layer, and the strip width of the first filling layer is a;

[0082] Figure 1 The 1.7 in the figure means that the surface of the substrate is made flat by the planarization technology, so that the surface of the first sacrificial layer is exposed.

[0083] On the basis of the above embodiment, in this embodiment, the thickness c of the first covering layer and the strip width a and the spacing b are in the relationship of a=b-2c.

[0084] There are two possible spacings between the lines prepared by the self-aligned double imaging technology. However, when preparing memory cells, it is necessary to ensure that the shape of each memory cell is as consistent as possible to improve the consistency of the memory cells. The spacing between the lines will directly affect the size of the memory cells. Therefore, special design is required to make the two possible spacings eventually approach the same.

[0085] The relationship between the thickness c of the first covering layer and the stripe width a and the spacing b is as follows: a=b-2c. The purpose is to make the two possible line spacings of the lines prepared by the self-aligned double imaging technology consistent.

[0086] On the basis of the above embodiment, in this embodiment, the preparation process and size of the second strip-shaped mask layer are the same as those of the first strip-shaped mask layer;

[0087] The angle α between the lines in the second strip-shaped mask layer and the lines in the first strip-shaped mask layer in the horizontal direction is greater than 30°.

[0088] Figure 1 1.8 to 1.13 are the process flow charts for preparing the second strip mask layer. The second strip mask layer and the first strip mask layer have an angle α in the horizontal direction, α>30°. α refers to the angle of the minimum angle between the lines in the horizontal direction. The rest of the process flow for preparing the second strip mask layer is the same as that of the first strip mask layer, and will not be repeated.

[0089] On the basis of the above embodiment, the preparation process of the first mesh mask layer in this embodiment includes:

[0090] forming a first stripe-shaped mask layer on the three-dimensional memory substrate;

[0091] forming a second stripe-shaped mask layer on the first stripe-shaped mask layer;

[0092] The first sacrificial layer in the first strip mask layer and the second strip mask layer is selectively removed, and the remaining first filling layer constitutes the first mesh mask layer.

[0093] Figure 1 1.14 in the figure represents the selective removal of the first sacrificial layer in the first strip mask layer and the second strip mask layer, and the remaining first filling layer constitutes the first mesh mask layer.

[0094] Figure 1 1.15 in the figure is to transfer the pattern of the first mesh mask layer to the three-dimensional memory substrate by etching using the first mesh mask layer as a template to form a circular hole array, and then remove the surface residue.

[0095] Based on the above embodiments, Figure 2 As shown, the preparation process of the third strip-shaped mask layer in this embodiment is the same as that of the first strip-shaped mask layer;

[0096] In the preparation process of the third strip mask layer, the strip width of the first strip photoresist is d, the spacing is e, the thickness of the first covering layer is f, the final strip width of the first sacrificial layer is f, and the final strip width of the first filling layer is d;

[0097] Among them, d+e=a+b.

[0098] In the preparation process of the third strip mask layer, only the strip width of the first strip photoresist is modified to d, the spacing is modified to e, and the thickness of the first covering layer is modified to f in the preparation process of the first strip mask layer; finally, the strip width of the first sacrificial layer is f, and the strip width of the first filling layer is d.

[0099] d+e=a+b means that during the first layer of photolithography, it is necessary to ensure that the line period of the rings used to make the holes is consistent. d<a means that during the first layer of photolithography, it is necessary to ensure that the photoresist lines used to make the rings are narrower than the photoresist lines used to make the holes.

[0100] Figure 2 2.1 to 2.7 are the process flow charts for preparing the third stripe mask layer, including:

[0101] First, a third hard mask layer, a third sacrificial layer and a fourth hard mask layer are sequentially deposited on a given three-dimensional memory substrate;

[0102] Figure 2 2.1 in which the first sacrificial layer, the first hard mask layer, the second sacrificial layer and the second hard mask layer are continuously deposited in sequence, and first parallel strips of photoresist are left on the second hard mask layer by photolithography, wherein the strip width is d and the spacing is e, and d+e=a+b;

[0103] Figure 2 2.2 in which the second hard mask layer and the second sacrificial layer are etched using the first strip photoresist as a mask;

[0104] Figure 2 2.3 in the figure is to uniformly deposit a first covering layer, and the first covering layer grows uniformly on the surface and the side surface;

[0105] Figure 2 2.4 in which the first covering layer on the surface is removed and the first covering layer on the side is retained. The thickness of the first covering layer is f, and d = e-2f;

[0106] Figure 2 2.5 in which the first hard mask layer and the first sacrificial layer are etched using the first cover layer as a mask;

[0107] Figure 2 2.6 in the figure means depositing a first filling layer, and the strip width of the first filling layer is d;

[0108] Figure 2 2.7 in the figure means that the surface of the substrate is made flat by the planarization technology so that the surface of the first sacrificial layer is exposed.

[0109] On the basis of the above embodiment, in this embodiment, the thickness f of the first covering layer, the strip width d, and the spacing e are in the relationship d=e-2f.

[0110] d=e-2f means that the two possible line spacings of the lines prepared by the self-aligned double imaging technology remain consistent.

[0111] On the basis of the above embodiment, the fourth strip-shaped mask layer in this embodiment has the same preparation process and size as the third strip-shaped mask layer;

[0112] The angle α between the fourth strip-shaped mask layer and the lines in the third strip-shaped mask layer in the horizontal direction is greater than 30°;

[0113] The lines in the third strip-shaped mask layer and the first strip-shaped mask layer are parallel to each other, and their projection centers coincide with each other in the vertical direction;

[0114] The lines in the fourth strip-shaped mask layer and the second strip-shaped mask layer are parallel to each other, and the projection centers of the lines in the vertical direction coincide with each other.

[0115] Figure 2 2.8-2.14 in the figure are the process flow charts for preparing the fourth strip mask layer. The fourth strip mask layer and the third strip mask layer have an angle α in the horizontal direction, α>30°, and α refers to the angle of the minimum angle between the lines in the horizontal direction. The rest of the process flow for preparing the fourth strip mask layer is the same as that of the third strip mask layer, and will not be repeated here.

[0116] Projection center coincidence means that the width of the lines can be different, but from a bird's-eye view, the center lines of the lines need to coincide.

[0117] On the basis of the above embodiment, the preparation process of the second mesh mask layer in this embodiment includes:

[0118] forming the third stripe-shaped mask layer on the three-dimensional memory substrate;

[0119] forming the fourth stripe-shaped mask layer on the third stripe-shaped mask layer;

[0120] The first sacrificial layer in the third strip-shaped mask layer and the fourth strip-shaped mask layer is selectively removed, and the remaining first filling layer constitutes the second mesh mask layer.

[0121] Based on the above embodiments, Figure 2 As shown, the preparation process of the annular groove array in this embodiment includes:

[0122] Depositing a third hard mask layer, a third sacrificial layer and a fourth hard mask layer in sequence on the three-dimensional memory substrate, and forming the second mesh mask layer on the fourth hard mask layer;

[0123] Using the second mesh mask layer as a template, etching the fourth hard mask layer and the third sacrificial layer to form a plurality of circular holes;

[0124] Uniformly depositing a second covering layer, wherein the second covering layer grows uniformly on the surface and the side, and the thickness of the second covering layer is g;

[0125] removing the second covering layer on the surface, retaining the second covering layer on the side, and removing the fourth hard mask layer and the third sacrificial layer remaining on the surface;

[0126] Depositing a second filling layer, and making the surface flat by a planarization technology, and exposing the surface of the second covering layer, wherein the strip ring width of the second covering layer is g;

[0127] The second covering layer is selectively removed, and the third hard mask layer and the three-dimensional memory substrate are etched using the remaining second filling layer as a template to form the annular groove array on the three-dimensional memory substrate, wherein the annular groove has a ring width of g.

[0128] Figure 2 2.15 is to selectively remove the first sacrificial layer in the third strip mask layer and the fourth strip mask layer, the remaining first filling layer constitutes the second mesh mask layer, and the fourth hard mask layer and the third sacrificial layer are etched using the second mesh mask layer as a template to form a plurality of circular holes;

[0129] Figure 2 2.16 in the figure is a uniform deposition of a second covering layer, the second covering layer grows uniformly on the surface and the side, and the thickness of the second covering layer is g;

[0130] Figure 2 2.17 means removing the second covering layer on the surface and retaining the second covering layer on the side;

[0131] Figure 2 2.18 is to remove the fourth hard mask layer and the third sacrificial layer remaining on the surface; and deposit a second filling layer;

[0132] Figure 2 2.19 in the figure means that the surface of the substrate is made flat by the flattening technology, so that the surface of the second covering layer is exposed, and the strip ring width of the second covering layer is g;

[0133] Figure 2 2.20 in which the second covering layer is selectively removed;

[0134] Figure 2 2.21 is etching the third hard mask layer and the three-dimensional memory substrate using the remaining second filling layer as a template;

[0135] Figure 2 2.22 is to remove surface residues and form an annular groove array on the three-dimensional memory substrate.

[0136] Figure 3 The schematic diagram of the preparation process provided by the present invention is shown in FIG. Figure 3 3.1 to 3.14 in the figure are the preparation process flow of circular holes, including:

[0137] Figure 3 In 3.1, the bottom layer is a three-dimensional memory substrate formed by alternately stacking 50nm W and 100nm SiO2, and the top layer of the three-dimensional memory substrate is 100nm SiO2; 50nm SiO2, 20nm Cr, 50nm SiO2, and 20nm Cr are grown on the three-dimensional memory substrate in sequence, and the top layer is a photoresist line with a line width of 50nm and a spacing of 80nm;

[0138] Figure 3In 3.2, the top layer of 50nm SiO2 and 20nm Cr is etched using the photoresist lines as a mask;

[0139] Figure 3 In 3.3, a 15 nm SiN layer is uniformly deposited using the ALD process;

[0140] Figure 3 In 3.4, ICP etching with good anisotropy is used to remove the SiN on the surface, and wet etching is used to selectively remove the residual SiO2 and Cr, leaving the SiN on the sidewalls. The remaining strips of SiN are parallel to each other, with a strip width of 15 nm, a spacing of 50 nm, and a period of 65 nm.

[0141] Figure 3 In 3.5, the SiN on the sidewall is used as a mask to etch the 50nm SiO2 and 20nm Cr in the lower layer;

[0142] Figure 3 In 3.6, a 100 nm SiN layer is deposited by PVD, and the SiN on the surface is removed by CMP to expose the upper surface of SiO2;

[0143] Figure 3 3.7 to 3.13 are repeated in Figure 3 The only difference between the processes 3.1 to 3.6 is that the topmost photoresist line is at a 45° angle to the photoresist line in 3.1;

[0144] Figure 3 In 3.14, a buffered oxide etchant (BOE) is used to selectively remove SiO2, and the remaining SiN is used as a template to etch the three-dimensional memory substrate to form a circular hole array on the substrate, and the diameter of the circular hole is 23nm;

[0145] Figure 3 3.15 to 3.36 are the process flow for preparing the annular groove;

[0146] Figure 3 In 3.15, 20nm Cr, 50nm SiO2, 20nm Cr, 50nm SiO2, 20nm Cr, 50nm SiO2, and 20nm Cr are sequentially deposited on the surface of the three-dimensional memory substrate on which the circular hole array is prepared, and the top layer is a photoresist line with a line width of 30nm and a spacing of 100nm, and the top layer of the photoresist line coincides with the projection center line of the top layer of the photoresist line in 3.1;

[0147] Figure 3 In 3.16, the top layer of 50nm SiO2 and 20nm Cr is etched using the photoresist lines as a mask;

[0148] Figure 3 In 3.17, a 35 nm SiN layer is uniformly deposited using the ALD process;

[0149] Figure 3 In 3.18, ICP etching with good anisotropy is used to remove the SiN on the surface, and wet etching is used to selectively remove the residual SiO2 and Cr, leaving the SiN on the sidewalls. The remaining strips of SiN are parallel to each other, with a strip width of 35 nm, a spacing of 30 nm, and a period of 65 nm.

[0150] Figure 3 In 3.19, the SiN on the sidewall is used as a mask to etch the lower layer of 50nm SiO2 and 20nm Cr;

[0151] Figure 3 In 3.20, a 100 nm SiN layer is deposited using PVD;

[0152] Figure 3 In 3.21, CMP is used to remove the SiN on the surface to expose the upper surface of SiO2;

[0153] Figure 3 3.22 to 3.28 are repeated in Figure 3 The only difference between the processes 3.15 to 3.21 is that the topmost photoresist line is at a 45° angle to the photoresist line in 3.15;

[0154] Figure 3 In 3.29, a buffered oxide etchant (BOE) is used to selectively remove SiO2, and the remaining SiN is used as a template to etch 20nm Cr and 50nm SiO2 to form a circular hole array with a diameter of 53nm;

[0155] Figure 3 In 3.30, a 10 nm SiN layer is uniformly deposited using the ALD process;

[0156] Figure 3 In 3.31, ICP etching with good anisotropy is used to remove SiN on the surface, and buffered oxide etchant (BOE) is used to selectively remove SiO2, leaving SiN on the sidewall;

[0157] Figure 3 In 3.32, a 100nm SiO2 layer is deposited using PVD;

[0158] Figure 3 In 3.33, CMP is used to remove SiO2 on the surface to expose the SiN upper surface;

[0159] Figure 3 In 3.34, SiN is selectively removed;

[0160] Figure 3 In 3.35, the remaining SiO2 is used as a template to etch the Cr and three-dimensional memory substrate;

[0161] Figure 3 In 3.36, an annular groove array and a circular hole array prepared on a three-dimensional memory substrate are obtained, wherein the diameter of the circular hole is 23nm, the inner diameter of the annular groove is 33nm, and the ring width of the annular groove is 10nm.

Claims

1. A three-dimensional memory manufacturing process based on self-aligned double imaging, characterized in that: include: Forming a first mesh mask layer on a three-dimensional memory substrate, and transferring the pattern of the first mesh mask layer to the three-dimensional memory substrate by etching to form a circular hole array; forming a second mesh mask layer on the three-dimensional memory substrate, and transferring the pattern of the second mesh mask layer to the three-dimensional memory substrate by etching to form an annular groove array; The annular grooves in the annular groove array correspond one to one with the circular holes in the circular hole array, and the circular holes are located at the centers of the corresponding annular grooves; The first mesh mask layer includes a first strip mask layer and a second strip mask layer, and the second mesh mask layer includes a third strip mask layer and a fourth strip mask layer; The first stripe mask layer, the second stripe mask layer, the third stripe mask layer and the fourth stripe mask layer are all prepared by self-aligned double imaging; The spacing between all the strip lines in the first strip mask layer and the second strip mask layer is c, and the width of the strip lines is a; The spacing between all the strip lines in the third strip mask layer and the fourth strip mask layer is f, and the width of the strip lines is d; Among them, a+c=d+f, d<a, f>c.

2. The three-dimensional memory manufacturing process based on self-aligned double imaging according to claim 1, characterized in that: The preparation process of the first stripe mask layer includes: forming a first sacrificial layer, a first hard mask layer, a second sacrificial layer and a second hard mask layer in sequence on the three-dimensional memory substrate; Leaving a plurality of parallel first strip photoresists on the second hard mask layer by photolithography, wherein the first strip photoresists have a strip width of a and a spacing of b; Using the first strip photoresist as a mask, etching the second hard mask layer and the second sacrificial layer; Uniformly depositing a first covering layer, wherein the first covering layer grows uniformly on the surface and the side, and the thickness of the first covering layer is c; removing the first covering layer on the surface and retaining the first covering layer on the side; Using the first covering layer as a mask, etching the first hard mask layer and the first sacrificial layer; A first filling layer is deposited, and the surface is flattened by a planarization technique, and the surface of the first sacrificial layer is exposed, the strip width of the first sacrificial layer is c, and the strip width of the first filling layer is a.

3. The three-dimensional memory manufacturing process based on self-aligned dual imaging according to claim 2, characterized in that: The thickness c of the first covering layer has a relationship with the strip width a and the spacing b of a=b-2c.

4. The three-dimensional memory manufacturing process based on self-aligned double imaging according to claim 2, characterized in that: The second strip-shaped mask layer has the same preparation process and size as the first strip-shaped mask layer; The angle α between the lines in the second strip-shaped mask layer and the lines in the first strip-shaped mask layer in the horizontal direction is greater than 30°.

5. The three-dimensional memory manufacturing process based on self-aligned double imaging according to claim 2, characterized in that: The preparation process of the first mesh mask layer includes: forming a first stripe-shaped mask layer on the three-dimensional memory substrate; forming a second stripe-shaped mask layer on the first stripe-shaped mask layer; The first sacrificial layer in the first strip mask layer and the second strip mask layer is selectively removed, and the remaining first filling layer constitutes the first mesh mask layer.

6. The three-dimensional memory manufacturing process based on self-aligned double imaging according to claim 2, characterized in that: The preparation process of the third strip-shaped mask layer is the same as that of the first strip-shaped mask layer; In the preparation process of the third strip mask layer, the strip width of the first strip photoresist is d, the spacing is e, the thickness of the first covering layer is f, the final strip width of the first sacrificial layer is f, and the final strip width of the first filling layer is d; Among them, d+e=a+b.

7. The three-dimensional memory manufacturing process based on self-aligned double imaging according to claim 6, characterized in that: The thickness f of the first covering layer, the strip width d, and the spacing e are in the relationship d=e-2f.

8. The three-dimensional memory manufacturing process based on self-aligned double imaging according to claim 6, characterized in that: The fourth strip-shaped mask layer has the same preparation process and size as the third strip-shaped mask layer; The angle α between the fourth strip-shaped mask layer and the lines in the third strip-shaped mask layer in the horizontal direction is greater than 30°; The lines in the third strip-shaped mask layer and the first strip-shaped mask layer are parallel to each other, and their projection centers coincide with each other in the vertical direction; The lines in the fourth strip-shaped mask layer and the second strip-shaped mask layer are parallel to each other, and the projection centers of the lines in the vertical direction coincide with each other.

9. The three-dimensional memory manufacturing process based on self-aligned double imaging according to claim 8, characterized in that: The preparation process of the second mesh mask layer includes: forming the third stripe-shaped mask layer on the three-dimensional memory substrate; forming the fourth stripe-shaped mask layer on the third stripe-shaped mask layer; The first sacrificial layer in the third strip-shaped mask layer and the fourth strip-shaped mask layer is selectively removed, and the remaining first filling layer constitutes the second mesh mask layer.

10. The three-dimensional memory manufacturing process based on self-aligned double imaging according to any one of claims 1 to 9, characterized in that: The preparation process of the annular groove array includes: Depositing a third hard mask layer, a third sacrificial layer and a fourth hard mask layer in sequence on the three-dimensional memory substrate, and forming the second mesh mask layer on the fourth hard mask layer; Using the second mesh mask layer as a template, etching the fourth hard mask layer and the third sacrificial layer to form a plurality of circular holes; Uniformly depositing a second covering layer, wherein the second covering layer grows uniformly on the surface and the side, and the thickness of the second covering layer is g; removing the second covering layer on the surface, retaining the second covering layer on the side, and removing the fourth hard mask layer and the third sacrificial layer remaining on the surface; Depositing a second filling layer, and making the surface flat by a planarization technology, and exposing the surface of the second covering layer, wherein the strip ring width of the second covering layer is g; The second covering layer is selectively removed, and the third hard mask layer and the three-dimensional memory substrate are etched using the remaining second filling layer as a template to form the annular groove array on the three-dimensional memory substrate, wherein the annular groove has a ring width of g.

Images