Semiconductor device, memory system, and method of manufacturing semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, a memory system and a manufacturing method of the semiconductor device. The semiconductor device comprises: a first semiconductor structure comprising a plurality of first memory cells arranged in an array along a first direction and a second direction; the first bit line is positioned on one side of the first storage units in the third direction, extends along the first direction and is connected with the first storage units arranged along the first direction; the second semiconductor structure comprises a plurality of second storage units which are arranged in an array along the first direction and the second direction; the second bit line is positioned on one side of the second storage unit in the third direction, extends along the first direction and is connected with the second storage unit arranged along the first direction; wherein the first semiconductor structure and the second semiconductor structure are connected and are arranged along a third direction, and the first direction, the second direction and the third direction intersect with each other.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a memory system, and a method for manufacturing a semiconductor device. Background Art

[0002] In the semiconductor field, the process technology limits the miniaturization performance of semiconductor devices. As the process node continues to shrink, the miniaturization of semiconductor devices becomes more difficult. For example, for semiconductor memory, the process technology affects the expansion of storage density. Summary of the invention

[0003] The present application provides a semiconductor device, a memory system, and a method for manufacturing a semiconductor device that can at least partially solve the above-mentioned problems existing in the related art or other problems in the art.

[0004] In a first aspect, some embodiments of the present application provide a semiconductor device. The semiconductor device includes: a first semiconductor structure, including: a plurality of first storage cells arranged in an array along a first direction and a second direction; a first bit line located on one side of the first storage cell in a third direction, extending along the first direction, and connected to the first storage cells arranged along the first direction; and a second semiconductor structure, including: a plurality of second storage cells arranged in an array along the first direction and the second direction; a second bit line located on one side of the second storage cell in the third direction, extending along the first direction, and connected to the second storage cells arranged along the first direction; wherein the first semiconductor structure is connected to the second semiconductor structure and arranged along the third direction, and the first direction, the second direction, and the third direction intersect with each other.

[0005] In some embodiments, the first bit line and the second bit line are close to each other at the connection interface between the first semiconductor structure and the second semiconductor structure; the first bit line has at least one first cut and is disconnected into a first part and a second part at the first cut, and the second bit line has at least one second cut and is disconnected into a third part and a fourth part at the second cut.

[0006] In some embodiments, the first cutout and the second cutout are at least partially aligned in the third direction.

[0007] In some embodiments, the first portion is connected to one of the third portion and the fourth portion, and the second portion is connected to the other of the third portion and the fourth portion.

[0008] In some embodiments, the first portion is connected to the third portion, and the second portion is connected to the fourth portion, wherein the first portion and the third portion are located on the same side of the first incision in the first direction.

[0009] In some embodiments, the first portion is connected to the fourth portion, and the second portion is connected to the third portion, wherein the first portion and the third portion are located on the same side of the first incision in the first direction.

[0010] In some embodiments, a plurality of first bit lines are arranged in the second direction, a plurality of second bit lines are arranged in the second direction, and two first cutouts respectively located in the first bit lines adjacent to each other have a spacing in the first direction.

[0011] In some embodiments, the semiconductor device further includes a sense amplifier, and the first bit line and the second bit line are connected to the same sense amplifier.

[0012] In some embodiments, a plurality of first bit lines are arranged in the second direction, a plurality of second bit lines are arranged in the second direction, in a pair of the first bit line and the second bit line, the first portion is connected to the fourth portion, and in another adjacent pair of the first bit line and the second bit line, the second portion is connected to the third portion.

[0013] In some embodiments, the second portion of the first bit line is connected to the first portion of the adjacent first bit line, and the third portion of the second bit line is connected to the fourth portion of the adjacent second bit line.

[0014] In some embodiments, the semiconductor device also includes a sensing amplifier; the first portion of the first bit line, the second portion of the second bit line, the second portion of the adjacent first bit line, and the third portion of the adjacent second bit line are connected to the same sensing amplifier; the second portion of the first bit line, the first portion of the adjacent first bit line, the third portion of the second bit line, and the fourth portion of the adjacent second bit line are connected to the same sensing amplifier.

[0015] In some embodiments, the first semiconductor structure further includes: a first interconnect layer, located on a side of the first bit line away from the plurality of first memory cells; the second semiconductor structure further includes: a second interconnect layer, located on a side of the second bit line away from the plurality of second memory cells; wherein the first semiconductor structure and the second semiconductor structure are connected via the first interconnect layer and the second interconnect layer.

[0016] In some embodiments, each first memory cell and each second memory cell includes: a semiconductor column extending along a third direction and having a first side wall intersecting the first direction; a gate dielectric layer located on a surface of the first side wall; a capacitor located on a side of the semiconductor column away from the first bit line or the second bit line; the first semiconductor structure also includes: a first word line extending along the second direction and connected to the gate dielectric layer in the first memory cell arranged along the second direction; and the second semiconductor structure also includes: a second word line extending along the second direction and connected to the gate dielectric layer in the second memory cell arranged along the second direction.

[0017] In a second aspect, some embodiments of the present application provide a memory system, which includes: a memory including a semiconductor device as mentioned in any of the above embodiments; and a controller coupled to the memory and used to control the memory to store data.

[0018] In a third aspect, some embodiments of the present application provide a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes: forming a first semiconductor structure, wherein the first semiconductor structure includes a plurality of first storage cells and a first bit line, and the plurality of first storage cells are arranged in an array along a first direction and a second direction; the first bit line is located on one side of the first storage cell in a third direction, extends along the first direction, and is connected to the first storage cells arranged along the first direction; forming a second semiconductor structure, wherein the second semiconductor structure includes a plurality of second storage cells and a second bit line, and the plurality of second storage cells are arranged in an array along the first direction and the second direction; the second bit line is located on one side of the second storage cell in the third direction, extends along the first direction, and is connected to the second storage cells arranged along the first direction; and connecting the first semiconductor structure to one side of the second semiconductor structure in the third direction, wherein the first direction, the second direction, and the third direction intersect with each other.

[0019] In some embodiments, forming a first semiconductor structure includes: forming a first bit line having at least one first cut, wherein the first bit line is disconnected into a first portion and a second portion at the first cut; wherein forming a second semiconductor structure includes: forming a second bit line having at least one second cut, wherein the second bit line is disconnected into a third portion and a fourth portion at the second cut; wherein connecting the first semiconductor structure to one side of the second semiconductor structure in a third direction includes: locating the first bit line and the second bit line between a plurality of first storage cells and a plurality of second storage cells, and connecting the first portion to one of the third portion and the fourth portion, and connecting the second portion to the other of the third portion and the fourth portion.

[0020] In some embodiments, forming the first semiconductor structure further includes: forming a first interconnect layer on a side of the first bit line away from the plurality of first memory cells; wherein forming the second semiconductor structure further includes: forming a second interconnect layer on a side of the second bit line away from the plurality of second memory cells; wherein connecting the first semiconductor structure to a side of the second semiconductor structure in a third direction includes: connecting the first semiconductor structure to a side of the second semiconductor structure in the third direction through the first interconnect layer and the second interconnect layer.

[0021] In some embodiments, forming a first semiconductor structure includes: forming a plurality of first semiconductor walls extending along a first direction and arranged along a second direction in a first semiconductor layer; filling an insulating material on the outside of the first semiconductor walls; forming a plurality of first grooves extending along the second direction and arranged along the first direction to divide the plurality of first semiconductor walls into a plurality of first semiconductor pillars; forming a first gate dielectric layer on a first side wall of the first semiconductor pillar; forming a first word line extending along the second direction, the first word line contacting a surface of the first gate dielectric layer in the first semiconductor pillar arranged along the second direction; and forming a first capacitor at a first end of the first semiconductor pillar.

[0022] In some embodiments, the depth of the first groove is smaller than the dimension of the first semiconductor wall in the third direction; wherein, forming a plurality of first semiconductor walls extending along the first direction and arranged along the second direction in the first semiconductor layer includes: forming at least one opening penetrating through at least one first semiconductor wall; wherein, forming a first bit line having at least one first notch includes: forming a first bit line at a second end of the first semiconductor column away from the first capacitor, the opening corresponding to the first notch.

[0023] In some embodiments, before forming a first bit line at a second end of the first semiconductor pillar away from the first capacitor, the method further includes: connecting a first supporting structure to a side of the first capacitor away from the plurality of first semiconductor pillars.

[0024] According to at least one embodiment of the present application, the semiconductor device, memory system and semiconductor device manufacturing method provided by the present application can save the plane area of ​​the semiconductor device and effectively improve the storage density by integrating the first semiconductor structure with the memory cell array and the second semiconductor structure in the vertical direction. At the same time, the two semiconductor structures can be manufactured in parallel, which is conducive to reducing the manufacturing time and improving the production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0026] Figure 1 is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present application;

[0027] Figure 2A is a perspective schematic diagram of a semiconductor device provided by an embodiment of the present application, wherein a first notch and a second notch are respectively provided in a first bit line and a second bit line;

[0028] Figure 2B yes Figure 2A A circuit diagram of a semiconductor device is shown;

[0029] Figure 3A is a perspective schematic diagram of a semiconductor device having a first cutout and a second cutout in a first bit line and a second bit line, respectively, provided by another embodiment of the present application;

[0030] Figure 3B yes Figure 3A A circuit diagram of a semiconductor device is shown;

[0031] Figure 4A is a perspective schematic diagram of a semiconductor device provided by another embodiment of the present application, wherein the first bit line and the second bit line have a first cutout and a second cutout respectively;

[0032] Figure 4B yes Figure 3A A circuit diagram of a semiconductor device is shown;

[0033] Figure 5A is a perspective schematic diagram of a semiconductor device having a first cutout and a second cutout in a first bit line and a second bit line, respectively, provided by yet another embodiment of the present application;

[0034] Figure 5B yes Figure 5A A circuit diagram of a semiconductor device is shown;

[0035] Figure 6 is a block diagram of a system having a memory system provided by an embodiment of the present application;

[0036] Figure 7 is a schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application; and

[0037] FIG. 8A to FIG. 20 It is a schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first bit line discussed in this application may also be referred to as the second bit line, and vice versa.

[0040] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0041] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0042] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0043] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0044] In addition, when "connect" or "couple" is used in the present application, it can indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context. The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0045] An embodiment of the present application provides a semiconductor device. Figure 1 is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present application. Figure 1As shown, the semiconductor device 100 may be a memory or a part of a memory. For example, the memory may be a dynamic random access memory (DRAM), a ferroelectric random access memory (FRAM), a phase change memory (PCM), a magnetoresistive random access memory (MRAM), or a resistive random access memory (RRAM).

[0046] It should be noted that, hereinafter, the D1 direction, the D2 direction, and the D3 direction in each of the drawings illustrate the spatial relationship of the components in the semiconductor device. For example, the D3 direction is the extension direction of the semiconductor column, and the D1 direction and the D2 direction are two directions that intersect (e.g., are perpendicular) to each other on a plane that intersects (e.g., is perpendicular) to the extension direction. For example, the D1 direction is the bit line direction, and the D2 direction is the word line direction. The same concept will be used throughout this application to describe the spatial relationship of the components in the semiconductor device.

[0047] like Figure 1 As shown, the semiconductor device 100 includes a first semiconductor structure 110 and a second semiconductor structure 150 arranged along the D3 direction. The first semiconductor structure 110 is connected to the second semiconductor structure 150 and arranged along the D3 direction. For example, the first semiconductor structure 110 and the second semiconductor structure 150 are bonded and connected at the connection interface 101. In other words, the first semiconductor structure 110 and the second semiconductor structure 150 are arranged on opposite sides of the connection interface 101 in the D3 direction. It should be noted that the bonding referred to in the present application may be any appropriate bonding technology, such as hybrid bonding, anodic bonding, melt bonding, transfer bonding, adhesive bonding, eutectic bonding, etc.

[0048] The first semiconductor structure 110 includes a plurality of first storage cells 111. The plurality of first storage cells 111 are arranged in an array along the D1 direction and the D2 direction. In some examples, when the semiconductor device 100 is a DRAM memory or a part of a DRAM memory, the first storage cell 111 may be a DRAM memory cell. In other examples, the first storage cell 111 may also be at least one of a FRAM memory cell, a PCM memory cell, an MRAM memory cell, and an RRAM memory cell. The first semiconductor structure 110 also includes a first bit line 112. The first bit line 112 is located on one side of the first storage cell 111 in the D3 direction and extends in the D1 direction. It is connected to a plurality of first storage cells 111 arranged along the D1 direction. For example, the first bit line 112 may be used to transmit a bit line signal between a plurality of first storage cells 111 connected thereto.

[0049] The second semiconductor structure 150 includes a plurality of second storage cells 151 and a second bit line 152. The plurality of second storage cells 151 are arranged in an array along the D1 direction and the D2 direction. For example, the second storage cell 151 may be at least one of a DRAM storage cell, a FRAM storage cell, a PCM storage cell, an MRAM storage cell, an RRAM storage cell, a NAND storage cell, and a NOR storage cell. The second bit line 152 is located on one side of the second storage cell 151 in the D3 direction and extends along the D1 direction. It is connected to a plurality of second storage cells 151 arranged along the D1 direction. For example, the second bit line 152 may be used to transmit a bit line signal between a plurality of second storage cells 151 connected thereto.

[0050] In some embodiments, the first bit line 112 and the second bit line 152 may extend continuously along the D1 direction (not shown). In other embodiments, the first bit line 112 may have at least one first notch 123, and the second bit line 152 may have at least one second notch 163. In other words, the first bit line 112 and the second bit line 152 may extend discontinuously along the D1 direction. For example, in this case, the first semiconductor structure 110 may have a first interconnect layer 124, and the second semiconductor structure 150 may have a second interconnect layer 164. In the D3 direction, the first interconnect layer 124 and the second interconnect layer 164 may be located between the first bit line 112 and the second bit line 152. The discontinuously extending first bit line 112 and the second bit line 152 may be connected through the first interconnect layer 124 and the second interconnect layer 164, and the first semiconductor structure 110 and the second semiconductor structure 150 are also connected. The case where the first bit line 112 and the second bit line 152 have the first notch 123 and the second notch 163, respectively, will be described in more detail below.

[0051] It should be noted that although Figure 1An example is shown in which the first bit line 112 and the second bit line 152 are located between the plurality of first storage cells 111 and the plurality of second storage cells 151, but the first semiconductor structure 110 and the second semiconductor structure 150 may have other connection forms, such as locating the plurality of first storage cells 111 and the second bit line 152 between the first bit line 112 and the plurality of second storage cells 151, or locating the plurality of first storage cells 111 and the plurality of second storage cells 151 between the first bit line 112 and the second bit line 152, and the present application does not impose any limitation on this.

[0052] According to the embodiment of the present application, by integrating the first semiconductor structure with the memory cell array and the second semiconductor structure in the vertical direction, the planar area of ​​the semiconductor device can be saved and the storage density can be effectively improved. At the same time, the two semiconductor structures can be manufactured in parallel, which is conducive to reducing the manufacturing time and improving the production efficiency.

[0053] The following description will be made by taking the semiconductor device 100 as a part of a DRAM memory or a DRAM memory as an example. In this case, the first storage unit 111 and the second storage unit 151 may be DRAM storage units.

[0054] In some embodiments, Figure 1 As shown, the first semiconductor structure 110 may include a plurality of first semiconductor pillars 113 arranged in an array along the D1 direction and the D2 direction. For example, each first semiconductor pillar 113 may extend along the D3 direction and have a first sidewall 114 perpendicular to the D1 direction. As will be described in detail below, the first semiconductor pillars 113 may be formed using a semiconductor substrate, and the extension direction of the first semiconductor pillars 113 (e.g., the D3 direction) may be perpendicular to the plane extension direction of the semiconductor substrate.

[0055] In some embodiments, the first semiconductor structure 110 may further include a first gate dielectric layer 115. The first gate dielectric layer 115 may be located on a surface of the first sidewall 114 of the first semiconductor pillar 113. In some examples, the material of the first gate dielectric layer 115 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. As another option, the material of the first gate dielectric layer 115 may include one or more of aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2) or any other suitable high dielectric constant material.

[0056] In some embodiments, the first semiconductor structure 110 may further include a first word line 116. The first word line 116 may extend along the D2 direction (e.g., extend continuously) and be connected to (e.g., directly contact) the first gate dielectric layer 115 on the surface of a plurality of first semiconductor pillars 113 arranged along the D2 direction. Exemplarily, the first word line 116 may include a first adhesive layer 1161 and a first metal layer 1162 that are attached to each other. The first adhesive layer 1161 may be located on the surface of the first gate dielectric layer 115 and extend along the D2 direction (e.g., extend continuously). The first metal layer 1162 may be located on the surface of the first adhesive layer 1161 and extend along the D2 direction (e.g., extend continuously). In other words, the first adhesive layer 1161 may be located between the first metal layer 1162 and the first gate dielectric layer 115. The first adhesive layer 1161 helps to improve the bonding performance between the first metal layer 1162 and the first gate dielectric layer 115. For example, the material of the first adhesion layer 1161 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any other suitable material. For example, the material of the first metal layer 1162 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), or any other suitable metal material. In other examples, the first word line 116 may not have a composite layer structure, but may be composed of a conductive material, which is not limited in the present application.

[0057] According to the above description, in some embodiments, a first semiconductor column 113, and a portion of the first gate dielectric layer 115 and the first word line 116 corresponding to the first side wall 114 of the first semiconductor column 113 (for example, on a projection plane perpendicular to the D1 direction, the first gate dielectric layer 115 and the first word line 116 respectively overlap with the projection of the first side wall 114) can constitute a first transistor. In the first transistor, the first semiconductor column 113 serves as a channel, the portion of the first word line 116 corresponding to the first side wall 114 of the first semiconductor column 113 serves as a gate, and the two ends of the first semiconductor column 113 in the extension direction serve as a source and a drain, respectively. Since the extension direction of the first semiconductor column 113 (for example, the D3 direction) is perpendicular to the plane extension direction of the semiconductor substrate, the first transistor can also be called a vertical channel transistor. The vertical channel transistor can effectively reduce the plane occupied area and improve the storage density. In this case, the first word line 116 can be used to transmit word line signals between the first transistors in the first storage units 111 connected thereto.

[0058] In some embodiments, the first semiconductor structure 110 may further include a first isolation structure 118. The first isolation structure 118 is located between first transistors adjacent to each other in the D1 direction. For example, the material of the first isolation structure 118 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the transistors adjacent to each other in the D1 direction are mirror-symmetric with respect to the first isolation structure 118.

[0059] In some embodiments, the first semiconductor structure 110 may further include a shielding structure 119. The shielding structure 119 may be located between semiconductor pillars 113 adjacent in the D1 direction and extend (e.g., continuously) in the D2 direction. For example, the shielding structure 119 and the first isolation structure 118 are arranged at intervals in the D1 direction. In some examples, the material of the shielding structure 119 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. For example, applying a voltage (e.g., a ground voltage) to the first transistor through the shielding structure 119 may improve the coupling effect between the first transistors adjacent in the D1 direction. In other examples, the material of the shielding structure 119 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the shielding structure 119 can provide electrical isolation between adjacent first transistors in the D1 direction.

[0060] In some embodiments, the first semiconductor structure 110 may further include a first capacitor 120. Exemplarily, the first capacitor 120 may include a first pole and a second pole made of a conductive material, and an insulating material layer (not shown) located between the first pole and the second pole. For example, the first pole, the insulating material layer and the second pole may be stacked along the D3 direction. The first pole of the first capacitor 120 is connected to the first end of the first semiconductor column 113 away from the first bit line 112, thereby connecting to the source or drain of the first transistor. The second poles of the first capacitor 120 may be connected to each other through a first capacitor interconnection structure 125. Optionally, the first semiconductor structure 110 may further include a first capacitor connection structure 121 connected between the first capacitor 120 and the first end of the first semiconductor column 113. For example, the materials of the first capacitor interconnection structure 125 and the first capacitor connection structure 121 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO) or any other suitable conductive material.

[0061] According to the above description, in some embodiments, a first transistor and a first capacitor 120 may constitute a first storage unit 111 (i.e., a DRAM storage unit). For example, the first capacitor 120 may be used to implement data storage, and the first transistor may be used as a switch for accessing the first capacitor 120. When the DRAM storage units are arranged in an array along the D1 direction and the D2 direction, at least one of the DRAM storage unit arrays may be selected by applying a word line signal and a bit line signal to the first word line 116 and the first bit line 112, respectively, and operations such as writing, reading, and erasing may be performed on it.

[0062] In some embodiments, the internal structure of the second semiconductor structure 150 may be substantially the same as that of the first semiconductor structure 110. For the purpose of concise description, the present application briefly describes the internal structure of the second semiconductor structure 150. Figure 1As shown, in the second semiconductor structure 150, a plurality of second semiconductor pillars 153 are arranged in an array along the D1 direction and the D2 direction. The second gate dielectric layer 155 may be located on the surface of the first side wall 154 of the second semiconductor pillar 153. The second word line 156 may extend along the D2 direction (e.g., continuously extend) and be connected to (e.g., directly contacted with) the second gate dielectric layer 155 on the surface of a plurality of second semiconductor pillars 153 arranged along the D2 direction. The first electrode of the second capacitor 160 may be connected to the first end of the second semiconductor pillar 153 away from the second bit line 152, and the second electrodes of the second capacitor 160 may be connected to each other. Among them, one second semiconductor pillar 153, and the second gate dielectric layer 155 and the second word line 156 corresponding to the first side wall 154 of the second semiconductor pillar 153 (e.g., on the projection plane perpendicular to the D1 direction, the second gate dielectric layer 155 and the second word line 156 respectively overlap with the projection of the first side wall 154) may constitute a second transistor. The second transistor and the second capacitor 160 may constitute a second storage unit 151 (i.e., a DRAM storage unit).

[0063] In some embodiments, the semiconductor device 100 may further include a first supporting structure 122 and a second supporting structure 162, both of which may be used to play a supporting role in the manufacturing process of the semiconductor device 100. For example, in the D3 direction, the first supporting structure 122 may be located on a side of the first semiconductor structure 110 away from the second semiconductor structure 150, and the second supporting structure 162 may be located on a side of the second semiconductor structure 150 away from the first semiconductor structure 110. For example, the first supporting structure 122 and the second supporting structure 162 may be semiconductor substrates. Optionally, in the manufacturing process of the semiconductor device 100, the first supporting structure 122 and the second supporting structure 162 may be removed after playing a supporting role, and do not appear in the final product.

[0064] In some embodiments, the semiconductor device 100 may further include a peripheral circuit (not shown) for controlling the plurality of first storage units 111 and the plurality of second storage units 151. In some examples, the peripheral circuit may be disposed in the first semiconductor structure 110 and / or the second semiconductor structure 150 (not shown). In other examples, the peripheral circuit may be disposed in another semiconductor structure connected to the semiconductor device 100 (not shown). The peripheral circuit may include a sense amplifier (SA). For example, the sense amplifier may be a differential amplifier, and in a read operation, the input terminal of the sense amplifier may be a sense signal on a pair of bit lines.

[0065] In some embodiments, as described above, the first bit line and the second bit line may have a first notch and a second notch respectively in their extension direction (eg, D1 direction), and the discontinuously extending first bit line and second bit line may be connected via a first interconnect layer and a second interconnect layer. FIG. 2A to FIG. 5B The connection form of the first bit line and the second bit line in the following embodiments is illustrated by way of example. It should be noted that, in order to clearly illustrate the connection form of the first bit line and the second bit line, Figure 2A , Figure 3A , Figure 4A as well as Figure 5A Some components of the semiconductor device have been omitted.

[0066] Figure 2A It is a perspective schematic diagram of a semiconductor device provided by an embodiment of the present application, wherein the first bit line and the second bit line have a first cutout and a second cutout respectively. Figure 2B yes Figure 2A A circuit diagram of a semiconductor device is shown.

[0067] like Figure 2A As shown, in the semiconductor device 200, a plurality of first semiconductor pillars 213 are arranged in an array along the D1 direction and the D2 direction. The first gate dielectric layer 215 may be located on the surface of the first semiconductor pillar 215. The first word line 216 may extend along the D2 direction (e.g., continuously extend) and be connected to (e.g., directly contact) the first gate dielectric layer 215 on the surface of the plurality of first semiconductor pillars 213 arranged along the D2 direction. Similarly, a plurality of second semiconductor pillars 253 are arranged in an array along the D1 direction and the D2 direction. The second gate dielectric layer 255 may be located on the surface of the second semiconductor pillar 253. The second word line 256 may extend along the D2 direction (e.g., continuously extend) and be connected to (e.g., directly contact) the second gate dielectric layer 255 on the surface of the plurality of second semiconductor pillars 253 arranged along the D2 direction.

[0068] The first bit line BL1.1 is located on one side of the plurality of first semiconductor columns 213 in the direction D3, and extends in the direction D1, and is connected to a plurality of first semiconductor columns 213 (e.g., the second end portions) arranged in the direction D1. The first bit line BL1.1 may have a first notch 223. The first bit line BL1.1 is broken into a first portion BL1.1 at the first notch 223. l and Part II BL1.1 r For example, the first part BL1.1 l and Part II BL1.1 rThe second bit line BL2.1 is arranged along the D1 direction and extends approximately in a collinear manner. Similarly, the second bit line BL2.1 is located on one side of the plurality of second semiconductor pillars 253 in the D3 direction and extends along the D1 direction to be connected to a plurality of second semiconductor pillars 253 (e.g., the second end portions) arranged along the D1 direction. The second bit line BL2.1 may have a second notch 263. The second bit line BL2.1 is disconnected at the second notch 263 into a third portion BL2.1. l and Part 4 BL2.1 r For example, Part III BL2.1 l and Part 4 BL2.1 r The first and second bit lines BL1.1 and BL2.1 are arranged along the direction D1 and extend approximately in the same line. Optionally, an isolation structure (not shown) is provided at the first cutout 223 and the second cutout 263 to electrically isolate the two parts of the first bit line BL1.1 and the second bit line BL2.1 after they are disconnected. Figure 2A An example is shown in which the first cutout 223 and the second cutout 263 are substantially aligned in the D3 direction. However, in other examples, the first cutout 223 and the second cutout 263 may have a spacing in the D1 direction, and the present application is not limited thereto.

[0069] The first interconnect layer 224 is located on a side of the first bit line BL1.1 away from the plurality of first semiconductor pillars 213, and the second interconnect layer 264 is located on a side of the second bit line BL2.1 away from the plurality of second semiconductor pillars 253. The first interconnect layer 224 and the second interconnect layer 264 may be located between the first bit line BL1.1 and the second bit line BL2.1. The first interconnect layer 224 may include first interconnect channels 2241a and 2241b. The second interconnect layer 264 may include second interconnect channels 2641a and 2641b. Exemplarily, the materials of the first interconnect channels 2241a and 2241b and the second interconnect channels 2641a and 2641b may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0070] One end of the first interconnection channel 2241a is connected to the first portion BL1.1 l , one end of the second interconnection channel 2641a is connected to the third part BL2.1 l , the other end of the first interconnection channel 2241a is connected to the other end of the second interconnection channel 2641a. In other words, the first interconnection channel 2241a and the second interconnection channel 2641a are connected to each other, and both are connected to the first portion BL1.1 of the first bit line BL1.1. l and a third portion BL2.1 of the second bit line BL2.1 l .

[0071] One end of the first interconnection channel 2241b is connected to the second portion BL1.1 r , one end of the second interconnection channel 2641b is connected to the fourth part BL2.1 r , the other end of the first interconnection channel 2241b is connected to the other end of the second interconnection channel 2641b. In other words, the first interconnection channel 2241b and the second interconnection channel 2641b are connected to each other, and both are connected to the second portion BL1.1 of the first bit line BL1.1. r and a fourth portion BL2.1 of the second bit line BL2.1 r .

[0072] In some embodiments, in addition to the first bit line BL1.1, the first semiconductor structure 210 may further include a plurality of first bit lines (e.g., BL1.2, BL1.3) (not shown) arranged along the D2 direction. Similarly, in addition to the second bit line BL2.1, the second semiconductor structure 250 may further include a plurality of second bit lines (e.g., BL2.2, BL2.3) (not shown) arranged along the D2 direction. For example, on a projection plane perpendicular to the D3 direction, the projection of the first bit line BL1.1 and the projection of the second bit line BL2.1 substantially overlap, the projection of the first bit line BL1.2 and the projection of the second bit line BL2.2 substantially overlap, and the projection of the first bit line BL1.3 and the projection of the second bit line BL2.3 substantially overlap. For example, the first bit line BL1.2 and the second bit line BL2.2 and the first bit line BL1.3 and the second bit line BL2.3 have the same Figure 2A The first bit line BL1.1 and the second bit line BL2.1 are shown to be connected in the same manner.

[0073] In the above embodiment, if Figure 2A and 2B As shown, when the first bit line BL1.1 and the second bit line BL2.1 are connected to the same sense amplifier, the first portion BL1.1 of the first bit line BL1.1 l and a third portion BL2.1 of the second bit line BL2.1 l Can be used to transmit a bit line signal, and the second part BL1.1 of the first bit line BL1.1 r and a fourth portion BL2.1 of the second bit line BL2.1 r It can be used to transmit a reference bit line signal, and it can be used to transmit a portion of a pair of bit line signals (for example, the first portion BL1.1 l and Part III BL2.1 l , and the second part BL1.1 r and Part 4 BL2.1 r) is folded in the direction D3 to connect the discontinuously extended first bit line BL1.1 and the second bit line BL2.1.

[0074] Figure 3A 1 is a perspective schematic diagram of a semiconductor device provided by another embodiment of the present application, wherein the semiconductor device has a first cutout and a second cutout in a first bit line and a second bit line, respectively. Figure 3B yes Figure 3A A circuit diagram of a semiconductor device is shown.

[0075] like Figure 3A As shown, the first interconnection layer 324 may include first interconnection channels 3241a, 3241b, 3241c and 3241d and first interconnection lines 3242a and 3242b. The second interconnection layer 364 may include second interconnection channels 3641a, 3641b, 3641c and 3641d and second interconnection lines 3642a and 3642b. Exemplarily, the materials of the first interconnection channels 3241a-3241d, the second interconnection channels 3641a-3641d, the first interconnection lines 3242a and 3242b, and the second interconnection lines 3642a and 3642b may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO) or any other suitable conductive material.

[0076] In some embodiments, the first interconnect lines 3242a and 3242b and the second interconnect lines 3642a and 3642b may have a larger extension dimension on a plane perpendicular to the D3 direction than the first interconnect channel (e.g., 3241a) or the second interconnect channel (e.g., 3641a), so that these interconnect lines have different shapes. For example, the first interconnect line 3242a and the second interconnect line 3642a may be approximately strip-shaped, and the first interconnect line 3242b and the second interconnect line 3642b may be approximately L-shaped. By connecting these interconnect lines and interconnect channels to each other, the first portion BL1.1 of the first bit line BL1.1 is realized. l and a fourth portion BL2.1 of the second bit line BL2.1 r Connect the second part BL1.1 of the first bit line BL1.1 r and the second bit line BL2.1 l Part 3 of BL2.1 l .

[0077] For example, the first part BL1.1 lThe first interconnection channel 3241a, the first interconnection line 3242a, the first interconnection channel 3241b, the second interconnection channel 3641b, the second interconnection line 3642a and the second interconnection channel 3641a are connected to the fourth part BL2.1 in sequence. r Part 2 BL1.1 r The first interconnection channel 3241c, the first interconnection line 3242b, the first interconnection channel 3241d, the second interconnection channel 3641d, the second interconnection line 3642b and the second interconnection channel 3641c are connected to the fourth part BL2.1 in sequence. r It is understandable that the shape and / or number of the first interconnection line and the second interconnection line, and the shape and / or number of the first interconnection channel and the second interconnection channel can be adjusted according to actual needs, for example, by pattern design, and the present application does not limit this.

[0078] In some embodiments, Figure 3A As shown, in the first semiconductor structure 310, in addition to the first bit line BL1.1, a plurality of first bit lines (for example, BL1.2, BL1.3) arranged along the D2 direction may also be included (wherein the first bit line BL1.3 is not shown). Similarly, in the second semiconductor structure 350, in addition to the second bit line BL2.1, a plurality of second bit lines (for example, BL2.2, BL2.3) arranged along the D2 direction may also be included (wherein the second bit line BL2.3 is not shown). For example, on a projection plane perpendicular to the D3 direction, the projection of the first bit line BL1.1 and the projection of the second bit line BL2.1 roughly overlap, the projection of the first bit line BL1.2 and the projection of the second bit line BL2.2 roughly overlap, and the projection of the first bit line BL1.3 and the projection of the second bit line BL2.3 roughly overlap. For example, the first bit line BL1.2 and the second bit line BL2.2 extend continuously along the D1 direction, and the first bit line BL1.3 and the second bit line BL2.3 have the same Figure 3A The first bit line BL1.1 and the second bit line BL2.1 are shown to be connected in the same manner.

[0079] In the above embodiment, if Figure 3A and 3B As shown, when the first bit line BL1.1 and the second bit line BL2.1 are connected to the same sense amplifier, the first portion BL1.1 of the first bit line BL1.1 l and a fourth portion BL2.1 of the second bit line BL2.1 r Can be used to transmit a bit line signal, and the second part BL1.1 of the first bit line BL1.1 r and a third portion BL2.1 of the second bit line BL2.1 l It can be used to transmit a reference bit line signal, and it can be used to transmit each bit line portion of a pair of bit line signals (for example, the first portion BL1.1l and Part 4 BL2.1 r , and the second part BL1.1 r and Part III BL2.1 l ) adopts a twisted pair routing form, which can suppress interference between each other, improve the bit line coupling effect, and help improve the reading accuracy. In addition, when the first notch 323 and the second notch 363 are at least partially aligned in the D3 direction, the overlapping area of ​​the first bit line BL1.1 and the second bit line BL2.1 on the plane perpendicular to the D3 direction can be reduced, thereby further suppressing interference between each other and further improving the bit line coupling effect.

[0080] Figure 4A 1 is a perspective schematic diagram of a semiconductor device provided by yet another embodiment of the present application, wherein the semiconductor device has a first cutout and a second cutout in a first bit line and a second bit line, respectively. Figure 4B yes Figure 4A The circuit diagram of the semiconductor device is shown. Figure 3A The semiconductor device shown, Figure 4A Further, some components in the semiconductor device are omitted from illustration.

[0081] like Figure 4A As shown, in the first semiconductor structure 410, a plurality of first bit lines BL1.1 and BL1.2 are arranged along the D2 direction. The first bit line BL1.1 may have a first cutout 423-1, and the second bit line BL1.2 may have first cutouts 423-2 and 423-2. Similarly, in the second semiconductor structure 450, a plurality of second bit lines BL2.1 and BL2.2 are arranged along the D2 direction. For example, on a projection plane perpendicular to the D3 direction, the projection of the first bit line BL1.1 and the projection of the second bit line BL2.1 roughly overlap, and the projection of the first bit line BL1.2 and the projection of the second bit line BL2.2 roughly overlap.

[0082] In two adjacent first bit lines BL1.1 and BL1.2, the first notch 423-1 is spaced apart from the first notch 423-2 and the first notch 423-3 in the D1 direction. Similarly, in two adjacent second bit lines BL2.1 and BL2.2, the second notch 463-1 is spaced apart from the second notch 463-2 and the second notch 463-3 in the D1 direction.

[0083] The first interconnection layer 424 may include a plurality of first interconnection channels 4241 and a plurality of first interconnection lines 4242. The second interconnection layer 464 may include a plurality of second interconnection channels 4641 and a plurality of second interconnection lines 4642. As described in detail above, from the D2 direction, two portions of the first bit line BL1.1 disconnected by the first cut 423-1 may be cross-connected with two portions of the second bit line BL2.1 disconnected by the second cut 463-1 through these interconnection lines and interconnection channels. Similarly, two portions of the first bit line BL1.2 disconnected by the first cut 423-2 may be cross-connected with two portions of the second bit line BL2.2 disconnected by the second cut 463-2, and two portions of the first bit line BL1.2 disconnected by the first cut 423-3 may be cross-connected with two portions of the second bit line BL2.2 disconnected by the second cut 463-3.

[0084] In some embodiments, in addition to the first bit lines BL1.1 and BL1.2, the first semiconductor structure 410 may further include a plurality of first bit lines (e.g., BL1.3) (not shown) arranged along the D2 direction. Similarly, in addition to the second bit lines BL2.1 and BL2.2, the second semiconductor structure 450 may further include a plurality of second bit lines (e.g., BL2.3) (not shown) arranged along the D2 direction. For example, on a projection plane perpendicular to the D3 direction, the projection of the first bit line BL1.3 and the projection of the second bit line BL2.3 substantially overlap. For example, the first bit line BL1.3 and the second bit line BL2.3 have the same Figure 4A The first bit line BL1.1 and the second bit line BL2.1 are shown to be connected in the same manner.

[0085] In the above embodiment, if Figure 4A and 4B As shown, when the first bit line BL1.1 and the second bit line BL2.1 are connected to a sensing amplifier, and the first bit line BL1.2 and the second bit line BL2.2 are connected to another sensing amplifier, in the adjacent first bit lines BL1.1 and BL1.2 and the adjacent second bit lines BL2.1 and BL2.2, the two pairs of bit lines used to transmit a pair of bit line signals both adopt a twisted pair routing form, and the torsion nodes of the two pairs of bit lines are staggered in the D1 direction, which can further suppress interference between each other, further improve the bit line coupling effect, and help improve the reading accuracy.

[0086] Figure 5A 1 is a perspective schematic diagram of a semiconductor device provided by yet another embodiment of the present application, wherein the semiconductor device has a first cutout and a second cutout in a first bit line and a second bit line, respectively. Figure 5B yes Figure 5A A circuit diagram of a semiconductor device is shown.

[0087] like Figure 5A As shown, in the first semiconductor structure 510, a plurality of first bit lines BL1.1, BL1.1 are arranged along the direction D2. The first bit line BL1.1 may have a first notch 523-1, and the first bit line BL1.1 is broken into a first portion BL1.1 at the first notch 523-1. l and Part II BL1.1 r The first bit line BL1.2 may have a first notch 523-2. The first bit line BL1.2 is broken into a first portion BL1.2 at the first notch 523-2. l and Part 2 BL1.2 r .

[0088] Similarly, in the second semiconductor structure 550, a plurality of second bit lines BL2.1 and BL2.2 are arranged along the direction D2, and the second bit line BL2.1 may have a second notch 563-1, and the second bit line BL2.1 is disconnected at the second notch 563-1 into a third portion BL2.1. l and Part 4 BL2.1 r The second bit line BL2.2 may have a second notch 563-2. The second bit line BL2.2 is disconnected into a third portion BL2.2 at the second notch 563-2. l and Part 4 BL2.2 r For example, on a projection plane perpendicular to the D3 direction, the projection of the first bit line BL1.1 and the projection of the second bit line BL2.1 roughly overlap, and the projection of the first bit line BL1.2 and the projection of the second bit line BL2.2 roughly overlap.

[0089] In a pair of first bit line BL1.1 and second bit line BL2.1, a first portion BL1.1 of the first bit line BL1.1 l and a fourth portion BL2.1 of the second bit line BL2.1 r For example, the first interconnect layer 524 and the second interconnect layer 564 are connected (solid line), and in an adjacent pair of first bit line BL1.2 and second bit line BL2.2, the second portion BL1.2 of the first bit line BL1.2 r and a third portion BL2.2 of the second bit line BL2.2 l For example, they are connected through the first interconnect layer 524 and the second interconnect layer 564 (solid line).

[0090] In the two pairs of first and second bit lines, namely, the first bit line BL1.1 and the second bit line BL2.1 and the first bit line BL1.2 and the second bit line BL2.2, the second portion BL1.1 of the first bit line BL1.1 r and the first part BL1.1 of the first bit line BL1.2 lFor example, the third portion BL2.1 of the second bit line BL2.1 is connected (dashed line) via the first interconnect layer 524. r and a fourth portion BL2.2 of the second bit line BL2.2 r For example, they are connected via a second interconnect layer 564 (dashed lines).

[0091] In the above embodiment, if Figure 5A and 5B As shown, the first part BL1.1 of the first bit line BL1.1 l , the fourth portion BL2.1 of the second bit line BL2.1 r , the second part BL1.2 of the adjacent first bit line BL1.2 r and a third portion of the adjacent second bit line BL2.2 l Can be connected to a sense amplifier, the second portion BL1.1 of the first bit line BL1.1 r , the first part BL1.1 of the adjacent first bit line BL1.2 l , the third portion BL2.1 of the second bit line BL2.1 r and a fourth portion BL2.2 of the adjacent second bit line BL2.2 r Can be connected to another sense amplifier. Each bit line part used to transmit a pair of bit line signals adopts a twisted pair routing form, which can suppress interference between each other, improve the bit line coupling effect, and help improve the reading accuracy.

[0092] An embodiment of the present application also provides a memory system. Figure 6 is a block diagram of a system with a memory system provided in an embodiment of the present application.

[0093] like Figure 6 As shown, the system 600 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device has the memory system 610 located therein). Figure 6As shown, system 600 may include a host 620 and a memory system 610. Memory system 610 has one or more memories 611 and a controller 612. Host 620 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). Host 620 may be configured to send or receive data to and from memory 611.

[0094] In some embodiments, the controller 612 is coupled to the memory 611 and the host 620, and is configured to control the memory 611. For example, the controller 612 may be configured to control operations such as read, erase, and program of the memory 611. The controller 612 may also manage data stored in the memory 611 and communicate with the host 620. For example, the controller 612 may communicate with an external device (e.g., the host 620) according to a specific communication protocol.

[0095] An embodiment of the present application also provides a method for manufacturing a semiconductor device. Figure 7 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application. Figure 7 As shown, semiconductor devices

[0096] The manufacturing method 700 (hereinafter referred to as the manufacturing method 700) may include the following steps.

[0097] S710, forming a first semiconductor structure, wherein the first semiconductor structure includes a plurality of first storage cells and a first bit line, the plurality of first storage cells are arranged in an array along a first direction and a second direction; the first bit line is located on one side of the first storage cell in a third direction, extends along the first direction, and is connected to the first storage cells arranged along the first direction.

[0098] S720, forming a second semiconductor structure, wherein the second semiconductor structure includes a plurality of second storage cells and a second bit line, and the plurality of second storage cells are arranged in an array along a first direction and a second direction; the second bit line is located on one side of the second storage cell in a third direction, extends along the first direction, and is connected to the second storage cells arranged along the first direction.

[0099] S730, connecting the first semiconductor structure to one side of the second semiconductor structure in a third direction, wherein the first direction, the second direction and the third direction are perpendicular to each other.

[0100] According to the method for manufacturing a semiconductor device provided by this embodiment, by integrating the first semiconductor structure having a memory cell array and the second semiconductor structure in the vertical direction, the planar area of ​​the semiconductor device can be saved and the storage density can be effectively improved. At the same time, the two semiconductor structures can be manufactured in parallel, which is conducive to reducing manufacturing time and improving production efficiency.

[0101] FIG. 8A to FIG. 20 Schematic diagram of the structure of the semiconductor device in the manufacturing process provided by the embodiment of the present application. FIG. 8A to FIG. 20 The above steps S710 to S730 are exemplarily described. FIG. 8A to FIG. 19 It may be a structural diagram of step S710 during the manufacturing process.

[0102] Fig. 8A and Figure 8B An intermediate structure 800a including a first semiconductor layer 831, a first dielectric layer 832 and a second dielectric layer 833 is shown. Fig. 8A is a schematic top view of the intermediate structure 800a. Figure 8B It is along Fig. 8A A schematic cross-sectional view taken along line AA' is shown.

[0103] In some embodiments, Fig. 8A and Figure 8B As shown, the first semiconductor layer 831 may be a semiconductor substrate. For example, the material of the semiconductor substrate may be silicon (Si), germanium (Ge), gallium arsenide (GaAs) or indium phosphide (InP). For another example, the semiconductor substrate may be a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) substrate, etc.

[0104] In some embodiments, the material of the first dielectric layer 832 may include silicon oxide (SiO2), and the material of the second dielectric layer 833 may include silicon nitride (Si3N4). In some examples, the first dielectric layer 832 and the second dielectric layer 833 may be sequentially formed on the first semiconductor layer 831 using a thin film deposition process of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In other examples, the first dielectric layer 832 may be formed on the first semiconductor layer 831 using a dry oxidation method or a wet oxidation method.

[0105] Fig. 9A and Fig. 9B The intermediate structure 800b is shown after forming a plurality of first semiconductor walls 834 and filling the insulating material 835. Fig. 9A is a schematic top view of the intermediate structure 800b. Fig. 9B It is along Fig. 9A It should be noted that in order to more clearly show the spatial relationship between the components in the intermediate structure 800b, Fig. 9A The first dielectric layer 832 and the second dielectric layer 833 are omitted in the figure, and the same illustration method is used for each top view schematic diagram below.

[0106] In some embodiments, Fig. 9A and Fig. 9B As shown, the first semiconductor layer 831 can be patterned from the first side (e.g., the front side of the first semiconductor layer 831) by photolithography and etching (e.g., dry etching and / or wet etching) processes to form a plurality of first semiconductor walls 834 extending along the D1 direction and arranged along the D2 direction. For example, the second dielectric layer 833 can be used as a hard mask layer for etching the first semiconductor layer 831. The first semiconductor walls 834 and the unetched first semiconductor layer 831 are arranged vertically in the D1 direction. Since the first semiconductor walls 834 are formed by etching the first semiconductor layer 831, the first semiconductor walls 834 are made of the same material as the first semiconductor layer 831. Further, a thin film deposition process of CVD, PVD, ALD, or any combination thereof can be used to fill the outer side of the plurality of first semiconductor walls 834 with an insulating material 835 to electrically isolate adjacent first semiconductor walls 834.

[0107] In some embodiments, during the process of forming the first semiconductor wall 834, at least one opening 839 penetrating at least one first semiconductor wall 834 may be formed by patterning. For example, the opening 839 may divide the first semiconductor wall 834 extending along the D1 direction into two parts. Further, during the process of filling the outer sides of the plurality of first semiconductor walls 834 with the insulating material 835, the insulating material 835 may be filled in the opening 839.

[0108] Fig.13A and Fig. 13B The intermediate structure 800f after forming the first trench 836 and the second trench 837 is shown. Fig.13A It is a top view schematic diagram of the intermediate structure 800f. Fig. 13B It is along Fig.13A A schematic cross-sectional view taken along line BB' is shown.

[0109] In some embodiments, Fig.13A and Fig. 13B As shown, a first semiconductor wall 834 (see FIG. 1 ) formed on the first semiconductor layer 831 from the first side can be etched by photolithography and etching (eg, dry etching and / or wet etching). Fig. 9A) and the insulating material 835 are patterned to form a plurality of first trenches 836 extending along the D2 direction and arranged along the D1 direction, and at the same time, a plurality of first semiconductor walls 834 (reference Fig. 9A ) is divided into a plurality of first semiconductor pillars 813. Optionally, in the process of forming a plurality of first trenches 836, a plurality of second trenches 837 may be formed. For example, the second trenches 837 extend along the D2 direction, and the first trenches 836 and the second trenches 837 are alternately arranged in the D1 direction. The first semiconductor pillars 813 and the unetched first semiconductor layer 831 are arranged vertically in the D1 direction. Since the first semiconductor pillars 813 are formed by etching the first semiconductor layer 831, the first semiconductor pillars 813 and the first semiconductor layer 831 are made of the same material.

[0110] In some embodiments, the depth of the first trench 836 and the second trench 837 are both less than the first semiconductor wall 834 (see Fig. 9A ) in the D3 direction. Thus, the ends (hereinafter referred to as second ends) of the plurality of first semiconductor pillars 813 arranged along the D1 direction can be connected to each other through the unetched first semiconductor walls 834. Fig. 9A The opening 839 shown penetrating the first semiconductor wall 834 may disconnect the unetched first semiconductor wall 834 , thereby electrically isolating the first semiconductor pillars 813 located on both sides of the opening 839 .

[0111] In some embodiments, Fig.13A and Fig. 13B As shown, the first semiconductor layer 831 may include a first region 802 and a second region 803 arranged along the D2 direction, wherein the second region 803 is located on both sides of the first region 802. For example, at least part of the first region 802 may be a storage region, and the second region 803 may be a connection region. The first trench 836 and the second trench 837 may extend in the first region 802 and the second region 803 on both sides.

[0112] In some embodiments, the dimension of the first trench 836 in the D1 direction may be greater than the dimension of the second trench 837 in the D1 direction. For example, the first trench 836 and the second trench 837 having the above-mentioned dimension relationship may be formed by the method described below.

[0113] Fig. 10A and Fig. 10B The intermediate structure 800c is shown after forming the initial first trench 836' and the second trench 837. Fig. 10A is a schematic top view of the intermediate structure 800c.

[0114] Fig. 10B It is along Fig. 10A A schematic cross-sectional view taken along line BB' is shown. Fig.11A and Fig. 11B The intermediate structure 800d is shown after the first sacrificial material 838 is filled in the initial first trench 836' and the second trench 837. Fig.11A is a schematic top view of the intermediate structure 800d. Fig. 11B It is along Fig.11A A schematic cross-sectional view taken along line BB' is shown. Fig. 12A and Fig. 12B The intermediate structure 800e is shown after removing the first sacrificial material 838 in the initial first trench 836'. Fig. 12A is a schematic top view of the intermediate structure 800e. Fig. 12B It is along Fig. 12A A schematic cross-sectional view taken along line BB' is shown.

[0115] In some embodiments, Fig. 10A and Fig. 10B As shown, the first semiconductor wall 834 and the insulating material 835 (see FIG. 1 ) formed on the first semiconductor layer 831 can be etched from the first side by photolithography and etching (eg, dry etching and / or wet etching). Fig. 9A ) is patterned to form initial first trenches 836' and second trenches 837 extending along the D2 direction. The initial first trenches 836' and second trenches 837 are alternately arranged in the D1 direction, and the size of the initial first trenches 836' in the D1 direction may be equal to the size of the second trenches 837 in the D1 direction.

[0116] Next, in some embodiments, as Fig.11A and Fig. 11B As shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to fill the initial first trench 836' and the second trench 837 with a first sacrificial material 838. For example, the first sacrificial material 838 may include polysilicon (Poly), carbon (Carbon), spin-on-carbon (SOC), spin-on-dielectric material (Spin-on-Dielectric) or any other appropriate sacrificial material.

[0117] Then, in some embodiments, Fig. 12A and Fig. 12B As shown, a mask material layer (e.g., a photoresist layer and / or a hard mask layer) may be covered on the top surface of the intermediate structure 800e to expose the initial first trench 836'. Further, an etching (e.g., dry etching and / or wet etching) process may be used to remove the first sacrificial material 838 in the initial first trench 836'.

[0118] Next, in some embodiments, Fig.13A and Fig. 13BAs shown, an etching (e.g., wet etching) process may be used to increase the size of the initial first trench 836' in the D1 direction to form a first trench 836 having a larger size in the D1 direction. Optionally, in the process of increasing the size of the initial first trench 836' in the D1 direction, the size of the initial first trench 836' in the D3 direction may also increase.

[0119] Fig.14A and Fig. 14B The intermediate structure 800g is shown after forming the initial first gate dielectric layer 815' and the initial first word line 816'. Fig.14A It is a schematic cross-sectional view of the intermediate structure 800g taken in a direction perpendicular to D2. Fig. 14B It is along Fig.14A A schematic cross-sectional view taken along line CC' is shown. Fig.15 is a schematic top view of the semiconductor device 800h after the shielding connection structure 841 is formed.

[0120] In some embodiments, FIG. 13A to FIG. 14B As shown, when the first trench 836 is in an unfilled state, a thin film deposition process such as CVD, PVD, ALD or any combination thereof, or an oxidation method (for example, a dry oxidation method or a wet oxidation method) may be used to form an initial first gate dielectric layer 815' on the inner wall of the first trench 836. Optionally, before forming the initial first gate dielectric layer 815', the first sacrificial material 838 in the second trench 837 may be removed, so that the second trench 837 is also in an unfilled state. For example, during the process of forming the initial first gate dielectric layer 815', a third gate dielectric layer (not shown) may be formed on the inner wall of the second trench 837.

[0121] Then, continue to refer to Fig.14A and Fig. 14B , an initial first adhesive layer 8161' and an initial first metal layer 8162' may be sequentially formed on the surface of the initial first gate dielectric layer 815' by using a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The initial first adhesive layer 8161' and the initial first metal layer 8162' may serve as an initial first word line 816'. Optionally, an etching process (e.g., dry etching and / or wet etching) may be used to remove a portion of the initial first word line 816' away from the first semiconductor layer 831, so that the surface of the initial first word line 816' away from the first semiconductor layer 831 is lower than the surface of the first semiconductor pillar 813 away from the first semiconductor layer 831. Next, a first isolation structure 818 may be formed on the inner side of the initial first word line 816' by using a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0122] In some embodiments, Fig. 14BAs shown, the second isolation structure 842 may be formed by an etching (e.g., dry etching and / or wet etching) process and a thin film deposition process. For example, the second isolation structure 842 is located in the second region 803. For example, the material of the second isolation structure 842 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. The second isolation structure 842 is used to disconnect the initial first word line 816' in a ring shape (seen from the direction D3), so that the initial first word line 816' is only located on one side of the first semiconductor column 813 in the first region 802 after disconnection.

[0123] In some embodiments, continue to refer to Fig.14A and Fig. 14B After forming the initial first word line 816', the first isolation structure 818, and the second isolation structure 842, the first sacrificial material 838 in the second trench 837 may be removed (refer to Fig.13A and Fig. 13B ). Further, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form a conductive layer 840 in the second trench 837 and on the top surface of the intermediate structure 800g. The conductive layer 840 in the second trench 837 may serve as a shielding structure 819. Further, an etching process (e.g., dry etching and / or wet etching) may be used to pattern the conductive layer 840 formed on the top surface of the intermediate structure 800g to remove a portion of the conductive layer 840 covering the top surface of the intermediate structure 800g. The retained conductive layer 840 serves as a shielding connection structure 841, such as Fig.15 As shown. The shielding connection structure 841 may be connected to (eg, directly contacted with) the plurality of shielding structures 819 in the direction D3. Optionally, during the process of forming the shielding connection structure 841, a portion of the shielding structure 819 away from the first semiconductor layer 831 may be removed so that the shielding structure 819 is aligned with the first word line 816 to be formed (see FIG. Fig.18 ) in the D3 direction.

[0124] Fig.16A and Fig. 16B The intermediate structure 800i after forming the first capacitor 820 is shown. Fig.16A and Fig. 16B They are schematic cross-sectional views of the intermediate structure 800i taken on different planes perpendicular to the D2 direction. Fig.16A is a schematic cross-sectional view of the intermediate structure 800i taken within the first region 802. Fig. 16B is a schematic cross-sectional view of the intermediate structure 800i taken within the second region 803.

[0125] In some embodiments, Fig.16A As shown, the first capacitor 820 may be formed at the first end of the first semiconductor column 813 (e.g., the end away from the first semiconductor layer 831) by any process known in the art. For example, the first semiconductor column 813 may be at least a portion of the plurality of first semiconductor columns 813 located in the first region 802. Optionally, the first capacitor connection structure 821 may be formed between the first capacitor 820 and the first end of the first semiconductor column 813 by any process known in the art. For example, the second electrodes of each of the plurality of first capacitors 820 may be connected to each other by forming a first capacitor interconnection structure 825.

[0126] In some embodiments, Fig. 16B As shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form an insulating cover layer 843 on the top side (e.g., in the second region 803) of the shielding connection structure 841. Exemplarily, the material of the insulating cover layer 843 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material or materials.

[0127] Fig.17 FIG. 8 is a cross-sectional schematic diagram of the intermediate structure 800j after being connected to the first supporting structure 822. Fig.17 is a schematic cross-sectional view of the intermediate structure 800j taken on a plane perpendicular to the D2 direction. For example, Fig.17 800j is a schematic cross-sectional view of the intermediate structure 800j taken within the first region 802.

[0128] In some embodiments, Fig.17 As shown in FIG. 8 , the first supporting structure 822 can be connected to a side of the first capacitor 820 away from the first semiconductor pillars 813. In other words, the first supporting structure 822 can be connected to the first capacitor 820. Fig.16A or Fig. 16B The intermediate structure 800i is shown connected (eg, bonded) in the D3 direction, and such that Fig.17 The intermediate structure 800j shown is relative to Fig.16A or Fig. 16B The intermediate structure 800 i is shown flipped 180° to allow subsequent processing from a second side of the first semiconductor layer 831 (eg, a back side of the first semiconductor layer 831 ).

[0129] Fig.18 The intermediate structure 800k after forming the first gate dielectric layer 815, the first word line 816 and the first bit line 812 is shown. Fig.18 is a schematic cross-sectional view of the intermediate structure 800k taken on a plane perpendicular to the D2 direction. For example, Fig.18 is a schematic cross-sectional view of the intermediate structure 800k taken within the first region 802.

[0130] In some embodiments, Fig.17 and Fig.18 As shown, the first semiconductor layer 831 may be planarized by using a CMP process from the second side of the first semiconductor layer 831. Then, a portion of the initial first gate dielectric layer 815' and the initial first word line 816' away from the first capacitor 820 may be removed from the second side of the first semiconductor layer 831, for example, by using an etching process (e.g., dry etching and / or wet etching), so that the initial first gate dielectric layer 815' is disconnected in the direction D1, thereby forming the first gate dielectric layer 815 and the first word line 816.

[0131] In some embodiments, during the formation of the first word line 816, an etching (e.g., dry etching and / or wet etching) process may be used to remove a portion of the shielding structure 819 away from the first capacitor 820, so that the shielding structure 819 matches the size of the first word line 816 in the D3 direction. Optionally, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to fill an insulating material in the space formed after removing the initial first gate dielectric layer 815', the initial first word line 816', and a portion of the shielding structure 819. For example, the insulating material may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material or materials.

[0132] In some embodiments, continue to refer to Fig.18 , the first bit line 812 can be formed by using a photolithography and etching process and a thin film deposition process. For example, the first bit line 812 and the first semiconductor wall 834 (refer to Fig. 9A ) are directly in contact with the unetched portion, thereby connecting the first bit line 812 to a plurality of first semiconductor pillars 813 arranged along the direction D1.

[0133] Fig.19 The intermediate structure 8001 (ie, the first semiconductor structure 810) is shown after forming the first interconnect layer 824. Fig.19 is a schematic cross-sectional view of the intermediate structure 8001 taken on a plane perpendicular to the D2 direction. For example, Fig.19 800 is a schematic cross-sectional view of the intermediate structure 8001 taken within the first region 802 .

[0134] In some embodiments, Fig.19 The first bit line 812 shown has a first cutout 823. For example, referring to Fig.19After forming the first bit line 812 extending continuously along the D1 direction, a first notch 823 may be formed by photolithography and etching (e.g., wet etching and / or dry etching) processes. The first notch 823 may separate the first bit line 812 extending continuously into a first portion and a second portion. For example, the first notch 823 may correspond to the opening 839. For example, the first notch 823 may be substantially aligned with the opening 839 in the D3 direction, thereby enhancing the electrical isolation effect between the first portion and the second portion after the first bit line 812 is disconnected.

[0135] In some embodiments, after forming the first bit line 812, a first interconnect layer 824 may be formed on a side of the first bit line 812 away from the first semiconductor pillar 813. For example, the step of forming the first interconnect layer 824 may include alternately forming first interconnect channels 8241 and first interconnect lines 8242, or only forming the first interconnect channels 8241.

[0136] In the above, combined with FIG. 8A to FIG. 19 right Figure 7 The step S710 shown in FIG. 1 is described exemplarily. It is understood that the first semiconductor structure may also be manufactured by any other method known in the art. For example, in the process of forming the first word line, the first trench 836 (see FIG. 1 ) may be formed. Fig.13A and Fig. 13B ), a barrier layer is formed at the bottom of the first trench 836, and an initial first gate dielectric layer and an initial first word line are sequentially formed on the surface of the barrier layer and the first trench. Further, a portion of the initial first gate dielectric layer and the initial first word line located on the surface of the barrier layer is removed by a punching etching process, so that the initial first word line is disconnected in the D1 direction.

[0137] Reference again Figure 7 In step S720, the FIG. 8A to FIG. 19 The method similar to the method of manufacturing the first semiconductor structure 810 is shown to form the second semiconductor structure 850 (refer to Fig. 20 ). For the purpose of concise description, the present application does not repeat the specific process of forming the second semiconductor structure 850. Thus, the first semiconductor structure 810 and the second semiconductor structure 850 can be manufactured in parallel to save production time, improve production efficiency, and reduce the impact of the thermal budget of one semiconductor structure on the other semiconductor structure when manufacturing one semiconductor structure.

[0138] Fig. 20 A semiconductor device 800 is shown. Fig. 20 is a schematic cross-sectional view of the semiconductor device 800 taken on a plane perpendicular to the D2 direction. Fig. 20 is a schematic cross-sectional view of the semiconductor device 800 taken within the first region 802 .

[0139] In step 730, if Fig. 20 As shown, the second semiconductor structure 850 can be connected to one side of the first semiconductor structure 810 in the direction D3 so that the two are connected to form an integral structure.

[0140] In some embodiments, the first semiconductor structure 810 and the second semiconductor structure 850 can be connected by aligning the first interconnection channel 8241 in the first interconnection layer 824 and the second interconnection channel 8641 in the second interconnection layer 864. At the same time, based on the design of the first interconnection layer 824 and the second interconnection layer 864, the disconnected first bit line 812 and the second bit line 952 can have Figure 2A , Figure 3A , Figure 4A or Figure 5A The connection method shown improves the bit line coupling effect, which is beneficial to improving the reading accuracy.

[0141] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device, characterized in that: include: A first semiconductor structure comprising: A plurality of first storage units are arranged in an array along a first direction and a second direction; a first bit line, located at one side of the first storage unit in the third direction, extending along the first direction, and connected to the first storage units arranged along the first direction; and The second semiconductor structure comprises: A plurality of second storage units are arranged in an array along the first direction and the second direction; A second bit line is located at one side of the second storage unit in the third direction, extends along the first direction, and is connected to the second storage units arranged along the first direction; The first semiconductor structure is connected to the second semiconductor structure and arranged along the third direction, and the first direction, the second direction and the third direction intersect with each other.

2. The semiconductor device according to claim 1, wherein The first bit line and the second bit line are close to each other at a connection interface between the first semiconductor structure and the second semiconductor structure; The first bit line has at least one first cutout and is divided into a first portion and a second portion at the first cutout, and the second bit line has at least one second cutout and is divided into a third portion and a fourth portion at the second cutout.

3. The semiconductor device according to claim 2, wherein: The first cutout and the second cutout are at least partially aligned in the third direction.

4. The semiconductor device according to claim 2, wherein: The first portion is connected to one of the third portion and the fourth portion, and the second portion is connected to the other of the third portion and the fourth portion.

5. The semiconductor device according to claim 4, wherein: The first portion is connected to the three portions, and the second portion is connected to the fourth portion, wherein the first portion and the third portion are located on the same side of the first incision in the first direction.

6. The semiconductor device according to claim 4, wherein: The first portion is connected to the fourth portion, and the second portion is connected to the third portion, wherein the first portion and the third portion are located on the same side of the first incision in the first direction.

7. The semiconductor device according to claim 6, wherein: A plurality of the first bit lines are arranged in the second direction, a plurality of the second bit lines are arranged in the second direction, and two first cutouts respectively located in the first bit lines adjacent to each other have a spacing in the first direction.

8. The semiconductor device according to any one of claims 2 to 6, wherein: The semiconductor device further includes a sense amplifier, and the first bit line and the second bit line are connected to the same sense amplifier.

9. The semiconductor device according to claim 4, wherein: A plurality of the first bit lines are arranged in the second direction, and a plurality of the second bit lines are arranged in the second direction. In one pair of the first bit line and the second bit line, the first portion is connected to the fourth portion, and in another adjacent pair of the first bit line and the second bit line, the second portion is connected to the third portion.

10. The semiconductor device according to claim 9, wherein The second portion of the first bit line is connected to the first portion of the adjacent first bit line, and the third portion of the second bit line is connected to the fourth portion of the adjacent second bit line.

11. The semiconductor device according to claim 10, wherein: The semiconductor device further includes a sense amplifier; A first portion of the first bit line, a second portion of the second bit line, an adjacent second portion of the first bit line, and a third portion of an adjacent second bit line are connected to the same sense amplifier; The second portion of the first bit line, the adjacent first portion of the first bit line, the third portion of the second bit line, and the adjacent fourth portion of the second bit line are connected to the same sense amplifier.

12. The semiconductor device according to claim 1, wherein The first semiconductor structure further comprises: A first interconnect layer, located on a side of the first bit line away from the plurality of first memory cells; The second semiconductor structure further includes: a second interconnect layer, located on a side of the second bit line away from the plurality of second storage cells; The first semiconductor structure and the second semiconductor structure are connected through the first interconnect layer and the second interconnect layer.

13. The semiconductor device according to claim 1, wherein Each of the first storage units and each of the second storage units comprises: a semiconductor column extending along the third direction and having a first sidewall intersecting the first direction; a gate dielectric layer, located on a surface of the first sidewall; a capacitor located at a side of the semiconductor column away from the first bit line or the second bit line; The first semiconductor structure further comprises: a first word line extending along the second direction and connected to the gate dielectric layer in the first memory cells arranged along the second direction; and The second semiconductor structure further includes: The second word line extends along the second direction and is connected to the gate dielectric layer in the second storage cells arranged along the second direction.

14. A memory system, characterized in that: include: A memory comprising a semiconductor device according to any one of claims 1 to 13; as well as The controller is coupled to the memory and is used to control the memory to store data.

15. A method for manufacturing a semiconductor device, characterized in that: include: A first semiconductor structure is formed, wherein the first semiconductor structure comprises a plurality of first memory cells and a first bit line, the plurality of first memory cells are arranged in an array along a first direction and a second direction; the first bit line is located on one side of the first memory cell in a third direction, extends along the first direction, and is connected to the first memory cells arranged along the first direction; forming a second semiconductor structure, wherein the second semiconductor structure comprises a plurality of second memory cells and a second bit line, the plurality of second memory cells are arranged in an array along the first direction and the second direction; the second bit line is located on one side of the second memory cell in the third direction, extends along the first direction, and is connected to the second memory cells arranged along the first direction; and The first semiconductor structure is connected to one side of the second semiconductor structure in the third direction, wherein the first direction, the second direction and the third direction intersect each other.

16. The manufacturing method according to claim 15, wherein: Forming a first semiconductor structure includes: forming a first bit line having at least one first notch, wherein the first bit line is broken into a first portion and a second portion at the first notch; Wherein, forming the second semiconductor structure comprises: forming a second bit line having at least one second notch, wherein the second bit line is broken into a third portion and a fourth portion at the second notch; Wherein, connecting the first semiconductor structure to the second semiconductor structure on one side of the third direction includes: The first bit line and the second bit line are located between the plurality of first memory cells and the plurality of second memory cells, the first portion is connected to one of the third portion and the fourth portion, and the second portion is connected to the other of the third portion and the fourth portion.

17. The manufacturing method according to claim 15, wherein: Forming the first semiconductor structure further includes: forming a first interconnect layer on a side of the first bit line away from the plurality of first memory cells; Wherein, forming the second semiconductor structure further comprises: forming a second interconnect layer on a side of the second bit line away from the plurality of second memory cells; Wherein, connecting the first semiconductor structure to the second semiconductor structure on one side of the third direction includes: The first semiconductor structure is connected to one side of the second semiconductor structure in the third direction through the first interconnect layer and the second interconnect layer.

18. The manufacturing method according to claim 16, wherein: Forming a first semiconductor structure includes: forming a plurality of first semiconductor walls extending along the first direction and arranged along the second direction in the first semiconductor layer; Filling an insulating material on the outer side of the first semiconductor wall; forming a plurality of first trenches extending along the second direction and arranged along the first direction to divide the plurality of first semiconductor walls into a plurality of first semiconductor pillars; forming a first gate dielectric layer on a first side wall of the first semiconductor column; forming a first word line extending along the second direction, the first word line contacting a surface of the first gate dielectric layer in the first semiconductor pillars arranged along the second direction; and A first capacitor is formed at a first end of the first semiconductor column.

19. The manufacturing method according to claim 18, wherein: The depth of the first trench is smaller than the dimension of the first semiconductor wall in the third direction; Wherein, forming a plurality of first semiconductor walls extending along the first direction and arranged along the second direction in the first semiconductor layer comprises: forming at least one opening through at least one of the first semiconductor walls; The step of forming a first bit line having at least one first notch comprises: The first bit line is formed at a second end of the first semiconductor column away from the first capacitor, and the opening corresponds to the first notch.

20. The manufacturing method according to claim 19, wherein: Before forming the first bit line at the second end of the first semiconductor column away from the first capacitor, the method further includes: The first supporting structure is connected to a side of the first capacitor away from the plurality of first semiconductor pillars.

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