Three-dimensional dynamic memory and preparation method thereof

Abstract

The invention discloses a three-dimensional dynamic memory and a preparation method thereof, and relates to the technical field of dynamic memorizers, the memory structure comprises a substrate layer, and a peripheral electrode layer and a memory array grown on the substrate layer; a plurality of vertical annular grooves are formed in the peripheral electrode layer, two vertical holes are formed in the area of each annular groove, and each annular groove and the two holes in the annular groove extend to the first dielectric layer on the bottommost layer of the peripheral electrode layer; and filling a capacitor dielectric layer in the annular groove, and respectively generating a gate layer and a bit line metal electrode layer in the two holes to form a read gate device and a write gate device, thereby forming the memory unit. According to the invention, two one-way gating devices are used for replacing a single two-way conduction device, when data erasing operation needs to be carried out, only specific voltage needs to be applied to the write gating layer and the read gating layer at the same time, the erasing operation of a string of storage units in the vertical direction can be completed, and the erasing operation of the memory is simplified.

Description

Technical Field

[0001] The present application relates to the technical field of dynamic memory, and in particular to a three-dimensional dynamic memory and a preparation method thereof. Background Art

[0002] With the explosive growth of data volume, especially in cloud computing, artificial intelligence, big data analysis and other fields, the demand for high-speed, large-capacity, and low-latency memory continues to rise. The market has a strong demand for DRAM products with higher density, lower power consumption, and greater bandwidth. Driven by market demand and technological innovation, 3D DRAM has become a new path for the industry to break through the higher limits of DRAM technology. In 2022, Huazhong University of Science and Technology disclosed a new type of dynamic memory device structure (CN2021112803491), namely the new 1S1C structure dynamic memory, which provides a feasible solution for the next generation of high-density dynamic memory, but its complex operation mode limits its further application. For example, the current 1S1C memory data erase operation is difficult. This is due to the dynamic memory properties of the 1S1C memory. The data stored in it will pass over time. Therefore, the voltage difference between the two ends of the capacitor corresponding to the storage data state is a range. When performing an erase operation, it is necessary to ensure that the applied erase voltage can be effectively erased when the voltage between the two ends of the capacitor is in any state, and high requirements are put forward for the erase operation window and the erase operation pulse. Therefore, how to optimize the structure of the dynamic memory and simplify its erase operation is a problem to be solved urgently in the art. Summary of the invention

[0003] The purpose of the present application is to provide a three-dimensional dynamic memory and a preparation method thereof, which optimizes the structure of the dynamic memory and simplifies the erasing operation of the three-dimensional dynamic memory.

[0004] To achieve the above objectives, this application provides the following solutions: In a first aspect, the present application provides a three-dimensional dynamic memory, comprising: a substrate layer, a peripheral electrode layer grown on the substrate layer, and a storage array; the peripheral electrode layer comprises a first dielectric layer and a first metal electrode layer alternately grown on the substrate layer, and the topmost and bottommost layers of the peripheral electrode layer are both first dielectric layers; a plurality of vertical annular grooves are provided on the peripheral electrode layer, and the bottoms of the annular grooves extend to at least the first dielectric layer at the bottom layer of the peripheral electrode layer; two vertical holes are provided in the region of each of the annular grooves, and the bottoms of the holes extend to at least the first dielectric layer at the bottom layer of the peripheral electrode layer.

[0005] The storage array includes a plurality of storage units, each of which includes a capacitor dielectric layer, a write enable device and a read enable device; the capacitor dielectric layer is filled in the annular groove; the write enable device includes a write enable layer, a write bit line metal electrode layer and a first metal electrode layer in contact with the write enable layer; the read enable device includes a read enable layer, a read bit line metal electrode layer and a first metal electrode layer in contact with the read enable layer; the read enable layer covers the inner wall surface of a hole, and the write enable layer covers the inner wall surface of another hole; the read bit line metal electrode layer is filled in the central area of ​​the read enable layer, and the write bit line metal electrode layer is filled in the central area of ​​the write enable layer.

[0006] Optionally, the write enable layer and the read enable layer are both composed of unidirectional threshold conductive materials; the conduction direction of the write enable layer is from the write bit line metal electrode layer to the first metal electrode layer in contact with the write enable layer, and the conduction direction of the read enable layer is from the first metal electrode layer in contact with the read enable layer to the read bit line metal electrode layer.

[0007] Optionally, the write bit line metal electrode layer is the upper electrode of the write enable device, and the first metal electrode layer in contact with the write enable layer is the lower electrode of the write enable device; the read bit line metal electrode layer is the upper electrode of the read enable device, and the first metal electrode layer in contact with the read enable layer is the lower electrode of the read enable device; the first metal electrode layer in the annular groove, the first metal electrode layer outside the annular groove and the capacitor dielectric layer constitute the capacitor of the storage unit, and data information is stored in the capacitor in the form of electric charge; the first metal electrode layer in the annular groove is the upper electrode of the capacitor, and the first metal electrode layer outside the annular groove is the lower electrode of the capacitor.

[0008] Optionally, when the voltage difference between the upper electrode and the lower electrode of the write enable device in the conduction direction is greater than the conduction threshold voltage of the write enable device, the write enable device will be turned on, and the current will flow to the capacitor through the write enable device. At this time, the charge is charged on the capacitor, and data can be written. Otherwise, the write enable device remains in the closed state; when the voltage difference between the upper electrode and the lower electrode of the read enable device in the conduction direction is greater than the conduction threshold voltage of the read enable device, the read enable device will be turned on, and the current will flow to the read enable device through the capacitor. At this time, the charge flows out of the capacitor, and data can be read. Otherwise, the read enable device remains in the closed state.

[0009] Optionally, a turn-on threshold voltage of the write-enabling device is smaller than a turn-on threshold voltage of the read-enabling device.

[0010] Optionally, for any annular groove, the annular groove forms a plurality of storage units in the vertical direction, and when a first preset voltage is applied to the write bit line metal electrode layer of any storage unit formed under the annular groove, and a second preset voltage is applied to the read bit line metal electrode layer of the storage unit, the upper electrode of the capacitor generates a data erasing potential, thereby performing a data erasing operation on all storage units formed under the annular groove.

[0011] Optionally, the relationship between the first preset voltage, the second preset voltage and the data erasing potential is as shown in the following formula: V initial =( V 1- V 2)* R on_read / ( R on_write + R on_read )+ V 2.

[0012] in, V initial is the data erase potential, V 1 is the first preset voltage, V 2 is the second preset voltage, R on_read is the on-resistance of the read gate device, R on_write is the on-resistance of the write-enable device.

[0013] Optionally, the write enable device has a first holding voltage in the conduction direction, and the first holding voltage is ≤ the conduction threshold voltage of the write enable device; the read enable device has a second holding voltage in the conduction direction, and the second holding voltage is ≤ the conduction threshold voltage of the read enable device.

[0014] In a second aspect, the present application provides a method for preparing a three-dimensional dynamic memory, comprising the following steps: A plurality of first dielectric layers and a plurality of first metal electrode layers are alternately grown on the substrate layer to form a peripheral electrode layer.

[0015] A plurality of annular grooves penetrating in the vertical direction are etched on the peripheral electrode layer, and the annular grooves are filled with capacitor dielectric layers; the bottom of the annular grooves at least extends to the first dielectric layer at the bottom of the peripheral electrode layer.

[0016] For any annular groove, two vertical holes are opened in the region of the annular groove; the bottom of the holes at least extends to the first dielectric layer at the bottom of the peripheral electrode layer.

[0017] A read enable layer is grown on the inner wall surface of a hole in the annular groove, and a read bit line metal electrode layer is filled in the central area of ​​the read enable layer; the read enable layer, the read bit line metal electrode layer and a first metal electrode layer in contact with the read enable layer constitute a read enable device.

[0018] A write enable layer is grown on the inner wall surface of another hole in the annular groove, and a write bit line metal electrode layer is filled in the central area of ​​the write enable layer; the write enable layer, the write bit line metal electrode layer and the first metal electrode layer in contact with the write enable layer constitute a write enable device; the first metal layer of any layer in the annular groove, the write enable device, the read enable device and the capacitor dielectric layer constitute a storage unit.

[0019] Optionally, for any annular groove, the annular groove constitutes a plurality of storage units in the vertical direction; when a first preset voltage is applied to the write bit line metal electrode layer of any storage unit formed under the annular groove, and a second preset voltage is applied to the read bit line metal electrode layer of the storage unit, the upper electrode of the capacitor generates a data erasing potential, thereby performing a data erasing operation on all storage units formed under the annular groove.

[0020] According to the specific embodiments provided in this application, this application discloses the following technical effects: The present application provides a three-dimensional dynamic memory and a preparation method thereof. The memory structure comprises: a substrate layer, a peripheral electrode layer grown on the substrate layer, and a storage array; a plurality of vertical annular grooves are provided on the peripheral electrode layer, and two vertical holes are provided in the region of each annular groove, and each annular groove and the two holes therein extend to the first dielectric layer at the bottom layer of the peripheral electrode layer; a capacitor dielectric layer is filled in the annular groove, and a read enable layer, a read bit line metal electrode layer, and a write enable layer, a write bit line metal electrode layer are generated in the two holes respectively, forming a read enable device and a write enable device respectively, and each first metal electrode layer, read enable device, and write enable device in the annular groove constitute a storage unit. The present application improves the 1S1C dynamic memory structure by replacing the previous single bidirectional conductive device with two unidirectional enabling devices, thereby reducing the leakage current of the memory device and improving the data retention time of the memory cell; and in the three-dimensional stacked dynamic memory, by introducing a read enabling device and a write enabling device, the read and write operations of the memory cell are controlled respectively. When a data erasing operation is required, it is only necessary to apply a specific voltage to the write enabling layer and the read enabling layer at the same time to complete the erasing operation of a string of memory cells in the vertical direction, and the memory cell can be operated to a specified potential, thereby simplifying the erasing operation of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A top view of a three-dimensional dynamic memory provided in one embodiment of the present application.

[0023] Figure 2 A cross-sectional schematic diagram of a peripheral electrode layer in a three-dimensional dynamic memory provided by an embodiment of the present application.

[0024] Figure 3 A schematic diagram of a trench on a peripheral electrode layer in a three-dimensional dynamic memory provided in one embodiment of the present application.

[0025] Figure 4 An IV schematic diagram of a read gating device and a write gating device selected in a three-dimensional dynamic memory provided in an embodiment of the present application.

[0026] Figure 5 A current diagram of a read-enable device in a three-dimensional dynamic memory provided by an embodiment of the present application.

[0027] Figure 6 A current diagram of a write-enable device in a three-dimensional dynamic memory provided by an embodiment of the present application.

[0028] Figure 7 A diagram showing a preset voltage V1, a preset voltage V2, and voltages of the upper plates of multiple storage unit capacitors in a three-dimensional dynamic memory provided by an embodiment of the present application.

[0029] Figure 8 A flowchart of a method for preparing a three-dimensional dynamic memory provided in one embodiment of the present application.

[0030] Reference numerals: 1. Write enable layer; 2. Read enable layer; 3a. First metal electrode layer in the annular groove; 3b. First metal electrode layer outside the annular groove; 4. Capacitor dielectric layer; 5. Write bit line metal electrode layer; 6. Read bit line metal electrode layer; 7. Groove; 8. Read enable device current; 9. Write enable device current; 10. Preset voltage V 1; 11, the potential of the upper plates of the capacitors of the plurality of storage units; 12, the second preset voltage V 2; Sw, write enable device; Sr, read enable device. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0032] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0033] In an exemplary embodiment, Figure 1 As shown, a three-dimensional dynamic memory is provided, comprising: a substrate layer, a peripheral electrode layer grown on the substrate layer, and a storage array; Figure 2 As shown, the peripheral electrode layer includes a first dielectric layer and a first metal electrode layer alternately grown on the substrate layer, and the topmost and bottommost layers of the peripheral electrode layer are both the first dielectric layer to ensure the insulation of the top of the array; a plurality of vertical annular grooves are provided on the peripheral electrode layer, and the bottom of the annular grooves at least extend to the first dielectric layer at the bottom of the peripheral electrode layer; two vertical holes are provided in the area of ​​each of the annular grooves, and the bottom of the holes at least extend to the first dielectric layer at the bottom of the peripheral electrode layer to ensure that storage units can also be formed in the bottom first metal electrode layer.

[0034] The storage array includes a plurality of storage units, and the storage unit includes a capacitor dielectric layer, a write gate device, and a read gate device; the capacitor dielectric layer is filled in the annular groove, and preferably, the capacitor dielectric layer grows in the annular groove layer by layer along the side wall of the annular groove, not from the bottom to the top; the write gate device includes a write gate layer, a write bit line metal electrode layer, and a first metal electrode layer in contact with the write gate layer; the read gate device includes a read gate layer, a read bit line metal electrode layer, and a first metal electrode layer in contact with the read gate layer; the read gate layer covers the inner wall surface of a hole, and the write gate layer covers the inner wall surface of another hole; the read bit line metal electrode layer is filled in the central area of ​​the read gate layer, and the write bit line metal electrode layer is filled in the central area of ​​the write gate layer. The bottom of the write bit line metal electrode layer and the write gate layer is lower than the bottom first metal electrode layer in the vertical direction, and similarly, the bottom of the read bit line metal electrode layer and the read gate layer is lower than the bottom first metal electrode layer in the vertical direction.

[0035] In each annular groove, each first metal electrode layer wrapped therein is a storage unit, and the wrapped first metal electrode layer is a storage node of the storage unit, and the potential thereof represents the stored information.

[0036] In an exemplary embodiment, in order to facilitate independent operation, the storage array is divided into small areas by a number of grooves, such as Figure 3 As shown, there are several grooves penetrating in the vertical direction in the peripheral electrode layer, the grooves are parallel to each other, and the bottom of the grooves is located below the bottom first dielectric layer. Each first metal electrode layer is divided into several independent strip electrodes by the grooves, and the strip electrodes are the word lines of the memory.

[0037] Specifically in this embodiment, the write enable layer and the read enable layer are both composed of unidirectional threshold conduction materials, which means that these layers will only conduct in one direction, and will always be in a closed state no matter how large the voltage applied in the opposite direction is, and in the conduction direction, they will only be conducted when the applied voltage is greater than the threshold voltage; the conduction direction of the write enable layer is from the write bit line metal electrode layer to the first metal electrode layer in contact with the write enable layer, and the conduction direction of the read enable layer is from the first metal electrode layer in contact with the read enable layer to the read bit line metal electrode layer.

[0038] Specifically in this embodiment, the write bit line metal electrode layer is the upper electrode of the write enable device, and the first metal electrode layer in contact with the write enable layer is the lower electrode of the write enable device; the read bit line metal electrode layer is the upper electrode of the read enable device, and the first metal electrode layer in contact with the read enable layer is the lower electrode of the read enable device; the first metal electrode layer in the annular groove, the first metal electrode layer outside the annular groove and the capacitor dielectric layer constitute the capacitor of the storage unit, and data information is stored in the capacitor in the form of electric charge; the first metal electrode layer in the annular groove is the upper electrode of the capacitor, and the first metal electrode layer outside the annular groove is the lower electrode of the capacitor.

[0039] In the three-dimensional dynamic memory structure provided in the present embodiment, the conduction modes of the write enable device and the read enable device are both threshold-on. When the voltage difference between the upper electrode and the lower electrode of the write enable device in the conduction direction is greater than the conduction threshold voltage Vth1 of the write enable device, the write enable device will be turned on, and the current will flow to the capacitor through the write enable device. At this time, the charge is charged on the capacitor, and data can be written. Otherwise, the write enable device remains in a closed state; when the voltage difference between the upper electrode and the lower electrode of the read enable device in the conduction direction is greater than the conduction threshold voltage Vth2 of the read enable device, the read enable device will be turned on, and the current will flow to the read enable device through the capacitor. At this time, the charge flows out of the capacitor, and data can be read. Otherwise, the read enable device remains in a closed state.

[0040] like Figure 4 As shown, the thick line Sw in the figure represents the IV curve of the opening process of the write enable device, and the thin line on the left of the thick line Sw represents the IV curve of the closing process of the write enable device. The thick line Sr in the figure represents the IV curve of the opening process of the read enable device, and the thin line on the left of the thick line Sr represents the IV curve of the closing process of the read enable device; when both enable devices are not turned on, under the same bias voltage, the read enable device has a leakage current smaller than that of the write enable device, wherein the threshold voltage Vth1 of the write enable device is about 1.8V, and the holding voltage is about 1.5V, the threshold voltage Vth2 of the read enable device is about 2.7V, and the holding voltage is about 2.2V, and the write enable device and the read enable device have the same on-resistance.

[0041] As a preferred embodiment, the conduction threshold voltage of the write gating device is less than the conduction threshold voltage of the read gating device. For general unidirectional gating devices, under the same voltage bias, a gating device with a large threshold voltage has a lower leakage current than a gating device with a small threshold voltage. That is, when the voltage applied to the write gating device and the read gating device in the conduction direction is greater than 0.2V and less than their respective conduction threshold voltages, the leakage current of the read gating device is less than that of the write gating device. This is to ensure that the read gating device has a smaller leakage current than the write gating device, which is convenient for extending the data retention time of the storage unit.

[0042] When a data erasing operation is required, for any annular groove, the annular groove forms a plurality of storage units in the vertical direction, and a first preset voltage is applied to the write bit line metal electrode layer of any storage unit formed under the annular groove. V 1. Apply a second preset voltage to the read bit line metal electrode layer of the memory cell. V 2, the upper electrode of the capacitor generates a data erase potential V initial, to perform a data erasing operation on all storage cells formed under the annular groove, that is, to restore the capacitor potentials of all storage cells to a logic "0" state.

[0043] Specifically in this embodiment, the relationship between the first preset voltage, the second preset voltage and the data erasing potential is shown in the following formula: V initial =( V 1- V 2)* R on_read / ( R on_write + R on_read )+ V 2.

[0044] in, V initial is the data erase potential, V 1 is the first preset voltage, V 2 is the second preset voltage, R on_read is the on-resistance of the read gate device, R on_write is the on-resistance of the write-enable device.

[0045] As an exemplary embodiment, the applied preset voltage V2 needs to meet the following conditions: when the upper electrode of the write enable device is suspended, by applying the preset voltage V2, the read enable device can be turned on regardless of the information stored in the storage unit; the applied preset voltages V1 and V2 need to meet the following conditions: the write enable device must be turned on before the read enable device is turned off.

[0046] Because the data writing of the three-dimensional dynamic memory provided in this embodiment is realized by writing the charge into the capacitor through the write gate device, the upper electrode of the capacitor is always at a positive potential. When performing an erase operation, in order to facilitate erasing the upper electrode potential of the capacitor to 0V, V1 is usually a positive voltage and V2 is a negative voltage. Therefore, the voltage across the read gate device will be higher than the write gate device. Therefore, the read gate device needs to be turned on earlier than the write gate device. Therefore, the applied voltage V2 needs to turn on the read gate device regardless of the information stored in the storage unit; after the read gate device is turned on, the applied voltage V1 needs to turn on the write gate device before the read gate device is turned off, so that the read gate device and the write gate device can be turned on at the same time to complete the data erase operation.

[0047] like Figure 5 Shown is a graph of the read gate device current. Figure 6 Shown is a diagram of the write-strobe device current. Figure 7The figure shows the voltage diagram of preset voltage V1, preset voltage V2 and the upper plates of multiple storage cell capacitors. The upper electrode potentials of the multiple storage cell capacitors are initially 0V, 1V, and 2V, which are used to simulate the same string of storage cells in the vertical direction being in different states. At this time, the preset voltage V1 is applied to the metal electrode layer of the write bit line, and the preset voltage V2 is applied to the metal electrode layer of the read bit line, both with amplitudes of 3V. It can be found that current is first generated on the read enable device, indicating that the read enable device is turned on first, and then current is generated on the write enable device. At this time, both the read enable device and the write enable device have current, indicating that the read enable device and the write enable device are turned on at the same time. Finally, the upper electrode potentials of the multiple storage cell capacitors all become 0V, indicating that this erasing method can simultaneously complete the erasing operation of the same string of storage cells in the vertical direction, and no matter what the initial state of the storage cell is, it can eventually be restored to the logic "0" state, that is, the upper electrode potential of the capacitor is 0V.

[0048] Obviously, for the three-dimensional dynamic memory structure provided in this embodiment, through the above erasing operation, a string of storage cells in the vertical direction can all be erased, thereby greatly improving the efficiency of erasing data in the storage cells.

[0049] As an exemplary embodiment, the write enable device has a first holding voltage in the conduction direction, and the first holding voltage is ≤ the conduction threshold voltage of the write enable device; the read enable device has a second holding voltage in the conduction direction, and the second holding voltage is ≤ the conduction threshold voltage of the read enable device.

[0050] In another exemplary embodiment, Figure 8 As shown, a method for preparing a three-dimensional dynamic memory is provided, comprising the following steps: A1. Alternately grow a plurality of first dielectric layers and a plurality of first metal electrode layers on the substrate layer to form a peripheral electrode layer, wherein the number of the first metal electrode layers grown is the same as the number of memory cell layers required by the three-dimensional dynamic memory structure.

[0051] A2. Etching a plurality of annular grooves penetrating in the vertical direction on the peripheral electrode layer, and filling the annular grooves with capacitor dielectric layers; the bottom of the annular grooves at least extends to the first dielectric layer at the bottom of the peripheral electrode layer.

[0052] A3. For any annular groove, two vertical holes are opened in the area of ​​the annular groove; the bottom of the holes at least extends to the first dielectric layer at the bottom of the peripheral electrode layer.

[0053] A4. A read enable layer is grown on the inner wall surface of a hole in the annular groove, and a read bit line metal electrode layer is filled in the central area of ​​the read enable layer; the read enable layer, the read bit line metal electrode layer and the first metal electrode layer in contact with the read enable layer constitute a read enable device.

[0054] A5. A write enable layer is grown on the inner wall surface of another hole in the annular groove, and a write bit line metal electrode layer is filled in the central area of ​​the write enable layer; the write enable layer, the write bit line metal electrode layer and the first metal electrode layer in contact with the write enable layer constitute a write enable device; the first metal layer of any layer in the annular groove, the write enable device, the read enable device and the capacitor dielectric layer constitute a storage unit.

[0055] In one embodiment, in order to facilitate independent operation, the storage array is divided into small areas by a plurality of grooves, and the above-mentioned preparation method further includes the following steps: A6. Etching a plurality of grooves penetrating in the vertical direction on the peripheral electrode layer, wherein the grooves are parallel to each other and the bottom of the grooves is located in the substrate, and the grooves divide the peripheral electrode layer into a plurality of independent strip-shaped parts.

[0056] The solutions provided by the above-mentioned multiple embodiments of the present application have improved the 1S1C three-dimensional dynamic memory structure, and replaced the previous single bidirectional conductive device with two unidirectional enabling devices, thereby reducing the leakage current of the memory device and improving the data retention time of the memory cell; and in the three-dimensional stacked dynamic memory, by introducing a read enabling device and a write enabling device to respectively control the read and write operations of the memory cell, when a data erasing operation is required, it is only necessary to apply a specific voltage to the write enabling layer and the read enabling layer at the same time to complete the erasing operation of a string of memory cells in the vertical direction, and the memory cell can be operated to a specified potential, thereby simplifying the erasing operation of the memory.

[0057] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0058] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A three-dimensional dynamic memory, characterized in that: include: A substrate layer, a peripheral electrode layer grown on the substrate layer, and a storage array; the peripheral electrode layer includes a first dielectric layer and a first metal electrode layer alternately grown on the substrate layer, and the topmost and bottommost layers of the peripheral electrode layer are both the first dielectric layer; the peripheral electrode layer is provided with a plurality of vertical annular grooves, and the bottoms of the annular grooves at least extend to the first dielectric layer at the bottom of the peripheral electrode layer; two vertical holes are provided in the region of each of the annular grooves, and the bottoms of the holes at least extend to the first dielectric layer at the bottom of the peripheral electrode layer; The storage array includes a plurality of storage units, each of which includes a capacitor dielectric layer, a write enable device and a read enable device; the capacitor dielectric layer is filled in the annular groove; the write enable device includes a write enable layer, a write bit line metal electrode layer and a first metal electrode layer in contact with the write enable layer; the read enable device includes a read enable layer, a read bit line metal electrode layer and a first metal electrode layer in contact with the read enable layer; the read enable layer covers the inner wall surface of a hole, and the write enable layer covers the inner wall surface of another hole; the read bit line metal electrode layer is filled in the central area of ​​the read enable layer, and the write bit line metal electrode layer is filled in the central area of ​​the write enable layer.

2. The three-dimensional dynamic memory according to claim 1, characterized in that: The write enable layer and the read enable layer are both composed of unidirectional threshold conductive materials; the conduction direction of the write enable layer is from the write bit line metal electrode layer to the first metal electrode layer in contact with the write enable layer, and the conduction direction of the read enable layer is from the first metal electrode layer in contact with the read enable layer to the read bit line metal electrode layer.

3. The three-dimensional dynamic memory according to claim 2, characterized in that: The write bit line metal electrode layer is the upper electrode of the write gating device, and the first metal electrode layer in contact with the write gating layer is the lower electrode of the write gating device; the read bit line metal electrode layer is the upper electrode of the read gating device, and the first metal electrode layer in contact with the read gating layer is the lower electrode of the read gating device; the first metal electrode layer in the annular groove, the first metal electrode layer outside the annular groove and the capacitor dielectric layer constitute the capacitor of the storage unit, and data information is stored in the capacitor in the form of electric charge; The first metal electrode layer in the annular groove is the upper electrode of the capacitor, and the first metal electrode layer outside the annular groove is the lower electrode of the capacitor.

4. The three-dimensional dynamic memory according to claim 3, characterized in that: The write enable device will be turned on when the voltage difference between the upper electrode and the lower electrode of the write enable device in the conduction direction is greater than the conduction threshold voltage of the write enable device, and the current will flow to the capacitor through the write enable device. At this time, the capacitor is charged and data can be written. Otherwise, the write enable device remains in the closed state; when the voltage difference between the upper electrode and the lower electrode of the read enable device in the conduction direction is greater than the conduction threshold voltage of the read enable device, the read enable device will be turned on, and the current will flow to the read enable device through the capacitor. At this time, the charge flows out of the capacitor and data can be read. Otherwise, the read enable device remains in the closed state.

5. The three-dimensional dynamic memory according to claim 4, characterized in that: A turn-on threshold voltage of the write gating device is less than a turn-on threshold voltage of the read gating device.

6. The three-dimensional dynamic memory according to claim 1, characterized in that: For any annular groove, the annular groove forms a plurality of storage units in the vertical direction. When a first preset voltage is applied to the write bit line metal electrode layer of any storage unit formed under the annular groove, and a second preset voltage is applied to the read bit line metal electrode layer of the storage unit, the upper electrode of the capacitor generates a data erasing potential, thereby performing a data erasing operation on all storage units formed under the annular groove.

7. The three-dimensional dynamic memory according to claim 6, characterized in that: The relationship between the first preset voltage, the second preset voltage and the data erasing potential is shown in the following formula: V initial =( V 1- V 2)* R on_read / ( R on_write + R on_read )+ V 2； in, V initial is the data erase potential, V 1 is the first preset voltage, V 2 is the second preset voltage, R on_read is the on-resistance of the read gate device, R on_write is the on-resistance of the write-enable device.

8. The three-dimensional dynamic memory according to claim 7, characterized in that: The write enable device has a first holding voltage in the conduction direction, and the first holding voltage is ≤ the conduction threshold voltage of the write enable device; the read enable device has a second holding voltage in the conduction direction, and the second holding voltage is ≤ the conduction threshold voltage of the read enable device.

9. A method for preparing a three-dimensional dynamic memory according to any one of claims 1 to 8, characterized in that: include: Alternatingly growing a plurality of first dielectric layers and a plurality of first metal electrode layers on the substrate layer to form a peripheral electrode layer; Etching a plurality of annular grooves penetrating in a vertical direction on the peripheral electrode layer, and filling the annular grooves with a capacitor dielectric layer; the bottom of the annular grooves at least extends to the first dielectric layer at the bottom of the peripheral electrode layer; For any annular groove, two vertical holes are opened in the region of the annular groove; the bottom of the holes at least extends to the first dielectric layer at the bottom of the peripheral electrode layer; A read gating layer is grown on the inner wall surface of a hole in the annular groove, and a read bit line metal electrode layer is filled in the central area of ​​the read gating layer; the read gating layer, the read bit line metal electrode layer and a first metal electrode layer in contact with the read gating layer constitute a read gating device; A write enable layer is grown on the inner wall surface of another hole in the annular groove, and a write bit line metal electrode layer is filled in the central area of ​​the write enable layer; the write enable layer, the write bit line metal electrode layer and the first metal electrode layer in contact with the write enable layer constitute a write enable device; the first metal layer of any layer in the annular groove, the write enable device, the read enable device and the capacitor dielectric layer constitute a storage unit.

10. The method for preparing a three-dimensional dynamic memory according to claim 9, characterized in that: For any annular groove, the annular groove forms a plurality of storage units in the vertical direction; when a first preset voltage is applied to the write bit line metal electrode layer of any storage unit formed under the annular groove, and a second preset voltage is applied to the read bit line metal electrode layer of the storage unit, the upper electrode of the capacitor generates a data erasing potential, thereby performing a data erasing operation on all storage units formed under the annular groove.

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