Three-dimensional memory device and forming method thereof

Abstract

A three-dimensional (3D) memory device and a method of forming the same are disclosed. According to an embodiment of the present disclosure, a three-dimensional (3D) memory device includes: a stack structure including a plurality of alternating dielectric layers and conductive layers; a first channel structure extending through the stack structure; a top select gate (TSG) layer over the stack structure; the etching stop layer is positioned above the top selection gate layer; a second channel structure extending through the etch stop layer and the top select gate layer, the second channel structure over and coupled to the first channel structure; the second channel structure is located above the etching stop layer, the contact plug is located above the second channel structure, the second channel structure comprises a first barrier layer part and a second barrier layer part which are continuous, the first barrier layer part completely covers the side wall of the top selection gate layer, and the second barrier layer part covers part of the side wall of the etching stop layer.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor technology, and more particularly to a three-dimensional (3D) memory device and a method for forming the same. Background Art

[0002] Planar memory cells have been scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and manufacturing techniques have become challenging and costly. As a result, the storage density of planar memory cells approaches the upper limit.

[0003] 3D memory architecture can address density limitations in planar memory cells. 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the invention

[0004] According to an embodiment of the present disclosure, a three-dimensional (3D) memory device is provided, comprising: a stack structure including a plurality of alternating dielectric layers and conductive layers; a first channel structure extending through the stack structure; a top select gate (TSG) layer located above the stack structure; an etch stop layer located above the top select gate layer; a second channel structure extending through the etch stop layer and the top select gate layer, the second channel structure being located above the first channel structure and coupled to the first channel structure; and a contact plug located above the second channel structure, wherein the second channel structure comprises a continuous first barrier layer portion and a second barrier layer portion, the first barrier layer portion completely covering a sidewall of the top select gate layer, and the second barrier layer portion covering a portion of the sidewall of the etch stop layer.

[0005] In some embodiments, the first channel structure includes, from inside to outside, a first semiconductor channel, a tunneling layer, a storage layer, and a first blocking layer.

[0006] In some embodiments, the second channel structure further includes a second semiconductor channel, the second semiconductor channel includes a first portion and a second portion, the first barrier layer portion and the second barrier layer portion surround the first portion, and the second portion contacts a sidewall of the etch stop layer.

[0007] In some embodiments, a dimension of the second portion close to the contact plug is greater than a dimension of the second portion far from the contact plug.

[0008] In some embodiments, the second portion has a cone shape.

[0009] In some embodiments, the second portion has a cylindrical shape.

[0010] In some embodiments, a size of the first portion is smaller than a size of the second portion.

[0011] In some embodiments, the first portion has a cylindrical shape.

[0012] According to an embodiment of the present disclosure, a method for forming a three-dimensional (3D) memory device is provided, comprising: forming a stack structure comprising a plurality of alternating dielectric layers and conductive layers; forming a first channel structure extending through the stack structure; forming a top select gate (TSG) layer above the stack structure; forming an etch stop layer above the top select gate layer; forming a second channel hole extending through the etch stop layer and the top select gate layer above the first channel structure; forming a continuous first barrier layer portion and a second barrier layer portion in the second channel hole, the first barrier layer portion completely covering the sidewall of the top select gate layer, and the second barrier layer portion covering a portion of the sidewall of the etch stop layer; filling the remaining second channel hole with a semiconductor material to form a second channel structure; and forming a contact plug above the second channel structure.

[0013] In some embodiments, forming the first channel structure includes: forming a first channel hole extending through the dielectric layer and the conductive layer; and sequentially forming a first barrier layer, a storage layer, a tunneling layer, and a first semiconductor channel in the first channel hole.

[0014] In some embodiments, forming the continuous first barrier layer portion and the second barrier layer portion includes: forming a barrier material layer covering the sidewalls of the top selection gate layer and the etch stop layer and the top of the etch stop layer through the second channel hole; forming a liner on the barrier material layer; performing facet dry etching on the barrier material layer and the liner so that the cross-section of the second channel hole above the top selection gate layer becomes larger and retains the barrier material layer covering part of the sidewalls of the etch stop layer to form the second barrier layer portion; and removing the remaining liner to expose the barrier material layer covering the sidewalls of the top selection gate layer to form the first barrier layer portion.

[0015] In some embodiments, forming the continuous first barrier layer portion and the second barrier layer portion includes: forming a barrier material layer covering the sidewalls of the top selection gate layer and the etch stop layer and the top of the etch stop layer through the second channel hole; forming a liner on the barrier material layer; removing the liner located at the top of the etch stop layer; removing the barrier material layer located at the top of the etch stop layer and covering a portion of the sidewalls of the etch stop layer to form the second barrier layer portion covering the remaining portion of the sidewalls of the etch stop layer; and removing the remaining liner in the second channel hole to expose the barrier material layer covering the sidewalls of the top selection gate layer to form the first barrier layer portion.

[0016] In some embodiments, forming the continuous first barrier layer portion and the second barrier layer portion includes: forming a barrier material layer on the sidewalls and bottom of the second channel hole and on the top of the etch stop layer; forming a liner on the barrier material layer; removing the liner located at the top of the etch stop layer and the bottom of the second channel hole; while removing the barrier material layer located at the bottom of the second channel hole, removing the barrier material layer located at the top of the etch stop layer and covering a portion of the sidewall of the etch stop layer to form the second barrier layer portion covering the remaining portion of the sidewall of the etch stop layer; and removing the remaining liner in the second channel hole to expose the barrier material layer covering the sidewall of the top selection gate layer to form the first barrier layer portion.

[0017] In some embodiments, forming the contact plug includes: forming a second dielectric layer covering the etch stop layer and the second channel structure; forming an opening penetrating the second dielectric layer, the opening exposing the second channel structure; and filling the opening with a conductive material to form the contact plug.

[0018] In some embodiments, forming the second channel structure includes forming a second semiconductor channel, the second semiconductor channel includes a first portion and a second portion, the first barrier layer portion and the second barrier layer portion surround the first portion, and the second portion contacts a sidewall of the etch stop layer.

[0019] In some embodiments, a dimension of the second portion close to the contact plug is greater than a dimension of the second portion far from the contact plug.

[0020] In some embodiments, the second portion has a cone shape.

[0021] In some embodiments, the second portion has a cylindrical shape.

[0022] In some embodiments, a size of the first portion is smaller than a size of the second portion.

[0023] In some embodiments, the first portion has a cylindrical shape.

[0024] According to an embodiment of the present disclosure, a storage system is provided, including: a storage device according to the present disclosure, the storage device being configured to store data; and a memory controller coupled to the storage device and configured to control the storage device.

[0025] In some embodiments, the memory system further includes a host coupled to the memory controller and configured to send or receive the data. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For those skilled in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0027] Figure 1 shows a cross-sectional view of a three-dimensional (3D) memory device according to a first embodiment of the present disclosure;

[0028] Figure 2 shows a cross-sectional view of a three-dimensional (3D) memory device according to a second embodiment of the present disclosure;

[0029] Figure 3 shows a cross-sectional view of a three-dimensional (3D) memory device according to a third embodiment of the present disclosure;

[0030] Figure 4(a)-4(o) shows a cross-sectional view of a 3D memory device at different stages of an exemplary manufacturing method according to a first embodiment of the present disclosure;

[0031] Figure 5(a)-5(g) shows a cross-sectional view of a 3D memory device at different stages of an exemplary manufacturing method according to a second embodiment of the present disclosure;

[0032] Figure 6(a)-6(g) shows a cross-sectional view of a 3D memory device at different stages of an exemplary manufacturing method according to a third embodiment of the present disclosure;

[0033] Figure 7(a)-7(g) shows a cross-sectional view of a 3D memory device at different stages of an exemplary manufacturing method according to a fourth embodiment of the present disclosure;

[0034] Figure 8 A flowchart showing a manufacturing method for forming a 3D memory device according to an embodiment of the present disclosure; and

[0035] Fig. 9 A block diagram of an exemplary system having a 3D memory device according to an embodiment of the present disclosure is shown.

[0036] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0037] The subject matter described herein will now be discussed with reference to example embodiments. It should be understood that the discussion of these embodiments is only to enable those skilled in the art to better understand and implement the subject matter described in the present disclosure, and is not a limitation of the scope of protection, applicability or examples set forth in the claims. The function and arrangement of the elements discussed can be changed without departing from the scope of protection of the present disclosure. Each example can omit, replace or add various processes or components as needed. For example, the described method can be performed in an order different from the described order, and each step can be added, omitted or combined. In addition, the features described relative to some examples can also be combined in other examples.

[0038] It should be noted that the references to "one embodiment", "embodiment", "some embodiments" and the like in the specification indicate that the embodiments described may include specific features, structures or characteristics, but not every embodiment may include the specific features, structures or characteristics. In addition, such expressions do not necessarily refer to the same embodiment. In addition, when specific features, structures or characteristics are described in conjunction with an embodiment, it should be within the knowledge of technicians in the relevant field to implement such features, structures or characteristics in conjunction with other embodiments that are explicitly or not explicitly described.

[0039] In general, terms may be understood, at least in part, by the context in which they are used. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, at least in part depending on the context. Similarly, terms such as "one," "an," or "the" may also be understood to convey singular usage or to convey plural usage, which may depend, at least in part, on the context. In addition, the term "based on" may be understood to not necessarily be intended to convey an exclusive set of factors, but may allow for the presence of other factors that may not be explicitly stated, which again may depend, at least in part, on the context.

[0040] It should be easily understood that the terms “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only being directly on something, but also includes being on something with intervening features or layers therebetween, and such that “on” or “over” includes not only the meaning of being on or over something, but also includes the meaning of being on or over something with no intervening features or layers therebetween (i.e., directly on something).

[0041] In addition, spatially relative terms, such as "below," "below," "beneath," "above," "above," etc., may be used herein for ease of description to describe the relationship of one element or feature to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0042] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned, or it can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, for example, silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0043] Embodiments of a three-dimensional (3D) memory device and a method of forming the same according to the present disclosure will now be described with reference to the accompanying drawings.

[0044] Figure 1 A cross-sectional view of a three-dimensional (3D) memory device 100 according to a first embodiment of the present disclosure is shown.

[0045] like Figure 1 As shown in , a three-dimensional (3D) memory device 100 includes a substrate 101 and a stacked structure 110 formed laterally on the substrate 101. The substrate 101 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material. In some embodiments, the substrate 101 is a thinned substrate (e.g., a semiconductor layer) that is thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. The substrate 101 of the 3D memory device 100 may include two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in a plane defined by an x-direction and a y-direction. In some embodiments, the substrate 101 may be a sacrificial layer and may be removed in subsequent manufacturing steps.

[0046] like Figure 1 As shown in , the stacked structure 110 includes a plurality of alternating conductive layers 102 and dielectric layers 103 stacked vertically. The number of pairs of conductive layers 102 and dielectric layers 103 in the stacked structure 110 determines the number of memory cells in the 3D memory device 100. The conductive layers 102 and dielectric layers 103 in the stacked structure 110 may alternate in the vertical direction. In other words, except for the layers at the top or bottom of the stacked structure 110, each conductive layer 102 may be adjacent to two dielectric layers 103 on both sides, and each dielectric layer 103 may be adjacent to two conductive layers 102 on both sides. The conductive layers 102 and the dielectric layers 103 may form a plurality of stepped structures (not shown). The conductive layer 102 may include a conductive material, which may include, for example, but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), tantalum (Ta), polysilicon, doped silicon, silicide, or any combination thereof. Each conductive layer 102 may include a gate electrode (gate line) and a gate dielectric layer surrounded by an adhesive layer. The gate electrode of the conductive layer 102 may extend laterally as a word line, which ends at one or more step structures in the step region (not shown). Each dielectric layer 103 may include a dielectric material, which may include, for example, but is not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The dielectric layer 103 may act as an insulating layer, thereby preventing the conductive layers and / or conductive lines from contacting each other, which may otherwise cause a short circuit or failure in the semiconductor device.

[0047] The channel structure 120 is formed in the stacked structure 110. The channel structure 120 includes a storage film 121, which in turn includes a tunneling layer 125, a storage layer 124 (also referred to as a "charge trapping layer"), and a blocking layer 123. The channel structure 120 also includes a semiconductor channel 122 formed by filling (one or more) semiconductor materials in the channel structure 120. In some embodiments, the channel structure 120 has a cylindrical shape, and the semiconductor channel 122 and the tunneling layer 125, the storage layer 124, and the blocking layer 123 of the storage film 121 are arranged radially in this order from the center of the cylinder toward the outer surface. A semiconductor plug (not shown) may be provided in the lower portion of the channel structure 120, which contacts the semiconductor channel 122 and acts as a channel controlled by the source select gate of the channel structure 120.

[0048] like Figure 1As shown in , a three-dimensional (3D) memory device 100 includes a top select gate (TSG) layer 106 located on a stack structure 110 and an etch stop layer 107 located on the top select gate (TSG) layer 106. In some embodiments, the top select gate layer 106 may include, for example, at least one of tungsten, cobalt, copper, aluminum, single crystal silicon, polycrystalline silicon, doped silicon, and silicide, and the etch stop layer 107 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric material such as aluminum oxide or hafnium oxide. In some embodiments, an insulating layer 105 may be further included between the stack structure 110 and the top select gate layer 106. In some embodiments, the insulating layer 105 may include the same material as the dielectric layer 103, such as silicon oxide.

[0049] like Figure 1 As shown in FIG. 1 , a three-dimensional (3D) memory device 100 includes a second channel structure 112 extending through an etch stop layer 107 and a top select gate layer 106, and the second channel structure 112 is located above and coupled to a channel structure 120. Figure 1 As shown in FIG. 1 , the second channel structure 112 includes a barrier material layer 109, and the barrier material layer 109 covers a portion of the sidewall of the top selection gate layer 106. In some embodiments, the barrier material layer 109 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric material such as aluminum oxide or hafnium oxide.

[0050] like Figure 1 As shown in FIG. 1 , a three-dimensional (3D) memory device 100 includes a dielectric layer 113 located above an etch stop layer 107. In some embodiments, the dielectric layer 113 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide. Figure 1 As shown in FIG. 1 , the three-dimensional (3D) memory device 100 further includes a contact plug 114 in the dielectric layer 113 and above the second channel structure 112. In some embodiments, the contact plug 114 may include, for example, but is not limited to, W, Co, Cu, Al, silicide, or any combination thereof.

[0051] like Figure 1 As shown in FIG. 1 , the contact plug 114 includes an extension portion 114 - 1 extending into the second channel structure 112. In this case, a short circuit may be formed between the extension portion 114 - 1 and the top selection gate layer 106, as shown in FIG. Figure 1 As shown in the circle.

[0052] Figure 2 FIG. 2 shows a cross-sectional view of a three-dimensional (3D) memory device 200 according to a second embodiment of the present disclosure. Figure 1The three-dimensional (3D) memory device 100 shown is substantially the same except that the second channel structure 212 is “expanded” above the top selection gate layer 206 and is formed with a barrier material layer that completely covers the sidewalls of the top selection gate layer 206 and covers a portion of the sidewalls of the etch stop layer 207. That is, Figure 2 As shown in FIG. 1 , the barrier material layer includes a continuous first barrier layer portion 209 - 1 and a second barrier layer portion 209 - 2 , the first barrier layer portion 209 - 1 completely covers the sidewall of the top selection gate layer 206 , and the second barrier layer portion 209 - 2 covers a portion of the sidewall of the etch stop layer 207 .

[0053] like Figure 2 As shown in , the second channel structure 212 includes a semiconductor channel, the semiconductor channel includes a first portion 212-1 and a second portion 212-2, the first barrier layer portion 209-1 and the second barrier layer portion 209-2 surround the first portion 212-1, and the second portion 212-2 contacts the sidewall of the etch stop layer 207. Figure 2 As shown in , the size of the second portion 212-2 close to the contact plug 214 is larger than the size of the second portion 212-2 away from the contact plug 214. Figure 2 As shown in FIG. 2 , the second portion 212 - 2 has a cone shape.

[0054] according to Figure 2 In the three-dimensional memory device 200 shown, the contact plug 214 is completely formed above the second channel structure 212 by “expanding” the second channel structure 212. In addition, the continuous first barrier layer portion 209-1 and the second barrier layer portion 209-2 ensure that the contact plug 214 does not contact the top selection gate layer 206, thereby preventing a short circuit from being formed between the contact plug 214 and the top selection gate 206 layer of the 3D memory device 200.

[0055] Figure 3 FIG. 4 is a cross-sectional view of a three-dimensional (3D) memory device 300 according to a third embodiment of the present disclosure. Figure 1 The three-dimensional (3D) memory device 100 shown is substantially the same except that the second channel structure 312 includes a continuous first barrier layer portion 309-1 and a second barrier layer portion 309-2, wherein the first barrier layer portion 309-1 completely covers the sidewalls of the top select gate layer 306 and the second barrier layer portion 309-2 covers a portion of the sidewalls of the etch stop layer 307.

[0056] like Figure 3As shown in , the second channel structure 312 includes a semiconductor channel, the semiconductor channel includes a first portion 312-1 and a second portion 312-2, the first barrier layer portion 309-1 and the second barrier layer portion 309-2 surround the first portion 312-1, and the second portion 312-2 contacts the sidewall of the etch stop layer 307. Figure 3 As shown in , the size of the first portion 312-1 is smaller than the size of the second portion 312-2. Figure 3 As shown in FIG. 3 , the second portion 312 - 2 has a cylindrical shape.

[0057] according to Figure 3 In the three-dimensional memory device 300 shown in FIG. 1 , the continuous first barrier layer portion 309 - 1 and the second barrier layer portion 309 - 2 ensure that the contact plug 314 does not contact the top selection gate layer 306 , thereby preventing a short circuit from being formed between the contact plug 314 and the top selection gate layer 306 of the 3D memory device 300 .

[0058] Figure 4(a)-4(o) A cross-sectional view of a 3D memory device at different stages of an exemplary manufacturing method 400 according to a first embodiment of the present disclosure is shown.

[0059] As shown in FIG. 4( a), in this operation, a substrate 401 is provided and a stacked structure 410 is formed on the substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material. In some embodiments, the substrate 401 is a thinned substrate (e.g., a semiconductor layer) that is thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. The substrate 401 may include two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in a plane defined by an x-direction and a y-direction (both perpendicular to the z-direction). In some embodiments, a stop layer (not shown) may be formed on the top surface of the substrate 401 using one or more thin film deposition processes, such as, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The stop layer acts as an etch stop.The stop layer may include any dielectric material including, for example, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0060] A stack structure 410 may be formed on a substrate 401, as shown in FIG4(a). A stack structure 410 including a plurality of alternating conductive layers 402 and dielectric layers 403 may be formed on a substrate 401. According to some embodiments, the stack structure 410 may include a plurality of alternating conductive layers 402 and dielectric layers 403. In other words, except for the top layer and the bottom layer of the stack structure 410, each of the other conductive layers 402 may be sandwiched by two adjacent dielectric layers 403, and each of the other dielectric layers 403 may be sandwiched by two adjacent conductive layers 402. In some embodiments, an initial stack structure including a plurality of alternating sacrificial layers and dielectric layers 403 may also be formed first, and the sacrificial layers may be replaced by conductive layers 402 next. In some embodiments, the dielectric layer 403 may include silicon oxide, and the conductive layer 402 may include, for example, at least one of tungsten, cobalt, copper, aluminum, single crystal silicon, polycrystalline silicon, doped silicon, and silicide. The stack structure 410 may be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof.

[0061] It should be noted that FIG4(a) only shows four alternately stacked conductive layers 402 and four dielectric layers 403 for illustrative purposes. However, those skilled in the art should understand and appreciate that the present disclosure is not limited to any specific number of arrangements of the conductive layers 402 and the dielectric layers 403.

[0062] Next, as shown in FIG4(b), a plurality of channel holes 404 are formed that penetrate the stacked structure 410 and extend into the semiconductor substrate 401. For simplicity, FIG4(b) schematically shows only one channel hole 404. In some embodiments, the channel hole 404 that penetrates the stacked structure 410 and extends into the semiconductor substrate 401 may be formed, for example, by a dry / wet etching process. Exemplarily, the channel hole 404 may have a cylindrical or columnar shape along the extension direction.

[0063] Next, as shown in FIG. 4( c ), after forming the channel hole 404, a channel structure 420 may be formed in the channel hole 404. The channel structure 420 includes a storage film 421 and a semiconductor channel 422. In some embodiments, the storage film 421 includes a blocking layer 423, a charge trapping layer 424, and a tunneling layer 425 sequentially disposed on the sidewalls of the channel hole 404. In some embodiments, the material for the blocking layer 423 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide; the material for the charge trapping layer 424 may include polysilicon, silicon nitride, silicon oxynitride, etc.; the material for the tunneling layer 425 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, etc. Exemplarily, the materials of the blocking layer 423, the charge trapping layer 424, the tunneling layer 425, and the semiconductor channel 422 may be silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively.

[0064] For example, the storage film 421 and the semiconductor channel 422 may be formed in the channel hole 404 by one or more thin film deposition processes such as CVD, PVD, ALD or any combination thereof. In some embodiments, after the storage film 421 and the semiconductor channel 422 are formed, a dielectric material may be filled in the remaining space of the channel hole 404 or an air gap may be formed, and a channel plug may be formed at the top of the channel hole 404 away from the semiconductor substrate 401.

[0065] Next, as shown in FIG. 4( d ), an insulating layer 405 is formed on the stacked structure 410 and the channel structure 420. In some embodiments, the insulating layer 405 may include the same material as the dielectric layer 403, such as silicon oxide. In some embodiments, the insulating layer 405 may be formed by one or more thin film deposition processes, which may include, for example, but not limited to, CVD, PVD, ALD, or any combination thereof. In some embodiments, after forming the insulating layer 405, a CMP process may be performed.

[0066] Next, as shown in FIG. 4( e), a top select gate (TSG) layer 406 is formed on the insulating layer 405. In some embodiments, the top select gate (TSG) layer 406 may include, for example, at least one of tungsten, cobalt, copper, aluminum, single crystal silicon, polycrystalline silicon, doped silicon, and silicide. In some embodiments, the top select gate (TSG) layer 406 may be formed by one or more thin film deposition processes, which may include, for example, but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments, after forming the top select gate (TSG) layer 406, a CMP process may be performed.

[0067] Next, as shown in FIG. 4( f), an etch stop layer 407 is formed on the top select gate (TSG) layer 406. In some embodiments, the etch stop layer 407 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide. In some embodiments, the etch stop layer 407 may be formed by one or more thin film deposition processes, which may include, for example, but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments, after the etch stop layer 407 is formed, a CMP process may be performed.

[0068] Next, as shown in FIG4(g), a channel hole 408 is formed that penetrates the etch stop layer 407, the top select gate (TSG) layer 406, and the insulating layer 405 and extends to the channel structure 420. In some embodiments, the channel hole 408 that penetrates the etch stop layer 407, the top select gate (TSG) layer 406, and the insulating layer 405 and extends to the channel structure 420 can be formed, for example, by a dry / wet etching process. Exemplarily, the channel hole 408 can have a cylindrical or columnar shape along the extension direction.

[0069] Next, as shown in FIG4(h), a barrier material layer 409 is formed on the sidewalls of the channel hole 408 and the etch stop layer 407. In some embodiments, the barrier material layer 409 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide. In some embodiments, the barrier material layer 409 may be formed by one or more thin film deposition processes, which may include, for example, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0070] Next, as shown in FIG4(i), a liner 411 is formed over the barrier material layer 409. In some embodiments, the liner 411 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide. In some embodiments, the liner 411 may be formed by one or more thin film deposition processes, which may include, for example, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0071] Next, as shown in FIG4(j), the portion of the liner 411 located in the channel hole 408 is removed. That is, only the portion of the liner 411 located above the etch stop layer 407 is retained. In some embodiments, the portion of the liner 411 located in the channel hole 408 may be removed, for example, by a dry / wet etching process.

[0072] 4(k), the barrier material layer 409 and the liner layer 411 above the etch stop layer 407 are removed. In some embodiments, the barrier material layer 409 and the liner layer 411 above the etch stop layer 407 may be removed, for example, by a dry / wet etching process.

[0073] Next, as shown in FIG. 4( l), the channel hole 408 is filled with a semiconductor material to form a second channel structure 412. In one embodiment, the semiconductor material may, for example, include polysilicon. In some embodiments, the channel hole 408 may be filled, for example, by one or more thin film deposition processes, which may, for example, include but are not limited to CVD, PVD, ALD, or any combination thereof. In one embodiment, after forming the second channel structure 412, CMP may be performed on the etch stop layer 407 and the second channel structure 412.

[0074] Next, as shown in FIG4(m), a dielectric layer 413 is formed over the etch stop layer 407 and the second channel structure 412. In some embodiments, the dielectric layer 413 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide. In some embodiments, the dielectric layer 413 may be formed by one or more thin film deposition processes, which may include, for example, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0075] Next, as shown in FIG. 4( n), a contact plug 414 is formed over the second channel structure 412. In some embodiments, to form the contact plug 414, an opening (not shown) is first formed through the dielectric layer 413 and exposing the second channel structure 412; and then the opening is filled with a conductive material to form the contact plug 414. The contact plug 414 may be formed by filling the opening with a conductive material using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. The conductive material may include, but is not limited to, W, Co, Cu, Al, silicide, or any combination thereof.

[0076] In order to form the contact plug 414, it is necessary to first form an opening through the dielectric layer 413, for example, by a dry / wet etching process. In the process of etching to form the opening, part of the blocking material layer 409 covering the sidewalls of the etching stop layer 407 and the top select gate (TSG) layer 406 may be etched away at the same time. When the opening is subsequently filled with a conductive material, the contact plug 414 may form an extension 414-1 extending into the second channel structure 412, as shown in FIG4(o). In this case, a short circuit may be formed between the extension 414-1 and the top select gate (TSG) layer 406, as shown by the circle in FIG4(o), which is not allowed. Therefore, a method for manufacturing a 3D memory device is needed, which can avoid the formation of a short circuit between the contact plug and the top select gate (TSG) layer of the 3D memory device.

[0077] Figure 5(a)-5(g) A cross-sectional view of a 3D memory device at different stages of an exemplary manufacturing method 500 according to a second embodiment of the present disclosure is shown.

[0078] In the second embodiment of the present disclosure, the first embodiment is performed Figure 4(a)-4(i) 5( a) is obtained by performing the steps shown in FIG. 5( a). As shown in FIG. 5( a), a barrier material layer 509 covering the sidewalls of the top selection gate layer 506 and the etching stop layer 507 and the top of the etching stop layer 507 is formed through the channel hole 508, and a liner 511 is formed on the barrier material layer 509.

[0079] Next, as shown in FIG5(b), faceted dry etching is performed on the barrier material layer 509 and the liner layer 511, so that the cross section of the channel hole 508 above the top selection gate layer 506 becomes larger and a portion of the barrier material layer 509 covering a portion of the sidewall of the etching stop layer 507 is retained. By performing the faceted dry etching, the upper portion of the channel hole 508 is "expanded". In one embodiment, by controlling the gas flow rate and directionality of the plasma gas, the etching speed of the channel hole 508 can be made faster as it goes up, thereby forming a cone shape as shown in FIG5(b).

[0080] 5(c), the remaining liner 511 is removed. The removal of the remaining liner 511 exposes the barrier material layer 509 covering the sidewalls of the top select gate layer 506. In some embodiments, the remaining liner 511 may be removed, for example, by a dry / wet etching process.

[0081] Next, as shown in FIG. 5( d ), the channel hole 508 after “expansion” is filled with a semiconductor material to form a second channel structure 512. In one embodiment, the semiconductor material may include, for example, polysilicon. In some embodiments, the channel hole 508 may be filled, for example, by one or more thin film deposition processes, which may include, for example, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0082] Next, as shown in FIG. 5( e ), after forming the second channel structure 512 , CMP is performed to remove the remaining barrier material layer 509 above the etch stop layer 507 .

[0083] Next, as shown in FIG5(f), a dielectric layer 513 is formed over the etch stop layer 507 and the second channel structure 512. In some embodiments, the dielectric layer 513 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide. In some embodiments, the dielectric layer 513 may be formed by one or more thin film deposition processes, which may include, for example, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0084] Next, as shown in FIG. 5( g), a contact plug 514 is formed over the second channel structure 512. In some embodiments, to form the contact plug 514, an opening (not shown) is first formed through the dielectric layer 513 and exposing the second channel structure 512; and then the opening is filled with a conductive material to form the contact plug 514. The contact plug 514 may be formed by filling the opening with a conductive material using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. The conductive material may include, but is not limited to, W, Co, Cu, Al, silicide, or any combination thereof.

[0085] As shown in FIG. 5( g ), the blocking material layer 509 includes a continuous first blocking layer portion 509 - 1 and a second blocking layer portion 509 - 2 , the first blocking layer portion 509 - 1 completely covering the sidewall of the top selection gate layer 506 , and the second blocking layer portion 509 - 2 covering a portion of the sidewall of the etch stop layer 507 .

[0086] As shown in FIG5(g), the second channel structure 512 includes a semiconductor channel, the semiconductor channel includes a first portion 512-1 and a second portion 512-2, the first barrier layer portion 509-1 and the second barrier layer portion 509-2 surround the first portion 512-1, and the second portion 512-2 is in contact with the sidewall of the etch stop layer 507. As shown in FIG5(g), the size of the second portion 512-2 close to the contact plug 514 is larger than the size of the second portion 512-2 away from the contact plug 514. As shown in FIG5(g), the second portion 512-2 has a cone shape.

[0087] As shown in FIG5(g), the contact plug 514 is completely formed above the second channel structure 512 by “expanding” the channel hole 508. In addition, the continuous first barrier layer portion 509-1 and the second barrier layer portion 509-2 ensure that the contact plug 514 does not contact the top selection gate layer 506, thereby preventing a short circuit from being formed between the contact plug and the top selection gate (TSG) layer of the 3D memory device.

[0088] Figure 6(a)-6(g) A cross-sectional view of a 3D memory device at different stages of an exemplary manufacturing method 600 according to a third embodiment of the present disclosure is shown.

[0089] In the third embodiment of the present disclosure, the first embodiment is performed Figure 4(a)-4(i) 6( a) is obtained by performing the steps shown in FIG. 6( a). As shown in FIG. 6( a), a barrier material layer 609 covering the sidewalls of the top selection gate layer 606 and the etch stop layer 607 and the top of the etch stop layer 607 is formed through the channel hole 608, and a liner 611 is formed on the barrier material layer 609.

[0090] 6(b), the liner layer 611 on the top of the etch stop layer 607 is removed. In some embodiments, the liner layer 611 on the top of the etch stop layer 607 may be removed, for example, by a dry / wet etching process.

[0091] Next, as shown in FIG6(c), the barrier material layer 609 located on the top of the etch stop layer 607 and covering a portion of the sidewall of the etch stop layer 607 is removed to form a recess 616. As shown in FIG6(c), a portion of the sidewall of the etch stop layer 607 and the sidewall of the top select gate layer 606 are still covered by the barrier material layer 609. In some embodiments, the barrier material layer 609 located on the top of the etch stop layer 607 and covering a portion of the sidewall of the etch stop layer 607 can be removed, for example, by a dry / wet etching process.

[0092] 6( d ), the remaining liner 611 in the channel hole 608 is removed to expose the blocking material layer 609 covering a portion of the sidewall of the etch stop layer 607 and the sidewall of the top select gate layer 606. In some embodiments, the remaining liner 611 in the channel hole 608 may be removed, for example, by a dry / wet etching process.

[0093] Next, as shown in FIG6( e), the channel hole 608 is filled with a semiconductor material to form a second channel structure 612. In one embodiment, the semiconductor material may include, for example, polysilicon. In some embodiments, the channel hole 608 may be filled, for example, by one or more thin film deposition processes, which may include, for example, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0094] Next, as shown in FIG6(f), a dielectric layer 613 is formed over the etch stop layer 607 and the second channel structure 612. In some embodiments, the dielectric layer 613 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide. In some embodiments, the dielectric layer 613 may be formed by one or more thin film deposition processes, which may include, for example, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0095] Next, as shown in FIG6(g), a contact plug 614 is formed over the second channel structure 612. In some embodiments, to form the contact plug 614, an opening (not shown) is first formed through the dielectric layer 613 and exposing the second channel structure 612; and then the opening is filled with a conductive material to form the contact plug 614. The contact plug 614 can be formed by filling the opening with a conductive material using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. The conductive material, for example, may include but is not limited to W, Co, Cu, Al, silicide, or any combination thereof.

[0096] As shown in FIG. 6( g ), the blocking material layer 609 includes a continuous first blocking layer portion 609 - 1 and a second blocking layer portion 609 - 2 , the first blocking layer portion 609 - 1 completely covering the sidewall of the top selection gate layer 606 , and the second blocking layer portion 609 - 2 covering a portion of the sidewall of the etch stop layer 607 .

[0097] As shown in FIG6(g), the second channel structure 612 includes a semiconductor channel, the semiconductor channel includes a first portion 612-1 and a second portion 612-2, the first barrier layer portion 609-1 and the second barrier layer portion 609-2 surround the first portion 612-1, and the second portion 612-2 is in contact with the sidewall of the etch stop layer 607. As shown in FIG6(g), the size of the first portion 612-1 is smaller than the size of the second portion 612-2. As shown in FIG6(g), the second portion 612-2 has a cylindrical shape.

[0098] As shown in FIG. 6( g ), the continuous first barrier layer portion 609 - 1 and the second barrier layer portion 609 - 2 ensure that the contact plug 614 does not contact the top select gate layer 606 , thereby preventing a short circuit from being formed between the contact plug and the top select gate (TSG) layer of the 3D memory device.

[0099] Figure 7(a)-7(g) 1 and 2. A cross-sectional view of a 3D memory device at different stages of an exemplary manufacturing method 700 according to a fourth embodiment of the present disclosure is shown.

[0100] In the fourth embodiment of the present disclosure, the first embodiment is performed Figure 4(a)-4(i) 4( h), except that when performing the step shown in FIG. 4( h), a barrier material layer 709 is formed on the sidewall and bottom of the channel hole 708 and on the top of the etch stop layer 707, and then a liner 711 is formed on the barrier material layer 709 as shown in FIG. 4( i), and the obtained device is shown in FIG. 7( a).

[0101] 7( b), the liner 711 located on the top of the etch stop layer 707 and the bottom of the channel hole 408 is removed. In some embodiments, the liner 711 located on the top of the etch stop layer 707 and the bottom of the channel hole 708 can be removed, for example, by a dry / wet etching process.

[0102] Next, as shown in FIG7(c), while removing the barrier material layer 409 at the bottom of the channel hole 708, the barrier material layer 709 at the top of the etch stop layer 707 and covering a portion of the sidewall of the etch stop layer 707 is removed to form a recess 716. As shown in FIG7(c), a portion of the sidewall of the etch stop layer 707 and the sidewall of the top select gate layer 706 are still covered by the barrier material layer 709. In some embodiments, the barrier material layer 709 can be removed, for example, by a dry / wet etching process.

[0103] 7( d), the remaining liner 711 in the channel hole 708 is removed to expose the blocking material layer 709 covering a portion of the sidewall of the etch stop layer 707 and the sidewall of the top select gate layer 706. In some embodiments, the remaining liner 711 in the channel hole 708 may be removed, for example, by a dry / wet etching process.

[0104] Next, as shown in FIG. 7( e), the channel hole 708 is filled with a semiconductor material to form a second channel structure 712. In one embodiment, the semiconductor material may include, for example, polysilicon. In some embodiments, the channel hole 708 may be filled, for example, by one or more thin film deposition processes, which may include, for example, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0105] Next, as shown in FIG. 7( f), a dielectric layer 713 is formed over the etch stop layer 707 and the second channel structure 712. In some embodiments, the dielectric layer 713 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide. In some embodiments, the dielectric layer 713 may be formed by one or more thin film deposition processes, which may include, for example, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0106] Next, as shown in FIG. 7( g), a contact plug 714 is formed over the second channel structure 712. In some embodiments, to form the contact plug 714, an opening (not shown) is first formed through the dielectric layer 713 and exposing the second channel structure 712; and then the opening is filled with a conductive material to form the contact plug 714. The contact plug 714 may be formed by filling the opening with a conductive material using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. The conductive material may include, but is not limited to, W, Co, Cu, Al, silicide, or any combination thereof.

[0107] As shown in Figure 7(g), the blocking material layer 709 includes a continuous first blocking layer portion 709-1 and a second blocking layer portion 709-2, the first blocking layer portion 709-1 completely covers the sidewall of the top selection gate layer 706, and the second blocking layer portion 709-2 covers a portion of the sidewall of the etch stop layer 707.

[0108] As shown in FIG7(g), the second channel structure 712 includes a semiconductor channel, the semiconductor channel includes a first portion 712-1 and a second portion 712-2, the first barrier layer portion 709-1 and the second barrier layer portion 709-2 surround the first portion 712-1, and the second portion 712-2 is in contact with the sidewall of the etch stop layer 707. As shown in FIG7(g), the size of the first portion 712-1 is smaller than the size of the second portion 712-2. As shown in FIG7(g), the second portion 712-2 has a cylindrical shape.

[0109] As shown in FIG. 7( g ), the continuous first barrier layer portion 709 - 1 and the second barrier layer portion 709 - 2 ensure that the contact plug 714 does not contact the top select gate layer 706 , thereby preventing a short circuit from being formed between the contact plug and the top select gate (TSG) layer of the 3D memory device.

[0110] Figure 8 800 for forming a 3D memory device according to an embodiment of the present disclosure. It should be understood that the operations shown in the method 800 are not exclusive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of the operations may be performed simultaneously or in different order. Figure 8 Executed in the order shown in .

[0111] like Figure 8 As shown in , the manufacturing method 800 according to the embodiment of the present disclosure includes steps S810 - S880 .

[0112] In S810, a stack structure including a plurality of alternating dielectric layers and conductive layers is formed. As shown in FIG4(a), a stack structure 410 including a plurality of alternating conductive layers 402 and dielectric layers 403 is formed.

[0113] In S820, a first channel structure extending through the stacked structure is formed. Figure 4(b)-4(c) As shown in FIG. 4 , a channel structure 420 is formed extending through the stack structure 410 .

[0114] In S830 , a top select gate (TSG) layer is formed above the stack structure. As shown in FIG. 4( e ), a top select gate (TSG) layer 406 is formed above the stack structure 410 .

[0115] In S840 , an etch stop layer is formed on the top select gate layer. As shown in FIG. 4( f ), an etch stop layer 407 is formed on the top select gate layer 406 .

[0116] In S850, a second channel hole extending through the etch stop layer and the top select gate layer is formed on the first channel structure. As shown in FIG4(g), a channel hole 408 extending through the etch stop layer 407 and the top select gate layer 406 is formed on the channel structure 420.

[0117] In S860, a first barrier layer portion and a second barrier layer portion are formed continuously in the second channel hole, wherein the first barrier layer portion completely covers the sidewall of the top selection gate layer, and the second barrier layer portion covers a portion of the sidewall of the etching stop layer. Figure 5(a)-5(c) As shown in , a continuous first barrier layer portion 509-1 and a second barrier layer portion 509-2 are formed in the channel hole 508, the first barrier layer portion 509-1 completely covers the sidewall of the top selection gate layer 506, and the second barrier layer portion 509-2 covers a portion of the sidewall of the etching stop layer 507; Figure 6(a)-6(d) As shown in , a continuous first barrier layer portion 609-1 and a second barrier layer portion 609-2 are formed in the channel hole 608, the first barrier layer portion 609-1 completely covers the sidewall of the top selection gate layer 606, and the second barrier layer portion 609-2 covers a portion of the sidewall of the etch stop layer 607; Figure 7(a)-7(d) As shown in FIG. 7 , a continuous first barrier layer portion 709 - 1 and a second barrier layer portion 709 - 2 are formed in the channel hole 708 , the first barrier layer portion 709 - 1 completely covers the sidewall of the top selection gate layer 706 , and the second barrier layer portion 709 - 2 covers a portion of the sidewall of the etch stop layer 707 .

[0118] In S870, the remaining second channel holes are filled with semiconductor material to form a second channel structure. As shown in FIG. 5( d ), the remaining channel holes 508 are filled with semiconductor material to form a channel structure 512; as shown in FIG. 6( e ), the remaining channel holes 608 are filled with semiconductor material to form a channel structure 612; and as shown in FIG. 7( e ), the remaining channel holes 708 are filled with semiconductor material to form a channel structure 712.

[0119] In S880, a contact plug is formed above the second channel structure. Figure 5(f)-5(g) As shown in , a contact plug 514 is formed above the channel structure 512; Figure 6(f)-6(g) As shown in , a contact plug 614 is formed above the channel structure 612; Figure 7(f)-7(g) As shown in FIG. 7 , a contact plug 714 is formed over the channel structure 712 .

[0120] Fig. 9900 is a block diagram of an exemplary system having a 3D storage device according to an embodiment of the present disclosure. The system 900 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Fig. 9 As shown in , system 900 may include a host 908 and a storage system 902, the storage system 902 having one or more 3D storage devices 904 and a memory controller 906. The host 908 may be a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host 908 may be configured to send or receive data to or from the storage device 904. In order to send or receive data to or from the storage device 904, the host 908 may also send instructions to the storage system 902 in addition to the data.

[0121] The 3D memory device 904 may be any 3D memory device / semiconductor structure disclosed herein. In some embodiments, each 3D memory device 904 may include a NAND flash memory. Consistent with the scope of the present disclosure, the continuous first barrier layer portion and the second barrier layer portion ensure that the contact plug does not contact the top select gate layer, thereby being able to avoid forming a short circuit between the contact plug and the top select gate (TSG) layer of the 3D memory device.

[0122] According to some embodiments, the memory controller 906 is coupled to the 3D memory device 904 and the host 908, and is configured to control the 3D memory device 904. The memory controller 906 may manage data stored in the 3D memory device 904 and communicate with the host 908. In some embodiments, the memory controller 906 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 906 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc. and an enterprise storage array. The memory controller 906 may be configured to control operations of the 3D memory device 904, such as read, erase, and program operations. The memory controller 906 may also be configured to manage various functions related to data stored or to be stored in the 3D storage device 904, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the memory controller 906 is also configured to process error correction code (ECC) related to data read from or written to the 3D storage device 904. Any other appropriate functions may also be performed by the memory controller 906, such as formatting the 3D storage device 904. The memory controller 906 may communicate with an external device (e.g., a host 908) according to a specific communication protocol. For example, the memory controller 906 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0123] The above description of specific embodiments will fully demonstrate the general nature of the present disclosure, so that others can easily modify and / or adjust various applications of such specific embodiments by applying knowledge within the technical scope of the art without excessive experimentation and without departing from the general concept of the present disclosure. Therefore, according to the disclosure and guidance given herein, such adjustments and modifications are intended to be within the meaning and scope of the equivalents of the embodiments disclosed herein. It should be understood that the wording or terminology herein is for illustrative purposes, not for limitation, so the terms or wording of this specification will be interpreted by the technician in accordance with the disclosure and guidance.

[0124] The Summary and Abstract sections may set forth one or more, but not necessarily all exemplary embodiments of the present disclosure contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0125] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A three-dimensional (3D) memory device, comprising: A stacked structure comprising a plurality of alternating dielectric layers and conductive layers; a first channel structure extending through the stack structure; a top select gate (TSG) layer located above the stacked structure; an etch stop layer located above the top select gate layer; a second channel structure extending through the etch stop layer and the top select gate layer, the second channel structure being overlying and coupled to the first channel structure; as well as a contact plug located above the second channel structure, The second channel structure includes a continuous first barrier layer portion and a second barrier layer portion, wherein the first barrier layer portion completely covers the sidewall of the top selection gate layer, and the second barrier layer portion covers a portion of the sidewall of the etching stop layer.

2. The three-dimensional memory device according to claim 1, wherein: The first channel structure includes, from inside to outside, a first semiconductor channel, a tunneling layer, a storage layer and a first blocking layer.

3. The three-dimensional memory device according to claim 1, wherein: The second channel structure further includes a second semiconductor channel including a first portion and a second portion, the first barrier layer portion and the second barrier layer portion surround the first portion, and the second portion contacts a sidewall of the etch stop layer.

4. The three-dimensional memory device according to claim 3, wherein: A dimension of a side of the second portion close to the contact plug is greater than a dimension of a side of the second portion far from the contact plug.

5. The three-dimensional memory device according to claim 4, wherein: The second portion has a cone shape.

6. The three-dimensional memory device according to claim 3, wherein: The second portion has a cylindrical shape.

7. The three-dimensional memory device according to claim 3, wherein: The first portion has a smaller size than the second portion.

8. The three-dimensional memory device according to claim 3, wherein: The first portion has a cylindrical shape.

9. A method for forming a three-dimensional (3D) memory device, comprising: forming a stack structure including a plurality of alternating dielectric layers and conductive layers; forming a first channel structure extending through the stacked structure; forming a top select gate (TSG) layer over the stack structure; forming an etch stop layer over the top select gate layer; forming a second channel hole extending through the etch stop layer and the top select gate layer over the first channel structure; forming a continuous first barrier layer portion and a second barrier layer portion in the second channel hole, the first barrier layer portion completely covering a sidewall of the top selection gate layer, and the second barrier layer portion covering a portion of the sidewall of the etch stop layer; Filling the remaining second channel holes with semiconductor material to form a second channel structure; as well as A contact plug is formed over the second channel structure.

10. The method according to claim 9, wherein: Forming the first channel structure includes: forming a first channel hole extending through the dielectric layer and the conductive layer; and A first barrier layer, a storage layer, a tunneling layer and a first semiconductor channel are sequentially formed in the first channel hole.

11. The method according to claim 9, wherein: Forming the first barrier layer portion and the second barrier layer portion continuously comprises: forming a barrier material layer covering sidewalls of the top selection gate layer and the etch stop layer and a top of the etch stop layer through the second channel hole; forming a liner on the barrier material layer; performing facet dry etching on the barrier material layer and the liner layer so that a cross section of the second channel hole above the top selection gate layer becomes larger and the barrier material layer covering a portion of the sidewall of the etch stop layer is retained to form the second barrier layer portion; and The remaining liner layer is removed to expose the barrier material layer covering the sidewall of the top selection gate layer to form the first barrier layer portion.

12. The method according to claim 9, wherein: Forming the first barrier layer portion and the second barrier layer portion continuously comprises: forming a barrier material layer covering sidewalls of the top selection gate layer and the etch stop layer and a top of the etch stop layer through the second channel hole; forming a liner on the barrier material layer; removing the liner layer located on top of the etch stop layer; removing the barrier material layer located on the top of the etch stop layer and covering a portion of the sidewall of the etch stop layer to form a second barrier layer portion covering a remaining portion of the sidewall of the etch stop layer; and The liner layer remaining in the second channel hole is removed to expose the barrier material layer covering the sidewall of the top selection gate layer to form the first barrier layer portion.

13. The method according to claim 9, wherein: Forming the first barrier layer portion and the second barrier layer portion continuously comprises: forming a barrier material layer on the sidewalls and the bottom of the second channel hole and on the top of the etch stop layer; forming a liner on the barrier material layer; removing the liner layer located on the top of the etch stop layer and the bottom of the second channel hole; While removing the barrier material layer at the bottom of the second channel hole, remove the barrier material layer at the top of the etch stop layer and covering a portion of the sidewall of the etch stop layer to form a second barrier layer portion covering the remaining portion of the sidewall of the etch stop layer; and The liner layer remaining in the second channel hole is removed to expose the barrier material layer covering the sidewall of the top selection gate layer to form the first barrier layer portion.

14. The method according to claim 9, wherein: Forming the contact plug includes: forming a second dielectric layer covering the etch stop layer and the second channel structure; forming an opening penetrating the second dielectric layer, the opening exposing the second channel structure; and The contact plug is formed by filling the opening with a conductive material.

15. The method according to claim 9, wherein: Forming the second channel structure includes forming a second semiconductor channel, the second semiconductor channel including a first portion and a second portion, the first barrier layer portion and the second barrier layer portion surrounding the first portion, and the second portion contacting a sidewall of the etch stop layer.

16. The method according to claim 15, wherein: A dimension of a side of the second portion close to the contact plug is greater than a dimension of a side of the second portion far from the contact plug.

17. The method according to claim 16, wherein: The second portion has a cone shape.

18. The method according to claim 15, wherein: The second portion has a cylindrical shape.

19. The method according to claim 15, wherein: The first portion has a smaller size than the second portion.

20. The method according to claim 15, wherein: The first portion has a cylindrical shape.

21. A storage system comprising: The memory device according to any one of claims 1 to 8, wherein the memory device is configured to store data; as well as A memory controller is coupled to the memory device and is configured to control the memory device.

22. The memory system of claim 21, further comprising a host coupled to the memory controller and configured to send or receive the data.

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