Memory device

Abstract

The invention provides a memory device. The memory device comprises a plurality of first peripheral circuits, a laminated memory cell array and a first addressing circuit, the first peripheral circuit is arranged on a first chip, wherein the first chip is provided with a plurality of first welding pads. The laminated memory cell array is arranged on the second chip, wherein the second chip is provided with a plurality of second welding pads. The second pads are coupled to the stacked memory cell array and are respectively coupled to the corresponding first pads. The first addressing circuit is disposed on the second chip, coupled to the stacked memory cell array, and disposed below the stacked memory cell array.

Description

Technical Field

[0001] The present disclosure relates to a memory device, and more particularly to a memory device constructed by stacking multiple chips. Background Art

[0002] As the storage capacity requirements of memory devices increase, the number of stacking levels of memory cell arrays, corresponding addressing circuits, and transistors of peripheral circuits in stacked memory devices also increases rapidly. As a result, the prior art practice of setting up a complete memory device on a single chip will make the chip size insufficient to set up too many transistors. A process called CMOS-under-array (CuA) is used to make peripheral circuits of stacked memories. It can save chip area. On the other hand, the under-array process may involve relatively high temperatures and consume a large amount of thermal budget, thus affecting the underlying circuits.

[0003] On the other hand, as the number of stacking layers of the memory cell array increases, the access rate of the memory device must also increase. However, some advanced process materials and structures cannot be used in CMOS processes under arrays that require relatively high process temperatures. This is because these advanced process materials and structures may be damaged by the thermal budget generated during the formation of the array. Therefore, in the prior art, the access rate of the memory device cannot be effectively improved. Summary of the invention

[0004] The present disclosure provides a variety of memory devices that can effectively improve access efficiency.

[0005] The memory device disclosed in the present invention includes a plurality of first peripheral circuits, a stacked memory cell array, and a first addressing circuit. The first peripheral circuit is arranged on a first chip, wherein the first chip has a plurality of first pads. The stacked memory cell array is arranged on a second chip, wherein a plurality of second pads are formed on the second chip. The second pads are coupled to the stacked memory cell array and are respectively coupled to the corresponding first pads. The first addressing circuit is arranged on the second chip, coupled to the stacked memory cell array and arranged below the stacked memory cell array.

[0006] Another memory device disclosed in the present invention includes a first chip and a second chip. The first chip includes a plurality of first peripheral circuits and a plurality of first pads, and the first pads are formed on the surface of the first chip. The second chip includes a stacked memory cell array and a first addressing circuit. The first addressing circuit is coupled to the stacked memory cell array and is arranged below the stacked memory cell array. The second pads are formed on the surface of the second chip and are respectively coupled to the corresponding first pads. The process temperature of the first chip is different from the thermal budget of the second chip.

[0007] Based on the above, the present disclosure arranges the peripheral circuit of the memory device on the first chip and arranges the stacked memory cell array on the second chip. The second chip can be applied to the CMOS (complementary metal oxide semiconductor) process (CMOS-under-array, CuA) under the array, while the first chip can be applied to the process with a relatively low thermal budget. In this way, the electrical characteristics of the peripheral circuit on the first chip can be effectively improved, and the access performance of the memory device can be improved. The problem of the chip being exposed to the process under the array may generate a temperature that may damage the chip. In this embodiment, the use of separate wafers can achieve the best result, which can prevent the chip from undergoing the process under the array and solve the above-mentioned problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A cross-sectional view schematically shows the structure of a memory device according to an embodiment of the present disclosure;

[0009] Figure 2A as well as Figure 2B Schematic cross-sectional views schematically illustrate structures of transistors in a first chip and a second chip of a memory device according to an embodiment of the present disclosure;

[0010] Figure 3A and Figure 3B Schematic diagrams respectively schematically show changes in electrical characteristics of transistors in a first chip before and after a silicide structure is added in a memory device according to an embodiment of the present disclosure;

[0011] Figure 4 A cross-sectional view schematically shows the structure of a memory device according to another embodiment of the present disclosure;

[0012] Figure 5 A cross-sectional view schematically shows the structure of a memory device according to another embodiment of the present disclosure;

[0013] Figure 6 A cross-sectional view schematically shows the structure of a memory device according to another embodiment of the present disclosure;

[0014] Figure 7 A block diagram of a memory device according to an embodiment of the present disclosure is schematically shown.

[0015] Description of reference numerals:

[0016] 100, 400, 500, 600, 700: Memory devices

[0017] 110, 410, 510_1, 610_1: First chip

[0018] 111, 122: base

[0019] 112, 123_1, 123_2: Transistor structure

[0020] 113, 124: Shallow Trench Isolation Structure

[0021] 114, 115, 125, 126: Dielectric layer

[0022] 116, 117, 127, 128: Metal layer

[0023] 120, 420_1, 520, 620_1: Second chip

[0024] 121, 421, 521, 710: stacked memory cell array

[0025] 210, 220: Transistor

[0026] 211_1, 211_2, 221_1, 221_2: Conductive structure

[0027] 212_1, 212_2: Silicide structure

[0028] 214, 224: Source structure

[0029] 215, 225: Drain structure

[0030] 311, 312: Line segment

[0031] 321, 322: Straight line

[0032] 420_2, 510_2, 610_2, 620_2: Third chip

[0033] 720: Addressing circuit

[0034] 731, 732: Input and output controller

[0035] 741, 742: row decoder

[0036] 751, 752: Page buffer

[0037] 760: Control pad

[0038] 770: Input and output pads

[0039] BL: Bit Line

[0040] FF:Flip-flop

[0041] GT1, GT2: Gate structure

[0042] Ioff: cut-off current

[0043] Ion: On-current

[0044] L: Latch

[0045] P: Write pulse generator

[0046] PD11~PD23: Solder pad

[0047] SUB1, SUB2, SUB1_1, SUB1_2, SUB2_1, SUB2_2: Base

[0048] TSV1~TSV3: Through Silicon Via

[0049] WE#: write control signal

[0050] WR1~WR3, W4, W5, WA, WB: transmission wires. DETAILED DESCRIPTION

[0051] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0052] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0053] Please refer to Figure 1 , Figure 1A cross-sectional schematic diagram of the structure of a memory device according to an embodiment of the present disclosure is shown. The memory device 100 includes a plurality of peripheral circuits, a stacked memory cell array 121, and an addressing circuit. The peripheral circuits are disposed in a first chip 110, and the stacked memory cell array 121 and the addressing circuit are disposed in a second chip 120. In the present embodiment, the first chip 110 has a substrate 111, a transistor structure 112, a shallow trench isolation structure 113, metal layers 116, 117, and dielectric layers 114 and 115. The transistor structure 112 is formed on the substrate 111 and is used to form a peripheral circuit. The shallow trench isolation structure 113 is formed on the substrate 111 and is formed on both sides of the transistor structure 112. The metal layers 116, 117 and the dielectric layers 114 and 115 are alternately disposed, and the metal layers 116, 117 are used to form a plurality of transmission wires WR1-WR3 for transmitting power or signals in the first chip 110 and the second chip 120. A plurality of pads PD11-PD13 may be formed on the surface of the first chip 110. One end of the transmission wires WR1-WR3 is coupled to the pads PD11-PD13 respectively. The other end of the transmission wires WR1-WR3 may be coupled to a plurality of transistor structures in the first chip 110 (eg, the transmission wire WR1 is coupled to the pad PD12).

[0054] In this embodiment, the dielectric layer 114 may be an interlayer dielectric (ILD), and the dielectric layer 115 may be an interlayer dielectric (IMD). In this embodiment, the interlayer dielectric is a dielectric layer disposed between a silicon layer and a metal layer, and the interlayer dielectric is a dielectric layer disposed between two metal layers.

[0055] On the other hand, the second chip 120 has a stacked memory cell array 121, a substrate 122, and the circuit under the stacked memory cell array 121 includes representative transistor structures 123_1, 123_2, a shallow trench isolation structure 124 as an example, metal layers 127, 128, and dielectric layers 125 and 126. Among them, the transistor structure 123 is formed on the substrate 122 and is part of the addressing circuit in this embodiment. The addressing circuit can be used to generate an addressing signal, such as a word line signal. The shallow trench isolation structure 124 is formed on the substrate 122 and is formed on the side of the transistor structures 123_1, 123_2. The metal layers 127, 128 and the dielectric layers 125 and 126 are arranged in an alternating manner, and the metal layers 127, 128 are used to form a plurality of transmission wires WR4, WR5. The transmission wire WR4 is connected between the transistor structure 123_2 and the stacked memory cell array 121 and can be coupled to the bonding pad PD22. The transmission wire WR5 is connected between the transistor structure 123_1 and the bonding pad PD23.

[0056] In this embodiment, the dielectric layer 126 may be a buried dielectric layer (ILD), and the dielectric layer 125 may be a gold interlayer dielectric layer (IMD).

[0057] A plurality of pads PD21-PD23 are formed on the surface of the second chip 120. The pads PD21-PD23 on the second chip 120 are used to be electrically connected to the pads PD11-PD13 on the surface of the first chip 110, respectively. In the second chip 120, a bit line BL may be formed on the stacked memory cell array 121. The bit line BL may be coupled between the pads PD21 and the memory cells in the stacked memory cell array 121.

[0058] In this embodiment, the first crystal 110 can be electrically connected to the pads PD21~PD23 of the second chip 120 through the pads PD11~PD13 respectively. And the bit line BL of the stacked memory cell array 121 in the second chip 120 can be coupled to the peripheral circuit in the first chip 110, so that the memory device 100 can have a complete architecture. In this embodiment, the peripheral circuit in the first chip 110 includes a plurality of page buffers, a plurality of address decoding circuits, and a plurality of input and output circuits. Specifically, in the memory device known to those skilled in the art, any circuit in the rear section of the bit line other than the memory cell array can be set in the peripheral circuit of the present embodiment without special restrictions. The addressing circuit in the second chip 120 can be the word line decoder and related circuits in the memory device.

[0059] It is worth mentioning that, in the present embodiment, the memory device 100 sets the peripheral circuit of the bit line BL segment in the first chip 110, and sets the stacked memory cell array 121 and the corresponding addressing circuit in the second chip 120. In this way, the first chip 110 is not limited to the CMOS (CuA) process required to be applied to the array, and can use materials with relatively low temperature resistance, which can effectively improve the electrical characteristics of the peripheral circuit in the first chip 110 and improve the working performance of the memory device 100.

[0060] Incidentally, in the embodiment of the present disclosure, the transmission wires WR4 and WR3 can also be used for power transmission.

[0061] In this embodiment, in the first chip 110, the metal layers 116 and 117 used to form the transmission wires WR1 to WR3 may be made of copper, aluminum or other materials with low resistance (less than 3×10 6Ohm-cm) and metals or alloys with low melting points (less than 400 degrees Celsius). The dielectric constants of the dielectric layers 114 and 115 in the first chip 110 may be less than a threshold value. For example, the dielectric layers 114 and 115 may be constructed using materials with a dielectric constant k < 3.0, such as Parylene-N (k = 2.7), B-stage polymer (k = 2.6-2.7) or Parylene-F (k = 2.4–2.5). Since the transistor structure 112 in the first chip 110 does not need to withstand relatively high stress, the dielectric layers 114 and 115 may be implemented using materials with low dielectric constants. In contrast, in the second chip 120, the material of the metal layers 127 and 128 used to form the transmission wires WR4 and WR5 may be tungsten, wherein tungsten has a relatively high melting point greater than 1000 degrees Celsius and a relatively high resistance value (greater than 5×10 6 Ohm-cm).

[0062] In this embodiment, the stacked memory cell array 121 can be any type of stacked memory cell array, such as a three-dimensional AND type, NOR type, or NAND type flash memory cell array, without any particular limitation.

[0063] Please refer to the following Figure 2A as well as Figure 2B , Figure 2A as well as Figure 2B Schematic cross-sectional views of a transistor structure 210 applicable to a first chip and a transistor structure 220 applicable to a second chip of a memory device in an embodiment of the present disclosure are respectively shown. Figure 2A In the embodiment, the transistor 210 disposed in the first chip includes a substrate SUB1, a gate structure GT1, a source structure 214, a drain structure 215, a plurality of silicide structures 212_1, 212_2, and a plurality of conductive structures 211_1, 211_2. The source structure 214 and the drain structure 215 are respectively formed on two sides of the substrate SUB1, and the gate structure GT1 can be formed between the source structure 214 and the drain structure 215. Two silicide structures 212_1, 212_2 can be respectively formed on the substrate SUB, and are respectively formed in the source structure 214 and the drain structure 215. The conductive structures 211_1, 211_2 are respectively formed on the silicide structures 212_1, 212_2, wherein the conductive structure 211_1 and the silicide structure 212_1 can form a contact window, and the conductive structure 211_2 and the silicide structure 212_2 form another contact window.

[0064] Please note that in this embodiment, by respectively disposing silicide structures 212_1 and 212_2 between the conductive structures 211_1, 211_2 and the substrate SUB1, the contact resistance provided by the formed contact window can be effectively reduced and the signal transmission performance can be improved. In this embodiment, the silicide structures 212_1 and 212_2 can be nickel silicide structures or cobalt silicide structures. The material of the conductive structures 211_1 and 211_2 can be tungsten.

[0065] The temperature resistance of the nickel silicide structure is less than 800 degrees Celsius, and the temperature resistance of the cobalt silicide structure is less than 900 degrees Celsius. In other words, the temperature resistance of the silicide structures 212_1 and 212_2 in the embodiment of the present disclosure is lower than that of the conductive structures 211_1 and 211_2.

[0066] Incidentally, a silicide structure 213 may be disposed on the gate structure GT1 of the transistor 210 and electrically connected to the gate structure GT1. In this embodiment, the silicide structures 212_1 and 212_2 may have the same material.

[0067] exist Figure 2B In the embodiment, the transistor 220 disposed in the second chip includes a substrate SUB2, a gate structure GT2, a source structure 224, a drain structure 225, and a plurality of conductive structures 221_1 and 221_2.

[0068] The source structure 224 and the drain structure 225 are formed on two sides of the substrate SUB2, and the gate structure GT2 is formed between the source structure 224 and the drain structure 225. The conductive structures 221_1 and 221_2 are formed on the substrate SUB2 and are formed in the source structure 224 and the drain structure 225, respectively, and form two contact windows respectively.

[0069] and Figure 2A In a different embodiment, the transistor 220 disposed in the second chip may not have a silicide structure, and is therefore suitable for a CMOS under array (CuA) process operated at a relatively high temperature.

[0070] Please refer to FIG. 3A and Figure 3B , Figure 3A and Figure 3BSchematic diagrams showing changes in electrical characteristics of transistors in the first chip before and after the addition of a silicide structure in the memory device of the disclosed embodiment are respectively shown. In FIG3A , the vertical axis is the resistance value of the contact resistance of the contact window in the transistor. The line segment 311 corresponding to one side of the horizontal axis is the case where no silicide structure is added to the contact window, and the line segment 312 corresponding to the other side of the horizontal axis is the case where a silicide structure is added to the contact window. It can be found that in the disclosed embodiment, when a silicide structure is added to the contact window, the contact resistance of the contact window can be effectively reduced, thereby improving the transmission efficiency of signals and / or power.

[0071] exist Figure 3B In the figure, the vertical axis is the off-current Ioff when the transistor is turned off, and the horizontal axis is the on-current Ion when the transistor is turned on. The straight line 321 represents the case where the contact window of the transistor has no silicide structure added, and the straight line 322 represents the case where the contact window of the transistor has a silicide structure added. When the contact window of the transistor has a silicide structure added, the straight line 322 formed by the relationship between the on-current Ion and the off-current Ioff is shifted toward the direction of a relatively high on-current compared to the straight line 321. Therefore, the current transmission efficiency of the transistor is significantly improved.

[0072] Please refer to Figure 4 , Figure 4 A cross-sectional schematic diagram of the structure of a memory device according to another embodiment of the present disclosure is shown. The memory device 400 is formed by a first chip 410, a second chip 420_1, and a third chip 420_2. The first chip 410 has a plurality of transistors to form a peripheral circuit. The implementation details of the first chip 410 have been described in the aforementioned embodiment, and will not be repeated here.

[0073] The second chip 420_1 includes a stacked memory cell array 421. The bit line BL on the stacked memory cell array 421 can be coupled to the pad PD11 formed on the first chip 410 through the pad PD21 formed on the second chip 420_1. On the other hand, the transmission wires W4 and W5 on the second chip 420_1 can be coupled to the pads PD12 and PD13 formed on the first chip 410 through the pads PD22 and PD23 formed on the second chip 420_1, respectively. The second chip 420_1 further includes an addressing circuit, wherein the addressing circuit is arranged below the stacked memory cell array 421. The implementation details of the second chip 420 have been described in the aforementioned embodiments, and will not be repeated here.

[0074] Different from the above-mentioned embodiment, the memory device 400 further has a third chip 420_2. The third chip 420_2 is arranged below the second chip 420_1 and is stacked with the second chip 420_1. The third chip 420_2 includes a plurality of transistor structures 421-423. The transistor structures 421-423 in the third chip 420_2 can be used to form an addressing circuit of a stacked memory cell array 421. That is, in this embodiment, the addressing circuit of the stacked memory cell array 421 can be distributed in the second chip 420_1 and the third chip 420_2, thereby increasing the number of transistors that can be set. Of course, the third chip 420_2 can also be used to set any peripheral circuit other than the addressing circuit, without specific restrictions.

[0075] The third chip 420_2 may also have a plurality of metal layers to form a plurality of transmission wires, such as the transmission wires WA. The second chip 420_1 and the third chip 420_2 may respectively have respective substrates SUB2_1 and SUB2_2.

[0076] In other embodiments, electrical signals may be communicated between the second chip 420_1 and the third chip 420_2 by forming a through-silicon via (TSV) therebetween, wherein each electrical signal includes power, control voltage, control current, bias voltage or bias current. In this embodiment, the transmission wire WB in the second chip 420_1 and the transmission wire WA in the third chip 420_2 may be electrically connected to each other through the through-silicon via TSV1. The through-silicon via TSV1 may be used to enable the transmission of signals or power between the second chip 420_1 and the third chip 420_2.

[0077] Please refer to Figure 5 , Figure 5 A cross-sectional schematic diagram of the structure of a memory device according to another embodiment of the present disclosure is shown. The memory device 500 is composed of a first chip 510_1, a second chip 520, and a third chip 510_2. The first chip 510_1 and the third chip 510_2 are stacked on each other. The first chip 510_1 and the third chip 510_2 can be used to set peripheral circuits respectively. In this way, the number of transistors in the peripheral circuit of the memory device 500 can be effectively increased. Of course, other circuits other than the peripheral circuit can also be set in the third chip 510_2 without special restrictions.

[0078] In this embodiment, the first chip 510_1 and the third chip 510_2 may have similar structures. The first chip 510_1 and the third chip 510_2 respectively have substrates SUB1_1 and SUB1_2.

[0079] And, with Figure 4 Similar to the embodiment, the first chip 510_1 and the third chip 510_2 can communicate power and signals through the through-silicon vias TSV2. Of course, the number of the through-silicon vias TSV2 can be one or more. Figure 5 The drawings are merely illustrative examples and are not intended to limit the scope of the present disclosure.

[0080] In addition, a plurality of bonding pads PD11 ˜ PD13 are formed on the first chip 510_1 , and are electrically connected to a plurality of bonding pads PD21 ˜ PD23 on the second chip 520 . A stacked memory cell array 521 is formed on the second chip 520 .

[0081] The implementation details of the first chip 510_1 and the second chip 520 have been described in detail in the aforementioned embodiments and will not be elaborated herein.

[0082] Please refer to Figure 6 , Figure 6 A cross-sectional schematic diagram of the structure of a memory device according to another embodiment of the present disclosure is shown. The memory device 600 is composed of a first chip 610_1, a second chip 620_1, a third chip 610_2 and a third chip 620_2. The first chip 610_1 and the third chip 610_2 are stacked on each other, and the second chip 620_1 and the third chip 620_2 are stacked on each other. The first chip 610_1 and the third chip 610_2 can transmit power or signals to each other through the through-silicon via TSV3. The second chip 620_1 and the third chip 620_2 can transmit power or signals to each other through the through-silicon via TSV4. The first chip 610_1 and the second chip 620_1 are electrically connected to each other through the pads PD11~PD13 and PD21~PD23 formed respectively through a wafer bonding process.

[0083] The implementations of the first chip 610_1 , the second chip 620_1 , the third chip 610_2 , and the third chip 620_2 have been described in detail in the aforementioned embodiments, and will not be repeated herein.

[0084] It is worth mentioning that in the embodiment of the present disclosure, the number of layers of the third chip 610_2 stacked with the first chip 610_1 can be one or more, without any specific limitation. The number of layers of the third chip 620_2 stacked with the second chip 620_1 can also be one or more, also without any specific limitation.

[0085] In addition, regarding the memory devices 400 to 600 of the above embodiments, the first chip does not necessarily need to be disposed above the second chip, and the upper and lower positional relationship of the chips can be adjusted arbitrarily without any specific restrictions.

[0086] Please refer to Figure 7 , Figure 7 A block diagram of a memory device according to an embodiment of the present disclosure is shown. The memory device 700 includes a stacked memory cell array 710, an addressing circuit 720, an input / output controller 731, 732, row decoders 741, 742, page buffers 751, 752, a control pad 760, and an input / output pad 770. In this embodiment, the input / output controllers 731, 732, the row decoders 741, 742, and the page buffers 751, 752 are all peripheral circuits and can be arranged on a first chip. The stacked memory cell array 710 and the addressing circuit 720 can be arranged on a second chip. The process temperature of the first chip is different from the process temperature of the second chip. For example, the process temperature of the first chip can be lower than the process temperature of the second chip. Each input / output controller 731, 732 has a plurality of latches L and a write pulse generator P. The write pulse generator P is used to write data to the corresponding latches L in the page buffers 751, 752.

[0087] In addition, the addressing circuit 720 has a plurality of flip-flops FF. The flip-flops FF are used to transmit address information to the row decoders 741 and 742.

[0088] According to the aforementioned embodiments, the page buffers 751 and 752 in this embodiment can be coupled to the pads on the second chip through the pads on the first chip, and then coupled to the stacked memory cell array 710 through the pads on the second chip. Similarly, the addressing circuit 720 can send address information to the row decoders 741 and 742 through the pads on the second chip and the corresponding pads on the first chip.

[0089] Furthermore, in this embodiment, the control pad 760 can receive the write control signal WE# and transmit the write control signal WE# to the input / output pad 770 .

[0090] In summary, the present disclosure arranges the peripheral circuit of the memory device in the first chip, and arranges the stacked memory cell array and the first addressing circuit in the second chip. The first chip and the second chip are electrically connected to each other through a wafer bonding process to form a complete memory device. Therefore, the peripheral circuit in the first chip can be applied to a relatively low temperature process, and a semiconductor material with a relatively low temperature resistance can be used to form the transistor structure therein. In this way, the electrical characteristics of the peripheral circuit can be effectively improved, thereby improving the working performance of the memory device.

[0091] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A memory device, comprising: A plurality of first peripheral circuits are arranged on a first chip, wherein the first chip has a plurality of first bonding pads; A stacked memory cell array is disposed on a second chip, wherein a plurality of second bonding pads are formed on the second chip, the plurality of second bonding pads are coupled to the stacked memory cell array, and are respectively coupled to the corresponding plurality of first bonding pads; as well as A first addressing circuit is disposed on the second chip, coupled to the stacked memory cell array and disposed below the stacked memory cell array.

2. The memory device according to claim 1, wherein the first chip comprises a plurality of transistors, each of the transistors comprising: a base; a gate structure disposed on the substrate; A source structure and a drain structure are formed on the substrate; A plurality of silicide structures are formed on the substrate and are respectively formed in the source structure and the drain structure; as well as A plurality of conductive structures are respectively formed on the plurality of silicide structures to form a plurality of contact windows. 3 . The memory device according to claim 2 , wherein a temperature resistance level of each of the silicide structures is lower than a temperature resistance level of each of the conductive structures. 4 . The memory device according to claim 2 , wherein each of the silicide structures is a nickel silicide structure or a cobalt silicide structure, and wherein a material of each of the conductive structures is tungsten.

5. The memory device according to claim 2, wherein the first chip further comprises: A plurality of metal layers, used to form a plurality of transmission wires so that each of the first bonding pads is coupled to the corresponding contact windows; as well as A plurality of dielectric layers are arranged alternately with the plurality of metal layers. 6 . The memory device according to claim 5 , wherein the material of the plurality of metal layers is copper or aluminum, and the dielectric constant of the plurality of dielectric layers is less than a threshold. 7 . The memory device according to claim 1 , wherein the plurality of second bonding pads are respectively coupled to a plurality of bit lines on the stacked memory cell array.

8. The memory device of claim 7, wherein the plurality of peripheral circuits comprises: A plurality of page buffers are respectively coupled to the plurality of first pads, and each of the page buffers is coupled to a corresponding bit line through a corresponding first pad and a corresponding second pad.

9. The memory device of claim 8, wherein the plurality of peripheral circuits further comprises: A plurality of address decoding circuits and a plurality of input-output circuits, wherein the plurality of address decoding circuits are respectively coupled to the plurality of page buffers, and the plurality of page buffers are respectively coupled to the input-output circuits.

10. The memory device according to claim 1, further comprising: A plurality of power transmission wires are formed in the second chip, and the plurality of power transmission wires are respectively coupled to a plurality of third bonding pads on the second chip, The plurality of third bonding pads are respectively coupled to the plurality of fourth bonding pads on the first chip and are used for performing power transmission operation with the second chip.

11. The memory device according to claim 1 , further comprising: A plurality of second peripheral circuits are arranged in at least one third chip, wherein the at least one third chip is stacked with the first chip, wherein at least one first transmission wire in the first chip is coupled to at least one second transmission wire in the at least one third chip through at least one through-silicon via.

12. The memory device according to claim 1, further comprising: A plurality of second addressing circuits are arranged in at least one third chip, wherein the at least one third chip is stacked with the second chip, wherein at least one first transmission conductor in the second chip is coupled to at least one second transmission conductor in the at least one third chip through at least one through-silicon via.

13. The memory device according to claim 1, wherein the second chip comprises a plurality of transistors, each of the transistors comprising: a base; a gate structure disposed on the substrate; A source structure and a drain structure are formed on the substrate; as well as A plurality of conductive structures are respectively formed in the source structure and the drain structure, and a plurality of contact windows are formed.

14. The memory device according to claim 1, wherein the stacked memory cell array is a three-dimensional AND, NAND or NOR memory cell array.

15. The memory device according to claim 1, wherein a material of the plurality of transmission wires in the second chip is tungsten.

16. A memory device comprising: A first chip, comprising a plurality of first peripheral circuits and a plurality of first bonding pads, wherein the plurality of first bonding pads are formed on a surface of the first chip; A second chip, comprising: a stacked memory cell array; and a first addressing circuit coupled to the stacked memory cell array and disposed below the stacked memory cell array; and A plurality of second bonding pads are formed on the surface of the second chip and are respectively coupled to the corresponding plurality of first bonding pads; The process temperature of the first chip is different from the process temperature of the second chip. 17 . The memory device of claim 16 , wherein a process temperature of the first chip is lower than a process temperature of the second chip.

18. The memory device according to claim 16, wherein the first chip comprises a plurality of transistors, each of the transistors comprising: a base; a gate structure disposed on the substrate; A source structure and a drain structure are formed on the substrate; A plurality of silicide structures are formed on the substrate and are respectively formed in the source structure and the drain structure; as well as A plurality of conductive structures are respectively formed on the plurality of silicide structures to form a plurality of contact windows.

19. The memory device of claim 16, further comprising: At least one third chip is stacked with the first chip, wherein the at least one third chip includes a plurality of second peripheral circuits, and at least one first transmission wire in the first chip is coupled to at least one second transmission wire in the at least one third chip through at least one through-silicon via.

20. The memory device of claim 16, further comprising: At least one third chip is stacked with the second chip, and the at least one third chip includes a plurality of second addressing circuits. At least one first transmission conductor in the second chip is coupled to at least one second transmission conductor in the at least one third chip through at least one through-silicon via.

Images