Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the steps that an initial structure is provided and comprises a dielectric layer and a conductive layer which are stacked, the conductive layer comprises a plurality of conductive strips, a first hole penetrates through the dielectric layer and the conductive strips in the first direction, and the first hole of each conductive strip is divided into two parts; laterally thinning the conductive strip to form a first gap; forming a first indium gallium zinc oxide in the first gap; laterally thinning the dielectric layer, exposing part of the first indium gallium zinc oxide, and forming a second gap; forming a second indium-gallium-zinc oxide on the surface of the exposed first indium-gallium-zinc oxide, wherein the concentration of indium in the first indium-gallium-zinc oxide is greater than that of indium in the second indium-gallium-zinc oxide; and forming a gate structure in the first hole and the second gap. According to the technical scheme, the first indium gallium zinc oxide with relatively high indium concentration is formed between the second indium gallium zinc oxide and the conductive strip, so that the contact resistance is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] In the manufacturing process of dynamic random access memory (DRAM), the buried bit line method is often used. As the size of semiconductor processes continues to shrink, the existing manufacturing process is gradually unable to meet the demand. At present, 3D DRAM based on indium gallium zinc oxide (IGZO) materials has also become a key research direction in the industry due to the excellent anti-leakage characteristics of the material, as well as low cost and relatively simple process.

[0003] However, the contact resistance between IGZO and metal electrodes is large, which affects the performance of the device. Therefore, how to reduce the contact resistance between IGZO and metal electrodes and improve device performance is a problem that needs to be solved at present. Summary of the invention

[0004] The technical problem to be solved by the present disclosure is to reduce the contact resistance between IGZO and metal electrodes, improve device performance, and provide a semiconductor structure and a preparation method thereof.

[0005] In order to solve the above problems, the present disclosure provides a method for preparing a semiconductor structure, comprising: providing an initial structure, the initial structure comprising a dielectric layer and a conductive layer stacked in sequence along a first direction, the conductive layer comprising a plurality of conductive strips extending along a second direction and arranged at intervals along a third direction, a first hole penetrating the dielectric layer and the conductive strip along the first direction, and the conductive strip is separated into two independent parts by the first hole in the second direction; thinning the conductive strip laterally along the second direction to form a first gap between two adjacent dielectric layers; forming a first indium gallium zinc oxide in the first gap; thinning the dielectric layer laterally along the second direction to expose a portion of the first indium gallium zinc oxide and form a second gap between two adjacent first indium gallium zinc oxides; forming a second indium gallium zinc oxide on the surface of the exposed first indium gallium zinc oxide, and the concentration of indium in the first indium gallium zinc oxide is greater than the concentration of indium in the second indium gallium zinc oxide; and forming a gate structure in the first hole and the second gap.

[0006] In some embodiments, after the step of laterally thinning the dielectric layer along the second direction, the following step is further included: performing plasma treatment on the exposed first indium gallium zinc oxide to form oxygen vacancies in the first indium gallium zinc oxide.

[0007] In some embodiments, during the plasma treatment of the exposed first indium gallium zinc oxide, the plasma concentration decreases with the treatment time.

[0008] In some embodiments, in the step of laterally thinning the dielectric layer along the second direction, the dielectric layer is laterally thinned along the second direction multiple times to partially expose the first indium gallium zinc oxide; after each time the dielectric layer is laterally thinned along the second direction, the exposed first indium gallium zinc oxide is processed to form oxygen vacancies in the first indium gallium zinc oxide.

[0009] In some embodiments, in the step of treating the exposed first indium gallium zinc oxide after each laterally thinning the dielectric layer along the second direction, the exposed first indium gallium zinc oxide is plasma treated after each laterally thinning the dielectric layer, and the plasma concentration decreases as the number of times the dielectric layer is laterally thinned increases, so as to form an oxygen vacancy concentration gradient in the first indium gallium zinc oxide.

[0010] In some embodiments, after performing plasma treatment on the first indium gallium zinc oxide, the method further includes: annealing the first indium gallium zinc oxide.

[0011] In some embodiments, the molar composition ratio of indium gallium zinc in the first indium gallium zinc oxide is (9-10):1:1.

[0012] In order to solve the above problems, the present disclosure also provides a semiconductor structure, including: an initial structure, the initial structure includes a dielectric layer and a conductive layer stacked in sequence along a first direction, the conductive layer includes a plurality of conductive strips extending along a second direction and arranged at intervals along a third direction, in the second direction, the conductive strips are separated into a first part and a second part independent of each other, and the opposite ends of the first part and the second part are both recessed in the dielectric layer; a first indium gallium zinc oxide is respectively arranged at the opposite ends of the first part and the second part of the conductive strip, and the ends of the first indium gallium zinc oxide are both protruding from the dielectric layer; a second indium gallium zinc oxide covers the surface of the area where the first indium gallium zinc oxide protrudes from the dielectric layer, and the concentration of indium in the first indium gallium zinc oxide is greater than the concentration of indium in the second indium gallium zinc oxide; a gate structure covers the second indium gallium zinc oxide.

[0013] In some embodiments, the oxygen vacancy concentration at one end of the first indium gallium zinc oxide close to the second indium gallium zinc oxide is greater than the oxygen vacancy concentration at the end of the first indium gallium zinc oxide far from the second indium gallium zinc oxide.

[0014] In some embodiments, the concentration of oxygen vacancies in the first indium gallium zinc oxide decreases gradually.

[0015] The method for preparing the semiconductor structure reduces the contact resistance between the second indium gallium zinc oxide and the conductive strip by forming a first indium gallium zinc oxide with a higher indium concentration between the second indium gallium zinc oxide and the conductive strip. In addition, the first indium gallium zinc oxide and the second indium gallium zinc oxide are made of the same material, and no interface is formed between the first indium gallium zinc oxide and the second indium gallium zinc oxide, which is conducive to further reducing the contact resistance between the second indium gallium zinc oxide and the conductive strip. Further, an oxygen vacancy concentration gradient is formed in the first indium gallium zinc oxide, which can prevent transistor leakage and reduce device power consumption. In addition, annealing the first indium gallium zinc oxide can improve the damage on the surface of the first indium gallium zinc oxide and improve its electrical properties, such as conductivity, carrier concentration and mobility.

[0016] The semiconductor structure reduces the contact resistance between the second indium gallium zinc oxide and the conductive strip by providing a first indium gallium zinc oxide with a higher indium concentration between the second indium gallium zinc oxide and the conductive strip. In addition, the first indium gallium zinc oxide and the second indium gallium zinc oxide are made of the same material, and no interface is formed between the first indium gallium zinc oxide and the second indium gallium zinc oxide, which is beneficial to further reduce the contact resistance between the second indium gallium zinc oxide and the conductive strip.

[0017] It should be understood that the above general description and the detailed description below are exemplary and explanatory only and cannot limit the present disclosure. Technologies, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, technologies, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the specific embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the specific embodiments. Obviously, the drawings described below are only some specific embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 It is a schematic diagram of the structure of a semiconductor structure in the prior art.

[0020] Figure 2 The present invention is a flowchart of one embodiment of a method for preparing a semiconductor structure.

[0021] Figure 3A to Figure 3H The present invention is a process flow chart of an embodiment of a method for preparing a semiconductor structure disclosed herein.

[0022] Figure 4A to Figure 4D The present invention is a process flow chart of another embodiment of the method for preparing a semiconductor structure disclosed herein. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0024] See also Figure 1 , which is a schematic diagram of the structure of a semiconductor structure in the prior art. Figure 1 As shown, the semiconductor structure includes: a silicon dioxide layer 11, a metal electrode 12, an annular channel 13, a gate dielectric layer 14 and a gate 15. The multiple silicon dioxide layers 11 are stacked in sequence, and the metal electrode 12 is located inside the stacked silicon dioxide layers 11. The metal electrode 12 is divided into two parts, which are respectively located on both sides of the annular channel 13, and the annular channel 13 is located on the surface of the part of the metal electrode 12 protruding from the silicon dioxide layer 11. The gate dielectric layer 14 and the gate 15 are located in the silicon dioxide layer 11 and between the two parts of the metal electrode 12, and are located on the surface of the annular channel 13. The material of the metal electrode 12 of the semiconductor structure is metal tungsten, and the material of the annular channel 13 is indium gallium zinc oxide, and the contact resistance between metal tungsten and indium gallium zinc oxide is large, which greatly affects the device performance.

[0025] In order to solve the above problems, the present disclosure provides a method for preparing a semiconductor structure. Figure 2 as well as Figure 3A to Figure 3H ,in, Figure 2 A flowchart of the steps of an embodiment of the method for preparing a semiconductor structure disclosed in the present invention; Figure 3A to Figure 3H FIG. 1 is a process flow chart of an embodiment of the method for preparing a semiconductor structure disclosed in the present invention. Figure 2 As shown, the method for preparing a semiconductor structure includes: step S21, providing an initial structure, the initial structure includes a dielectric layer and a conductive layer stacked in sequence along a first direction, the conductive layer includes a plurality of conductive strips extending along a second direction and arranged at intervals along a third direction, a first hole penetrates the dielectric layer and the conductive strip along the first direction, and the conductive strip is divided into two independent parts by the first hole in the second direction; step S22, laterally thinning the conductive strip along the second direction to form a first gap between two adjacent dielectric layers; step S23, forming a first indium gallium zinc oxide in the first gap; step S24, laterally thinning the dielectric layer along the second direction to expose a portion of the first indium gallium zinc oxide, and forming a second gap between two adjacent first indium gallium zinc oxides; step S25, forming a second indium gallium zinc oxide on the surface of the exposed first indium gallium zinc oxide, and the concentration of indium in the first indium gallium zinc oxide is greater than the concentration of indium in the second indium gallium zinc oxide; step S26, forming a gate structure in the first hole and the second gap.

[0026] See also Figure 3A And step S21, providing an initial structure, the initial structure includes a dielectric layer 31 and a conductive layer 32 stacked in sequence along a first direction D1, the conductive layer 32 includes a plurality of conductive strips 320 extending along a second direction D2 and arranged at intervals along a third direction D3, a first hole 391 penetrates the dielectric layer 31 and the conductive strip 320 along the first direction D1, and the conductive strip 320 is separated into two independent parts by the first hole 391 in the second direction D2. As shown in the figure, the two independent conductive strips are respectively a first part 321 and a second part 322. In some embodiments, the material of the dielectric layer 31 is silicon oxide, and the material of the conductive strip 320 is metal, such as tungsten.

[0027] The first direction D1 is a direction perpendicular to the initial structure surface, the second direction D2 and the third direction D3 are directions parallel to the initial structure surface, and the second direction D2 is perpendicular to the third direction D3. In this embodiment, the first direction D1 is the Z direction in the Cartesian coordinate system, the second direction D2 is the X direction in the Cartesian coordinate system, and the third direction is the Y direction in the Cartesian coordinate system.

[0028] See also Figure 3B And step S22, thinning the conductive strip 320 laterally along the second direction D2 to form a first gap 381 between two adjacent dielectric layers 31. In some embodiments, the conductive strip 320 is thinned laterally along the second direction D2 by an etching process on the sidewall of the first hole 391, and the portion of the conductive strip 320 exposed to the sidewall of the first hole 391 is removed to form the first gap 381.

[0029] See also Figure 3D And step S23, forming the first indium gallium zinc oxide 331 in the first gap 381. In some embodiments, the step of forming the first indium gallium zinc oxide 331 in the first gap 381 further includes the following steps:

[0030] like Figure 3C As shown, in the first hole 391 and the first gap 381 (shown in Figure 3B ) is deposited in the first hole 391 and the first gap 381. In some embodiments, the molar ratio of indium gallium zinc in the first indium gallium zinc oxide material layer 371 is (9-10): 1: 1, that is, a material layer with a high indium gallium ratio is formed. In this embodiment, the first indium gallium zinc oxide layer 371 can be deposited in the first hole 391 and the first gap 381 by an atomic layer deposition process, and the ratio of indium to gallium is controlled by the gas flow rate of the precursor.

[0031] like Figure 3D As shown, the first indium gallium zinc oxide material layer 371 in the first hole 391 is removed, and the first gap 381 (shown in FIG. Figure 3B) as the first indium gallium zinc oxide 331. In this embodiment, the first indium gallium zinc oxide material layer 371 in the first hole 391 is removed by dry etching.

[0032] After completing the above steps, the first gap 381 (shown in FIG. Figure 3B ) within the first indium gallium zinc oxide 331.

[0033] In some embodiments, the molar composition ratio of indium gallium zinc in the first indium gallium zinc oxide 331 is (9-10):1:1, that is, the first indium gallium zinc oxide 331 is a high-indium structure.

[0034] See also Figure 3E And step S24, the dielectric layer 31 is laterally thinned along the second direction D2 to expose a portion of the first indium gallium zinc oxide 331, and a second gap 382 is formed between two adjacent first indium gallium zinc oxides 331. In some embodiments, the dielectric layer 31 can be laterally thinned along the second direction D2 on the sidewall of the first hole 391 by an etching process, and the area where the dielectric layer 31 is removed constitutes the second gap 382.

[0035] like Figure 3F As shown, in some embodiments, after the step of laterally thinning the dielectric layer 31 along the second direction D2, the following step is further included: performing plasma treatment on the exposed first indium gallium zinc oxide 331 to form oxygen vacancies 34 in the first indium gallium zinc oxide 331. The formation of oxygen vacancies 34 in the first indium gallium zinc oxide 331 can prevent leakage of the semiconductor structure and reduce device power consumption.

[0036] In some embodiments, plasma includes but is not limited to methods for increasing the concentration of oxygen vacancies, such as hydrogen ion plasma treatment, indium ion doping, and argon ion plasma treatment. In this embodiment, the first indium gallium zinc oxide 331 is plasma treated by hydrogen ion plasma treatment, and hydrogen ions bombard the metal-oxygen bonds to break them, so as to form oxygen vacancies in the first indium gallium zinc oxide.

[0037] In this embodiment, during the plasma treatment of the exposed first indium gallium zinc oxide 331, the plasma concentration decreases with the treatment time. The plasma concentration decreases with time, and an oxygen vacancy concentration gradient can also be formed in the first indium gallium zinc oxide 331, which can prevent transistor leakage and reduce device power consumption.

[0038] After the first InGaZnO 331 is subjected to plasma treatment, the method further includes: annealing the first InGaZnO 331. The annealing process can improve the damage of the first InGaZnO 331 caused by the plasma treatment and improve its electrical properties, such as conductivity, carrier concentration and mobility.

[0039] In the above embodiment, after the dielectric layer 31 is thinned along the second direction, the first indium gallium zinc oxide 331 is subjected to plasma treatment. In other embodiments, in the step of laterally thinning the dielectric layer 31 along the second direction D2, the dielectric layer 31 may be laterally thinned along the second direction D2 for multiple times to partially expose the first indium gallium zinc oxide 331; and after each laterally thinning the dielectric layer 31 along the second direction D2, the exposed first indium gallium zinc oxide 331 is treated to form oxygen vacancies 34 in the first indium gallium zinc oxide 331. The formation of oxygen vacancies 34 in the first indium gallium zinc oxide 331 can prevent transistor leakage and reduce device power consumption. Please refer to Figure 4A to Figure 4D , which is a process flow chart of another embodiment of performing plasma treatment on the first indium gallium zinc oxide 331.

[0040] Please refer to Figure 4A to Figure 4D The example shown:

[0041] like Figure 4A As shown, a portion of the dielectric layer 31 is laterally thinned along the second direction D2 to expose the first indium gallium zinc oxide 331. For example, the dielectric layer 31 is laterally thinned along the second direction D2 by an etching process.

[0042] like Figure 4B As shown, the exposed first indium gallium zinc oxide 331 is subjected to plasma treatment to form oxygen vacancies 34 in the first indium gallium zinc oxide 331. In some embodiments, the plasma treatment includes but is not limited to methods of increasing the concentration of oxygen vacancies such as hydrogen ion plasma treatment, indium ion doping, and argon ion plasma treatment. In this embodiment, the first indium gallium zinc oxide 331 is subjected to plasma treatment by a hydrogen ion plasma treatment process.

[0043] like Figure 4C As shown, a portion of the dielectric layer 31 is thinned laterally continuously along the second direction D2 to expose the first InGaZn oxides 331 to a target position, and a second gap 382 is formed between two adjacent first InGaZn oxides 331 .

[0044] like Figure 4D As shown, the exposed first indium gallium zinc oxide 331 is subjected to plasma treatment to form oxygen vacancies 34 in the first indium gallium zinc oxide 331. In some embodiments, the plasma treatment includes but is not limited to methods of increasing the concentration of oxygen vacancies such as hydrogen ion plasma treatment, indium ion doping, and argon ion plasma treatment. In this embodiment, the first indium gallium zinc oxide 331 is subjected to plasma treatment by a hydrogen ion plasma treatment process.

[0045] In this step, all exposed areas of the first indium gallium zinc oxide 331 are plasma treated. The oxygen vacancy concentrations of the areas that have been plasma treated previously are superimposed, and the oxygen vacancy concentration of the areas that are plasma treated for the first time in this step is the oxygen vacancy concentration formed by the current plasma treatment, thereby forming an oxygen vacancy concentration gradient in the exposed areas of the first indium gallium zinc oxide 331.

[0046] In some embodiments, in the step of treating the exposed first indium gallium zinc oxide 331 after each lateral thinning of the dielectric layer 31, the exposed first indium gallium zinc oxide 331 is plasma treated after each lateral thinning of the dielectric layer 31, and the plasma concentration decreases as the number of lateral thinning of the dielectric layer 31 increases, so as to further form an oxygen vacancy concentration gradient in the first indium gallium zinc oxide 331. The formation of the oxygen vacancy concentration gradient in the first indium gallium zinc oxide 331 can further improve the conductive effect and reduce the contact resistance.

[0047] In the embodiment of thinning the dielectric layer 31 step by step and performing plasma treatment on the exposed first indium gallium zinc oxide 331 after each thinning of the dielectric layer 31 along the second direction D2, an annealing process is performed uniformly after all the thinning and plasma treatment steps are completed. The annealing process can improve the damage of the first indium gallium zinc oxide 331 caused by the plasma treatment and improve its electrical properties, such as conductivity, carrier concentration and mobility.

[0048] In the above embodiment, the dielectric layer 31 is laterally thinned twice and the plasma treatment is performed twice. In other embodiments, the dielectric layer 31 may be laterally thinned multiple times and the plasma treatment may be performed multiple times, for example, three times or more.

[0049] Please continue reading Figure 2 , Figure 3G And step S25, forming a second indium gallium zinc oxide 332 on the surface of the exposed first indium gallium zinc oxide 331, and the concentration of indium in the first indium gallium zinc oxide 331 is greater than the concentration of indium in the second indium gallium zinc oxide 332. The second indium gallium zinc oxide 332 covers the exposed surface of the first indium gallium zinc oxide 331, and can be electrically connected to the conductive strip 320 through the first indium gallium zinc oxide 331. The semiconductor structure disclosed in the present invention reduces the contact resistance between the second indium gallium zinc oxide 332 and the conductive strip 320 by forming the first indium gallium zinc oxide 331 with a higher indium concentration between the second indium gallium zinc oxide 332 and the conductive strip 320. In some embodiments, the second indium gallium zinc oxide 332 can be deposited by an atomic layer deposition process.

[0050] In this step, the second InGaZnO 332 only covers the exposed surface of the first InGaZnO 331 , the surface of the dielectric layer 31 is not covered by the second InGaZnO 332 , and the second gap 382 is not filled by the second InGaZnO 332 .

[0051] In addition, in the embodiment in which the dielectric layer 31 is laterally thinned multiple times and the plasma treatment is performed twice, the second indium gallium zinc oxide 332 formed in step S25 is the same as that in the present embodiment.

[0052] See also Figure 1 , Figure 3H And step S26, forming a gate structure 35 in the first hole 391 and the second gap 382. The method of forming the gate structure 35 includes but is not limited to thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition and atomic layer deposition. The gate structure 35 further includes a gate 351 and a gate dielectric layer 352, and the gate dielectric layer 352 is at least disposed between the gate 351 and the second indium gallium zinc oxide 332 to insulate the gate 351 from the second indium gallium zinc oxide 332.

[0053] In addition, in the embodiment where the dielectric layer 31 is thinned laterally multiple times and the plasma treatment is performed twice (i.e. Figure 4A to Figure 4D The embodiment shown in the figure), the gate structure 35 formed in step S26 is the same as that of the present embodiment. The above technical solution reduces the contact resistance between the second indium gallium zinc oxide and the conductive strip by forming a first indium gallium zinc oxide with a higher indium concentration between the second indium gallium zinc oxide and the conductive strip. In addition, the first indium gallium zinc oxide and the second indium gallium zinc oxide are made of the same material, and no interface is formed between the first indium gallium zinc oxide and the second indium gallium zinc oxide, which is beneficial to further reduce the contact resistance. And further forming an oxygen vacancy concentration gradient in the first indium gallium zinc oxide can prevent transistor leakage and reduce device power consumption. In addition, annealing the first indium gallium zinc oxide can improve the damage on the surface of the first indium gallium zinc oxide and improve its electrical properties, such as conductivity, carrier concentration and mobility.

[0054] Based on the same inventive concept, an embodiment of the present disclosure further provides a semiconductor structure.

[0055] See also Figure 3H , which is a schematic diagram of the structure of an embodiment of the semiconductor structure disclosed in the present invention. Figure 3HAs shown, the semiconductor structure includes: an initial structure, a first indium gallium zinc oxide 331, a second indium gallium zinc oxide 332, and a gate structure 35. The initial structure includes a dielectric layer 31 and a conductive layer 32 stacked in sequence along a first direction D1, and the conductive layer 32 includes a plurality of conductive strips 320 extending along a second direction D2 and arranged at intervals along a third direction D3. In the second direction D2, the conductive strip 320 is separated into a first portion 321 and a second portion 322 that are independent of each other, and the opposite ends of the first portion 321 and the second portion 322 are both recessed in the dielectric layer 31. The first indium gallium zinc oxide 331 is respectively disposed at the opposite ends of the first portion 321 and the second portion 322 of the conductive strip 320, and the ends of the first indium gallium zinc oxide 331 are both protruding from the dielectric layer 31. The second indium gallium zinc oxide 332 covers the surface of the region where the first indium gallium zinc oxide 331 protrudes from the dielectric layer 31, and the concentration of indium in the first indium gallium zinc oxide 331 is greater than the concentration of indium in the second indium gallium zinc oxide 332. The gate structure 15 covers the second InGaZnO 332 .

[0056] The above technical solution reduces the contact resistance between the second indium gallium zinc oxide and the conductive strip by arranging the first indium gallium zinc oxide with a higher indium concentration between the second indium gallium zinc oxide and the conductive strip. In addition, the first indium gallium zinc oxide and the second indium gallium zinc oxide are made of the same material, and no interface is formed between the first indium gallium zinc oxide and the second indium gallium zinc oxide, which is conducive to further reducing the contact resistance between the second indium gallium zinc oxide and the conductive strip.

[0057] The gate structure, the second InGaZnO 332 , the first InGaZnO 331 and the conductive strip constitute a transistor. The first portion of the conductive strip can be used as a source region of the transistor, and the second portion of the conductive strip can be used as a drain region of the transistor.

[0058] In some embodiments, the molar composition ratio of indium gallium zinc in the first indium gallium zinc oxide 331 is (9-10): 1: 1. The first indium gallium zinc oxide 331 with a high indium gallium ratio can reduce the contact resistance between the second indium gallium zinc oxide 332 and the conductive strip.

[0059] In some embodiments, oxygen vacancies 34 are formed in the first indium gallium zinc oxide 331, which can prevent transistor leakage and reduce device power consumption. Figure 3H The embodiment shown differs in that Figure 4D In the illustrated embodiment, the concentration of oxygen vacancies 34 at one end of the first indium gallium zinc oxide 331 close to the second indium gallium zinc oxide 332 is greater than the concentration of oxygen vacancies 34 at the side away from the second indium gallium zinc oxide 332. Figure 4DIn the embodiment shown, the concentration of oxygen vacancies 34 in the first InGaZn oxide 331 decreases gradually. The formation of an oxygen vacancies concentration gradient in the first InGaZn oxide 331 can further improve the conductive effect and reduce the contact resistance between the second InGaZn oxide and the conductive strip.

[0060] It should be noted that references in the specification to "an embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0061] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. Similarly, terms such as "one", "a" or "the" can also be understood to express singular usage or to express plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connected / coupled" refers not only to the direct coupling of one component to another component, but also to the indirect coupling of one component to another component through an intermediate component.

[0062] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present disclosure are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates otherwise. It should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments of the present disclosure and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concepts of the present disclosure. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0063] The above are only preferred embodiments of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as the protection scope of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: An initial structure is provided, the initial structure comprising a dielectric layer and a conductive layer stacked in sequence along a first direction, the conductive layer comprising a plurality of conductive strips extending along a second direction and arranged at intervals along a third direction, a first hole penetrating the dielectric layer and the conductive strips along the first direction, and the conductive strips are separated into two independent parts by the first hole in the second direction; Laterally thinning the conductive strip along a second direction to form a first gap between two adjacent dielectric layers; forming a first indium gallium zinc oxide in the first gap; Laterally thinning the dielectric layer along a second direction to expose a portion of the first indium gallium zinc oxide and form a second gap between two adjacent first indium gallium zinc oxides; forming a second indium gallium zinc oxide on the exposed surface of the first indium gallium zinc oxide, wherein the concentration of indium in the first indium gallium zinc oxide is greater than the concentration of indium in the second indium gallium zinc oxide; A gate structure is formed in the first hole and the second gap.

2. The method according to claim 1, characterized in that After the step of laterally thinning the dielectric layer along the second direction, the method further includes the following step: performing plasma treatment on the exposed first indium gallium zinc oxide to form oxygen vacancies in the first indium gallium zinc oxide.

3. The method according to claim 2, characterized in that During the process of performing plasma treatment on the exposed first indium gallium zinc oxide, the plasma concentration decreases with the treatment time.

4. The method according to claim 1, characterized in that In the step of laterally thinning the dielectric layer along the second direction, the dielectric layer is laterally thinned along the second direction for multiple times to partially expose the first indium gallium zinc oxide; After each time the dielectric layer is laterally thinned along the second direction, the exposed first indium gallium zinc oxide is processed to form oxygen vacancies in the first indium gallium zinc oxide.

5. The method according to claim 4, characterized in that In the step of treating the exposed first indium gallium zinc oxide after each time the dielectric layer is laterally thinned along the second direction, the exposed first indium gallium zinc oxide is plasma treated after each time the dielectric layer is laterally thinned, and the plasma concentration decreases as the number of times the dielectric layer is laterally thinned increases, so as to form an oxygen vacancy concentration gradient in the first indium gallium zinc oxide.

6. The method according to claim 2, 3 or 5, characterized in that: After the first indium gallium zinc oxide is subjected to plasma treatment, the method further includes: annealing the first indium gallium zinc oxide.

7. The method according to claim 1, characterized in that The molar composition ratio of indium gallium zinc in the first indium gallium zinc oxide is (9-10):1:

1.

8. A semiconductor structure, characterized in that: include: An initial structure, the initial structure comprising a dielectric layer and a conductive layer stacked in sequence along a first direction, the conductive layer comprising a plurality of conductive strips extending along a second direction and arranged at intervals along a third direction, in the second direction, the conductive strips are separated into a first part and a second part independent of each other, and opposite ends of the first part and the second part are both recessed in the dielectric layer; A first indium gallium zinc oxide is disposed at opposite ends of the first portion and the second portion of the conductive strip, and the ends of the first indium gallium zinc oxide protrude from the dielectric layer; A second indium gallium zinc oxide covers a surface of a region where the first indium gallium zinc oxide protrudes from the dielectric layer, and a concentration of indium in the first indium gallium zinc oxide is greater than a concentration of indium in the second indium gallium zinc oxide; The gate structure covers the second indium gallium zinc oxide.

9. The semiconductor structure according to claim 8, characterized in that: The oxygen vacancy concentration at one end of the first indium gallium zinc oxide close to the second indium gallium zinc oxide is greater than the oxygen vacancy concentration at a side away from the second indium gallium zinc oxide.

10. The semiconductor structure according to claim 9, characterized in that: The concentration of oxygen vacancies in the first indium gallium zinc oxide decreases gradually.

Images