Electronic device and manufacturing method thereof

Abstract

An electronic device and a method of manufacturing the same are provided. The electronic device comprises a substrate, a buffer layer, a semiconductor oxide layer and a gate electrode. The buffer layer is disposed on the substrate. The semiconductor oxide layer is disposed on the buffer layer and has a first portion and a second portion adjacent to the first portion. The gate electrode overlaps the first portion. A portion of the buffer layer overlaps the second portion of the semiconductor oxide layer, the portion of the buffer layer having a first portion and a second portion disposed on the first portion, and a boron concentration in the first portion is greater than a boron concentration in the second portion.

Description

Technical Field

[0001] The present invention relates to an electronic device and a manufacturing method thereof, and in particular to an electronic device including a buffer layer and a manufacturing method thereof. Background Art

[0002] Electronic products including chips, such as monitors, smartphones, tablets, laptops and TVs, have become an indispensable necessity in modern society. With the booming development of such electronic products, consumers have high expectations for the quality, functions or prices of these electronic products.

[0003] Electronic products often include transistors to perform operations. However, since doping is required in the process of manufacturing transistors, unnecessary diffusion of dopants may occur, which may reduce the stability of the transistors. Therefore, these electronic products do not meet the expectations of consumers in all aspects, and there are still some problems with electronic products. Developing improved electronic devices and manufacturing methods thereof is still one of the current goals. Summary of the invention

[0004] In some embodiments, an electronic device is provided. The electronic device includes a substrate, a buffer layer, a semiconductor oxide layer, and a gate electrode. The buffer layer is disposed on the substrate. The semiconductor oxide layer is disposed on the buffer layer and has a first portion and a second portion adjacent to the first portion. The gate electrode overlaps with the first portion. A portion of the buffer layer overlaps with the second portion of the semiconductor oxide layer, the portion of the buffer layer has a first portion and a second portion disposed on the first portion, and a boron concentration in the first portion is greater than a boron concentration in the second portion.

[0005] In some embodiments, a method for manufacturing an electronic device is provided. The method for manufacturing an electronic device includes providing a substrate. Forming a buffer layer on the substrate. Forming a semiconductor oxide layer on the buffer layer, and the semiconductor oxide layer has a first portion and a second portion. Forming a gate electrode on the buffer layer, and the gate electrode overlaps with the first portion. Performing an ion implantation process on the semiconductor oxide layer by boron. A portion of the buffer layer overlaps with the second portion of the semiconductor oxide layer. The portion of the buffer layer has a first portion and a second portion disposed on the first portion. After the ion implantation process, the boron concentration in the first portion is greater than the boron concentration in the second portion.

[0006] The electronic device and the manufacturing method thereof disclosed in the present invention can be applied to various types of electronic devices. To make the features and advantages of the present invention more obvious and easy to understand, various embodiments are specifically cited below and described in detail with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description in conjunction with the accompanying drawings will provide a better understanding of the concepts of the disclosed embodiments. It is worth noting that, according to standard industry practice, some features may not be drawn to scale. In fact, the sizes of different features may be increased or decreased for clarity of discussion.

[0008] Figure 1 A cross-sectional schematic diagram of an electronic device according to some embodiments of the present disclosure is shown.

[0009] Figure 2 A cross-sectional schematic diagram of an electronic device according to some embodiments of the present disclosure is shown.

[0010] Figure 3 A cross-sectional schematic diagram of an electronic device according to some embodiments of the present disclosure is shown.

[0011] FIG. 4A to FIG. 4E Elemental analysis schematic diagrams of electronic devices according to some embodiments of the present disclosure are respectively shown.

[0012] Figure 5 A schematic diagram showing elemental analysis of an electronic device according to some embodiments of the present disclosure is shown.

[0013]

Explanation of symbols

[0014] 1,2,3: Electronic devices

[0015] 10:Substrate

[0016] 20:Metal layer

[0017] 22: First metal layer

[0018] 24: Second metal layer

[0019] 30: Buffer layer

[0020] 30P,70P:Part

[0021] 32: First buffer layer

[0022] 32B: Lower part

[0023] 32P,72B:Part 1

[0024] 32U: Upper

[0025] 34: Second buffer layer

[0026] 34P,72U: Part 2

[0027] 40: Semiconductor oxide layer

[0028] 40A: Part 1

[0029] 40B: Part 2

[0030] 50: First insulation layer

[0031] 60: Gate electrode

[0032] 62: first conductive layer

[0033] 64: Second conductive layer

[0034] 70: Second insulation layer

[0035] 80: passivation layer

[0036] AA: Section

[0037] D1: First direction

[0038] D2: Second direction

[0039] IPB: Ion Implantation Process

[0040] L1: First line segment

[0041] L2: Second line segment DETAILED DESCRIPTION

[0042] The following is a detailed description of the electronic device and the manufacturing method thereof for each embodiment of the present disclosure. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific components and arrangements described below are only for simple and clear description of some embodiments of the present disclosure. Of course, these are only used as examples and not for limitation of the present disclosure. In addition, similar and / or corresponding component symbols may be used in different embodiments to indicate similar and / or corresponding components to clearly describe the present disclosure. However, the use of these similar and / or corresponding component symbols is only for the simple and clear description of some embodiments of the present disclosure, and does not represent any correlation between the different embodiments and / or structures discussed.

[0043] It should be understood that relative terms, such as "lower" or "bottom" or "upper" or "top", may be used in various embodiments to describe the relative relationship of one component of the drawings to another component. It is understood that if the device in the drawings is turned upside down, the component described on the "lower" side will become the component on the "upper" side. The embodiments of the present disclosure may be used in conjunction with the attached drawings. Figure 1 It is also understood that the drawings of the present disclosure are also considered as part of the disclosure.

[0044] Furthermore, when a first material layer is said to be located on or over a second material layer, it may include a situation where the first material layer is in direct contact with the second material layer, or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly located on the second material layer, it means that the first material layer and the second material layer are in direct contact.

[0045] In addition, it should be understood that the ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify components. They are not intended to imply any previous ordinal numbers of the component (or components), nor do they represent the order of one component and another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The claims and the specification may not use the same words. For example, the first component in the specification may be the second component in the claims.

[0046] In some embodiments of the present disclosure, terms related to bonding and connection, such as "connect", "interconnect", "bond", etc., unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein other structures are disposed between the two structures. Such terms related to connection and bonding may also include situations where both structures are movable, or both structures are fixed. In addition, the terms "electrically connected" or "electrically coupled" include any direct and indirect electrical connection means.

[0047] In the text, the terms "approximate", "about", "substantially" usually mean within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The quantity given here is an approximate quantity, that is, in the absence of a specific description of "about", "approximately", "substantially", the meaning of "about", "approximately", "substantially" can still be implied. The term "within the range of a first value to a second value" means that the range includes the first value, the second value and other values ​​between them. Furthermore, there may be a certain error between any two values ​​or directions used for comparison. If the first value is equal to the second value, it implies that there may be an error of about 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% between the first value and the second value. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees. If the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0048] Certain words are used throughout the specification and claims of this disclosure to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following specification and claims, words such as "comprise", "contain", "have" are open-ended words, so they should be interpreted as "including but not limited to...". Therefore, when the terms "comprise", "contain" and / or "have" are used in the description of this disclosure, they specify the existence of corresponding parts, areas, steps, operations and / or components, but do not exclude the existence of one or more corresponding parts, areas, steps, operations and / or components.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0050] In the present disclosure, the directions are not limited to the three axes of rectangular coordinates such as the X-axis, the Y-axis and the Z-axis, and can be interpreted in a broader sense. For example, the X-axis, the Y-axis and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following, the X-axis direction is the first direction D1, and the Z-axis direction is the second direction D2. In some embodiments, the cross-sectional schematic diagram described herein is a cross-sectional schematic diagram for observing the XZ plane. In some embodiments, the normal direction of the substrate may be the second direction D2.

[0051] It should be understood that according to the embodiments of the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an ellipsometer, or other suitable methods may be used to measure the relative setting relationship, depth, thickness, width or height of each component, or the spacing or distance between components. According to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structural image including the components to be measured, and measure the depth, thickness, width or height of each component, or the spacing or distance between components.

[0052] It should be understood that according to the embodiments of the present disclosure, time of flight secondary ion mass spectrometer (TOF-SIMS) or other suitable mass spectrometry can be used to quantitatively analyze and / or qualitatively analyze the elements in each component. According to some embodiments, a sample including the component to be measured can be obtained from an electronic device, and the elements in the sample can be analyzed. In some embodiments, the sample can be analyzed using TOF-SIMS in negative ion mode, TOF-SIMS in positive ion mode, or a combination thereof. In some embodiments, the concentration of the sample that can be obtained depends on the accuracy of the analytical method used, and different analytical methods may have different minimum analyzable values. When the concentration of an element in the sample is less than the minimum analyzable value, only the presence of the element can be qualitatively analyzed and the relative content relationship between the element and other elements can be described, but the concentration of the element cannot be quantitatively analyzed. In other words, the sample may substantially not include the element, that is, the concentration of the element is substantially equal to 0, or the sample may substantially include the element, that is, the concentration of the element is substantially greater than 0, but the concentration of the element is lower than the minimum analyzable value.

[0053] It should be understood that, hereinafter, the unit of concentration "atoms / cc" represents the number of atoms included in each cubic centimeter. hereinafter, when describing "the concentration of an element in a first component is greater than the concentration of the element in a second component", it means that the concentration of the element measured at an arbitrary point in the first component is greater than the concentration of the element measured at an arbitrary point in the second component. For example, the concentration of the element at half the thickness of the first component is greater than the concentration of the element at half the thickness of the second component. For example, the maximum concentration of the element in the first component is greater than the maximum concentration of the element in the second component, but the present disclosure is not limited thereto. For example, the concentration of the element measured at a first point in the first component is greater than the concentration of the element measured at a second point in the second component, and the concentration of the element measured at a third point in the first component that is different from the first point may be less than or equal to the concentration of the element measured at the second point in the second component. In addition, when describing "the concentration of an element in a first component is greater than the concentration of the element in a second component", it includes the case where the second component does not substantially include the element. In other words, it includes the case where the concentration of the element in the first component is greater than the concentration of the element in the second component, and the concentration of the element in the second component is substantially 0.

[0054] In the present disclosure, the electronic device may include a display module, a backlight module, an antenna module, a sensing module or a splicing module, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display module may be a non-self-luminous display module or a self-luminous display module. The antenna module may be a liquid crystal type antenna module or a non-liquid crystal type antenna module, and the sensing module may be a sensing module for sensing capacitance, light, heat or ultrasound, but is not limited thereto. Electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light emitting diode or a photodiode. The light emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro light emitting diode (micro LED) or a quantum dot light emitting diode (quantum dot LED), but is not limited thereto. The splicing module may, for example, be a display splicing module or an antenna splicing module, but is not limited thereto.

[0055] In addition, the appearance of the electronic device can be rectangular, circular, polygonal, with curved edges or other suitable shapes. The electronic device can have peripheral systems such as processing system, driving system, control system, light source system, shelf system, etc. to support the display module or splicing module.

[0056] It should be understood that, for the sake of clarity, some components of the electronic device may be omitted in the drawings, and only some components are schematically shown. In some embodiments, additional components may be added to the electronic device described below. In other embodiments, some components of the electronic device described below may be replaced or omitted. It should be understood that in some embodiments, additional operating steps may be provided before, during and / or after the method of forming the electronic device. In some embodiments, some of the operating steps described may be replaced or omitted, and the order of some of the operating steps described is interchangeable.

[0057] Reference Figure 1 , which shows a cross-sectional schematic diagram of an electronic device 1 according to some embodiments of the present disclosure. In some embodiments, Figure 1 A substrate 10 is provided as shown. In some embodiments, the substrate 10 may include glass, quartz, sapphire, ceramic, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), other suitable materials or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the substrate 10 may include a light-transmitting substrate, a semi-transmitting substrate or an opaque substrate.

[0058] In some embodiments, a metal layer 20 may be formed on the substrate 10. In some embodiments, the metal layer 20 may be disposed between the substrate 10 and a buffer layer formed subsequently. In other words, before forming the buffer layer, a metal layer 20 may be formed on the substrate 10. In some embodiments, the metal layer 20 may include a conductive material. In some embodiments, the conductive material may include a metal, a metal nitride, a semiconductor material, other suitable conductive materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the conductive material may include (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), silver (Ag), magnesium (Mg), alloys thereof, compounds thereof, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the conductive material may include a transparent conductive oxide (TCO). For example, the transparent conductive oxide may include indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), antimony tin oxide (ATO), other suitable transparent conductive materials or combinations thereof, but the present disclosure is not limited thereto.

[0059] In some embodiments, the metal layer 20 may be formed by a deposition process, an etching process, a patterning process, other suitable processes or a combination thereof. For example, the deposition process may include a chemical vapor deposition (CVD) process, a sputtering process, an evaporation process, a physical vapor deposition (PVD) process, other suitable deposition processes or a combination thereof, but the present disclosure is not limited thereto. For example, the etching process may include dry etching, a wet etching process, other suitable etching processes or a combination thereof, but the present disclosure is not limited thereto.

[0060] In some embodiments, the metal layer 20 may be a single layer (not shown in the figure) or include multiple layers (such as Figure 1). In some embodiments, the metal layer 20 may include a first metal layer 22 and a second metal layer 24. In some embodiments, in the normal direction of the substrate 10 (i.e., the second direction D2), the first metal layer 22 may be disposed on the substrate 10, and the second metal layer 24 may be disposed on the first metal layer 22. In some embodiments, the first metal layer 22 may serve as an interface layer between the second metal layer 24 and the substrate 10. In some embodiments, the first metal layer 22 may include titanium, and the second metal layer 24 may include copper. In some embodiments, the metal layer 20 may serve as a bottom gate electrode and / or a light shielding layer in a double gate electrode in the electronic device 1. For example, the metal layer 20 may be used to electrically connect to a gate electrode formed subsequently to transmit a gate signal. Alternatively, the metal layer 20 may be used to block backlight and / or light scattered within each component.

[0061] In some embodiments, Figure 1 As shown, a buffer layer 30 may be formed on the substrate 10. In some embodiments, the buffer layer 30 may include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, other suitable buffer materials or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the buffer layer 30 may be formed by the aforementioned deposition process, thermal oxidation process or other suitable processes.

[0062] In some embodiments, the buffer layer 30 may be a single layer (not shown in the figure) or include multiple layers (such as Figure 1). In some embodiments, the buffer layer 30 may include a first buffer layer 32 and a second buffer layer 34. In some embodiments, in the normal direction of the substrate 10 (i.e., the second direction D2), the first buffer layer 32 may be disposed on the metal layer 20, and the second buffer layer 34 may be disposed on the first buffer layer 32. In some embodiments, the first buffer layer 32 may include silicon nitride, and the second buffer layer 34 may include silicon oxide. Accordingly, the second buffer layer 34 can prevent or reduce the diffusion of hydrogen (H) ions in the first buffer layer 32 into the subsequently formed semiconductor oxide layer. In detail, since the second buffer layer 34 is in contact with the subsequently formed semiconductor oxide layer, when the second buffer layer 34 includes silicon oxide, the second buffer layer 34 can prevent or reduce the diffusion of hydrogen ions generated from the precursor of silicon nitride into the subsequently formed semiconductor oxide layer. Among them, the second buffer layer 34 can prevent hydrogen ions from diffusing into the first portion of the semiconductor oxide layer, which makes the conductivity of the first portion of the semiconductor oxide layer too high, causing unnecessary conduction in the first portion of the semiconductor oxide layer, and causing the transistor to deteriorate. Once the first portion of the semiconductor oxide layer serving as the channel region is unnecessarily turned on, the switching of the transistor cannot be controlled by the gate electrode, thereby deteriorating the transistor.

[0063] In some embodiments, Figure 1 As shown, a semiconductor oxide layer 40 may be formed on the buffer layer 30. In some embodiments, the semiconductor oxide layer 40 may include a transparent conductive oxide. In some embodiments, the semiconductor oxide layer 40 may include indium, gallium, zinc, or a combination thereof, but the present disclosure is not limited thereto. For example, the semiconductor oxide layer 40 may include indium and gallium. In some embodiments, the semiconductor oxide layer 40 may include indium gallium oxide (IGO) or indium gallium zinc oxide (IGZO). In some embodiments, the semiconductor oxide layer 40 may be disposed between the metal layer 20 and a gate electrode formed subsequently.

[0064] In some embodiments, Figure 1As shown, the semiconductor oxide layer 40 may have a first portion 40A and a second portion 40B adjacent to the first portion 40A. In some embodiments, along the first direction D1, the first portion 40A may be disposed between the second portions 40B. In some embodiments, along the normal direction of the substrate 10, the first portion 40A of the semiconductor oxide layer 40 may correspond to a gate electrode formed subsequently. In some embodiments, the projection range of the gate electrode on the semiconductor oxide layer 40 is the range of the first portion 40A. In other words, a portion of the semiconductor oxide layer 40 on which the gate electrode is disposed may be referred to as the first portion 40A, and the remaining portion of the semiconductor oxide layer 40 on which the gate electrode is not disposed may be referred to as the second portion 40B. In some embodiments, the first portion 40A of the semiconductor oxide layer 40 may be used as a channel region of the electronic device 1, and the second portion 40B of the semiconductor oxide layer 40 may be used as a conductive region of the electronic device 1. In some embodiments, the second portion may be an N+ region doped with an N-type dopant so that the semiconductor oxide layer 40 is electrically connected to other components, but the present disclosure is not limited thereto.

[0065] In some embodiments, Figure 1 As shown, a first insulating layer 50 may be formed on the semiconductor oxide layer 40. In other words, before forming a subsequent gate electrode, the first insulating layer 50 is formed on the semiconductor oxide layer 40. In some embodiments, the first insulating layer 50 may include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, other suitable insulating materials or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the first insulating layer 50 may serve as a gate insulating layer.

[0066] In some embodiments, Figure 1As shown, the gate electrode 60 may be formed on the first insulating layer 50. For example, the gate electrode 60 may be disposed on the buffer layer 30. In some embodiments, the material and the forming method of the gate electrode 60 may be the same as or different from the material and the forming method of the metal layer 20. In some embodiments, the gate electrode 60 may include a first conductive layer 62 and a second conductive layer 64. In some embodiments, the first conductive layer 62 may be disposed on the first insulating layer 50, and the second conductive layer 64 may be disposed on the first conductive layer 62. In some embodiments, the first conductive layer 62 may include titanium, and the second conductive layer 64 may include copper. In some embodiments, the first conductive layer 62 may serve as an interface layer between the second conductive layer 64 and the first insulating layer 50. In some embodiments, in the normal direction of the substrate 10, the gate electrode 60 may overlap with the first portion 40A of the semiconductor oxide layer 40, and the gate electrode 60 does not overlap with the second portion 40B of the semiconductor oxide layer 40. In some embodiments, in a cross section, the width of the first insulating layer 50 is greater than the width of the gate electrode 60. However, in some embodiments, in a cross-section, the width of the first insulating layer 50 is substantially equal to the width of the gate electrode 60 .

[0067] In some embodiments, Figure 1 As shown, a second insulating layer 70 may be formed on the buffer layer 30, the semiconductor oxide layer 40, the first insulating layer 50, and the gate electrode 60. In some embodiments, the material and the forming method of the second insulating layer 70 may be the same as or different from the material and the forming method of the first insulating layer 50. In some embodiments, the second insulating layer 70 may serve as an interlayer dielectric (ILD) layer. In some embodiments, the second insulating layer 70 may include silicon oxynitride.

[0068] In some embodiments, before forming the second insulating layer 70, a surface treatment process such as a plasma bombardment process may be performed on the top surface of the semiconductor oxide layer 40 by hydrogen (H) to improve the conductivity of the second portion 40B of the semiconductor oxide layer 40. Then, the second insulating layer 70 is formed on the semiconductor oxide layer 40, and the hydrogen ions on the top surface of the semiconductor oxide layer 40 partially diffuse into the second insulating layer 70. It should be noted that since the surface treatment process is performed on the top surface of the semiconductor oxide layer 40 and the first portion 40A of the semiconductor oxide layer 40 is blocked by the gate electrode 60, it is possible to prevent the hydrogen ions from diffusing into the first portion 40A of the semiconductor oxide layer 40, thereby making the conductivity of the first portion 40A of the semiconductor oxide layer 40 too high, causing the first portion 40A of the semiconductor oxide layer 40 to be unnecessarily turned on.

[0069] In other embodiments, during the process of forming the second insulating layer 70 on the semiconductor oxide layer 40, the hydrogen ion concentration in the environment is increased, for example, the hydrogen ion concentration in the process chamber is increased, so that the hydrogen ions in the environment enter the semiconductor oxide layer 40 and the second insulating layer 70 to improve the conductivity of the semiconductor oxide layer 40. In some embodiments, the surface treatment process may be performed first, and then the ion implantation process described below may be performed. In other embodiments, the ion implantation process described below may be performed first, and then the surface treatment process may be performed.

[0070] In some embodiments, Figure 1 As shown, a passivation layer 80 may be formed on the second insulating layer 70. In some embodiments, the material and formation method of the passivation layer 80 may be the same as or different from the material and formation method of the first insulating layer 50. In some embodiments, the passivation layer 80 may include silicon nitride.

[0071] In some embodiments, Figure 1 As shown, an ion implantation process IPB can be performed on the semiconductor oxide layer 40 by boron (B). In some embodiments, after forming the gate electrode 60 and after forming the second insulating layer 70 on the buffer layer 30, the semiconductor oxide layer 40, the first insulating layer 50 and the gate electrode 60, an ion implantation process IPB is performed on the semiconductor oxide layer 40. Since the ion implantation process IPB is blocked by the gate electrode 60, boron ions are implanted into the second portion 40B of the semiconductor oxide layer 40, and substantially not implanted into the first portion 40A of the semiconductor oxide layer 40.

[0072] When the semiconductor oxide layer 40 is subjected to an ion implantation process IPB by boron, the boron ions will collide with oxygen atoms in the semiconductor oxide layer 40, so that the semiconductor oxide layer 40 generates oxygen vacancies, that is, generates free electrons, thereby improving the conductivity of the second portion 40B of the semiconductor oxide layer 40. Therefore, the second portion 40B of the semiconductor oxide layer 40 can be a conductive region, so that the semiconductor oxide layer 40 is electrically connected to other components by the second portion 40B of the semiconductor oxide layer 40. Compared with the use of other ions such as hydrogen ions to perform an ion implantation process, the parameters of the boron ion implantation process can be accurately adjusted to avoid the diffusion of hydrogen ions into the channel region of the electronic device 1, which causes the channel region of the electronic device 1 to generate unnecessary conduction. Accordingly, the use of a boron ion implantation process can improve the controllability of the method for manufacturing the electronic device 1 and / or improve the reliability of the electronic device 1.

[0073] It should be noted that the process sequence of performing the ion implantation process IPB is not limited to this, and may be as follows Figure 2 and Figure 3 shown.

[0074] Hereinafter, the same or similar component symbols and descriptions are omitted.

[0075] Reference Figure 2 , which shows a cross-sectional schematic diagram of an electronic device 2 according to some embodiments of the present disclosure. In some embodiments, Figure 2 As shown, after conformally forming the first insulating layer 50 on the buffer layer 30 and the semiconductor oxide layer 40, the gate electrode 60 is formed on the first insulating layer 50. Then, after forming the gate electrode 60, an ion implantation process IPB is performed on the semiconductor oxide layer 40. In this embodiment, a patterning process may be optionally performed to pattern the first insulating layer 50. Then, a second insulating layer 70 and a passivation layer 80 may be further formed.

[0076] Reference Figure 3 , which shows a cross-sectional schematic diagram of an electronic device 3 according to some embodiments of the present disclosure. In some embodiments, Figure 3 As shown, after conformally forming the first insulating layer 50 on the buffer layer 30 and the semiconductor oxide layer 40, the gate electrode 60 is formed on the first insulating layer 50. Next, a patterning process is performed to pattern the first insulating layer 50 to expose the top surface of the second portion 40B of the semiconductor oxide layer 40. Furthermore, after patterning the first insulating layer 50, an ion implantation process IPB is performed on the semiconductor oxide layer 40. In other embodiments, such as Figure 3 As shown, after conformally forming the first insulating layer 50 on the buffer layer 30 and the semiconductor oxide layer 40, a patterning process is performed to pattern the first insulating layer 50 to expose the top surface of the second portion 40B of the semiconductor oxide layer 40. Next, a gate electrode 60 is formed on the patterned first insulating layer 50. Furthermore, an ion implantation process IPB is performed on the semiconductor oxide layer 40.

[0077] Hereinafter, the electronic device 1 is taken as an example to illustrate the result of element analysis after performing the ion implantation process IPB, but the present disclosure is not limited thereto.

[0078] For the sake of convenience, in the following, FIG. 4A to FIG. 4E Different components are marked separately (e.g., with slashes and shading), but FIG. 4A to FIG. 4E Represents essentially the same analytical results.

[0079] Reference FIG. 4A to FIG. 4E , which respectively show elemental analysis schematic diagrams of the electronic device 1 according to some embodiments of the present disclosure. Figure 4E Respectively represent along Figure 1Schematic diagram of elemental analysis of cross section AA of electronic device 1 in negative ion mode TOF-SIMS analysis. The minimum analyzable concentration of TOF-SIMS analysis in negative ion mode is in the range of 1.0E+19 atoms / cc to 1.0E+20 atoms / cc. - ) ions and boron (B - The concentration of ) ions refers to the vertical axis coordinate on the left (concentration (atoms / cm3)), and its concentration is the concentration after quantitative analysis. - 、Si - 、SiN - 、ZnO - 、GaO - and InO - The content of boron (B) is referred to the right vertical axis coordinate (intensity (counts)), and the intensity is the count after quantitative analysis. In some embodiments, the boron negative (B) is analyzed by TOF-SIMS in negative ion mode. - ) ions are equivalent to the concentration of boron.

[0080] Also with reference Figure 1 and Figure 4A In some embodiments, Figure 1 As shown, in the normal direction of the substrate 10, a portion 30P of the buffer layer 30 may overlap with the second portion 40B of the semiconductor oxide layer 40. In some embodiments, in the normal direction of the substrate 10, the portion 30P of the buffer layer 30 may have a first portion 32P and a second portion 34P disposed on the first portion 32P. In some embodiments, when the buffer layer 30 includes multiple layers, for example, when the buffer layer 30 includes a composite material, the first portion and the second portion of the buffer layer 30 are distinguished by different material types. In some embodiments, as Figure 1 As shown, the buffer layer 30 includes a first buffer layer 32 and a second buffer layer 34, so the first portion 32P of the portion 30P of the buffer layer 30 may be a portion of the first buffer layer 32, and the second portion 34P of the portion 30P of the buffer layer 30 may be a portion of the second buffer layer 34. In other embodiments, when the buffer layer 30 is a single layer (not shown in the figure), the first portion and the second portion of the buffer layer 30 are distinguished by half of the thickness of the buffer layer 30 in the normal direction of the substrate 10.

[0081] In some embodiments, Figure 1 and Figure 4AAs shown, the boron concentration in another portion of the buffer layer 30 away from the semiconductor oxide layer 40 is higher than that in the portion of the buffer layer 30 adjacent to the semiconductor oxide layer 40. In some embodiments, after performing the ion implantation process IPB, the boron concentration in the first portion 32P (marked with shading) of the portion 30P of the buffer layer 30 is greater than the boron concentration in the second portion 34P (marked with slashes) of the portion 30P of the buffer layer 30. Accordingly, by adjusting the parameters of performing the ion implantation process IPB, it is possible to avoid, for example, during a subsequent thermal process performed on the semiconductor oxide layer 40, allowing boron ions to diffuse into the first portion 40A of the semiconductor oxide layer 40, thereby causing the first portion 40A of the semiconductor oxide layer 40 to be unnecessarily turned on.

[0082] For example, the parameters of the ion implantation process IPB can be adjusted by increasing the doping energy of the ion implantation process IPB and / or increasing the doping depth, so that the doped boron ions are further away from the semiconductor oxide layer 40. Therefore, the ion implantation process IPB can improve the problem that the first part of the semiconductor oxide layer as the channel region is unnecessarily turned on, and the switching of the transistor cannot be controlled by the gate electrode, thereby deteriorating the transistor. Furthermore, since the doping energy of the ion implantation process IPB can be higher, more oxygen vacancies can be formed at the semiconductor oxide layer 40, thereby improving the conductivity of the semiconductor oxide layer 40.

[0083] In some embodiments, Figure 1 and Figure 4B As shown, the boron concentration in another portion of the first portion 32P of the buffer layer 30 away from the semiconductor oxide layer 40 is higher than that in a portion of the first portion 32P of the buffer layer 30 adjacent to the semiconductor oxide layer 40. In some embodiments, the first line segment L1 is a virtual extension line representing a position of half the thickness of the first portion 32P in the normal direction of the substrate 10, so the first portion 32P is divided into a lower portion 32B and an upper portion 32U disposed on the lower portion 32B by the first line segment L1. In some embodiments, after performing the ion implantation process IPB, the boron concentration in the lower portion 32B (marked with shading) is greater than the boron concentration in the upper portion 32U (marked with oblique lines). Accordingly, it is possible to prevent boron ions from diffusing into the semiconductor oxide layer 40, so that the first portion 40A of the semiconductor oxide layer 40 is unnecessarily turned on.

[0084] In some embodiments, Figure 1 and Figure 4CAs shown in FIG. 1 , after performing the ion implantation process IPB, the metal layer 20 (marked with a shading) includes boron. Accordingly, boron can be used to protect the metal layer 20 from oxidation. For example, when the metal layer 20 includes copper, boron can act as a deoxidizer (or antioxidant) to reduce the possibility that copper is oxidized and the conductivity of the metal layer 20 is degraded. In some embodiments, as shown in FIG. Figure 1 and Figure 4C As shown, after performing the ion implantation process IPB, the boron concentration in the metal layer 20 (marked with shaded lines) is greater than the boron concentration in the second portion 34P (marked with diagonal lines) of a portion 30P of the buffer layer 30. Accordingly, it is possible to prevent the boron ions from diffusing into the semiconductor oxide layer 40, so that the first portion 40A of the semiconductor oxide layer 40 is not turned on unnecessarily.

[0085] In some embodiments, Figure 1 and Figure 4D As shown, after performing the ion implantation process IPB, the boron concentration in the second portion 40B (marked with shading) of the semiconductor oxide layer 40 is less than the boron concentration in the first portion 32P (marked with shading) of a portion 30P of the buffer layer 30. Accordingly, by controlling the parameters of performing the ion implantation process IPB, the boron ions are prevented from affecting the properties of the semiconductor oxide layer 40. Thus, the boron ions can be prevented from diffusing into the semiconductor oxide layer 40, so that the first portion 40A of the semiconductor oxide layer 40 is not necessarily turned on.

[0086] Also with reference Figure 1 and Figure 4E In some embodiments, Figure 1 As shown, in the normal direction of the substrate 10, a portion 70P of the second insulating layer 70 may overlap with the second portion 40B of the semiconductor oxide layer 40. In some embodiments, in the normal direction of the substrate 10, a portion 70P of the second insulating layer 70 may have a first portion and a second portion disposed on the first portion. In some embodiments, when the second insulating layer 70 includes multiple layers (not shown in the figure), for example, when the second insulating layer 70 includes a composite material, the first portion and the second portion of the second insulating layer 70 are distinguished by different material types. In other embodiments, such as Figure 1 As shown in FIG. 1 , when the second insulating layer 70 is a single layer, the first portion 72B of the second insulating layer 70 and the second portion 72U disposed on the first portion 72B are distinguished by half of the thickness of the second insulating layer 70 in the normal direction of the substrate 10. In some embodiments, the second line segment L2 is a virtual extension line representing a position where half of the thickness of the second insulating layer 70 in the normal direction of the substrate 10 is located, and thus the second insulating layer 70 is distinguished by the second line segment L2 into the first portion 72B and the second portion 72U. In some embodiments, as Figure 1 and Figure 4EAs shown, the hydrogen concentration in another portion of the second insulating layer 70 away from the semiconductor oxide layer 40 is lower than that in a portion of the second insulating layer 70 adjacent to the semiconductor oxide layer 40. In some embodiments, after performing the ion implantation process IPB, the hydrogen concentration in the first portion 72B (marked with shading) of the portion 70P of the second insulating layer 70 is greater than the hydrogen concentration in the second portion 72U (marked with slashes) of the portion 70P of the insulating layer 70. Accordingly, the conductivity of the second portion 40B of the semiconductor oxide layer 40 can be improved by performing a surface treatment process on the top surface of the semiconductor oxide layer 40 with hydrogen.

[0087] In some embodiments, the hydrogen concentration in the first portion 72B of the portion 70P of the second insulating layer 70 is in a range of 1.0E+20 atoms / cm3 to 1.0E+23 atoms / cm3. For example, the hydrogen concentration in the first portion 72B of the portion 70P of the second insulating layer 70 is in a range of 1.0E+21 atoms / cm3 to 1.0E+22 atoms / cm3. For example, the hydrogen concentration in the first portion 72B of a portion 70P of the second insulating layer 70 may be 1.0E+21 atoms / cm3, 2.0E+21 atoms / cm3, 3.0E+21 atoms / cm3, 4.0E+21 atoms / cm3, 5.0E+21 atoms / cm3, 6.0E+21 atoms / cm3, 7.0E+21 atoms / cm3, 8.0E+21 atoms / cm3, 9.0E+21 atoms / cm3, 1.0E+22 atoms / cm3, or any value between the foregoing values ​​or a numerical range consisting of any values, but the present disclosure is not limited to this. In other embodiments, the thickness of the portion 70P of the second insulating layer 70 is divided into three equal parts in the normal direction of the substrate 10, so that the portion 70P of the second insulating layer 70 may include a lower portion, a middle portion, and an upper portion, the middle portion is disposed on the lower portion, and the upper portion is disposed on the middle portion. In some embodiments, the boron concentration in the lower portion of the portion 70P of the second insulating layer 70 is greater than the boron concentration in the middle portion and the upper portion of the portion 70P of the second insulating layer 70.

[0088] It should be noted that if FIG. 4A to FIG. 4EAs shown, the curve of the boron concentration in the second portion 34P of the portion 30P of the buffer layer 30, the semiconductor oxide layer 40, the second insulating layer 70, and the passivation layer 80 is close to a horizontal line, indicating that the second portion 34P of the portion 30P of the buffer layer 30, the semiconductor oxide layer 40, the second insulating layer 70, and the passivation layer 80 may include boron, but the boron concentration may be lower than the minimum analyzable value of the concentration analyzed by TOF-SIMS in the negative ion mode. Therefore, the TOF-SIMS analysis in the positive ion mode is described below. In some embodiments, the boron positive (B) value analyzed by TOF-SIMS in the positive ion mode + ) ions are equivalent to the concentration of boron (e.g., the concentrations may be substantially equal).

[0089] Reference Figure 5 , which shows an elemental analysis diagram of the electronic device 1 according to some embodiments of the present disclosure. Figure 5 Indicates that along Figure 1 Schematic diagram of elemental analysis of cross section AA of electronic device 1 in positive ion mode TOF-SIMS analysis. The minimum analyzable concentration of TOF-SIMS analysis in positive ion mode is about 1.0E+17 atoms / cc. + ) ion concentration refers to the vertical axis coordinate on the left (concentration (atoms / cm3)), and its concentration is the concentration after quantitative analysis. + , Ga + 、Si2N + and + The content is referred to the vertical axis coordinate (intensity (counts)) on the right, and its intensity is the count after qualitative analysis. In some embodiments, since the minimum analyzable value of the positive ion mode is lower than the minimum analyzable value of the negative ion mode, the positive ion mode can more sensitively display the concentration.

[0090] In some embodiments, Figure 5As shown, the boron concentration in the second portion 40B of the semiconductor oxide layer 40 is in the range of 1.0E+17 atoms / cc to 1.0E+18 atoms / cc. For example, the boron concentration in the second portion 40B of the semiconductor oxide layer 40 may be 1.0E+17 atoms / cc, 2.0E+17 atoms / cc, 3.0E+17 atoms / cc, 4.0E+17 atoms / cc, 5.0E+17 atoms / cc, 6.0E+17 atoms / cc, 7.0E+17 atoms / cc, 8.0E+17 atoms / cc, 9.0E+17 atoms / cc, 1.0E+18 atoms / cc, or any value therebetween or a range of any values, but the present disclosure is not limited thereto. In some embodiments, after performing the ion implantation process IPB, the boron concentration in the second portion 40B of the semiconductor oxide layer 40 is less than the boron concentration in the first portion 32P of the portion 30P of the buffer layer 30. Accordingly, by controlling the parameters of performing the ion implantation process IPB, the boron ions are prevented from affecting the properties of the semiconductor oxide layer 40.

[0091] In some embodiments, Figure 5 As shown, the boron concentration in the first portion 32P of the portion 30P of the buffer layer 30 is in the range of 1.0E+17 atoms / cm3 to 1.0E+21 atoms / cm3. For example, the boron concentration in the first portion 32P of the portion 30P of the buffer layer 30 may be 1.0E+17 atoms / cm3, 5.0E+17 atoms / cm3, 1.0E+18 atoms / cm3, 5.0E+18 atoms / cm3, 1.0E+19 atoms / cm3, 5.0E+19 atoms / cm3, 1.0E+20 atoms / cm3, 5.0E+20 atoms / cm3, 1.0E+21 atoms / cm3, or any value between the aforementioned values ​​or a numerical range consisting of any values, but the present disclosure is not limited thereto. Accordingly, it is possible to prevent the boron ions from diffusing into the semiconductor oxide layer 40 , thereby preventing the first portion 40A of the semiconductor oxide layer 40 from being unnecessarily turned on.

[0092] In some embodiments, the electronic devices 1-3 of the present disclosure may be display devices, and the display devices may include transistors with dual gate electrodes. Accordingly, the semiconductor oxide layer may provide high carrier mobility to improve the properties of the electronic devices 1-3.

[0093] In summary, according to the embodiments of the present disclosure, an electronic device and a manufacturing method thereof are provided, which can form a buffer layer by adjusting the parameters of the ion implantation process, such as doping energy, doping depth, doping concentration, dopant type, etc., so as to improve the properties of the electronic device. For example, the present disclosure can improve the conductivity of the electronic device, prevent heat diffusion from affecting other components, and / or prevent electrode degradation.

[0094] The features between the embodiments of the present disclosure can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufactures, material compositions, devices, methods and steps from the disclosure of the present disclosure. As long as substantially the same functions can be implemented in the embodiments described herein or substantially the same results can be obtained, they can be used according to the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufactures, material compositions, devices, methods and steps. The scope of protection of the present disclosure shall be determined by the scope of the claims. Any embodiment or claim of the present disclosure is not required to achieve all the purposes, advantages and / or features disclosed in this disclosure.

[0095] Several embodiments are summarized above so that those skilled in the art can better understand the concepts of the embodiments of the present disclosure. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure.

Claims

1. An electronic device, comprising: a substrate; a buffer layer disposed on the substrate; a semiconductor oxide layer disposed on the buffer layer and having a first portion and a second portion adjacent to the first portion; and a gate electrode overlapping the first portion; A portion of the buffer layer overlaps with the second portion of the semiconductor oxide layer, the portion of the buffer layer has a first portion and a second portion disposed on the first portion, and the boron concentration in the first portion is greater than the boron concentration in the second portion.

2. The electronic device according to claim 1, wherein: The first portion has a lower portion and an upper portion disposed on the lower portion, wherein a boron concentration in the lower portion is greater than a boron concentration in the upper portion. 3 . The electronic device as claimed in claim 1 , further comprising a metal layer disposed between the substrate and the buffer layer, wherein the metal layer comprises boron.

4. The electronic device as claimed in claim 3, characterized in that: A boron concentration in the metal layer is greater than a boron concentration in the second portion of the buffer layer.

5. The electronic device according to claim 1, wherein: A boron concentration in the second portion of the semiconductor oxide layer is less than a boron concentration in the first portion of the buffer layer.

6. The electronic device as claimed in claim 5, characterized in that: The boron concentration in the second portion of the semiconductor oxide layer is in a range of 1.0E+17 atoms / cc to 1.0E+18 atoms / cc.

7. The electronic device as described in claim 1 further includes an insulating layer disposed on the semiconductor oxide layer, wherein a portion of the insulating layer overlaps with the second portion of the semiconductor oxide layer, the portion of the insulating layer has a first portion and a second portion disposed on the first portion, and the hydrogen concentration in the first portion of the insulating layer is greater than the hydrogen concentration in the second portion of the insulating layer.

8. The electronic device as claimed in claim 7, characterized in that: The hydrogen concentration in the first portion is in the range of 1.0E+20 atoms / cm 3 to 1.0E+23 atoms / cm 3 .

9. The electronic device as claimed in claim 1, wherein: The boron concentration in the first portion of the buffer layer is in a range of 1.0E+17 atoms / cm 3 to 1.0E+21 atoms / cm 3 .

10. The electronic device according to claim 1, wherein: The semiconductor oxide layer is arranged between a metal layer and the gate electrode.

11. The electronic device according to claim 1, wherein: The semiconductor oxide layer includes indium and gallium.

12. The electronic device as claimed in claim 1, which is a display apparatus.

13. A method for manufacturing an electronic device, comprising: providing a substrate; forming a buffer layer on the substrate; forming a semiconductor oxide layer on the buffer layer, the semiconductor oxide layer having a first portion and a second portion; forming a gate electrode on the buffer layer, wherein the gate electrode overlaps the first portion; and performing an ion implantation process on the semiconductor oxide layer by using boron; Wherein, a portion of the buffer layer overlaps with the second portion of the semiconductor oxide layer, the portion of the buffer layer has a first portion and a second portion disposed on the first portion, and after the ion implantation process, the boron concentration in the first portion is greater than the boron concentration in the second portion.

14. The method according to claim 13, characterized in that After forming the gate electrode, the ion implantation process is performed. 15 . The method of claim 14 , further comprising forming a first insulating layer on the semiconductor oxide layer before forming the gate electrode. 16 . The method of claim 15 , further comprising patterning the first insulating layer to expose the second portion of the semiconductor oxide layer before performing the ion implantation process. 17 . The method of claim 13 , further comprising forming a second insulating layer on the gate electrode after forming the gate electrode, wherein the ion implantation process is performed after forming the second insulating layer. 18 . The method of claim 13 , further comprising forming a metal layer on the substrate before forming the buffer layer.

19. The method according to claim 18, characterized in that After performing the ion implantation process, the metal layer includes boron.

20. The method of claim 13, wherein: The semiconductor oxide layer includes indium and gallium.

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